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Preliminary
MSM9563 IC for FM Multiplex Data Demodulation User's Manual [Hardware]
ISSUE DATE: Jan. 26, 1999 Version: 0.8
IMPORTANT NOTICE
DARC (DAta Radio Channel), an FM multiplex broadcast technology, has been developed by NHK (Japan Broadcasting Corporation). DARC is a registered trademark of NHK Engineering Service (NHK-ES). Any manufacturer who intends to manufacture/sell products that utilize DARC technology needs to be licensed by NHK-ES. For detailed information on licenses, please contact: NHK Engineering Service Phone: (+81) 3-3481-2650
DARC (DAta Radio Channel), an FM multiplex broadcast technology, has been developed by NHK (Japan Broadcasting Corporation). DARC is a registered trademark of NHK Engineering Service (NHK-ES). Any manufacturer licensed by NHK-ES can manufacture and sell products that utilize the DARC technology. The products utilizing the DARC technology can be marked with the logotype shown to the left. In the DARC system, 16kbps of digital data L-MSK modulated at 76KHz are multiplied on an ordinary FM broadcast base band signal. An FM multiplex demodulation LSI performs decoding of the digital data signal. For detailed information on license, please contact: NHK Engineering Service Phone: 81-3-3481-2650
E2Y0001-29-11
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents cotained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation.
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Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
TABLE OF CONTENTS
1. GENERAL DESCRIPTION ...................................................................................1-1 2. BLOCK DIAGRAM ........................................................................................... 2-1
3. PIN INFORMATION ........................................................................................... 3-1 3.1 PIN CONFIGURATION (TOP VIEW) ............................................................3-1 3.2 PIN DESCRIPTIONS ...................................................................................3-2 4. ELECTRICAL CHARACTERISTICS .....................................................................4-1 4.1 ABSOLUTE MAXIMUM RATINGS ..............................................................4-1 4.2 RECOMMENDED OPERATING CONDITIONS ........................................... 4-1 4.3 DC CHARACTERISTICS .............................................................................4-2 4.4 AC CHARACTERISTICS .............................................................................4-3 4.5 FILTER CHARACTERISTICS .......................................................................4-4 4.6 TIMING DIAGRAM ......................................................................................4-5 5. CONTROL REGISTERS ......................................................................................5-1 5.1 OPERATING MODE REGISTERS ...............................................................5-1 5.2 INTERRUPT REGISTERS ............................................................................5-5 5.3 RECEIVE DATA REGISTERS ......................................................................5-7 5.4 TIMING INTERRUPT REGISTERS ..............................................................5-21 5.5 CLOCK REGENERATION REGISTERS....................................................... 5-28 5.6 BLOCK SYNCHRONIZATION REGISTERS ................................................ 5-30 5.7 FRAME SYNCHRONIZATION REGISTERS ................................................ 5-34 5.8 ERROR CORRECTION REGISTERS ........................................................... 5-36 5.9 LAYER 4 CRC REGISTERS ........................................................................5-38 5.10 ANALOG TEST REGISTER ......................................................................... 5-40 5.11 POWER DOWN REGISTER ........................................................................5-41 5.12 TEST CONTROL REGISTERS.....................................................................5-42 5.13 EXTENSION PORT REGISTER ...................................................................5-43 6. EXTERNAL CONNECTION EXAMPLE ................................................................ 6-1 7. APPLICATION CIRCUIT ......................................................................................7-1 APPENDIX: LIST OF REGISTERS ............................................................................Appendix-1
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- ii -
Chapter 1
GENERAL DESCRIPTION
MSM9563 User's Manual Chapter 1 GENERAL DESCRIPTION
1.
GENERAL DESCRIPTION
The MSM9563 is an IC which demodulates FM character multiplex signals in the DARC (DAta Radio Channel) format to acquire digital data. This IC operates at 3 V. In the DARC format, baseband signals at ordinary FM broadcasting frequencies are multiplexed with 16 kbps digital data which is L-MSK-modulated at 76 kHz. The MSM9563 has a bandpass filter consisting of an SCF, frame synchronization circuit, and error correction circuit on a single chip. They allow a system for acquisition of digital data to be easily constructed by externally mounting an FM receiver tuner, microcontroller for control, and memory for temporary storage of data. The MSM9563, a FM multiplex demodulator, has a simple configuration, and is equipped with only necessary functions. By making changes to software for the external microcontroller, the MSM9563 meets the various requirements of FM multiplex broadcasting services to be offered in future. *1 DARC is a registered trademark of NHK Engineering Services. Any manufacturer licensed by NHK Engineering Service can manufacture and sell products that utilize the DARC technology. For detailed information on license, please contact: NHK Engineering Service Phone: 81-3481-2650 FEATURES * Built-in two receive channels including main channel and sub-channel (one of two FM stations can be selected) * Pin compatible with MSM9553 / MSM9555 * Internal frame memory enables automatic error correction. * Built-in bandpass filter (SCF) * Built-in block synchronization circuit and frame synchronization circuit * The number of synchronization protecting steps can be set * Regeneration of data clocks by digital PLL * 1T delay detector * Built-in error correcting circuit (Vertical/Horizontal) * Built-in layer-4 and layer-2 CRC processing circuit * International frame formats A (supporting a real time block), B, and C available * Microcontroller parallel interface * Clock output for external devices (64 kHz to 8.192 MHz selectable) * Power source: 2.7 to 3.6 V * Package: 44-pin plastic QFP (QFP44-P-910-0.80-2K) (Product name: MSM9563GA)
1-1
MSM9563 User's Manual Chapter 1 GENERAL DESCRIPTION
1-2
Chapter 2
BLOCK DIAGRAM
2. BLOCK DIAGRAM
FM multiplex signal input
LPF
Variable gain AMP
BPF (SCF)
Clock regeneration
Block synchronization
Frame synchronization
Timing control
Clock generator
Timer
INT
Vref SG
Filter Section
PN Descrambler Receive RAM SAEP FRAME memory Error correction & Layer 2 CRC Layer 4 CRC
2-1
IC internal clock
Data bus
Delay Detection Section
Frequency divider
Address bus
MSM9563 User's Manual Chapter 2 BLOCK DIAGRAM
1T delay circuit
CPU interface
LPF
Digital Signal Processing Section
XTAL2
XTAL1
Data
Add
RD
WR
CS
CLR
INT
Figure 2.1 Block Diagram
MSM9563 User's Manual Chapter 1 BLOCK DIAGRAM
2-2
Chapter 3
PIN INFORMATION
3. 3.1
,
PIN INFORMATION PIN CONFIGURATION (TOP VIEW)
42 *NC 41 *NC 40 CLR 43 *NC 44 *NC 39 *NC 38 A5 MON 1 ADETIN AVDD 2 3 4 5 6 7 8 9 AGND SG AIN XOUTC MOUT0 MOUT1 MOUT2 10 MOUT3 11 MOUT4 12 MOUT5 13 MOUT6 14 INT 15 WR 16 *NC 17 RD 18 44-Pin Plastic QFP
MSM9563 User's Manual Chapter 3 PIN INFORMATION
37 A4
36 A3
35 A2
34 A1 33 A0 32 XOUT 31 CS 30 XTAL2 29 XTAL1 28 DVDD 27 DGND 26 DB7 25 DB6 24 DB5 23 DB4 DB3 22
DB0 19
DB1 20
Figure 3.1 Pin Layout * Leave the NC pins (17, 39, 41, 42, 43, and 44) open.
3-1
DB2 21
MSM9563 User's Manual Chapter 3 PIN INFORMATION
3.2
PIN DESCRIPTIONS
Table 3.1 Pin Description Function Symbol WR RD INT CS CLR A0 to A5 DB0 to DB7 Pin 16 18 15 31 40 33 to 38 19 to 26 6 5 Type I I O I I I I/O I O Description Write signal to internal register. Read signal to internal register. Interrupt signal to microcontroller. When set to "L", an interrupt is generated. Chip select signal. When set to "L", the read, write, and data bus signals become effective. When set to "L", the internal register is initialized, and the IC enters power down mode. Address signal to internal register. Data bus signal to internal register. FM multiple signal input. Analog reference voltage pin. Connect a capacitor between this pin and the analog ground pin to prevent noise.
Microcontroller interface
Tuner interface
AIN SG
Analog section test
MON
1
O
Analog section waveform monitoring pin. The mode setting for the blocks in the analog section is specified by the analog section control register.
ADETIN Digital section test Clock MOUT0 to MOUT6 XTAL1 XTAL2 XOUT XOUTC
2 8 to 14 29 30 32 7
I O I O O I
Analog signal input pin for testing. Digital section test signal output and monitor output pins. 8.192 MHz crystal connection. 8.192 MHz crystal connection. Pin to supply variable clock (64 kHz to 8.192 MHz) to external devices. XOUT control. "L" sets XOUT output, "H" sets XOUT output inhibit. This pin is pulled up internally.
Power supply
AVDD AGND DVDD DGND
3 4 28 27
-- -- -- --
Analog power supply. Analog ground. Digital power supply. Digital ground.
3-2
Chapter 4
ELECTRICAL CHARACTERISTICS
MSM9563 User's Manual Chapter 4 ELECTRICAL CHARACTERISTICS
4. 4.1
No. 1 2 3 4
ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input voltage Output voltage Maximum power dissipation Storage temperature Symbol AVDD DVDD VI VO PD TSTG Ta = 25C, per package Ta = 25C, per output -- AVDD = DVDD Ta = 25C Condition Rating -0.3 to +7.0 V -0.3 to AVDD + 0.3 -0.3 to DVDD + 0.3 400 50 -55 to +150 mW C Unit
4.2
No. 1 2
RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Crystal oscillation frequency FM multiplex signal input voltage Operating temperature Symbol AVDD DVDD fXTAL Condition AVDD = DVDD -- Variable amplifier gain: 1 Range 2.7 to 3.6 8.192 MHz 100 ppm 0.6 to 0.9 0.4 to 0.6 0.3 to 0.4 0.2 to 0.3 -40 to +85 C -- VP-P AIN Unit V -- Applied Pin AVDD DVDD XTAL1, XTAL2
3
VAIN*
Variable amplifier gain: 1.5 Variable amplifier gain: 2 Variable amplifier gain: 3 --
4
Ta
* Peak values (a total voltage of the following signals (a) to (c)) of composite signals including multiplex signals. (a) Voice signals (100% modulated: voice max.) (b) Pilot signal (c) FM multiplex signals (10%: LMSK max.) The maximum amplitude of an input signal is in the range of 0.9 VP-P in which the internal IC circuit is not saturated. Therefore, multiplex singnals of up to 0.9 VP-P can be input if only multiplex signals (excluding composite signals) are input from a signal generator.
4-1
MSM9563 User's Manual Chapter 4 ELECTRICAL CHARACTERISTICS
4.3
No.
DC CHARACTERISTICS
(DVDD = AVDD = 2.7 to 3.6 V, DGND = AGND = 0 V, Ta = -40 to +85C) Parameter Symbol VIH Condition Min. 0.8 DVDD -- VIL VOH IOH = -1 mA IOL = 2 mA VIH = DVDD VIL = DGND VIH = AVDD VIL = AGND VIH = DVDD DVDD = 3 V, VIL = DGND VOH = AVDD
During nonmonitoring (Hiz)
Typ. --
Max. --
Unit
Applied Pin WR, RD, XOUTC,
1
Input voltage
V -- DVDD -0.5 -- -- -2 -- -2 -- 3 -- -2 -- -- -- -- -- -- -- -- -- -- 15 -- -- 14 -- 0.2 DVDD -- V 0.45 2 mA -- 2 mA
DB0 to DB7, CS, A0 to A5, CLR MOUT0 to MOUT6, INT, DB0 to DB7, XOUT WR, RD, CS, DB0 to DB7, A0 to A5, CLR
2
Output voltage VOL IIH1
3
Input current 1 IIL1 IIH2
4
Input current 2 IIL2 -- 2 50 2
ADETIN
5 6
Input current 3 Pull-up current
IIH3 Ipull IOH IOL
mA mA XOUTC
7
Output off-leakage current
VOL = AGND
During nonmonitoring (Hiz) During operation, no load
mA -- 28 50 mA
MON
8
Supply current
IDD
f = 8.192 MHz During power down, no load
AVDD, DVDD mA
4-2
MSM9563 User's Manual Chapter 4 ELECTRICAL CHARACTERISTICS
4.4
No. 1
AC CHARACTERISTICS
(DVDD = AVDD = 2.7 to 3.6 V, DGND = AGND = 0 V, Ta = -40 to +85C) Parameter Write setup time tSWR2 tHWR1 See figure 4.1 See figure 4.1 See figure 4.1 See figure 4.1 See figure 4.2 See figure 4.2 See figure 4.2 See figure 4.2 See figure 4.2 Layer 4 CRC mode See figure 4.3 Layer 4 CRC mode See figure 4.3 See figure 4.4 Continuously writing 90 -18 10 90 3 -18 90 -- -- -- -- -- -- -- -- -- -- -- -- -- ns tHWR2 -- -- -- -- -- 90 20 ns ns ns ns ns ns tWWR tSRD tHRD tWRD tDRD1 tDRD2 Symbol* tSWR1 Condition See figure 4.1 Min. 3 Typ. -- Max. -- ns Unit Applied Pin WR, CS, A0 to A5, DB0 to DB7 WR, CS, A0 to A5, DB0 to DB7 WR RD, CS, A0 to A5 RD, CS, A0 to A5 RD RD, DB0 to DB7 RD, DB0 to DB7 WR
2 3 4 5 6 7 8
Write hold time Write pulse width Read setup time Read hold time Read pulse width Read data output delay (1) Read data output delay (2) Layer 4 data Interval between write and write Layer 4 data
9
tIWRWR2
620
--
--
ns
10 Interval between write and read 11 Interval between write and write Interval between write and write Interval between write and read Interval between read and read
tIWRRD1
1.2
--
--
ms
WR, RD
tIWRWR
300
--
--
ns
WR
12
tIWRWR1
0x3B to 0x3D to the same address See figure 4.5
550
--
--
ns
WR
13 14
tIWRRD tIRDRD tDINTCLR tWCLR
See figure 4.4 See figure 4.6 See figure 4.7 See figure 4.8
300 300 200 200
-- -- -- --
-- -- -- --
ns ns ns ns
WR, RD RD INT, WR CLR
15 Interrupt CLR delay 16 CLR pulse width
* See "TIMING DIAGRAM".
4-3
MSM9563 User's Manual Chapter 4 ELECTRICAL CHARACTERISTICS
4.5
No. 1
FILTER CHARACTERISTICS
(DVDD = AVDD = 2.7 to 3.6 V, DGND = AGND = 0 V, Ta = -40 to +85C) Parameter BPF pass band attenuation BPF block band attenuation (1) BPF block band attenuation (2) Symbol GAIN1 Condition 72 to 80 kHz Variable gain amplifier gain: 0 dB 0 to 53 kHz GAIN2 Variable gain amplifier gain: 0 dB 100 to 500 kHz GAIN3 Variable gain amplifier gain: 0 dB 50 -- -- dB MON 50 -- -- dB MON -- -- 3.0 dB MON Min. Typ. Max. Unit Applied Pin
2
3
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MSM9563 User's Manual Chapter 4 ELECTRICAL CHARACTERISTICS
4.6
TIMING DIAGRAM
Address input tSWR1 CS input tSWR1 WR input tWWR tSWR2 Data bus input Figure 4.1 Write Timing tHWR2 tHWR1 tHWR1
Address input tSRD CS input tSRD RD input tWRD tDRD1 tDRD2 tHRD tHRD
Data bus output
Figure 4.2 Read Timing
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MSM9563 User's Manual Chapter 4 ELECTRICAL CHARACTERISTICS
Address input
0x29
0x2A
Data bus input
Layer 4 data tIWRWR2
Layer 4 data
Layer 4 data
CRC result
WR
tIWRRD1
RD
Figure 4.3 Layer 4 CRC mode and Layer 4 VICS mode Timing
Address input
0x3B tIWRWR
0x3C
0x3D
0x38
WR
tIWRRD RD
Figure 4.4 Internal between write and write or between write and read
0x3D 0x3C Address input 0x3B tIWRWR1
0x3D 0x3C 0x3B
WR
Figure 4.5 When 0x3B to 0x3D are continuously written at the same address (This is a rare case)
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MSM9563 User's Manual Chapter 4 ELECTRICAL CHARACTERISTICS
Address input tIRDRD
RD
Figure 4.6 Intarval between read and read
Address signal input
0x00
Data signal input
XXXX01XX
WR input (INTCLR signal)
INT output
tDINTCLR
Figure 4.7 Interrupt CLR Timing
CLR signal tWCLR
Figure 4.8 Clear pulse width
4-7
MSM9563 User's Manual Chapter 4 ELECTRICAL CHARACTERISTICS
4-8
Chapter 5
CONTROL REGISTERS
MSM9563 User's Manual Chapter 5 CONTROL REGISTERS
5. 5.1 5.1.1
CONTROL REGISTERS OPERATING MODE REGISTERS Mode setting of main channel and subchannel
Table 5.1.1 Main channel mode and subchannel mode
Address 0x04
R/W W Initial value
DB7 -- --
DB6 -- --
DB5 -- --
DB4 MOD_ SUB 0
DB3 -- --
DB2 -- --
DB1 -- --
DB0 MOD_ MAIN 1
There are two modes available, namely, the main channel mode in which connection is made to the broadcasting station of the same channel and reception is made in units of a frame (the conventional method), and the subchannel mode in which the tuner is switched intermittently to other channels and reception is made in units of several packets of information. The channel switching mode setting for simultaneously receiving subchannels by switching to high speed subchannel during main channel reception is shown in the following table. Channel switching mode setting for simultaneous reception of main channel and subchannels. Mode MOD_MAIN/SUB MOD_MAIN MOD_SUB MOD_OFF Set value DB4 1 0 1 0 DB0 1 1 0 0 initial setting). Main channel reception mode Subchannel reception mode The mode used for isolating the synchronization circuit after tuner switching until the tuning becomes stable. Description The mode used for subchannel timing extraction (at the time of
5.1.2
Frame format
Table 5.1.2 Frame format
Address 0x1F
R/W W Initial value
DB7 -- -- Frame configuration Format A Format B Format C
DB6 -- --
DB5 -- --
DB4 -- --
DB3 -- --
DB2 -- --
DB1 B1 1
DB0 B0 0
Set value DB1 0 0 1 1 DB0 0 1 0 1
Symbol A0 A1 B C
Remarks
Includes real time information blocks Used in Japan
5-1
MSM9563 User's Manual Chapter 5 CONTROL REGISTERS
Timing interrupt _SUB (R_00)
Bus
Channel connection/ disconnection _SUB (R_04) Clock regeneration _SUB
Timer _SUB
Block synchronization _SUB (L1BF_SUB) Receive RAM switching (R_02)
Tuner Sub station Data reproduction
Receive RAM after first horizontal error correction _SUB
Receive RAM after first horizontal error correction _MAIN
(L1BF)
5-2
Main station Frame memory
Tuner switching _MAIN/SUB
Clock regeneration _MAIN Channel connection/ disconnection _MAIN (R_04)
Block synchronization _MAIN
Frame synchronization _MAIN
Timer _MAIN
Timing interrupt _MAIN (R_00) Tuner MSM9563
Figure 5.1 Main/Subchannel switching receive block diagram
MSM9563 User's Manual Chapter 5 CONTROL REGISTERS
5.1.3
Page mode
Table 5.1.3 Page mode
Address 0x3E
R/W W (Note) Initial value
DB7 -- --
DB6 MAINCH _CLRB 0
DB5 -- --
DB4 MOD_ 0
DB3 CLRMC0 0
DB2 MOD_ PAGE 0
DB1 PAGE1 0
DB0 PAGE0 0
PARITERC2 _PAGE
Note:
The settings MOD_SUB=1 and MOD_MAIN=0 should be made in the register 0x04. By setting the page mode, it is possible to automatically accumulate the received data after the first horizontal error correction in the frame memory. However, the frame synchronization, vertical error correction, and the second horizontal error correction are not made in the page mode. The frame memory can be divided into the receive data accumulation area after first horizontal error correction and the user area, and the sizes of the two areas are variable. DB3: The received packets are written startig from the packet address "0" if CLRMC0_PAGE is set to "1".
Frame memory configuration (page mode) Receive data accumulation area after the first horizontal error correction
User area
Receive data accumulation area after the first horizontal error correction and user area Register 0x3E set value 0x04 0x05 0x06 0x07 Receive data accumulation area after the first horizontal error correction Packets 0 to 31 Packets 0 to 63 Packets 0 to 127 Packets 0 to 271 Packets 32 to 272 Packets 64 to 272 Packets 128 to 272 Not present User area
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MSM9563 User's Manual Chapter 5 CONTROL REGISTERS
5.1.4
Main channel clear bit (MAINCH_CLRB)
This MAINCH_CLRB bit (DB6 of register 0x3E) has been provided to speed up switching to the main channel. When this bit is set to "1" (MAINCH_CLRB, BIT 6 =1), the main channel synchronization, error correction, internal frame memory control section, and interrupt will be reset. However, the parameter setting registers, the counter for synchronization, and the pointer for reading out the frame memory are not cleared. Since the reset condition is retained, after switching the tuner, reset this bit to "0" (MAINCH_CLRB, DB6=0) thereby releasing the reset condition. Thereafter, reception starts even if the register is not set again. Although the frame memory is not cleared, the new receive data will be written over the old ones.
Main channel tuner switching
Main channel clearing R_3E=0x40
Tuner switching
Main channel reset release R_3E=0x00
End
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MSM9563 User's Manual Chapter 5 CONTROL REGISTERS
5.2 5.2.1
INTERRUPT REGISTERS Interrupt register
When an interrupt occurs, a "1" is written in this register and the INT Pin is set to the "0" level. After reading out this register, write a "1" in the corresponding bit of this register to clear the interrupt. Table 5.2.1 Interrupt register
Address
R/W R
DB7
Receive interrupt after the first horizontal error correction _SUB
DB6
DB5
DB4
Receive interrupt after the second horizontal error correction
DB3 --
DB2
DB1
DB0 REAL Packet -- 0
TIMINT_ TIMINT_ SUB MAIN
0x00 W Initial value (1)
Out-of- Receive interrupt synchronization after the first horizontal error interrupt correction _MAIN Clear interruptClear interrupt
Clear interruptClear interruptClear interruptClear interrupt
-- --
0
0
0
0
0
0
DB7: Receive interrupt after the first horizontal error correction_SUB
1: Indicates that a packet was received in a subchannel. 0: There is no interrupt in the subchannels. (2) DB6: TIMINT_SUB
1: Indicates that an interrupt set by the subchannel timer has occurred. 0: There is no interrupt in the subchannels. (3) DB5: TIMINT_MAIN
1: Indicates that an interrupt set by the main channel timer has occurred. 0: There is no interrupt in the main channel. Settings of the registers 0x05, 0x16, 0x17, 0x1D, and 0x1E are necessary to activate the main channel timer interrupt. (4) DB4: Receive interrupt after the second horizontal error correction
1: Indicates that an interrupt of the frame data reception after the second horizontal error correction of the main channel has occurred. 0: There is no interrupt in the main channel. (5) DB2: Out-of-synchronization interrupt
1: Indicates that an interrupt of frame out-of-synchronization has occurred. 0: There is no interrupt in the main channel. (6) DB1: Receive interrupt after the first horizontal error correction_MAIN
1: Indicates that a packet was received in the main channel. 0: There is no interrupt in the main channel.
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MSM9563 User's Manual Chapter 5 CONTROL REGISTERS
(7)
DB0: REAL
This bit is not an interrupt. This bit is cleared simultaneously with the receive interrupt after the first horizontal error correction _MAIN when a "1" is written in DB1. 1: Indicates that the received packet is a REAL packet. 0: The received packet is not a REAL packet.
5.2.2
Interrupt mask
This is a register that controls the interrupts corresponding to the bit numbers of the interrupt register (0x00). Table 5.2.2 Interrupt mask
Address 0x01
R/W W Initial value
DB7 0
DB6 0
DB5 0
DB4 0
DB3 -- --
DB2 0
DB1 0
DB0 -- --
Interrupt mask Interrupt mask Interrupt mask Interrupt mask
Interrupt mask Interrupt mask
1: Interrupt enabled. 0: Interrupt disabled.
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MSM9563 User's Manual Chapter 5 CONTROL REGISTERS
5.3
RECEIVE DATA REGISTERS
When data is received, that fact is reported by generating an interrupt and setting the INT pin to the "0" level, after which the received data should be read out from the receive data port. The receive data ports are the recive port (0x03) after first horizontal error correction from which data should be read out in units of a packet after the first horizontal error correction has been completed, and the receive port (0x38) after second horizontal error correction from which data can be read out in units of a frame after the second horizontal error correction has been completed. Receive port after the first horizontal error correction Since the receive port after the first horizontal error correction is internally separated into one for the main channel and one for the subchnnel, it is necessary to select the required port before reading data. The receive data interrupt after the first horizontal error correction can be set to be enabled or disabled according to the conditions of parity packet, error correction result, service identifier, etc. Receive port after the second horizontal error correction The receive data of the receive port after the second horizontal error correction is reported by an interrupt at the timing of the 13th packet of the next frame. When all the packets of the frame have been received, the vertical error correction would have been completed. However, the vertical error correction would have been omitted when all the packets in the frame have not been received, such as when frame synchronization is entered in the middle of a frame. The second horizontal error correction is carried out for the packet received under frame synchronization and its result is indicated in register 0x37 by dividing it into four groups as the frame synchronization condition. The test settings described later are necessary for reading the received data including the parity packet, and in this case, the reception is reported by an interrupt generated at the timing of the 15th packet. Before reading data from the receive port after the second horizontal error correction, it is necessary to set the address pointer (0x3B to 0x3D) and the access mode (0x39) of the frame memory. The address pointer consists of the packet number and the byte number, and specifies the starting address of reading. The setting of the access mode consists of setting the modes of horizontal/vertical reading direction, the parity read, etc., of the frame memory. The frame data (for example, 190x24 bytes) of the receive port after the second horizontal error correction can be read out either successively or intermittently.
5.3.1
Switching the receive port after the first horizontal error correction
Table 5.3.1 Switching the receive port after the first horizontal error correction
Address 0x02
R/W W Initial value
DB7 -- --
DB6 -- --
DB5 -- --
DB4 -- --
DB3 -- --
DB2 -- --
DB1 -- --
DB0 MAINB/ SUB 0
Since the receive port after the first horizontal error correction is connected to the 36-byte RAM for the main channel (LIBF) and the RAM for the subchannel (LIBF_SUB) (see Figure 5.1), it is necessary to switch between them according to the content of the receive interrupt register. When a value is set in this register, the RAM address pointer is reset and it is possible to read from the leading byte.
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MSM9563 User's Manual Chapter 5 CONTROL REGISTERS
DB0: MAINB/SUB 1: The receive port after the first horizontal error correction is connected to the RAM (LIBF_SUB) for the subchannel. 0: The receive port after the first horizontal error correction is connected to the RAM (LIBF) for the main channel.
5.3.2
Receive port after the first horizontal error correction and the receive data format
Table 5.3.2.1 Receive port after the first horizontal error correction
Address 0x03
R/W R W Initial value
DB7 B7 B7 --
DB6 B6 B6 --
DB5 B5 B5 --
DB4 B4 B4 --
DB3 B3 B3 --
DB2 B2 B2 --
DB1 B1 B1 --
DB0 B0 B0 --
Read This is the one-packet receive data port after the first horizontal error correction. The read address of the internal RAM is "0x00" when a receive interrupt after the first horizontal error correction has occurred. When this port is read, the read address is automatically incremented to the next read address and hence it is possible to carry out successive reads. Write For testing only. Writing to this port is prohibited during normal use. Table 5.3.2.2 Receive data format after the first horizontal error correction Bit No. DB7 BYTE0 BYTE1 BYTE2 ** ** BYTE23 BYTE24 BYTE25 BYTE26 BYTE35 ** CRC0 VICSRDY DB6 ERC0 PARITY ** ** First horizontal correction receive data No. 21 CRC PARITY PARITY PARITY ** CRC DB5 RECCRC INT0 DB4 FSYNC 0 DB3 BSYNC 0 DB2 BICDET FNCHG DB1 BIC1 FRNO1 DB0 BIC0 FRNO0
First horizontal correction receive data No. 0
Byte No.
BYTE0 and BYTE1 of the receive RAM data after the first horizontal error correction indicate the status of the received packet, BYTE2 to BYE23 are data, and BYTE 24 to BYTE 35 are the CRC/ parity data. BYTE24 to BYTE35 are for testing and cannot be read out.
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BYTE0 (1) DB7: CRC0 1: Indicates that there is an error in the CRC of the packet after the first horizontal error correction. 0: Indicates that the CRC of the packet is normal after the first horizontal error correction. (2) DB6: ERC0
1: Indicates that there is an error in the correction result of the packet after the first horizontal error correction. 0: Indicates that the correction result of the packet is normal after the first horizontal error correction. (3) DB5: RECCRC
1: Indicates that there is an error in the CRC of the received packet before error correction. 0: Indicates that the CRC of the received packet is normal before error correction. (4) DB4: FSYNC
1: Indicates that the received packet is in a frame synchronization state. 0: Indicates that the received packet is in a frame out-of-synchronizaiton state. (5) DB3: BSYNC
1: Indicates that the received packet is in a block synchronization state. 0: Indicates that the received packet is in a block out-of-synchronization state. (6) DB2 to DB0: BIC Data
Indicate the detection condition of the block identification code (BIC). DB2 1 1 1 1 0 BYTE1 (1) DB7: VICSRDY 1: Indicates that the received packet is a VICS packet. 0: Indicates that the received packet is not a VICS packet. (2) DB6: PARITY DB1 0 0 1 1 -- DB0 0 1 0 1 -- BIC No. 1 2 3 4
Not detected
This bit indication is made only in a frame synchronization state. 1: Indicates that the received packet is a parity packet. 0: Indicates that the received packet is not a parity packet.
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(3)
DB5: INT0
This bit indicates the receive interrupt after the first horizontal error correction. Even though this bit indication is made in the reception condition after the second horizontal correction, it is possible to confirm that reading has been made when a receive interrupt has occurred after the first horizontal error correction. 1: Indicates that the received packet is one in which the receive interrupt occurred after the first horizontal error correction. 0: Indicates that the received packet is one in which no receive interrupt occurred after the first horizontal error correction. (4) (5) DB4, DB3: 0 DB2: FNCHG
This bit indication is made only in a frame synchronization state. 1: Indicates that the packet is one given in the following table. 0: Indicates that the packet is one other than those indicated in the following table. Frame format Format B Packet with a block number of 0, 13, 136, or 149. Note: or 190. Format A1, A0 Packet with a block number of 0, 60, 130,
The packet numbers are expressed in this manual as 0 to 271 (A1: 0 to 283).
(6)
DB1, DB0: FRNO1, FRNO0
These bit indications are made only in a frame synchronization state. These bits indicate that the packet is one with the block numbers given in the following table. Frame format DB1 0 0 1 1 DB0 0 1 0 1 Format B Packet with a block number of 0 to 12. Packet with a block number of 13 to 135. Packet with a block number of 149 to 271. Format A1, A0 Packet with a block number of 0 to 59 Packet with a block number of 60 to 129 A0 A1 Note: Packet with a block number of 190 to 271 Packet with a block number of 190 to 283
Packet with a block number of 136 to 148. Packet with a block number of 130 to 189
The packet numbers are expressed in this manual as 0 to 271 (A1: 0 to 283).
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5.3.3
Conditions of receive interrupt after the first horizontal error correction
Table 5.3.3.1 Conditions of receive interrupt after the first horizontal error correction
Address 0x34
R/W W Initial value
DB7 MOD_ FSYNC 0
DB6 MOD_CH OFFDET 0
DB5 MOD_ INT0 1
DB4 MOD_ ERC0 0
DB3 MOD_ PARIT0 0
DB2 MOD_ BICDET0 0
DB1 MOD_ SI 0
DB0 SISEL 0
This is the register for setting the conditions of interrupt after the first horizontal error correction. During the initial setting, all packets received in a synchronization state are set to generate an interrupt. It is possible to specify the four types of interrupt conditions shown in the following table regarding good (error-free) packets, frame synchronization, and specified SI (service identifier). It is possible to specify 16 types of service identifiers (SI0 to SI15) for which it is necessary to set this register and the register 0x35. The packets that generated an interrupt after the first horizontal error correction are recorded in the frame memory (bit 3 of byte 1) after the second horizontal error correction. Therefore, there is no need to read out good packets after the first horizontal error correction after the second horizontal error correction. Table 5.3.3.2 Interrupt conditions after the first horizontal error correction Interrupt condition 1 2 3 4 All packets received in a synchronization state Good packets received in a synchronization state Packets in a frame synchronization state (including bad packets) Good packets with the specified service identifier SI. 0xE2 0xE3 SI0 to SI7 written in units of a bit SI8 to SI15 written in units of a bit Set value of 0x34 0x20 0x70 0xA0 -- -- -- Set value of 0x35
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5.3.4
Specification of SI (Service identifier)
Table 5.3.4 SI Specification
Address
R/W W (Note 1)
DB7 SI7 SI15 1
DB6 SI6 SI14 1
DB5 SI5 SI13 1
DB4 SI4 SI12 1
DB3 SI3 SI11 1
DB2 SI2 SI10 1
DB1 SI1 SI9 1
DB0 SI0 SI8 1
0x35
W (Note 2) Initial value
Note 1: The setting SISEL=0 should have been made in the register 0x34. Note 2: The setting SISEL=1 should have been made in the register 0x34. This is the register for setting the service identifier SI which is an interrupt condition after the first horizontal error correction. It is possible to specify multiple service identifiers by setting "1" to the bits corresponding to the required service identifiers among the 16 types SI0 to SI15 in the above table.
5.3.5
Receive port after the second horizontal error correction
Table 5.3.5 Receive data port after the second horizontal error correction
Address 0x38
R/W R W Initial value
DB7 B7 B7 --
DB6 B6 B6 --
DB5 B5 B5 --
DB4 B4 B4 --
DB3 B3 B3 --
DB2 B2 B2 --
DB1 B1 B1 --
DB0 B0 B0 --
The receive port after the second horizontal error correction is connected to the frame memory. It is possible to read the frame memory successively since the frame memory address is incremented automatically whenever this port is read. It is also possible to read this port starting from any required address. Packets in a frame synchronization state are accumulated in the frame memory. When the reception of one full frame is completed, the vertical error correction and the second horizontal error correction are made, and the receive interrupt after the second horizontal error correction occurs at the timing of the 13th packet in the next frame. Although it is possible to receive from the middle of a frame, the vertical error correction will be omitted in that case. The frame synchronization state is indicated in the register 0x37 by dividing it into four groups. On the other hand, it is also possible to know this from the status indication byte at the beginning of each packet. The volume of data in the frame memory is; * 24x190 bytes in the case of 4-layer data including packet status indication; * 36x273 bytes in the case of data including parity, etc. See the data format of the receive frame memory after the second horizontal error correction in Section 5.3.6 for the detailed contents of data. CAUTION: The frame memory has segments that are prohibited from being accessed. See Figure 5.3 for details.
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Figure 5.3 Access prohibited segments of the frame memory (R_38) (1) (2) The frame memory access inhibited time occurs when the intersection of the packet number and the byte number correspond to the hatched parts in the follwoing figure. It is possible to know the packet number and the byte number by reading out the registers R_1E, R_1D, R_16, and R_17. (See the precautions to be taken at the time of reading out the packet number and byte number given in the next page.)
Packet number 270 271 0 1 2
, ,
0 1 2 3 4 33 34 35 11 12 13 Receive interrupt after the second horizontal error correction 270 271 0
Byte number
Memory access inhibited segment due to vertical and second horizontal error corrections
Memory access inhibited segment due to the first horizontal error correction (when using only the main channel) Memory access inhibited segment due to the first horizontal error correction (when receiving by switching between main and sub channels)
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Precautions in reading the packet number and byte number
Since the microcontroller and data clocks are not mutually synchronized, it is possible that wrong values are read out when reading out is made when the packet number or the byte number is changing. Therefore, it is necessary to read them twice successively and use only after confirming that there is a match between the two successive values.
(1) Memory access is possible for about 16msec after the timing interrupt (2) Checking the byte number and the packet number of Figure 5.3
Timing interrupt setting
Timing interrupt setting
Second horizontal correction receive interrupt
Second horizontal correction receive interrupt
Timing interrupt setting _MAIN R_05=0x01
FLG_ERC2=1
Byte number 2 setting _MAIN R_16=0x10 R_17=0x00
Timing interrupt setting
FLG_ERC2==1 Timing interrupt setting _MAIN for each packet R_1E=0x02 Byte number read _MAIN
Timing interrupt EN_MAIN R_05=0x02 First read = second read
Timing interrupt setting 1 < Byte number < (34-n)
Access possible
Access possible
n is the time of accessing the memory
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5.3.6
Data configuration of the receive frame memory after the second horizontal error correction
Table 5.3.6.1 Receive frame memory data configuration after the second horizontal error correction Byte No.
Packet No. 0 ** 189 190 ** 271 272 (1) (2)
0 Reception status 0 Reception status 0 Reception status 0 Reception status 0 -- ** DB7: CRC0 DB6: ERC0 **
1 Reception status 1 Reception status 1 Reception status 1 Reception status 1 -- ** DB7 **
2 Data 0 ** Data 0 Vertical correction parity Vertical correction parity Vertical correction result 0 ** DB6 ERC0 PARITY DB5
** ** ** ** Vertical correction parity Vertical correction parity ** ** DB4 FSYNC CRC2
23 Data 21 ** Data 21 Vertical correction parity Vertical correction parity ** ** DB3 BSYNC ERC2
24 CRC/ PARITY CRC/ PARITY Vertical correction parity Vertical correction parity ** ** DB2 BICDET FNCHG **
** ** ** ** Vertical correction parity Vertical correction parity ** ** DB1 BIC1 FRNO1
35 PARITY ** PARITY Vertical correction parity Vertical correction parity Vertical correction result 33 ** DB0 BIC0 FRNO0
The frame memory data configuration is shown in Table 5.3.6.1. The data consists of 190 data packets, 82 parity packets, and one vertical correction result packet. Normally, the second horizontal error correction of the parity packets 190 to 271 are omitted. To read packets including the parity packets after the second horizontal error correction, it is necessary to set and carry out the error correction separately for testing purposes. The leading two bytes of each packet indicate the reception status. The details of the reception status are shown in Table 5.3.6.2. Table 5.3.6.2 Reception status after the second horizontal error correction
Reception status 0 Reception status 1
CRC0 VICSRDY
RECCRC INT0
Reception status 0 The reception status 0 is equal to the contents of BYTE0 received after the first horizontal error correction.
1: Indicates that there is an error in the CRC of the packet after the first horizontal error correction. 0: Indicates that the CRC of the packet is normal after the first horizontal error correction.
1: Indicates that there is an error in the correction result of the packet after the first horizontal error correction. 0: Indicates that the correction result of the packet is normal after the first horizontal error correction.
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(3)
DB5: RECCRC
1: Indicates that there is an error in the CRC of the received packet before error correction. 0: Indicates that the CRC of the received packet is normal before error correction. (4) DB4: FSYNC
1: Indicates that the received packet is in a frame synchronization state. 0: Indicates that the received packet is in a frame out-of-synchronizaiton state. (5) DB3: BSYNC
1: Indicates that the received packet is in a block synchronization state. 0: Indicates that the received packet is in a block out-of-synchronization state. (6) DB2 to DB0: BIC Monitor
Indicate the detection condition of the block identification code (BIC). DB2 1 1 1 1 0 Reception status 1 (1) DB7: VICSRDY 1: Indicates that the received packet after the second horizontal error correction is a VICS packet. 0: Indicates that the received packet after the second horizontal error correction is not a VICS packet. (2) DB6: PARITY DB1 0 0 1 1 -- DB0 0 1 0 1 -- BIC No. 1 2 3 4
Not detected
This bit indication is made only in a frame synchronization state. 1: Indicates that the received packet is a parity packet. 0: Indicates that the received packet is not a parity packet. (3) DB5: INT0
1: Indicates that the received packet is the one in which the receive interrupt occurred after the first horizontal error correction. It is not necessary to read this if the reading has already been done during the reception after the first horizontal error correction. 0: Indicates that the received packet is one in which no receive interrupt occurred after the first horizontal error correction.
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(4)
DB4: CRC2
1: Indicates that there is an error in the CRC of the packet after the second horizontal error correction. 0: Indicates that the CRC of the packet is normal after the second horizontal error correction. (5) DB3: ERC2
1: Indicates that there is an error in the correction result of the packet after the second horizontal error correction. 0: Indicates that the correction result of the packet is normal after the second horizontal error correction. Note: CRC2=ERC2=0 is necessary for the packet to be good (error-free). (6) DB2: FNCHG
This bit indication is made only in a frame synchronization state. 1: Indicates that the packet is one with a block number of 1, 14, 137, or 150 in the case of the frame format B, and with a block numaber of 1, 61, 131, or 191 in the case of the frame formats A0 and A1. 0: Indicates that the packet is one other than the above. (7) DB1, DB0: FRNO1, FRNO0
These bit indications are made only in a frame synchronization state. These bits indicate that the packet is one with the block numbers given in the following table. Frame format DB1 0 0 1 1 DB0 0 1 0 1 Format B Packet with a block number of 0 to 12. Packet with a block number of 13 to 135. Packet with a block number of 149 to 271. Format A1, A0 Packet with a block number of 0 to 59 Packet with a block number of 60 to 129 A0 A1 Note: Packet with a block number of 190 to 271 Packet with a block number of 190 to 283
Packet with a block number of 136 to 148. Packet with a block number of 130 to 189
The packet numbers are expressed in this manual as 0 to 271 (A1: 0 to 283).
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5.3.7
Setting the receive frame memory access mode after the second horizontal error correction
Table 5.3.7 Frame memory access mode
Address 0x39
R/W W Initial value
DB7 BANK CONT1 0
DB6 BANK CONT0 0
DB5 VLBCNT 0
DB4 PCTL1 BL2 0
DB3 VBACK 0
DB2 LBACK1 1
DB1 LBACK0 0
DB0 LSTART 0
This is the register for setting the access mode so that reading can be done efficiently when reading the frame memory successively. (1) DB7, DB6: BANK1, BANK0
These bits are for making settings for testing purposes. Normally use with the settings of DB7=DB6=0. (2) DB5: VLBCNT
1: The frame memory is read in the vertical direction (in an ascending order of the packet number with the byte number being kept fixed). 0: The frame memory is read in the horizontal direction (in an ascending order of the byte number with the packet number being kept fixed). The packet number is incremented by 1 when the byte number reaches that specified by LBACK0 and LBACK1. (3) DB4: PCTL1BL2
The readable frame memory address (packet number) is selected from the registers 0x3C and 0x3D. 1: Enables the MSM9563 to read the address (packet number) of the receive data packet that is being written. 0: Enables an external microcontroller to read the address (packet number) of the receive data packet that is being accessed. (4) DB3: VBACK
1: When the packet number becomes 272, the next packet number will be reset to 0. For testing purposes only. 0: When the packet number becomes 189, the next packet number will be reset to 0. (5) DB2, DB1: LBACK1, LBACK0
The next byte number is reset to the byte number specified by LSTART when the current byte number becomes the returning byte number given in the following table. LBACK1 LBACK0 Returning byte No. 0 0 1 1 (6) DB0: LSTART 0 1 0 1 1 2 23 35
1: The next byte number is reset to 2 when the current byte number becomes equal to the value specified by LBACK0 and LBACK1. 0: The next byte number is reset to 0 when the current byte number becomes equal to the value specified by LBACK0 and LBACK1.
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5.3.8
Receive frame memory pointer after the second horizontal error correction
Table 5.3.8.1 Frame memory address (1/3)
Address 0x3B
R/W R/W Initial value
DB7 -- --
DB6 -- --
DB5 EXT BYTE5 0
DB4 EXT BYTE4 0
DB3 EXT BYTE3 0
DB2 EXT BYTE2 0
DB1 EXT BYTE1 0
DB0 EXT BYTE0 0
Table 5.3.8.2 Frame memory address (2/3) Address R/W R (Note 1) R 0x3C (Note 2) W Initial value DB7 EXT PCT7 L1BF PCT7 EXT PCT7 0 DB6 EXT PCT6 L1BF PCT6 EXT PCT6 0 DB5 EXT PCT5 L1BF PCT5 EXT PCT5 0 DB4 EXT PCT4 L1BF PCT4 EXT PCT4 0 DB3 EXT PCT3 L1BF PCT3 EXT PCT3 0 DB2 EXT PCT2 L1BF PCT2 EXT PCT2 0 DB1 EXT PCT1 L1BF PCT1 EXT PCT1 0 DB0 EXT PCT0 L1BF PCT0 EXT PCT0 0
Note 1: The setting PCTL1BL2=0 should have been made in the register 0x39. Note 2: The setting PCTL1BL2=1 should have been made in the register 0x39 (used in the page mode). Table 5.3.8.3 Frame memory address (3/3) Address R/W R (Note 1) R 0x3D (Note 2) W Initial value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DB7 MEMSTAT DB6 -- DB5 -- DB4 -- DB3 -- DB2 -- DB1 -- DB0 EXT PCT8 L1BF PCT8 EXT PCT8 0
Note 1: The setting PCTL1BL2=0 should have been made in the register 0x39. Note 2: The setting PCTL1BL2=1 should have been made in the register 0x39. Write Before reading from the receive port after the second horizontal error correction of the register 0x38, it is necessary to set the packet number and the byte number in the register. Specify the packet number of the starting byte and the starting byte number of the data to be read according to Table 5.3.6.1 "Data configuration of the receive frame memory after the second horizontal error correction". Thereafter successive reads will be possible according to the "Access mode setting of the receive frame memory after the second horizontal error correction".
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Read (PCTL1BL2=0) It is possible to know the byte number and the packet number of the data to be read next by reading these registers 0x3B, 0x3C, and 0x3D. However, it is necessary to set PCTL1BL2 of the register 0x39 to "0". Before reading these registers. Read (PCTL1BL2=1) The registers 0x3C and 0x3D indicate the frame memory address (packet number) of the data packet received after the first horizontal error correction, which is to be written next.
5.3.9
Reception status of the receive frame memory after the second horizontal error correction
Table 5.3.9 Frame synchronization status
Address
R/W R
DB7 BANK -- --
DB6 -- BANKLT _CLR 0
DB5 --
DB4 --
DB3 BANK BANK 0
DB2 BANK BANK 0
DB1 BANK BANK 0
DB0 BANK BANK 0
_ERCFR0 _ERCFR1 _ERCFR2 _ERCFR3 0x37 W Initial value Read (1) DB0 to DB3: BANK_ERCFR3 to BANK_ERCFR0 MOD_ EXPCTCNT EXERC 0 0 STARTB _ERCFR0 _ERCFR1 _ERCFR2 _ERCFR3
When data is read after a receive interrupt after the second horizontal error correction, these four bits indicate whether the four packet groups listed in the following table are in a frame synchronization state or not. The vertical error correction is carried out only when DB0=DB1=DB2=DB3=1. The second horizontal error correction is carried out only for the concerned packet group among DB0 to DB3. However, a separate setting and implementation of error correction for testing are required in the case of parity packets. Frame format Format B DB3 DB2 DB1 DB0 Packet with a block number of 0 to 12. Packet with a block number of 13 to 135. Packet with a block number of 149 to 271. Format A1, A0 A0, A1 Packet with a block number of 0 to 59 A0, A1 Packet with a block number of 60 to 129 A0 A1 Note: (2) Packet with a block number of 190 to 271 Packet with a block number of 190 to 283
Packet with a block number of 136 to 148. A0, A1 Packet with a block number of 130 to 189
The packet numbers are expressed in this manual as 0 to 271 (A1: 0 to 283). DB7: BANK
For testing purposes only. Write This register is for making settings for testing and writing is prohibited under normal use.
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5.4
TIMING INTERRUPT REGISTERS
There are the two timing interrupts of TIMINT_MAIN which operates in synchronization with the main channel and the timing interrupt TIMINT_SUB which operates in synchronization with the subchannel. The block diagram of TIMINT_MAIN is shown in Figure 5.4.1. The timing interrupt TIMINT_MAIN occurs when the packet number and byte number of the main channel match with the set interrupt timing. The block diagram of TIMINT_SUB is shown in Figure 5.4.2. The timing interrupt TIMINT_SUB occurs when the packet number, byte number, and frame number of the subchannel match with the set interrupt timing. It is possible to set TIMINT_SUB at intervals of 0 to 15 frames. It is necessary to carry out initial setting of the timing of the packet number and frame number when synchronized with a subchannel.
Bus
Setting of FRCK_MAIN and BCK_MAIN Timing interrupt setting register
TIMINTEN_MAIN
Compare & enable Packet and byte counter Data clock _MAIN
TIMINT_MAIN
Figure 5.4.1 TIMINT_MAIN block diagram
Bus
Setting of INTFNCK_SUB, INTFRCK_SUB, and INTBCK_SUB
TIMINTEN_SUB Timing interrupt setting register Compare & enable Frame, packet, and byte counter TIMINT_SUB
Setting of MAXFNCK_SUB, FNCK_SUB, and FRCK_SUB
BRK_SUB Adjustment
Data clock _SUB
Figure 5.4.2 TIMINT_SUB block diagram
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5.4.1
Timing interrupt mode
Since some of the interrupt timing registers have been mapped to the same address, this register controls their selection and timing enable conditions. Table 5.4.1 Interrupt timing mode
Address 0x05
R/W W Initial value
DB7 -- --
DB6 _SUB 0
DB5 _SUB 0
DB4 SETCK0 _SUB 0
DB3 RDBSCK _SUB 0
DB2 -- --
DB1 TIMINT 0
DB0 SETINT 0
TIMINTEN SETCK1
EN_MAIN CK_MAIN
(1)
DB6: TIMINTEN_SUB
1: Activates the timing interrupt of the subchannel. 0: Disables the timing interrupt operation of the subchannel Set the interrupt timing after making this bit "0" and change this bit to "1" after the setting is completed. (2) DB5, DB4: SETCK1_SUB, SETCK0_SUB DB4 1 0 1 0 Set mode SETMAX_SUB SETINTCK_SUB SETTIMCK_SUB -- Description Enables the setting of a count value of the maximum number of frames in the register 0x09. 1 0 0 (3) Enables the setting of the interrupt timing value in the registers 0x06 to 0x09. Enables the setting of the initial value of the timer counter in the registers 0x08 to 0x09. --
DB5 1
DB3: RDBSCK_SUB
1: Makes it possible to read the block counter value latched immediately before block synchronization of the subchannel. 0: Makes it possible to read the block counter value of the subchannel. (4) DB1: TIMINTEN_MAIN
1: Activates the timing interrupt of the main channel. 0: Disables the timing interrupt operation of the main channel. Set the interrupt timing after setting this bit to "0", and set this bit to "1" after the interrupt timing setting is completed. (5) DB0: SETINTCK_MAIN
1: Makes it possible to write the main channel interrupt timing values in the registers 0x16, 0x17, 0x1D, and 0x1E. 0: It is not possible to write the main channel interrupt timing values in the registers.
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5.4.2
Interrupt byte number specification (main channel)
Table 5.4.2.1 Interrupt timing _MAIN (byte number 1/2)
Address
R/W R W (Note 1) Initial value
DB7 BCK7
DB6 BCK6
DB5 BCK5
DB4 BCK4
DB3 BCK3
DB2 BCK2 -- 0
DB1 BCK1 -- 0
DB0 BCK0 -- 0
0x16
INTBCK7 INTBCK6 INTBCK5 INTBCK4 INTBCK3 0 0 0 0 0
Note 1: The setting SETINTCK=1 should have been made in the register 0x05. Table 5.4.2.2 Interrupt timing _MAIN (byte number 2/2) Address R/W R 0x17 W (Note 1) Initial value -- -- -- -- -- -- -- 0 DB7 -- -- DB6 -- -- DB5 -- -- DB4 -- -- DB3 -- -- DB2 -- -- DB1 -- -- DB0 BCK8 INTBCK8
Note 1: The setting SETINTCK=1 should have been made in the register 0x05. Read BCK8 (MSB) to BCK0 (LSB) indicate the bit numbers of the packet being received. The upper 6 bits indicate the byte number. Write This is the register for specifying the main channel interrupt byte number. Before setting this register, set TIMINTEN_MAIN=1 and SETINTCK=1 in the register 0x05. This matches with the received data byte number in a block synchronization state. The interrupt occurs at the leading part of a change in the byte number. Specify bytes 0 to 35 using the 6 bits INTBCK3 to INTBCK8.
5.4.3
Interrupt packet number specification (main channel)
Table 5.4.3.1 Interrupt timing _MAIN (packet number 1/2)
Address
R/W R W (Note 1) Initial value
DB7 FRCK7 INT FRCK7 0
DB6 FRCK6 INT FRCK6 0
DB5 FRCK5 INT FRCK5 0
DB4 FRCK4 INT FRCK4 0
DB3 FRCK3 INT FRCK3 0
DB2 FRCK2 INT FRCK2 0
DB1 FRCK1 INT FRCK1 0
DB0 FRCK0 INT FRCK0 0
0x1D
Note 1: The setting SETINTCK=1 should have been made in the register 0x05.
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Table 5.4.3.2 Interrupt timing _MAIN (packet number 2/2) Address R/W R 0x1E W (Note 1) Initial value 0 0 0 0 -- -- DB7 _SUB -- -- -- -- -- -- INT 0 INT 0 ALLFRCKTIM FRCK8 DB6 DB5 DB4 DB3 -- DB2 -- DB1 -- DB0 FRCK8
ACTMC0 ACTMC2 ACTMC1 ACTMC0
Note 1: The setting SETINTCK=1 should have been made in the register 0x05. Read FRCK8 (MSB) to FRCK0 (LSB) indicate the packet number of the packet being received. Write This is the register for specifying the main channel interrupt packet number. Timing interrupts occur at all packets when the setting ALLFRCKTIM=1 is made. Before setting this register, set TIMINTEN_MAIN=0 and SETINTCK=1 in the register 0x05. This matches with the packet number of received data in a frame synchronization state.
5.4.4
Interrupt byte number specification (subchannel)
Table 5.4.4.1 Interrupt timing _SUB (byte number 1/2)
Address
R/W R (Note 1) R
DB7 _SUB BCK7 _SUB _SUB 0
DB6 _SUB BCK6 _SUB _SUB 0
DB5 _SUB BCK5 _SUB _SUB 0
DB4 _SUB BCK4 _SUB _SUB 0
DB3 _SUB BCK3 _SUB _SUB 0
DB2 _SUB BCK2 _SUB -- 0
DB1 _SUB BCK1 _SUB -- 0
DB0 _SUB BCK0 _SUB -- 0
PRE_BCK7 PRE_BCK6 PRE_BCK5 PRE_BCK4 PRE_BCK3 PRE_BCK2 PRE_BCK1 PRE_BCK0
0x06
(Note 2) W (Note 3) Initial value
INTBCK7 INTBCK6 INTBCK5 INTBCK4 INTBCK3
Note 1: The setting RDBSCK_SUB=0 (R_05[DB3]=0) should have been made in the register 0x05. Note 2: The setting RDBSCK_SUB=1 (R_05[DB3]=1) should have been made in the register 0x05. Note 3: The setting SETINTCK_SUB (R_05[DB4]=0, R_05[DB5]=1) should have been made in the register 0x05.
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Table 5.4.4.2 Interrupt timing _SUB (byte number 2/2) Address R/W R (Note 1) R 0x07 (Note 2) W (Note 3) Initial value -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DB7 -- DB6 -- DB5 -- DB4 -- DB3 -- DB2 -- DB1 -- DB0 PRE_BCK8 _SUB BCK8 _SUB INTBCK8 _SUB 0
Note 1: The setting RDBSCK_SUB=0 (R_05[DB3]=0) should have been made in the register 0x05. Note 2: The setting RDBSCK_SUB=1 (R_05[DB3]=1) should have been made in the register 0x05. Note 3: The setting SETINTCK_SUB (R_05[DB4]=0, R_05[DB5]=1) should have been made in the register 0x05. Read (RDBSCK=1) BCK8_SUB (MSB) to BCK0_SUB (LSB) indicate the bit numbers of the packet being received. The upper 5 bits indicate the byte number. Read (RDBSCK=0) BCK8_SUB (MSB) to BCK0_SUB (LSB) indicate the bit numbers of the packet immediately before the subchannel enters block synchronization. Write (SETINTCK_SUB) This is the register for specifying the subchannel interrupt byte number. Before setting this register, make the setting of SETINTCK_SUB in the register 0x05. This matches with the byte number of received data in a block synchronization state. The interrupt occurs at the leading part of a change in the byte number. Specify bytes 0 to 35 using the 6 bits INTBCK3 to INTBCK8.
5.4.5
Interrupt packet number setting (subchannel)
Table 5.4.5 Interrupt timing setting _SUB (packet number)
Address
R/W R W
DB7 FRCK7 _SUB FRCK7 _SUB _SUB 0
DB6 FRCK6 _SUB FRCK6 _SUB _SUB 0
DB5 FRCK5 _SUB FRCK5 _SUB _SUB 0
DB4 FRCK4 _SUB FRCK4 _SUB _SUB 0
DB3 FRCK3 _SUB FRCK3 _SUB _SUB 0
DB2 FRCK2 _SUB FRCK2 _SUB _SUB 0
DB1 FRCK1 _SUB FRCK1 _SUB _SUB 0
DB0 FRCK0 _SUB FRCK0 _SUB _SUB 0
0x08
(Note 1) W (Note 2) Initial value
INT FRCK7 INT FRCK6 INT FRCK5 INT FRCK4 INT FRCK3 INT FRCK2 INT FRCK1 INT FRCK0
Note 1: The setting SETTIMCK_SUB (R_05[DB4]=1, R_05[DB5]=0) should have been made in the register 0x05. Note 2: The setting SETINTCK_SUB (R_05[DB4]=0, R_05[DB5]=1) should have been made in the register 0x05.
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Read FRCK8_SUB (MSB) to FRCK0_SUB (LSB) indicate the packet number of the packet being received. (FRCK8_SUB is allocated to DB0 of the register 0x09.) Write (FRCK8_SUB to FRCK0_SUB) This is the register for specifying the initial value of the packet number in the subchannel packet counter. Since the subchannel does not have a built-in frame synchronization circuit, it is necessary for the user to set the packet number. To obtain the packet number, achieve frame synchronization temporarily with the main channel, and write that packet number. (FRCK8_SUB is allocated to DB0 of the register 0x09.) Write (INTFRCK0_SUB to INTFRCK8_SUB) This is the register for specifying the interrupt packet number of the subchannel. Timing interrupts occur at all packets if the setting INTALLFRCK_SUB=1 (register 0x09) is made. Carry out the setting of SETINTCK_SUB in the register 0x09 before setting this register. (INTFRCK8_SUB is allocated to DB0 of the register 0x09.)
5.4.6
Interrupt frame number setting (subchannel)
Table 5.4.6 Interrupt timing setting _SUB (frame interval)
Address
R/W R W
DB7 -- -- -- -- --
DB6 -- -- -- -- --
DB5 -- --
DB4 FNCK3 _SUB FNCK3 _SUB
DB3 FNCK2 _SUB FNCK2 _SUB _SUB _SUB 0
DB2 FNCK1 _SUB FNCK1 _SUB _SUB _SUB 0
DB1 FNCK0 _SUB FNCK0 _SUB _SUB _SUB 0
DB0 FNCK8 _SUB FNCK8 _SUB _SUB -- 0
0x09
(Note 1) W (Note 2) W (Note 3) Initial value 0 _SUB --
INT ALLFRCK INT FNCK3 INT FNCK2 INT FNCK1 INT FNCK0 INT FNCK8 _SUB _SUB 0 MAX FNCK3MAX FNCK2MAX FNCK1MAX FNCK0
Note 1: The setting SETTIMCK_SUB (R_05[DB4]=1, R_05[DB5]=0) should have been made in the register 0x05. Note 2: The setting SETINTCK_SUB (R_05[DB4]=0, R_05[DB5]=1) should have been made in the register 0x05. Note 3: The setting SETMAX_SUB (R_05[DB4]=1, R_05[DB5]=0) should have been made in the register 0x05. Read (FNCK0 to FNCK3) FNCK8 (MSB) to FNCK0 (LSB) indicate the frame number being counted. Write (FRCK0_SUB to FRCK3_SUB) This is the register for specifying the initial value of the frame number in the 4-bit frame number counter of the subchannel. The 4-bit frame number counter is one for generating subchannel timing interrupts at intervals of 0 to 15 frames. The frame interval is specified by MAXFNCK0_SUB to MAXFNCK3_SUB.
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Write (INTFNCK0_SUB to INTFNCK3_SUB) This is the register for specifying the subchannel interrupt frame number. The range of setting is 0 to 15. Carry out the settings of TIMINTEN_SUB and SETINTCK of the register 0x05 before setting this register. Write (MAXFNCK0_SUB to MAXFNCK3_SUB) This is the register for setting the maximum value of the frame number counter. The range of setting is 0 to 15. When the frame number counter reaches the set value, it is reset to "0" and continues counting.
5.4.7
Clock timing adjustment (subchannel)
Table 5.4.7 Subchannel BCK adjustment
Address 0x0A
R/W W Initial value
DB7 -- --
DB6 -- --
DB5 -- --
DB4 -- --
DB3 BCKINC _SUB 0
DB2 B2 0
DB1 B1 0
DB0 B0 0
The subchannel packet interval is adjusted in units of a bit. When intermittent reception is being made at intervals of several frames, this function enables the accurate setting of the position of the packet to be received next. The range of adjustment at a time is 7 bits. Carry out this adjustment at the most once per packet when no reception is being made. The number of bits of adjustment required is the difference between "16" and the value of the registers 0x06 to 0x07 when a subchannel packet is received. (1) DB3: BCKINC_SUB
1: The adjustment is made in the negative direction by the number of bits set in DB0 to DB2. 0: The adjustment is made in the positive direction by the number of bits set in DB to DB2. (2) DB0 to DB2: B0 to B2
These specify the range of adjustment (in number of bits). The maximum value is 7 bits.
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5.5 5.5.1
CLOCK REGENERATION REGISTERS Fixed phase
Table 5.5.1 Fixed phase adjustment
Address 0x0B
R/W W Initial value
DB7 -- --
DB6 B6 0
DB5 B5 0
DB4 B4 0
DB3 B3 0
DB2 B2 0
DB1 B1 0
DB0 B0 0
The phase of the regenerated data clock is adjusted. Use with the initial value left unchanged.
5.5.2
Integration constant before synchronization
Table 5.5.2 Integration constant before synchronization
Address 0x0C
R/W W Initial value
DB7 -- --
DB6 -- --
DB5 -- --
DB4 -- --
DB3 B3 0
DB2 B2 0
DB1 B1 1
DB0 B0 0
This register specifies the number of times of extracting the timing necessary for carrying out phase control before block synchronization. Specify "6" (0x06) as a typical setting value.
5.5.3
Integration constant after synchronization
Table 5.5.3 Integration constant after synchronization
Address 0x0D
R/W W Initial value
DB7 -- --
DB6 -- --
DB5 B5 0
DB4 B4 1
DB3 B3 1
DB2 B2 0
DB1 B1 0
DB0 B0 0
This register specifies the number of times of extracting the timing necessary for carrying out phase control after block synchronization. Specify "16" (0x10) as a typical setting value.
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5.5.4
Phase correction step
Table 5.5.4 Phase correction step
Address 0x0E
R/W W Initial value
DB7 -- --
DB6 B6 0
DB5 B5 0
DB4 B4 1
DB3 -- --
DB2 B2 0
DB1 B1 0
DB0 B0 1
This register is used for setting the phase correction step width of the digital PLL for data clock regeneration. DB0 to DB2: The phase correction step before block synchronization. DB4 to DB6: The phase correction step after block synchronization. DB2 (DB6) 0 0 0 0 1 1 1 1 DB1 (DB5) 0 0 1 1 0 0 1 1 DB0 (DB4) 0 1 0 1 0 1 0 1 Phase correction step width 250nSec 500nSec 750nSec 1000nSec 1250nSec 1500nSec 1750nSec 2000nSec
Set "1000ns" (0x33) as a typical setting value.
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5.6 5.6.1
BLOCK SYNCHRONIZATION REGISTERS Allowable number of BIC errors
Table 5.6.1 Allowable number of BIC errors Address 0x10 Initial value R/W W DB7 DB6 DB5 -- -- DB4 -- -- DB3 B3 0 DB2 B2 1 DB1 B1 1 DB0 B0 0
BICGATE BICGATE SEL1_SUB SEL0_SUB 0 1
This is a specification related to the synchronization and clock regeneration processing of the MSM9563, and consists of the specification of the allowable number of error bits in the block identification code (BIC). (1) DB1 to DB0: Allowable number of BIC errors before block synchronization (common to main channel and subchannels) Set value DB1 0 0 1 1 (2) DB0 0 1 0 1 Allowable number of BIC errors before block synchronization 0 1 2 3
DB3 to DB2: Allowable number of BIC errors after block synchronization (common to main channel and subchannels) Set value DB3 0 0 1 1 DB2 0 1 0 1 Allowable number of BIC errors after block synchronization 0 1 2 3
(3)
DB7 to DB6: BICGATESEL1_SUB to BICGATE SEL0_SUB
The segments given in the following table are added to the BIC detection segments in addition to the leading two bytes of the packet when used in the subchannel mode. Set value DB7 0 0 1 1 DB6 0 1 0 1
BIC Detection gate width -- 1 Byte 1.5 Byte 2 Byte
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5.6.2
Number of block synchronization backward protection steps
Table 5.6.2 Number of block synchronization backward protection steps
Address 0x11
R/W W Initial value
DB7 -- --
DB6 -- --
DB5 B1_SUB 0
DB4 B0_SUB 0
DB3 -- --
DB2 -- --
DB1 B1 0
DB0 B0 1
This register is used for setting the number of successive detections of the block identification code (BIC) before considering that a block has been synchronized. Number of main channel block synchronization backward protection steps Set value DB1 0 0 1 1 DB0 0 1 0 1 Number of block synchronization backward protection steps 0 1 2 3
Number of subchannel block synchronization backward protection steps Set value DB5 0 0 1 1 DB4 0 1 0 1 Number of block synchronization backward protection steps 0 1 2 3
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5.6.3
Number of block synchronization forward protection steps
Table 5.6.3 Number of block synchronization forward protection steps
Address 0x12
R/W R/W Initial value
DB7 B3_SUB 1
DB6 B2_SUB 0
DB5 B1_SUB 0
DB4 B0_SUB 0
DB3 B3 1
DB2 B2 0
DB1 B1 0
DB0 B0 0
Write This register is used for setting the number of successive detection failures of the block identification code (BIC) before considering that the block has been synchronized. DB0 to DB3: Setting of the main channel block synchronization forward protection steps DB4 to DB7: Setting of the subchannel block synchronization forward protection steps Number of block synchronization forward protection steps 0 (Prohibited) 1 O 15
DB3 (DB7) 0 0 O 1
DB2 (DB6) 0 0 O 1
DB1 (DB5) 0 0 O 1
DB0 (DB4) 0 1 O 1
Read When BICs cannot be detected successively in a block synchronization state, the number of detection failures is decremented from the number of block synchronization forward protection steps, and when the value of this register changes from 1 to 0, the block is considered to have been out of synchronization. Remaining number of DB3 DB2 DB1 DB0 block synchronization (DB7) (DB6) (DB5) (DB4) forward protection steps Synchronization detection 0 0 0 0 0 0 O 1 0 O 1 0 O 1 1 O 1 1 O 15
Out of synchronization
When BIC cannot be detected Loaded during synchronization
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5.6.4
Block synchronization monitor
Table 5.6.4 Block synchronization monitor
Address 0x13
R/W R Initial value
DB7 -- --
DB6 -- --
DB5 -- --
DB4 BSYNC_SUB 0
DB3 -- --
DB2 -- --
DB1 -- --
DB0 BSYNC 0
DB0: Main channel block synchronization state 0: Block out-of-synchronization 1: Block synchronized DB4: Subchannel block synchronization state 0: Block out-of-synchronization 1: Block synchronized
5.6.5
Setting/clearing block synchronization
Table 5.6.5 Setting/clearing block synchronization
Address 0x14
R/W W Initial value
DB7 -- --
DB6 -- --
DB5 B1_SUB 0
DB4 B0_SUB 0
DB3 -- --
DB2 -- --
DB1 B1 0
DB0 B0 0
Setting/clearing main channel block synchronization DB1 1 0 DB0 Setting or clearing synchronization 0 1 Clearing synchronization Setting synchronization
Setting/clearing subchannel block synchronization DB5 1 0 DB4 Setting or clearing synchronization 0 1 Clearing synchronization Setting synchronization
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5.7 5.7.1
FRAME SYNCHRONIZATION REGISTERS Number of frame synchronization backward protection steps
Table 5.7.1 Number of frame synchronization backward protection steps
Address 0x18
R/W W Initial value
DB7 -- --
DB6 -- --
DB5 -- --
DB4 -- --
DB3 -- --
DB2 -- --
DB1 B1 0
DB0 B0 1
This register is used for setting the number of successive detections of synchronization points required before considering that the frame has been synchronized. Number of frame synchronization backward protection steps 1 2 3 4
DB1 0 0 1 1
DB0 0 1 0 1
5.7.2
Number of frame synchronization forward protection steps
Table 5.7.2 Number of frame synchronization forward protection steps
Address 0x19
R/W R/W Initial value
DB7 -- --
DB6 -- --
DB5 -- --
DB4 -- --
DB3 B3 0
DB2 B2 1
DB1 B1 0
DB0 B0 0
Write This register is used for setting the number of successive detection failures of synchronization points before considering that the frame has been out-of-synchronized. Number of frame synchronization forward protection steps 0 (Prohibited) 1 O 15
DB3 0 0 O 1
DB2 0 0 O 1
DB1 0 0 O 1
DB0 0 1 O 1
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Read When synchronization points cannot be detected successively in a frame synchronization state, the number of detection failures is decremented from the set number of frame synchronization forward protection steps, and when the value of this register changes from 1 to 0, the frame is considered to have been out-of-synchronization. Remaining number of frame synchronization forward protection steps Synchronization detection 0 1 O 15
DB3 0 0 O 1
DB2 0 0 O 1
DB1 0 0 O 1
DB0 0 1 O 1
Out of synchronization
When frame synchronization point cannot be detected Loaded during synchronization detection
5.7.3
Frame synchronization monitor
Table 5.7.3 Frame synchronization monitor
Address 0x1A
R/W R Initial value
DB7 -- --
DB6 -- --
DB5 -- --
DB4 -- --
DB3 -- --
DB2 -- --
DB1 -- --
DB0 FSYNC 0
DB0: Frame synchronization monitor 0: Frame out-of-synchronization 1: Frame synchronized
5.7.4
Setting frame synchronization
Table 5.7.4 Setting frame synchronization
Address 0x1B
R/W W Initial value
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
5.7.5
Clearing frame synchronization
Table 5.7.5 Clearing frame synchronization
Address 0x1C
R/W W Initial value
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
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5.8
ERROR CORRECTION REGISTERS
The first horizontal error correction, vertical error correction, and the second horizontal error correction have been automated. The results of correction and CRC can be read together with the receive data from the receive port after the first horizontal error correction and the receive port after the second horizontal error correction. In addition, the number of corrections and the threshold value have been set optimally. Therefore, normally, there is no need to set the registers 0x20, 0x21, 0x22, 0x23, 0x24, and 0x25.
5.8.1
Clearing address
Table 5.8.1 Clearing address
Address 0x20
R/W W Initial value
DB7 -- --
DB6 -- --
DB5 -- --
DB4 -- -- B1
DB3 -- -- B0 1 0
DB2 -- --
DB1 B1 0
DB0 B0 0
Address Clear ERC0_CHG (for testing)
0 1
5.8.2
Error correction data port
Table 5.8.2 Error correction data port
Address 0x21
R/W R W Initial value
DB7 B7 B7 --
DB6 B6 B6 --
DB5 B5 B5 --
DB4 B4 B4 --
DB3 B3 B3 --
DB2 B2 B2 --
DB1 B1 B1 --
DB0 B0 B0 --
5.8.3
Error correction start
Table 5.8.3 Error correction start
Address
R/W R
DB7 -- -- --
DB6 -- -- --
DB5 -- -- --
DB4 -- -- --
DB3 -- -- --
DB2
DB1
DB0
0x22
W Initial value
Second First Vertical horizontal horizontal correction correction correction state state state Start second Start Start first horizontal vertical horizontal correction correction correction
--
--
--
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5.8.4
Number of corrections and error correction results
Table 5.8.4 Number of corrections and error correction results
Address
R/W R
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0x23
W Initial value
Result of Result of First Second -- -- -- -- second first horizontal horizontal horizontal horizontal CRC result CRC result correction correction Number of Number of Number of MOD_ MOD_ Number of Number of Number of second second second vertical vertical vertical VSTAT ERC0CH horizontal horizontal horizontal corrections _B2 corrections _B1 corrections _B0 corrections _B2 corrections _B1 corrections _B0 RAM G
1
1
1
1
1
0
1
1
5.8.5
Results of vertical error correction
Table 5.8.5 Results of vertical error correction
Address 0x24
R/W R Initial value
DB7 0
DB6 0
DB5 0
DB4 0
DB3 0
DB2 0
DB1 0
DB0 0
CRCOUT7 CRCOUT6 CRCOUT5 CRCOUT4 CRCOUT3 CRCOUT2 CRCOUT1 CRCOUT0
5.8.6
Number of corrections and threshold value
Table 5.8.6 Number of corrections and threshold value
Address 0x25
R/W W Initial value
DB7
DB6
DB5
Number of Number of Number of first first first horizontal horizontal horizontal corrections _B2 corrections _B1 corrections _B0
1
1
1
DB4 DB3 DB2 DB1 DB0 Threshold Threshold Threshold Threshold Threshold value value value value value TH4 TH3 TH2 TH1 TH0 0 1 1 1 0
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5.9 5.9.1
LAYER 4 CRC REGISTERS Layer 4 CRC registers
Table 5.9.1 Layer 4 CRC register
Address
R/W R
DB7 L4CRC OUT MOD2 1
DB6 -- MOD1 1
DB5 -- MOD0 0
DB4 -- -- --
DB3 -- -- 0
DB2 -- -- 0
DB1 --
DB0 --
0x28
W Initial value Write (1)
MEMTST CLRCRC 0 0
DB0: CLRCRC Write a "1" before executing layer 4 CRC However, (111X0001) is valid only when DB5=DB6=DB7=1. DB1: MEMTEST The use of any value other than "0" is prohibited. DB5 to DB7: Setting of the test mode Use one of the modes given in the following table. DB7 1 0 0 0 DB6 1 1 0 0 DB5 1 0 1 0 DB4 -- -- -- -- -- -- 0 -- DB3 0 DB2 0 DB1 0 DB0 1
(2) (3)
Set mode CLRCRC Other than CLRCRC
Read (1) DB7: L4CRCOUT (Display of layer 4 CRC result) 1: There is an error in the layer 4 CRC result. 0: The layer 4 CRC result is normal.
5.9.2
Layer 4 CRC data port
Table 5.9.2 Layer 4 CRC data port
Address 0x29
R/W R W Initial value
DB7 B7 B7
DB6 B6 B6
DB5 B5 B5
DB4 B4 B4
DB3 B3 B3
DB2 B2 B2
DB1 B1 B1
DB0 B0 B0
Write the data group for which CRC processing is to be made in units of a byte at a cycle period of 620ns or more.
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5.9.3
Layer 4 CRC result
Table 5.9.3 Layer 4 CRC result
Address 0x2A
R/W R Initial value
DB7 -- --
DB6 -- --
DB5 -- --
DB4 -- --
DB3 -- --
DB2 -- --
DB1 -- --
DB0 L4CRC result 0
(1)
DB0: L4CRC result 0: Normal 1: Error Read out the layer 4 CRC result when a time of 1.2ms or more has elapsed after writing the last data of the data group.
5.9.4
Layer 4 CRC register
This is the register for writing the initial value directly in the CRC computation registers and for reading out the intermediate result. It is possible to execute the layer 4 CRC processing of a short data group by interrupting the layer 4 CRC processing of a long data group. Table 5.9.4.1 Layer 4 CRC register upper 8 bits
Address 0x2B
R/W R/W Initial value
DB7 B7 0
DB6 B6 0
DB5 B5 0
DB4 B4 0
DB3 B3 0
DB2 B2 0
DB1 B1 0
DB0 B0 0
Table 5.9.4.2 Layer 4 CRC register lower 8 bits Address 0x2C R/W R/W Initial value DB7 B7 0 DB6 B6 0 DB5 B5 0 DB4 B4 0 DB3 B3 0 DB2 B2 0 DB1 B1 0 DB0 B0 0
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5.10
ANALOG TEST REGISTER
Table 5.10.1 Analog test
Address 0x30
R/W W Initial value
DB7 -- --
DB6 DET0 DTST 0
DB5 M2 0
DB4 M1 0
DB3 M0 0
DB2 SGAIN1 0
DB1 SGAIN0 0
DB0 DETC 0
(1)
DB0: DETC For testing purposes only. Use normally with DETC=0. DB2 to DB1: SGAIN1 to SGAIN0 These set the variable gain amplifier for the analog signal input (composite signal). Set so that peak value of the analog input signal (composite signal)gain=0.5 to 0.9VP-P. DB2 (SGAIN1) 0 0 1 1 DB1 (SGAIN0) 0 1 0 1
(2)
Gain 1 1.5 2 3
(3)
DB3 to DB5: M2 to M0 This register controls the monitor terminal (pin MON) for the analog section output waveform. DB5 (M2) 0 1 1 DB4 (M1) 0 0 1 DB3 (M0) 0 1 1
MON Terminal (pin 1) HZ Output Band pass filter output Equivalent waveform output (for observing the eye pattern)
(4)
DB6: DEST0DTST For testing purpose only. Normally use with the setting DB6=0.
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5.11
POWER DOWN REGISTER
Table 5.11 Power down
Address 0x31
R/W W Initial value
DB7 -- --
DB6 XCK2 0
DB5 XCK1 0
DB4 XCK0 0
DB3 -- --
DB2 B2 0
DB1 B1 0
DB0 B0 0
(1)
DB4 to DB6: XCK0 to XCK2 (setting the divided frequency of external clock) Set the divided frequency of the clock that is output to the XOUT pin, as follows (when XOUTC=0) DB6 0 0 0 0 1 1 1 1 DB5 0 0 1 1 0 0 1 1 DB4 0 1 0 1 0 1 0 1 XOUT Pin output clock frequency 8.192 MHz 4.096 MHz 2.048 MHz 1.024 MHz 0.512 MHz 0.256 MHz 0.128 MHz 0.064 MHz
(2)
DB2: External clock input This controls the operation of the crystal oscillator circuit as follows when the XOUTC pin is "1". Also, in this case, the XOUT output pin is set to the "L" level. 0: The operation of the crystal oscillator circuit is stopped. 1: The crystal oscillator circuit is acrivated. When the XOUTC pin is "0", the crystal oscillator circuit will be operating continuously and the XOUT pin also will be outputting the clock signal continuously.
(3)
DB1: Digital section power down 0: The power is down and the internal clock stops at the "H" level. 1: The power is turned on and the clock for operating the digital section starts from the "H" level. DB0: Analog section power down 0: Power down (operation stops) 1: Power on (several milliseconds will be required for the circuit operation to become stable after the power is turned on.)
(4)
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5.12
TEST CONTROL REGISTERS
5.12.1 Test control 0
Table 5.12.1 Test control 0
Address 0x32
R/W W Initial value
DB7 B7 0
DB6 B6 0
DB5 B5 0
DB4 -- --
DB3 -- --
DB2 -- --
DB1 -- --
DB0 -- --
This is the register for controlling the selection of the test output pins (MOUT0 to MOUT4), and is used for testing only. Set value Pin name MOUT0 MOUT1 MOUT2 MOUT3 MOUT4 Pin No. 8 9 10 11 12 0xC0, 0x00, 0xA0 Extension port DB0 of register 0x0F DB1 of register 0x0F DB2 of register 0x0F DB3 of register 0x0F DB4 of register 0x0F TSTC FSYNC (Note 1) BSYNC (Note 2) BIC0 (Note 3) BIC1 (Note 3) BICDET1 (Note 3) 0xE0
Note 1: FSYNC 1: Frame synchronized 0: Frame out-of-synchronization Note 2: BSYNC 1: Block synchronized 0: Block out-of-synchronization Note 3: BIC Detection BICDET1 1 1 1 1 0 BIC1 0 0 1 1 -- BIC0 0 1 0 1 -- BIC NO. 1 2 3 4 Not detected
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5.12.2 Test control 1
Table 5.12.2 Test Control 1 Address 0x33 Initial value -- R/W W DB7 -- DB6
Delay detector output control 1
DB5
DB4
DB3
DB2
Delay Differential detector Serial output PN Decoding decoding output control 1 control control control 0
DB1 Clock output control 0
DB0 Serial output control 0 0
0
0
0
0
1
Set one of the following two types of set values depending on whether or not the serial receive data and the 16kHz regenerated clcok are monitored from an external device. Set value DB0 to DB7 1 2 0x04 0x17
MOUT5 0 16kHz regenerated data clock
MOUT6 0 Serial receive data
5.13
EXTENSION PORT REGISTER
It is possible to output the write data (DB0 to DB4) of this register to the monitor output terminal by setting 0xC0, and 0xA0, or 0x00 in the register 0x32. Table 5.13 Extension port register
Address 0x0F
R/W W Initial value
DB7 -- --
DB6 -- --
DB5 -- --
DB4 DB4 0
DB3 DB3 0
DB2 DB2 0
DB1 DB1 0
DB0 DB0 0
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Chapter 6
EXTERNAL CONNECTION EXAMPLE
MSM9563 User's Manual Chapter 6 EXTERNAL CONNECTION EXAMPLE
6.
EXTERNAL CONNECTION EXAMPLE
MSM9563
1 Tuner section 330 pF (10%) 2 MON ADETIN CLR A5 A4 A3 A2 A1 A0 40 38 37 36 35 34 33
CPU interface
6 5
AIN SG
2.2 mF (Note 1) (Note 3) (Note 2) 2.2 mF (Note 1)
+ -
XOUT 32 31 CS XTAL2 30 XTAL1 29 15 pF 8.192 MHz crystal 15 pF (Note 2) 2.2 mF (Note 1)
3 + -4 14 13 12 11 10 9 8
AVDD AGND MOUT6 MOUT5 MOUT4 MOUT3 MOUT2 MOUT1 MOUT0
DVDD
+ 27 - DGND DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RD WR INT 26 25 24 23 22 21 20 19 18 16 15
28
DVDD AVDD DGND AGND (Note 2) + -
+3 V power supply input
(Note 1) Use a tantalum capacitor. (Note 2) The AVDD and DVDD should have different paths, respectively. (Note 3) The AGND and tuner ground should use the same ground.
6-1
MSM9563 User's Manual Chapter 6 EXTERNAL CONNECTION EXAMPLE
6-2
Chapter 7
APPLICATION CIRCUIT
MSM9563 User's Manual Chapter 7 APPLICATION CIRCUIT
7.
APPLICATION CIRCUIT
Antena
FM tuner
FM multiplex data demodulation IC MSM9563 SRAM Font ROM
8 bits CPU (ROM)
LCD control driver
LCD display (16 kanji characters 2 lines)
7-1
MSM9563 User's Manual Chapter 7 APPLICATION CIRCUIT
7-2
APPENDIX
LIST OF REGISTERS (1/2)
MSM9552/9553 (reference) Register address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A Clock BIC Monitor Fixed phase adjustment Integration constant (1/4) Integration constant (2/4) Integration constant (3/4) Integration constant (4/4) Phase correction step Block Allowable number of BIC errors Number of block synchronization forward protection steps Block synchronization monitor Block synchronization clearing In-block bit number monitor (1/2) In-block bit number monitor (2/2) Frame Number of block synchronization backward protection steps Frame synchronization monitor Frame synchronization clearing In-frame block number monitor (1/2) In-frame block number monitor (2/2) International frame format specification synchronizaiton Number of block synchronization backward protection steps regeneration Bit gate ----000 -0000000 ----0000 ----0010 ----0010 --011000 --011000 ----0101 ----0110 ------01 ----1000 0000---0 xxxxxxxx 00000000 -------0 ------01 ----0100 0000--0xxxxxxxx 00000000 -------0 ------10 -- 10000000 11110000 11110110 11110110 11010000 11010000 11111111 11111001 11111101 11111111 -- -- -- -- 11111100 11110100 -- -- -- -- -- R R R R R R R R W W W R W R R W W R W R R Timing interrupt Timing interrupt Frame Block Clock Category Interrupt Interrupt cause Interrupt mask Receive data Receive block condition Receive data and first horizontal error correction data port Receive RAM, data accumulation condition, and address clear Register name Initial Recommended value 0-000000 --000000 00000000 Undefined ------0value *1 -- -- -- -- 11111111 R/W Category R/W W R R Timing interrupt Interrupt Interrupt register Interrupt mask
MSM9562/9563 Register name Page No. 5-5 5-6 5-7 5-8 5-1 5-22 5-24 5-25 5-25 5-26 5-27 5-28 5-28 5-28 5-29 5-30 5-31 5-32 5-33 5-33 5-23 5-23 5-34 5-34 5-35 5-35 5-35 5-23 5-24 5-1 Initial Recommended value 0000-000 0000-00-------0 Undefined ---0---1 -0000-00 00000000 -------0 00000000 00000000 ----0000 -0000000 ----0010 --011000 -001-001 01--0110 --00--01 10001000 ---0---0 --00--00 00000000 -------0 ------01 ----0100 -------0 Undefined Undefined 00000000 0000--00 ------10 value *2 -- -- -- -- -- -- -- -- -- -- -- -- ----0110 --010000 -011-011 00--1001 --01--10 01001111 -- -- -- -- ------00 -- -- -- -- -- -- -- R/W R/W W W R W W R/W R/W R/W R/W W W W W W W W R/W R W R/W R/W W R/W R W W R/W R/W W Register address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x10 0x11 0x12 0x13 0x14 0x15 Interrupt timing _MAIN (byte number 1/2) Interrupt timing _MAIN (byte number 2/2) Number of frame synchronization backward protection steps Frame synchronization monitor Frame synchronization setting Frame synchronization clearing Interrupt timing _MAIN (packet number 1/2) Interrupt timing _MAIN (packet number 2/2) 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F
Receive data Receive port selection after first horizontal error correction Receive port after first horizontal error correction Timing interrupt mode Interrupt timing _SUB (byte number 1/2) Interrupt timing _SUB (byte number 2/2) Interrupt timing _SUB (packet number) Interrupt timing _SUB (frame interval) Clock timing adjustment (subchannel) Fixed phase adjustment Integration constant after synchronization Phase correction step Allowable number of BIC errors Number of clock synchronization forward protection steps Block synchronization monitor Block synchronization setting/clearing synchronization Number of block synchronization backward protection steps regeneration Integration constant before sysnchronization
W Operating mode Main channel/subchannel mode setting
Appendix-1
0x0B 0x0C 0x0D 0x0E 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F
MSM9563 User's Manual APPENDIX
0x19 synchronization Number of block synchronization forward protection steps
synchronization Number of frame synchronization forward protection steps
W Operating mode Frame format specification
*1 Unused bits are entered as "1".
*2 Unused bits are entered as "--".
MSM9563 User's Manual APPENDIX
LIST OF REGISTERS (2/2)
MSM9552/9553 (reference) Register address 0x20 0x21 0x22 0x23 0x24 0x25 0x28 0x29 0x2A Category Error correction Register name Internal address counter clear Data transfer port for error correction Start signal for error correction CRC Result display/second horizontal error Error correction result display Majority logic threshold value Layer 4 CRC Clear layer 4 CRC registers Layer 4 CRC data buffer Layer 4 CRC result display Layer 4 CRC register (1/2) Layer 4 CRC register (2/2) Initial Recommended value xxxxxxxx Undefined -----000 -----0-0 00000000 ---01000 11000000 00000000 -------0 00000000 00000000 -- -- -- -- value -- -- -- -- -- 11101001 R/W Category W R/W R/W R R W R/W R R/W R/W Error correction
MSM9562/9563 Register name Internal address counter clear Data transfer port for error correction Start signal for error correction Number of corrections and error correction result Vertical error correction result Number of vertical error corrections and threshold value Layer 4 CRC data buffer Layer 4 CRC result display Layer 4 CRC register (upper 8 bits) Layer 4 CRC register (lower 8 bits) Page No. 5-36 5-36 5-36 5-37 5-37 5-37 5-38 5-38 5-39 5-39 5-39 Initial Recommended value ------00 --------------11111011 00000000 11101110 110-0000 Undefined -------0 00000000 00000000 value -- -- -- -- -- -- -- -- -- -- -- R/W W R/W R/W R/W R W R/W R/W R R/W R/W Register address 0x20 0x21 0x22 0x23 0x24 0x25 0x28 0x29 0x2A 0x2B 0x2C
R/W Layer 4 CRC Layer 4 CRC
Appendix-2
0x2B 0x2C 0x2D 0x2E 0x30 0x31 0x32 0x33 0x34 0x35 0x37 0x38 0x39 0x3B 0x3C 0x3D 0x3E 0x0F
Analog control Analog section control/monitor Power down Power down register Test control Test control 0 Test control 1
--000000 -000-000 000-----0000000
11111110 10001111 00011111 10010111
W Analog control Analog test W W W Power down Power down Test control Test control 0 Test control 1 Receive data Receive interrupt conditions after first horizontal error correction SI (service identifier) specification Frame synchronization condition Receive port after second horizontal error correction Frame memory access mode Frame memory address (1/3) Frame memory address (2/3) Frame memory address (3/3) Operating mode Page mode/clear main channel
5-40 5-41 5-42 5-43 5-11 5-12 5-20 5-12 5-18 5-19 5-19 5-19 5-3 5-43
-0000000 0000-000 000-----0000100 00100000 11111111 -0000000 Undefined 00000100 --000000 00000000 -------0 -0-00000 ---00000
-- -- -- -- -- -- -- -- -- -- -- -- -- --
W W W W W W R R/W W R/W R/W R/W W W
0x30 0x31 0x32 0x33 0x34 0x35 0x37 0x38 0x39 0x3B 0x3C 0x3D 0x3E 0x0F
Extension port Extension port
---00000
--
W
Extension port Extension port

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