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| STP40NF10L N-CHANNEL 100V - 0.028 - 40A TO-220 LOW GATE CHARGE STripFETTM POWER MOSFET TYPE STP40NF10L s s s s VDSS 100 V RDS(on) < 0.033 ID 40 A TYPICAL RDS(on) = 0.028 EXCEPTIONAL dv/dt CAPABILITY 100% AVALANCHE TESTED APPLICATION ORIENTED CHARACTERIZATION TO-220 3 1 2 DESCRIPTION This Power Mosfet series realized with STMicroelectronics unique STripFET process has specifically been designed to minimize input capacitance and gate charge. It is therefore suitable as primary switch in advanced high-efficiency isolated DC-DC converters for Telecom and Computer application. It is also intended for any application with low gate charge drive requirements. APPLICATIONS s HIGH-EFFICIENCY DC-DC CONVERTERS s UPS AND MOTOR CONTROL s AUTOMOTIVE INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID ID IDM (l) PTOT EAS (1) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuos) at TC = 25C Drain Current (continuos) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature Value 100 100 17 40 25 160 150 1 430 -65 to 175 175 (1) Starting T j = 25C, I D = 20A, VDD = 40V Unit V V V A A A W W/C mJ C C (q) Pulse width limited by safe operating area June 2002 1/8 STP40NF10L THERMAL DATA Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 1 62.5 300 C/W C/W C ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 17V Min. 100 1 10 100 Typ. Max. Unit V A A nA ON (1) Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS, ID = 250A VGS = 10V, ID = 20 A VGS = 5V, ID = 20 A Min. 1 Typ. 1.7 0.028 0.030 Max. 2.5 0.033 0.036 Unit V DYNAMIC Symbol gfs (1) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS = 15V, ID = 20 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 25 2300 290 125 Max. Unit S pF pF pF 2/8 STP40NF10L ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 50 V, ID = 20 A RG = 4.7 VGS = 4.5V (see test circuit, Figure 3) VDD = 80V, ID =40A,VGS = 5V Min. Typ. 25 82 46 12 22 64 Max. Unit ns ns nC nC nC SWITCHING OFF Symbol td(off) tf td(off) tf tc Parameter Turn-off-Delay Time Fall Time Off-voltage Rise Time Fall Time Cross-over Time Test Conditions VDD = 50 V, ID = 20 A, RG = 4.7, VGS = 4.5V (see test circuit, Figure 3) Vclamp =80V, ID = 40 A RG = 4.7, VGS = 4.5V (see test circuit, Figure 3) Min. Typ. 64 24 51 29 53 Max. Unit ns ns ns ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (1) VSD (2) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 40 A, VGS = 0 ISD = 40 A, di/dt = 100A/s, VDD = 30V, Tj = 150C (see test circuit, Figure 5) 110 467 8 Test Conditions Min. Typ. Max. 40 160 1.3 Unit A A V ns nC A Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Safe Operating Area Thermal Impedance 3/8 STP40NF10L Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8 STP40NF10L Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized Drain-Source Breakdown vs Temperature 5/8 STP40NF10L Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STP40NF10L TO-220 MECHANICAL DATA DIM. MIN. A C D D1 E F F1 F2 G G1 H2 L2 L4 L5 L6 L7 L9 DIA. 13.0 2.65 15.25 6.2 3.5 3.75 0.49 0.61 1.14 1.14 4.95 2.4 10.0 16.4 14.0 2.95 15.75 6.6 3.93 3.85 0.511 0.104 0.600 0.244 0.137 0.147 4.40 1.23 2.40 1.27 0.70 0.88 1.70 1.70 5.15 2.7 10.40 0.019 0.024 0.044 0.044 0.194 0.094 0.393 0.645 0.551 0.116 0.620 0.260 0.154 0.151 mm TYP. MAX. 4.60 1.32 2.72 MIN. 0.173 0.048 0.094 0.050 0.027 0.034 0.067 0.067 0.203 0.106 0.409 inch TYP. MAX. 0.181 0.051 0.107 A C D1 L2 D F1 G1 E Dia. L5 L7 L6 L4 P011C L9 F2 F G H2 7/8 STP40NF10L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com 8/8 |
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