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Preliminary Technical Data
FEATURES
800 MHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs AD9510
FUNCTIONAL BLOCK DIAGRAM
VS
Low phase noise phase-locked loop core Reference input frequencies to 250 MHz Programmable dual-modulus prescaler Programmable charge pump (CP) current Separate CP supply (VCP) extends tuning range Two 1.5 GHz, differential clock inputs 8 programmable dividers, 1 to 32, all integers Phase select for output-to-output coarse delay adjust 4 independent 800 MHz LVPECL outputs Additive output jitter 225 fs rms 4 independent 800 MHz/250 MHz LVDS/CMOS clock outputs Additive output jitter 275 fs rms Fine delay adjust on 2 outputs, 6-bit delay words 4-wire or 3-wire serial control port Space-saving 64-lead LFCSP
GND
RSET
CPRSET VCP
DISTRIBUTION
REF
REFIN
REFINB
N DIVIDER
AD9510
PHASE FREQUENCY DETECTOR
PLL REF
R DIVIDER
CHARGE PUMP
CP
FUNCTION
CLK1 CLK1B
SYNCB , RESETB PDB
PLL SETTINGS
STATUS
CLK2
PROGRAMMABLE DIVIDERS
& PHASE ADJUST
CLK2B
LVPECL
/1,/2,/3 ... /31,/32
LVPECL
OUT0 OUT0B
OUT1
/1,/2,/3 ... /31,/32
SCLK SDIO
OUT1B
LVPECL
OUT2
SDO CSB
SERIAL CONT ROL PO RT
/1,/2,/3 ... /31,/32
LVPECL
OUT2B
/1,/2,/3 ... /31,/32
LVDS/CMOS
OUT3
OUT3B
/1,/2,/3 ... /31,/32
OUT4
OUT4B
APPLICATIONS
/1,/2,/3 ... /31,/32
T
LVDS/CMOS
OUT5 OUT5B
Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDS, DDC, DUC, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure
LVDS/CMOS
/1,/2,/3 ... /31,/32
T
LVDS/CMOS
OUT6
OUT6B
/1,/2,/3 ... /31,/32
OUT7
OUT7B
Figure 1.
GENERAL DESCRIPTION
The AD9510 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise in order to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. The PLL section consists of a programmable reference divider (R); a low noise phase frequency detector (PFD); a precision charge pump (CP); and a programmable feedback divider (N). By connecting an external VCXO or VCO to the CLK2/CLK2B pins, frequencies up to 1.5 GHz may be synchronized to the input reference. There are eight independent clock outputs. Four outputs are LVPECL, and four are selectable as either LVDS or CMOS levels. The LVPECL and LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
Each output has a programmable divider that may be bypassed or set to divide by any integer up to 32. The phase of one clock output relative to another clock output may be varied by means of a divider phase select function that serves as a coarse timing adjustment. Two of the LVDS/CMOS outputs also feature programmable delay elements with a range of up to 10 ns of delay. This fine tuning delay block has 6-bit resolution, giving 64 possible delays from which to choose. The AD9510 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter. The AD9510 is available in a 64-lead LFCSP and may be operated from a single 3.3 V supply. An external VCO which requires an extended voltage range may be accommodated by connecting the charge pump supply (VCP) to 5.5 V. The temperature range is -40C to +85C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD9510 TABLE OF CONTENTS
Specifications..................................................................................... 3 PLL Characteristics ...................................................................... 3 Clock Inputs .................................................................................. 4 Clock Outputs ............................................................................... 5 Timing Characteristics ................................................................ 5 Clock Output Phase Noise .......................................................... 7 Clock Output Additive Time Jitter........................................... 10 PLL and Distribution Phase Noise and Spurious................... 10 Serial Control Port ..................................................................... 11 Function Pin................................................................................ 11 Status Pin ..................................................................................... 12 Power............................................................................................ 12 Timing Diagrams............................................................................ 13 Absolute Maximum Ratings.......................................................... 14 Thermal Characteristics ............................................................ 14 ESD Caution................................................................................ 14 Pin Configuration and Function Descriptions........................... 15 Terminology .................................................................................... 17 Typical Performance Characteristics ........................................... 18 Typical Modes of Operation ......................................................... 19 Function Description ..................................................................... 21 Overall.......................................................................................... 21 PLL Operation ............................................................................ 21 PLL Reference Input................................................................... 21 PLL Reference Divider............................................................... 21 VCO/VCXO Clock Input .......................................................... 21
Preliminary Technical Data
VCO/VCXO Feedback Divider ................................................ 21 A and B Counters ....................................................................... 22 Setting Values for P, A, B, and R ................................................ 22 Phase Frequency Detector (PFD) and Charge Pump............ 23 Status Pin ..................................................................................... 23 CLK1 Clock Input ...................................................................... 23 Serial Control Port ......................................................................... 24 Serial Control Port Pin Descriptions....................................... 24 General Operation of Serial Control Port............................... 24 The Instruction Word (16 Bits) ................................................ 25 MSB/LSB First Transfers ........................................................... 25 Register Map and Description ...................................................... 27 Summary Table........................................................................... 27 Register Map Description ......................................................... 30 Applications..................................................................................... 38 Using the AD9510 Outputs for ADC Clock Applications .... 38 CMOS Clock Distribution ........................................................ 38 LVPECL Clock Distribution ..................................................... 39 LVDS Clock Distribution .......................................................... 40 Power and Grounding Considerations, and Power Supply Rejection...................................................................................... 40 Outline Dimensions ....................................................................... 41 Ordering Guide .......................................................................... 41
REVISION HISTORY
11/04--Revision PrA: Preliminary Version
Rev. PrA | Page 2 of 41
Preliminary Technical Data SPECIFICATIONS
VS = 3.3 V 5%; VS VCP 5.5 V, TA = 25C, RSET = 4.12 k, CPRSET = 5.1 k, unless otherwise noted.
AD9510
PLL CHARACTERISTICS
Table 1.
Parameter REFERENCE INPUTS (REFIN) Input Frequency Input Sensitivity, Differential Input Voltage, Single-Ended Input Common-Mode Voltage Input Capacitance Input Resistance PHASE/FREQUENCY DETECTOR (PFD) Phase Frequency Detector Input Frequency Phase Frequency Detector Input Frequency Phase Frequency Detector Input Frequency Antibacklash Pulse Width Antibacklash Pulse Width Antibacklash Pulse Width CHARGE PUMP (CP) ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature RF CHARACTERISTICS (CLK2 - PLL FEEDBACK) Input Frequency Input Sensitivity, Differential Input Common-Mode Voltage, VCM Input Single-Ended Sensitivity Input Resistance Input Capacitance 200 1.6 VCM 100 5 2 Min 0 200 1.1 1.6 2 5 80 1.7 Typ Max 250 Unit MHz mV V V pF k MHz MHz MHz ns ns ns Test Conditions/Comments
REFINB capacitively bypassed to RF ground Self-bias voltage of REFINB
1.3 2.9 6.0
Antibacklash pulse width 0D <1:0> = 00 Antibacklash pulse width 0D <1:0> = 01 Antibacklash pulse width 0D <1:0> = 10 0D <1:0> = 00 0D <1:0> = 01 0D <1:0> = 10 Programmable
5 625 2.5 2.7/10 1 2 1.5 2
mA A % k nA % % %
VCP = VS/2
1.5
GHz mV V mV k pF
0.5 V < CP < VCP - 0.5 V 0.5 V < CP < VCP - 0.5 V CP = VS/2 CLK2 is electrically identical to CLK1, the distribution only input (see Clock Inputs); can be used as differential or single-ended inputs Frequencies > 800 MHz require a minimum divide-by-2 see the Distribution section Self biased; enables ac coupling When dc-coupled, B input capacitively bypassed to RF ground
Rev. PrA | Page 3 of 41
AD9510
Parameter NOISE CHARACTERISTICS In-band noise of the charge pump/ phase frequency detector (inband means within the LBW of the PLL) @ 50 kHz PFD Frequency @ 2 MHz PFD Frequency @ 10 MHz PFD Frequency @ 50 MHz PFD Frequency PLL Figure of Merit Min Typ Max Unit
Preliminary Technical Data
Test Conditions/Comments The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value). -172 -156 -149 -142 -219 + 10 x log (fPFD) dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
Approximation of the PFD/CP phase noise floor (in the flat region) inside the PLL loop bandwidth. When running closed loop this phase noise is gained up by 20 x log(N)1
PRESCALER Prescaler Input Frequency P = 2 DM (2/3) P = 4 DM (4/5) P = 8 DM (8/9) P = 16 DM (16/17) P = 32 DM (32/33) Prescaler Output Frequency PLL DIGITAL LOCK DETECT WINDOW Required to Lock (Coincidence of Edges) Low Range High Range To Unlock after Lock (Hysteresis) Low Range High Range
500 750 1500 1500 1500 300
MHz MHz MHz MHz MHz MHz Signal available at STATUS pin when selected by 08h <5:2> Selected by register ODh <5> = 1 <5> = 0 Selected by register ODh <5> = 1 <5> = 0
3.5 9.5 7 15
ns ns ns ns
1
Example: -219 + 10 x log (fPFD) + 20 x log(N) should give the values for the in-band noise at the VCO output.
CLOCK INPUTS
Table 2.
Parameter CLOCK INPUTS Min Typ Max Unit Test Conditions/Comments CLK1 and CLK2 are electrically identical; can be used as differential or single-ended inputs Frequencies > 800 MHz require a minimum divide-by-2 see the Distribution section Self-biased; enables ac coupling When dc-coupled, B input capacitively bypassed to RF ground Self-biased
Input Frequency
1.5
GHz
Input Sensitivity, Differential Input Common-Mode Voltage , VCM Input Single-Ended Sensitivity Input Resistance Input Capacitance CLK1 to CLK2 Isolation
200 1.6 VCM 100 5 2
mV V mV k pF dB
Rev. PrA | Page 4 of 41
Preliminary Technical Data
CLOCK OUTPUTS
Table 3.
Parameter LVPECL CLOCK OUTPUTS OUT0, OUT1 OUT2, OUT3; Differential Output Frequency Output High Voltage (VOH) Output Low Voltage (VOL) Output Differential Voltage (VOD) Isolation LVPECL to LVPECL Output Isolation LVDS to LVPECL Output Isolation CMOS to LVPECL Output LVDS CLOCK OUTPUTS OUT4, OUT5, OUT6, OUT7; Differential Output Frequency Differential Output Voltage (VOD) Delta VOD Output Offset Voltage (VOS) Delta VOS Short-Circuit Current (ISA, ISB) Isolation LVDS to LVDS Isolation LVPECL to LVDS Isolation CMOS to LVDS CMOS CLOCK OUTPUTS OUT4, OUT5, OUT6, OUT7; Single Ended Output Frequency Output Voltage High (VOH) Output Voltage Low (VOL) Isolation CMOS to CMOS Isolation LVPECL to CMOS Isolation LVDS to CMOS Min Typ Max Unit
AD9510
Test Conditions/Comments Termination = 50 to VS - 2 V; default Output level setting 3C (3D) (3E) (3F) <3:2> = 10 @ dc @ dc @ dc 100 MHz output with 50 MHz aggressor 100 MHz output with 50 MHz aggressor 100 MHz output with 50 MHz aggressor Termination = 100 differential; default Output Level setting 40 (41) (42) (43) <2:1> = 01, 3.5 mA termination current
VS - 1.2 VS - 1.8 800
800 VS - 0.8 VS - 1.6
MHz V V mV dB dB dB
800 350 5 1.25 5 13
MHz mV mV V mV mA dB dB dB
Output shorted to GND 100 MHz output with 50 MHz aggressor 100 MHz output with 50 MHz aggressor 100 MHz output with 50 MHz aggressor B outputs are inverted; termination = open
250 2.7 0.4
MHz V V dB dB dB
5 pF load
100 MHz output with 50 MHz aggressor 100 MHz output with 50 MHz aggressor 100 MHz output with 50 MHz aggressor
TIMING CHARACTERISTICS
Table 4.
Parameter LVPECL Output Rise Time, tRP Output Fall Time, tFP CLK-TO-LVPECL OUT Propagation Delay, tPECL Divide = Bypass Divide = 2 - 32 Output Skew, tSKP Output Skew, tSKP_AB Min Typ Max Unit Test Conditions/Comments Termination = 50 to VS - 2 V; default Output level setting 3C (3D) (3E) (3F) <3:2> = 10 20% to 80% 80% to 20% CLK1 or CLK2
120 120
ps ps
0.65 0.65 25 150
50 300
ns ns ps ps
LVPECL to LVPECL on same part1 LVPECL to LVPECL on different parts2
Rev. PrA | Page 5 of 41
AD9510
Parameter LVDS Min Typ Max Unit
Preliminary Technical Data
Test Conditions/Comments Termination = 100 differential; default Output level setting 40 (41) (42) (43) <2:1> = 01, 3.5 mA termination current 20% to 80% 80% to 20%
Output Rise Time, tRL Output Fall Time, tFL CLK-TO-LVDS OUT Propagation Delay, tLVDS Divide = Bypass Divide = 2 - 32 Output Skew, tSKL Output Skew, tSKL_AB CLK-TO-LVDS OUT DELAY ADJUST CHANNEL Propagation Delay, tLVDSD Divide = Bypass Divide = 2 - 32 Output Skew, tSKLD CMOS Output Rise Time, tRL Output Fall Time, tFL CLK-TO-CMOS OUT Propagation Delay, tCMOS Divide = Bypass Divide = 2 - 32 Output Skew, tSKC Output Skew, tSKC_AB CLK-TO-CMOS OUT DELAY ADJUST CHANNEL Propagation Delay, tCMOSD Divide = Bypass Divide = 2 - 32 Output Skew, tSKCD LVPECL-TO-LVDS OUT Output Skew, tSKP_L LVPECL-TO-CMOS OUT Output Skew, tSKP_C LVDS-TO-CMOS OUT Output Skew, tSKL_C DELAY ADJUST Shortest Delay Range Zero Scale Full Scale Linearity Longest Delay Range Zero Scale Full Scale Linearity
250 250
ps ps
1.4 1.4 50 200
100 400
ns ns ps ps
OUT4 to OUT7 on same part LVDS on different parts Delay off OUT5 to OUT6 on same part
1.45 1.45 50 300 300
100
ns ns ps ps ps
OUT5 to OUT6 on same part B outputs are inverted; termination = open 20% to 80%; CLOAD = 3 pF 80% to 20%; CLOAD = 3 pF CLOAD = 3 pF
1.4 1.4 50 200
150 400
ns ns ps ps
CMOS to CMOS on same part CMOS to CMOS on different parts Delay off CLOAD = 3 pF
1.45 1.45 50 0.75 0.75 100
150
ns ns ps ns ns
150
ps
0.3 1.0
ns ns %LSB ns ns %LSB
OUT5 to OUT6 on same part Everything the same; different logic LVPECL to LVDS on same part Everything the same; different logic LVPECL to CMOS on same part Everything the same; different logic LVDS to CMOS on same part OUT5 (OUT6); LVDS and CMOS 35h (39h) <5:0> 111111 36h (3Ah) <5:0> 000000 36h (3Ah) <5:0> 111111 35h (39h) <5:0> 000000 36h (3Ah) <5:0> 000000 36h (3Ah) <5:0> 111111
0.5 10
1 2
Defined as the worst-case difference between any two similar delay paths within a single device operating at the same voltage and temperature. Defined as the absolute worst-case difference between any two delay paths on any two devices operating at the same voltage and temperature. Part-to-part skew is the total skew difference; pin-to-pin skew + part-to-part skew.
Rev. PrA | Page 6 of 41
Preliminary Technical Data
CLOCK OUTPUT PHASE NOISE
Table 5.
Parameter CLK1 TO LVPECL ADDITIVE PHASE NOISE CLK1 = 622.08 MHz, OUTN = 622.08 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CLK1 = 622.08 MHz, OUTN = 155.52 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CLK1 = 622.08 MHz, OUTN = 38.88 MHz Divide Ratio = 16 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CLK1 = 491.52 MHz, OUTN = 61.44 MHz Divide Ratio = 8 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset > 1 MHz Offset CLK1 = 491.52 MHz, OUTN = 245.76 MHz Divide Ratio = 2 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CLK1 = 245.76 MHz, OUTN = 61.44 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset Min Typ Max Unit
AD9510
Test Conditions/Comments Distribution section only; does not include PLL or external VCO/VCXO Input slew rate > 1 V/ns
-125 -132 -140 -148 -153 -154
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
-130 -140 -148 -155 -161 -161
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
-145 -152 -161 -165 -165 -166
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
-131 -142 -153 -160 -165 -165
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
-127 -136 -144 -153 -157 -158
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
-140 -144 -154 -163 -164
Rev. PrA | Page 7 of 41
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
AD9510
Parameter >1 MHz Offset CLK1-TO-LVDS ADDITIVE PHASE NOISE Min Typ -165 Max Unit dBc/Hz
Preliminary Technical Data
Test Conditions/Comments Distribution section only; does not include PLL or external VCO/VCXO Characterization ongoing
CLK1 = 622.08 MHz, OUTN = 622.08 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CLK1 = 622.08 MHz, OUTN = 155.52 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CLK1 = 622.08 MHz, OUTN = 38.88 MHz Divide Ratio = 16 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CLK1 = 491.52 MHz, OUTN = 61.44 MHz Divide Ratio = 8 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset > 1 MHz Offset CLK1 = 491.52 MHz, OUTN = 245.76 MHz Divide Ratio = 2 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CLK1 = 245.76 MHz, OUTN = 61.44 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
Rev. PrA | Page 8 of 41
Preliminary Technical Data
Parameter CLK1 to CMOS ADDITIVE PHASE NOISE CLK1 = 245.76 MHz, OUTN = 245.76 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset > 10 MHz Offset CLK1 = 245.76 MHz, OUTN = 61.44 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1 = 78.6432 MHz, OUTN = 78.6432 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1 = 78.6432 MHz, OUTN = 39.3216 MHz Divide Ratio = 2 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset > 1 MHz Offset Min Typ Max Unit
AD9510
Test Conditions/Comments Distribution section only; does not include PLL or external VCO/VCXO
-117 -124 -131 -141 -146 -150 -156
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
-128 -136 -144 -152 -158 -160 -162
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
-127 -135 -142 -151 -156 -158 -160
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
-134 -140 -148 -156 -161 -162
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
Rev. PrA | Page 9 of 41
AD9510
CLOCK OUTPUT ADDITIVE TIME JITTER1
Table 6.
Parameter LVPECL OUTPUT ADDITIVE TIME JITTER CLK1 = 622.08 MHz, OUT0:3 = 622.08 MHz Divide Ratio = 1 CLK1 = 622.08 MHz, OUT0:3 = 155.52 MHz Divide Ratio = 4 CLK1 = 200 MHz, OUT0:3 = 100 MHz Divide Ratio = 2 LVDS OUTPUT ADDITIVE TIME JITTER CLK1 = 200 MHz, OUT4 = 100 MHz CMOS OUTPUT ADDITIVE TIME JITTER CLK1 = 200 MHz, OUT4 = 100 MHz 275 fs rms 275 fs rms 225 fs rms 55 fs rms Min Typ Max Unit
Preliminary Technical Data
40
fs rms
Test Conditions/Comments Distribution section only; does not include PLL or external VCO/VCXO BW = 12 kHz - 20 MHz (OC-12) BW = 12 kHz - 20 MHz (OC-3) Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz
Distribution section only; does not include PLL or external VCO/VCXO Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz Distribution section only; does not include PLL or external VCO/VCXO Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz
1
Distribution section only; does not include PLL or external VCO/VCXO.
PLL AND DISTRIBUTION PHASE NOISE AND SPURIOUS
Table 7. PLL and Distribution
Parameter PHASE NOISE AND SPURIOUS Setup No.1 245.76 MHz VCXO, FPFD = 1.2288 MHz; R = 25, N = 200 245.76 MHz Output Phase Noise @100 kHz Offset Spurious 61.44 MHz Output Phase Noise @100 kHz Offset Spurious Setup No. 2 245.76 MHz VCXO, FPFD = 30.72 MHz; R = 1, N = 8 245.76 MHz Output Phase Noise @100 kHz Offset Spurious 61.44 MHz Output Phase Noise @100 kHz Offset Spurious Min Typ Max Unit Test Conditions/Comments Depends on VCO/VCXO selection. Characterization ongoing. Measured at LVPECL clock outputs; ABP = 6 ns; ICP = 5 mA; Ref = 30.72 MHz Divide by 1 dBc/Hz dBc dBc/Hz dBc First and second harmonics of FPFD Divide by 4 First and second harmonics of FPFD Measured at LVPECL clock outputs; ABP = 6 ns; ICP = 5 mA; Ref = 30.72 MHz Divide by 1 dBc/Hz dBc dBc/Hz dBc First and second harmonics of FPFD Divide by 4 First and second harmonics of FPFD
Rev. PrA | Page 10 of 41
Preliminary Technical Data
SERIAL CONTROL PORT
Table 8.
Parameter SDIO, CSB, SCLK Input Logic 1 Voltage Input Logic 0 Voltage Input Capacitance SDIO, SDO Output Logic 1 Voltage Output Logic 0 Voltage CSB, SCLK Input Logic 1 Current Input Logic 0 Current TIMING Clock Rate (SCLK, 1/tSCLK) Pulse-Width High, tPWH Pulse-Width Low, tPWL SDIO and CSB to SCLK Setup, tDS SCLK to SDIO Hold, tDH SCLK to Valid SDIO and SDO, tDV Min Typ CMOS Levels Max Unit V V pF CMOS Levels V V CMOS Levels A A 25 24 24 MHz ns ns ns ns ns Test Conditions/Comments
AD9510
CSB and SCLK have 30 k internal pull-down resistors
16 16
FUNCTION PIN
Table 9.
Parameter INPUT CHARACTERISTICS Logic 1 Voltage Logic 0 Voltage Input Capacitance Logic 1 Current Logic 0 Current RESET TIMING Pulse-Width Low SYNC TIMING Pulse-Width Low Setup Time Hold Time Min Typ CMOS Levels Max Unit V V pF A A ns 1.5 Clock cycles ps ps Sync single chip; CLK1 or CL2, whichever is being used for distribution Sync multichip; Write CLK1 or CLK2, whichever is being used for distribution Sync multichip; Write CLK1 or CLK2, whichever is being used for distribution Test Conditions/Comments
Rev. PrA | Page 11 of 41
AD9510
STATUS PIN
Table 10.
Parameter OUTPUT CHARACTERISTICS Output Voltage High (VOH) Output Voltage Low (VOL) MAXIMUM TOGGLE RATE Min Typ Max Unit mV mV MHz Test Conditions/Comments
Preliminary Technical Data
100
Applies when PLL mux is set to any divider or counter output, or PFD up/down pulse. Also applies in analog lock detect mode. Usually debug mode only. Beware that spurs may couple to output when this pin is toggling. On-chip capacitance; used to calculate RC time constant for analog lock detect readback. Use pull-up resistor.
ANALOG LOCK DETECT Capacitance
3
pF
POWER
Table 11.
Parameter POWER-UP DEFAULT MODE POWER DISSIPATION Min Typ 650 Max Unit mW Test Conditions/Comments Power-up default state; does not include power dissipated in output load resistors. All functions enabled, all outputs on and terminated, maximum clock rates, and frequencies. Does not include power dissipated in load resistors. (Pick these conditions.)
MAXIMUM POWER DISSIPATION
1050
mW
POWER DELTA CLK1, CLK2 Power-Down Divider, DIV 2 - 32 to Bypass LVPECL Output Power-Down Safe Power-Down (PD2)
mW mW 56 mW PD2 mode (safe) power-down is required when load resistors are connected. Delta does not include dissipation in load resistors. PD3 mode; use only with no load resistors connected.
Total Power-Down (PD3) LVDS Output Power-Down CMOS Output Power-Down Delay Block Bypass Delay Block Power-Down PLL Section Power-Down
58 33 24
46 38
40
mW mW mW mW mW mW
Rev. PrA | Page 12 of 41
Preliminary Technical Data TIMING DIAGRAMS
t CLK1
CLK1
AD9510
t PECL
t LVDS
t CMOS
Figure 2. CLK1/CLK1B to Clock Output Timing, DIV = 1 Mode
Rev. PrA | Page 13 of 41
AD9510 ABSOLUTE MAXIMUM RATINGS
Table 12.
With Respect to GND GND VS GND GND CLK1B CLK2B GND
Preliminary Technical Data
Parameter or Pin VS VCP VCP REFIN, REFINB RSET CPRSET CLK1. CLK1B, CLK2, CLK2B CLK1 CLK2 SCLK, SDIO SDO, CSB Outputs 0, 1, 2, 3 Outputs 4, 5, 6, 7 FUNCTION STATUS Junction Temperature Storage Temperature Lead Temperature (10 sec)
Min -0.3 -0.3 -0.3
Max +3.6 +6
-65
150 +150 300
Unit V V V V V V V V V V V V V V C C C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
THERMAL CHARACTERISTICS1
Thermal Resistance 64-Lead LFCSP JA = 24C/W
1
Thermal impedance measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrA | Page 14 of 41
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VS CPRSET GND RSET VS VS OUT0 OUT0B VS GND OUT1 OUT1B VS VS GND GND
AD9510
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
REFIN REFINB GND VS VCP CP GND GND VS CLK2 CLK2B GND VS CLK1 CLK1B FUNCTION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PIN 1 INDICATOR
AD9510
TOP VIEW (Not to Scale)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VS OUT4 OUT4B VS VS OUT5 OUT5B VS VS OUT6 OUT6B VS VS OUT2 OUT2B VS
STATUS SCLK SDIO SDO CSB GND VS OUT7B OUT7 VS GND OUT3B OUT3 VS VS GND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 3. 64-Lead LFCSP Pin Configuration
Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be attached to ground, GND.
Rev. PrA | Page 15 of 41
05046-002
AD9510
Table 13. Pin Function Descriptions
Pin No. 1 2 3, 7, 8, 12, 22, 27, 32, 49, 50, 55, 62 4, 9, 13, 23, 26, 30, 31, 33, 36, 37, 40, 41, 44, 45, 48, 51, 52, 56, 59, 60, 64 5 6 10 11 14 15 16 17 18 19 20 21 24 25 28 29 34 35 38 39 42 43 46 47 53 54 57 58 61 63 Mnemonic REFIN REFINB GND Description PLL Reference Input. Complementary PLL Reference Input. Ground.
Preliminary Technical Data
VS
Power Supply (3.3 V).
VCP CP CLK2 CLK2B CLK1 CLK1B FUNCTION STATUS SCLK SDIO SDO CSB OUT7B OUT7 OUT3B OUT3 OUT2B OUT2 OUT6B OUT6 OUT5B OUT5 OUT4B OUT4 OUT1B OUT1 OUT0B OUT0 RSET CPRSET
Charge Pump Power Supply. It should be greater than or equal to VS. VCP may be set as high as 5.5 V for VCOs requiring extended tuning range. Charge Pump Output. Clock Input Used to Connect External VCO/VCXO to Feedback Divider, N. CLK2 also drives the distribution section of the chip and may be used as a generic clock input when PLL is not used. Complementary Clock Input Used in Conjunction with CLK2. Clock Input That Drives Distribution Section of the Chip. Complementary Clock Input Used in Conjunction with CLK1. Multipurpose Input May Be Programmed as a Reset (RESETB), Sync (SYNCB), or Power-Down (PDB) Pin. Output Used to Monitor PLL Status and Sync Status. Serial Data Clock. Serial Data I/O. Serial Data Output. Serial Port Chip Select. Complementary LVDS/Inverted CMOS Output. LVDS/CMOS Output. Complementary LVPECL Output. LVPECL Output. Complementary LVPECL Output. LVPECL Output. Complementary LVDS/Inverted CMOS Output. OUT6 includes a delay block. LVDS/CMOS Output. OUT6 includes a delay block. Complementary LVDS/Inverted CMOS Output. OUT5 includes a delay block. LVDS/CMOS Output. OUT5 includes a delay block. Complementary LVDS/Inverted CMOS Output. LVDS/CMOS Output. Complementary LVPECL Output. LVPECL Output. Complementary LVPECL Output. LVPECL Output. Current Set Resistor to Ground. Nominal value = 4.147 k. Charge Pump Current Set Resistor to Ground. Nominal value = 5.1 k.
Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be attached to ground, GND.
Rev. PrA | Page 16 of 41
Preliminary Technical Data TERMINOLOGY
Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 degrees for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although there are many causes that can contribute to phase jitter, one major component is due to random noise which is characterized statistically as being Gaussian (normal) in distribution. This phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in dB) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement the offset from the carrier frequency is also given. It is also meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 kHz to 10 MHz). This is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval. Phase noise has a detrimental effect on the performance of ADCs and DACs and RF mixers. It lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways.
AD9510
Time Jitter Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings is seen to vary. In the case of a square wave, the time jitter is seen as a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Since these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the Gaussian distribution. Time jitter that occurs on a sampling clock for a DAC or an ADC decreases the SNR and dynamic range of the converter. A sampling clock with the lowest possible jitter provides the highest performance from a given converter. Additive Phase Noise It is the amount of phase noise that is attributable to the device or subsystem being measured. The phase noise of any external oscillators or clock sources has been subtracted. This makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contribute their own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. Additive Time Jitter It is the amount of time jitter that is attributable just to the device or subsystem being measured. The time jitter of any external oscillators or clock sources has been subtracted. This makes it possible to predict the degree to which the device will impact the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contribute their own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.
Rev. PrA | Page 17 of 41
AD9510 TYPICAL PERFORMANCE CHARACTERISTICS
Preliminary Technical Data
Figure 4. Phase Noise - LVPECL 245.76 MHz
Figure 7. Phase Noise - CMOS 245.76 MHz
Figure 8. Figure 5. Phase Noise - LVPECL 622MHz
Figure 9. Figure 6. Phase Noise - CMOS 61.44MHz
Rev. PrA | Page 18 of 41
Preliminary Technical Data TYPICAL MODES OF OPERATION
PLL with External VCXO/VCO Followed by Clock Distribution
This is the most common operational mode for the AD9510. An external oscillator (shown as VCO/VCXO) is phase locked to a reference input frequency applied to REFIN. The loop filter is usually a passive design. A VCO or a VCXO may be used. The CLK2 input is connected internally to the feedback divider, N. The CLK2 input provides the feedback path for the PLL. If the VCO/VCXO frequency exceeds maximum frequency of the output(s) being used, an appropriate divide ratio must be set in the corresponding divider(s) in the distribution section.
REFIN
Vref R Function N PLL Ref PFD Status CP
AD9510
REFIN
Vref R
PLL Ref PFD Status CP
Function
N
Clock Input 1
CLK1
CLK2
AD9510
Divide Divide Serial Port Divide Divide
LVPE CL LVPE CL
Clock Input 2
LVPE CL
LVPE CL LVDS/ CMOS LVDS/ CMOS
Reference Input
Loop Filter
Divide Divide Divide Divide
Clock Outputs
T T
LVDS/ CMOS LVDS/ CMOS
CLK1
CLK2
VCXO, VCO
AD9510
Divide Divide Serial Port Divide Divide Divide Divide Divide Divide
LVPECL
LVPECL
Figure 11. Clock Distribution Mode
LVPECL
PLL with External VCO and Band-Pass Filter Followed by Clock Distribution
Clock Outputs
LVPECL LVDS/ CMOS LVDS/ CMOS
T T
LVDS/ CMOS LVDS/ CMOS
An external band-pass filter may be used to possibly improve the phase noise and spurious characteristics of the PLL output. This option is most appropriate when the desire is to optimize cost by choosing a less expensive VCO combined with a moderately priced filter. Note that the BPF is shown outside of the VCO to N divider path, with the BP filter outputs routed to CLK1.
Figure 10. PLL and Clock Distribution Mode
Clock Distribution Only
In this mode, the PLL is not used. A customer can save power by initiating a PLL power-down and by powering down any unused clock channels. In distribution mode, both CLK1 and CLK2 inputs are available for distribution to outputs via a low jitter multiplexer (MUX).
Reference Input
REFIN
Vref R Function N PLL Ref PFD Status CP
Loop Filter
CLK1
CLK2
VCO AD9510
Divide Divide Serial Port Divide Divide Divide Divide Divide Divide
LVPECL
LVPECL
BPF
LVPECL
LVPECL LVDS/ CMOS LVDS/ CMOS
Clock Outputs
T T
LVDS/ CMOS LVDS/ CMOS
Figure 12. AD9510 with VCO and BPF Filter
Rev. PrA | Page 19 of 41
AD9510
VS GND RSET
Preliminary Technical Data
CPRSET VCP
DISTRIBUTION REF
AD9510
PLL REF
REFIN REFINB
R DIVIDER PHASE FREQUENCY DETECTOR N DIVIDER CHARGE PUMP CP
FUNCTION
SYNCB, RESETB PDB
PLL SETTINGS
STATUS
CLK1 CLK1B PROGRAMMABLE DIVIDERS
& PHASE ADJUST
CLK2 CLK2B LVPECL OUT0 /1, /2, /3 ... /31, /32 OUT0B LVPECL OUT1 /1, /2, /3 ... /31, /32 OUT1B
SCLK SDIO SDO CSB /1, /2, /3 ... /31, /32 SERIAL CONTROL PORT /1, /2, /3 ... /31, /32
LVPECL OUT2 OUT2B LVPECL OUT3 OUT3B LVDS/CMOS /1, /2, /3 ... /31, /32 OUT4 OUT4B LVDS/CMOS /1, /2, /3 ... /31, /32
T
OUT5 OUT5B LVDS/CMOS
/1, /2, /3 ... /31, /32
T
OUT6 OUT6B LVDS/CMOS OUT7
/1, /2, /3 ... /31, /32 OUT7B
05 046- 001
Figure 13. Functional Block Diagram
Rev. PrA | Page 20 of 41
Preliminary Technical Data FUNCTION DESCRIPTION
OVERALL
Figure 13 shows a block diagram of the AD9510. The chip combines a programmable PLL core with a configurable clock distribution system. A complete PLL requires the addition of a suitable external VCO (or VCXO) and loop filter. This PLL can be used to lock to a reference input signal and produce an output that is related to the input frequency by the ratio defined by the programmable R and N dividers. The PLL offers some jitter clean up of the external reference signal, depending on the loop bandwidth and the phase noise performance of the VCO (VCXO). The output from the VCO (VCXO) can be applied to the clock distribution section of the chip, where it can be divided by any integer value from 1 to 32. The duty cycle and relative phase of the outputs can be selected. There are four LVPECL outputs, (OUT0, OUT1, OUT2, and OUT3) and four outputs that can be selected as either LVDS or CMOS level outputs (OUT4, OUT5, OUT6, and OUT7). Two of these outputs (OUT5, OUT6) can also make use of a variable delay block. Alternatively, the clock distribution section can be driven directly by an external clock signal, and the PLL can be powered off. Whenever the clock distribution section is used alone, there is no clock clean-up. The jitter of the input clock signal is passed along directly to the distribution section and may dominate at the clock outputs.
AD9510
PLL REFERENCE DIVIDER
The REFIN/REFINB inputs are routed to reference divider, R, which is a 14-bit counter. R may be programmed to any value from 0 to 16383 via its control register. The output of the R divider goes to one of the phase/frequency detector inputs. The maximum allowable frequency into the phase/frequency detector (PFD) must not be exceeded. This means that the REFIN frequency divided by R must be less than the maximum allowable PFD frequency.
VCO/VCXO CLOCK INPUT
The CLK2 differential input may be used as a second distribution input, or it may be used to connect an external VCO or VCXO to the PLL . Only the CLK2 input port has a connection to the PLL N divider. This input can receive up to 1.5 GHz. These inputs are internally self-biased and must be capacitively coupled. CLK1 is electrically identical, but normally feeds the distribution section instead. See Figure 16 for the equivalent circuit of CLK1/CLK2.
VCO/VCXO FEEDBACK DIVIDER
The N divider is a combination of a prescaler and two counters, A and B. Although the AD9510's PLL is similar to the ADF4106, the AD9510 has a redesigned prescaler that allows for lower values of N. The prescaler has both a dual modulus (DM) mode and a fixed divide (FD) mode. The AD9510 prescaler modes are shown in Table 14. Table 14. PLL Prescaler Modes
Mode (FD = Fixed Divide; DM = Dual Modulus) FD FD P = 2 DM P = 4 DM P = 8 DM P = 16 DM P = 32 DM FD Divide By 1 2 P/P + 1 = 2/3 P/P + 1 = 4/5 P/P + 1 = 8/9 P/P + 1 = 16/17 P/P + 1 = 32/33 3
PLL OPERATION
The AD9510 has a complete PLL core on-chip, requiring only an external loop filter and VCO/VCXO. This PLL is based on the ADF4106, a PLL noted for its superb low phase noise performance. The operation of the AD9510 PLL is nearly identical to that of the ADF4106, offering an advantage to those with experience with the ADF series of PLLs. Differences include the addition of differential inputs at REFIN and CLK2, a different control register architecture, and the prescaler has been changed to allow N as low as 1. The AD9510 PLL also implements the digital lock detect feature somewhat differently than does the ADF4106 offering improved functionality at higher PFD rates. Refer to Register Map Description for details. The PLL section can be used entirely separately from the distribution system, if so desired.
When using the prescaler in a FD mode, the A counter is not used, and the B counter may need to be bypassed. The DM prescaler modes set some upper limits on the frequency, which can be applied to CLK2 . These are shown in Table 15.
PLL REFERENCE INPUT
The REFIN and REFINB pins can be driven differentially or single-ended. These pins are internally self-biased, so they should always be capacitively coupled. This also applies to the unused side when single-ended input is used.
Rev. PrA | Page 21 of 41
AD9510
Table 15. Frequency Limits per Prescaler Mode
Mode (DM = Dual Modulus) P = 2 DM (2/3) P = 4 DM (4/5) P = 8 DM (8/9) P = 16 DM P = 32 DM CLK2 < 500 MHz < 750 MHz < 1.5 GHz < 1.5 GHz < 1.5 GHz
Preliminary Technical Data
SETTING VALUES FOR P, A, B, AND R
When operating the AD9510 in a dual-modulus mode, the input reference frequency, FREF, is related to the VCO output frequency, FVCO. FVCO = (FREF/R) x (PB + A) = FREF x N/R When operating the prescaler in a fixed divide mode the A counter is not used and the equation simplifies to FVCO = (FREF/R) x (PB) = FREF x N/R By using combinations of dual modulus and fixed divide modes, the AD9510 can achieve values of N all the way down to N = 1. Table 16 shows how a 10 MHz reference input may be locked to any integer multiple of N. Note that the same value of N may be derived in different ways, as illustrated by the case of N = 12.
A AND B COUNTERS
The AD9510 B Counter has a bypass mode (B = 1) that is not available on the ADF4106. The B counter bypass mode is only valid when using the prescaler in a FD mode. The B counter is bypassed by writing 1 to the B counter bypass bit in the register map. Note that the A counter is not used when prescaler is in FD mode. Note also that the A/B Counters have their own reset bit that is primarily intended for test. A and B counters can also be reset using the shared R, A, and B counters reset bit. Table 16. P, A, B, R - Smallest Values for N
FREF 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 P 1 2 1 1 1 2 2 2 2 2 2 2 2 2 2 4 4 A X X X X X X 0 1 2 1 X 0 1 X 0 0 1 B 1 1 3 4 5 3 3 3 3 4 5 5 5 6 6 3 3 N 1 2 3 4 5 6 6 7 8 9 10 10 11 12 12 12 13 FVCO 10 20 30 40 50 60 60 70 80 90 100 100 110 120 120 120 130
Mode FD FD FD FD FD FD DM DM DM DM FD DM DM FD DM DM DM
Notes P = 1, B = 1 (Bypassed) P = 2, B = 1 (Bypassed) P = 1, B = 3 P = 1, B = 4 P = 1, B = 5 P = 2, B = 3 P/P + 1 = 2/3, A = 0, B = 3 P/P + 1 = 2/3, A = 1, B = 3 P/P + 1 = 2/3, A = 2, B = 3 P/P + 1 = 2/3, A = 1, B = 4 P = 2, B = 5 P/P + 1 = 2/3, A = 0, B = 5 P/P + 1 = 2/3, A = 1, B = 5 P = 2, B = 6 P/P + 1 = 2/3, A = 0, B = 6 P/P + 1 = 4/5, A = 0, B = 3 P/P + 1 = 4/5, A = 1, B = 3
Rev. PrA | Page 22 of 41
Preliminary Technical Data
control for analog lock detect mode
AD9510
Sync Detect
Off (low) (default) Digital Lock Detec (active high) N Divider Output Digital Lock Detec (active low) R Divider Output Analog Lock Detec (n-channel open drain) A Counter Output Prescaler Outpu (NCLK) PFD U Pulse PFD Down Pulse Loss o Reference (active high) TriState Analog Lock Detec (p-channel open drain) Loss o reference or Lock Detec (active high) Loss o reference or Lock Detec (active low) Loss o Reference (active low)
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP
The PFD takes inputs from the R counter and N counter (N = BP + A) and produces an output proportional to the phase and frequency difference between them. Figure 14 is a simplified schematic. The PFD includes a programmable delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs. Two bits in Register 0D <1:0> control the width of the pulse.
VP CHARGE PUMP HI D1 Q1 U1 R DIVIDER CLR1 UP
VS
STATUS pin
GND
SYNC DETECT ENABLE 58h <0>
PLL MUX CONTROL 08h <5:2>
Figure 15. STATUS Pin Circuit
CLK1 CLOCK INPUT
CLK1 is the distribution only clock input. This clock input is selected by default on power-up. It is usable for inputs up to 1500 MHz.
PROGRAMMABLE DELAY
U3 CP
Antibacklash pulse width
CLK2 is electrically identical but feeds the PLL N divider as well as being selectable as the input for the distribution section through the clock select MUX. If the distribution section is being used only, it is recommended that the unselected clock input be powered down in order to eliminate any possibility of unwanted crosstalk between the selected clock input and the unselected clock input.
HI
CLR2 DOWN D2 Q2 U2
N DIVIDER GND
Clock input stage
Figure 14. PFD Simplified Schematic and Timing (In Lock)
STATUS PIN
The output multiplexer on the AD9510 allows access to various internal points on the chip. The state of the STATUS pin is controlled by Register 08 <5:2>. Figure 15 shows the STATUS pin section in block diagram form.
VS
CLK
Lock Detect
The STATUS pin can be programmed for two types of lock detect: digital and analog. See Table 20 OD <5> for the description of this function. The N-channel, open-drain, analog lock detect should be operated with an external pull-up resistor of 30 k nominal. When lock is detected, the output is high with narrow, low going pulses.
CLKB
2.5k
2.5k
5k
5k
Figure 16. CLK1, CLK2 Equivalent Input Circuit
Rev. PrA | Page 23 of 41
AD9510 SERIAL CONTROL PORT
The AD9510 serial control port is a flexible, synchronous, serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. The AD9510 serial control port is compatible with most synchronous transfer formats, including both the Motorola SPI(R) and Intel(R) SSR protocols. The serial control port allows read/write access to all registers that configure the AD9510. Single or multiple byte transfers are supported, as well as MSB first or LSB first transfer formats. The AD9510 serial control port can be configured for single pin I/O (SDIO only) or two unidirectional pins for in/out (SDIO/SDO).
Preliminary Technical Data
Write
If the instruction word (Phase 1) is for a write operation (I15 = 0), then Phase 2 is the transfer of data into the serial control port buffer of the AD9510. The length of the transfer (1, 2, 3, or 4 data bytes) is indicated by 2 bits (W1:W0) in the instruction byte. Multibyte data transfer is the preferred method. Single byte data transfers are useful to reduce CPU overhead when only one byte of data needs to be loaded. CSB can be raised after each sequence of 8 bits (except the last byte) to stall the bus. The serial transfer resumes when CSB is lowered. Stalling on nonbyte boundaries resets the serial control port. Since data is written into a serial control port buffer area, not directly into the AD9510's actual control registers, a Phase 3 operation is needed in order to transfer the serial control port buffer contents to the actual control registers of the AD9510, thereby causing them to take effect. Phase 3 consists of writing a high bit (one) to Address 5Ah, Bit <0>. This update bit is selfclearing (it is not required to write a 0 to it in order to clear it). Since any number of bytes of data may be changed before issuing an update, the update simultaneously enables all register changes since any previous update.
SERIAL CONTROL PORT PIN DESCRIPTIONS
SCLK (serial clock) is the serial shift clock. This pin is an input. SCLK is used to synchronize serial control port reads and writes. Write data bits are registered on the rising edge of this clock, and read data bits are registered on the falling edge. This pin is internally pulled down by a 30 k resistor to ground. SDIO (serial data input/output) is a dual-purpose pin and acts as either an input only in 4-wire mode or as an input/output in 3-wire mode. The AD9510 defaults to 3-wire mode (single pin I/O--SDIO only). Four-wire mode (two unidirectional pins for I/O - SDIO/SDO) may be enabled by setting 1 into the SDO enable register at Address 00h, Bit <7>. SDO (serial data out) is used in the 4-wire mode only as a separate output pin for readback data. The AD9510 defaults to 3-wire mode. Four-wire mode may be enabled by setting 1 into the SDO enable register at Address 00h, Bit <7>. CSB (chip select bar) is an active low control that gates the read and write cycles. When CSB is high, SDO and SDIO are in a high impedance state. This pin is internally pulled down by a 30 k resistor to ground.
SCLK (pin 18) SDI0 (pin 19) SD0 (pin 20) CSB (pin 21) AD9510 SERIAL CONTROL PORT
Read
If the instruction word (Phase 1) is for a read operation (I15 = 1), the next N x 8 SCLK cycles clock out the data from the address specified in the instruction word, where N is 1 to 4 as determined by W1:W0. The readback data is valid on the falling edge of SCLK. The default mode of the AD9510 serial control port is 3-wire mode; therefore, the requested data normally appears on the SDIO pin. It is possible to set the AD9510 to 4-wire mode by setting 1 into the SDO enable register at Address 00h, Bit <7>. In 4-wire mode, the readback data appears on the SDO pin. A readback request reads the data that is in the serial control port buffer area not the active data in the AD9510's actual control registers.
Figure 17. Serial Control Port
REGISTER BUFFERS
There are three phases to a communication cycle with the AD9510. Phase 1 is the instruction cycle, which is the writing of a 16-bit instruction word into the AD9510, coincident with the first 16 SCLK rising edges. The instruction word provides the AD9510 serial control port with information regarding the data transfer cycle (Phase 2) of the communication cycle. The Phase 1 instruction word defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer.
SCLK
SDIO SDO CSB
* UPDATE REGISTERS 5Ah <0>
SERIAL CONTROL PORT
Figure 18. Relationship between Serial Control Port Register Buffers and Control Registers of the AD9510
Rev. PrA | Page 24 of 41
CONTROL REGISTERS
AD9510 CORE
GENERAL OPERATION OF SERIAL CONTROL PORT
Preliminary Technical Data
The AD9510 uses Addresses 00h to 5Ah. Although the AD9510 serial control port allows for both 8-bit and 16-bit instructions, the 8-bit instruction mode provides access only to five address bits (A4 to A0), which restricts its use to the address space 00h to 01F. The AD9510 defaults to 16-bit instruction mode on power-up. The 8-bit instruction mode (although defined for this serial control port) is not useful for the AD9510; therefore, it is not discussed in this data sheet.
AD9510
MSB/LSB FIRST TRANSFERS
The AD9510 instruction word and byte data may be MSB first or LSB first. The default for the AD9510 is MSB first. The LSB first mode may be set by writing 1 to Address 00h, Bit <6>. This takes effect immediately (since it only affects the operation of the serial control port) and does not require that an update be executed. Immediately after the LSB first bit is set, all serial control port operations are changed to LSB first order. When MSB first mode is active, the instruction and data bytes must be written from MSB to LSB. Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes must follow in order from high address to low address. In MSB first mode, the serial control port internal byte address generator decrements for each data byte of the multibyte transfer cycle. When LSB_First = 1 (LSB first), the instruction and data bytes must be written from LSB to MSB. Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. The serial control port internal byte address generator increments for each byte of the multibyte transfer cycle. The AD9510 serial control port data address decrements from the data address written toward 0x00 for multibyte I/O operations if the MSB first mode is active. The serial control port address increments from the data address written toward 0x1F for multibyte I/O operations if the LSB first mode is active.
THE INSTRUCTION WORD (16 BITS)
The MSB of the instruction word is R/W , which indicates whether the instruction will be a read or a write. The next two bits, W1:W0, indicate the length of the transfer in bytes. The final 13 bits are the address (A12:A0) at which to begin the read or write operation. For a write, the instruction word is followed by the number of bytes of data indicated by Bits W1:W0, which is interpreted according to Table 17. Table 17. Byte Transfer Count
W1 0 0 1 1 W0 0 1 0 1 Bytes to Transfer 1 2 3 4
A12:A0: These 13 bits select the address within the register map which is written to or read from during the data transfer portion of the communications cycle. For multibyte transfers, this address is the starting byte address. In MSB first mode, subsequent bytes increment the address.
Table 18. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB I15 R/W I14 W1 I13 W0 I12 A12 I11 A11 I10 A10 I9 A9 I8 A8 I7 A7 I6 A6 I5 A5 I4 A4 I3 A3 I2 A2 I1 A1 LSB I0 A0
Rev. PrA | Page 25 of 41
AD9510
Preliminary Technical Data
CSB
SCLK DON'T CARE
DON'T CARE
SDIO DON'T CARE
R/W
W1 W0 A11 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
DON'T CARE
16 BIT INSTRUCTION HEADER
REGISTER (N) DATA
REGISTER (N-1) DATA
Figure 19. Serial Control Port Write--MSB First, 16-Bit Instruction, 2 Bytes Data
CSB
SCLK DON'T CARE
DON'T CARE
SDIO
DON'T CARE
R/W
W1 W0 A11 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DON'T CARE
SDO
DON'T CARE
D7 16 BIT INSTRUCTION HEADER
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
DON'T CARE
REGISTER (N) DATA
REGISTER (N-1) DATA
REGISTER (N-2) DATA
REGISTER (N-3) DATA
Figure 20. Serial Control Port Read--MSB First, 16-Bit Instruction, 4 Bytes Data
tDS tS
CSB
tHI tDH tLO
tCLK
tH
SCLK
DON'T CARE
DON'T CARE
SDIO
DON'T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
D4
D3
D2
D1
D0
DON'T CARE
Figure 21. Serial Control Port Write-MSB First, 16-Bit Instruction, Timing Measurements
CSB
SCLK
tDV
SDIO SDO DATA BIT n DATA BIT n -1
Figure 22. Timing Diagram for Serial Control Port Register Read
CSB
SCLK DON'T CARE
DON'T CARE
SDIO DON'T CARE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10 A11 A12 W0 W1 R/W
03152-PrD-007
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
DON'T CARE
16 BIT INSTRUCTION HEADER
REGISTER (N) DATA
REGISTER (N+1) DATA
Figure 23. Serial Control Port Write--LSB First, 16-Bit Instruction, 2 Bytes Data
Rev. PrA | Page 26 of 41
Preliminary Technical Data REGISTER MAP AND DESCRIPTION
SUMMARY TABLE
Table 19. AD9510 Register Map
Addr (Hex) 00 Parameter Name Serial Control Port Configuration Bit 7 (MSB) SDO Active Bit 0 (LSB) SDO Active Def. Value (Hex) 10
AD9510
Bit 6 LSB First
Bit 5 Soft Reset
Bit 4 Long_Ins
Bit 3 Long_Ins
Bit 2 Soft Reset
Bit 1 LSB First
Notes <7:4> Mirror <3:0>
01 02 03 PLL
Blank Reserved Blank PLL Starts in PowerDown N Divider (A) N Divider (B) N Divider (B)
04 05 06 07 08 09 0A 0B 0C 0D
A Counter B Counter B Counter PLL 1 PLL 2 PLL 3 PLL 4 R Divider R Divider PLL 5
Blank Blank
6-Bit A Counter <5:0> 13-Bit B Counter Bits (MSB) 12:8 <4:0> 13-Bit B Counter Bits 7:0 (LSB) <7:0>
00 00 00 Test Test 00 00 00 01 00 00 00
Reserved Reserved Reserved Reserved
LOR lock_del <6:5>
LOR Mode <4:3>
LOR Enable
PLL Mux Select <5:2> PFD Polarity CP Current <6:4> Reserved B Bypass Reserved
CP Mode <1:0> Reset N Reset All Counter Counters Power-Down <1:0>
Reset R Counter Prescaler P <4:2>
Blank Reserved Digital Lock Det. Enable
OE33 FINE DELAY ADJUST 34 35 36 37 38 39 3A Delay Bypass 5 Delay FullScale 5 Delay Word 5 Delay FS Adjust 5 Delay Bypass 6 Delay FullScale 6 Delay Word 6 Blank Blank Blank Blank
14-Bit R Divider Bits (MSB) 13:8 <5:0> 14-Bit R Divider Bits (MSB) 13:8 <5:0> Reserved Digital Antibacklash PulseLock Width <1:0> Det. Window Blank
N Divider (P) R Divider R Divider
Blank Ramp Capacitor <5:3>
Bypass Ramp Current <2:0>
01 00 00 04 01 00 00
6-Bit Delay Word <5:0> Blank Blank Ramp Capacitor <5:3> I Adjust for Process <2:0> Bypass Ramp Current <2:0>
Fine Delays Bypassed Bypass Delay Max. Delay Full-Scale Min. Delay Value Midpoint Bypass Delay Max. Delay Full-Scale Min. Delay Value
6-Bit Delay Word <5:0>
Rev. PrA | Page 27 of 41
AD9510
Addr (Hex) 3B Parameter Name Delay FS Adjust 6 OUTPUTS LVPECL OUT0 LVPECL OUT1 LVPECL OUT2 LVPECL OUT3 LVDS_CMOS OUT 4 Bit 7 (MSB) Bit 6 Bit 5 Blank Bit 4 Bit 3
Preliminary Technical Data
Bit 0 Bit 2 Bit 1 (LSB) I Adjust for Process <2:0> Def. Value (Hex) 04 Notes Midpoint
3C 3D 3E 3F 40
Blank Blank Blank Blank Blank CMOS Inverted Driver On CMOS Inverted Driver On CMOS Inverted Driver On CMOS Inverted Driver On Test
Output Level <3:2> Power-Down <1:0> Output Level <3:2> Power-Down <1:0> Output Level <3:2> Power-Down <1:0> Output Level <3:2> Power-Down <1:0> Output Level <2:1> Logic Output Select Power
0A 08 08 08 02
OFF ON ON ON LVDS, ON
41
LVDS_CMOS OUT 5
Blank
Logic Select
Output Level <2:1>
Output Power
02
LVDS, ON
42
LVDS_CMOS OUT 6
Blank
Logic Select
Output Level <2:1>
Output Power
03
LVDS, OFF
43
LVDS_CMOS OUT 7
Blank
Logic Select
Output Level <2:1>
Output Power
03
LVDS, OFF
44 CLK1 AND CLK2 Clocks select, Power-Down (PD) Options DIVIDERS Divider 0 Divider 0 Divider 1 Divider 1 Divider 2 Divider 2 Divider 3 Divider 3 Divider 4 Divider 4 Divider 5 Divider 5 Divider 6 Divider 6 Divider 7
Blank
Test Input Receivers All Clocks ON, Select CLK1
45
Test
CLKs in PD
REFIN PD
CLK to PLL PD
CLK2 PD
CLK1 PD
Select CLK IN
01
46,47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 Low Cycles <7:4> Force No Sync Low Cycles <7:4> Force No Sync Low Cycles <7:4> Force No Sync Low Cycles <7:4> Force No Sync Low Cycles <7:4> Force No Sync Low Cycles <7:4> Force No Sync Low Cycles <7:4> Force No Sync Low Cycles <7:4>
Blank High Cycles <3:0> Phase Offset <3:0> High Cycles <3:0> Phase Offset <3:0> High Cycles <3:0> Phase Offset <3:0> High Cycles <3:0> Phase Offset <3:0> High Cycles <3:0> Phase Offset <3:0> High Cycles <3:0> Phase Offset <3:0> High Cycles <3:0> Phase Offset <3:0> High Cycles <3:0> 00 00 00 00 11 00 33 00 00 00 11 00 00 00 00 Divide by 2 Phase = 0 Divide by 2 Phase = 0 Divide by 4 Phase = 0 Divide by 8 Phase = 0 Divide by 2 Phase = 0 Divide by 4 Phase = 0 Divide by 2 Phase = 0 Divide by 2
Bypass
Start H/L
Bypass
Start H/L
Bypass
Start H/L
Bypass
Start H/L
Bypass
Start H/L
Bypass
Start H/L
Bypass
Start H/L
Rev. PrA | Page 28 of 41
Preliminary Technical Data
Addr (Hex) 57 Parameter Name Divider 7 FUNCTION FUNCTION Pin and Sync Bit 7 (MSB) Bypass Bit 6 No Sync Bit 5 Force Bit 4 Start H/L Bit 3 Bit 2 Bit 1 Phase Offset <3:0> Bit 0 (LSB) Def. Value (Hex) 00
AD9510
Notes Phase = 0
58
Reserved
Set FUNCTION Pin
PD Sync
PD All Ref.
Sync Reg.
Sync Select
Sync Enable
00
FUNCTION Pin = RESETB SelfClearing Bit
59 5A
Update Registers END
Reserved Blank
Update Registers
00
Rev. PrA | Page 29 of 41
AD9510
REGISTER MAP DESCRIPTION
Preliminary Technical Data
The is a detailed description of each of the control register functions. The registers are listed by hexadecimal address. Reference to a specific bit or range of bits within a register is accomplished by the use of angle brackets. For example, <3> refers to Bit 3, while <5:2> refers to the range of bits from Bit 5 through Bit 2. Table 20 describes the functionality of the control registers on a bit-by-bit basis. For a more concise (but less descriptive) table see Table 19. Table 20. AD9510 Register Descriptions
Reg. Addr. (Hex)
Bit(s)
00 00
<0> <1>
Name Serial Control Port Configuration SDO Active LSB First
00
<2>
Soft Reset
00 00 00 00 00 01 02 03 04 04 05 05 06 07 07 07 07
<3> <4> <5> <6> <7> <7:0> <7:0> <7:0>
Long Instruction Long Instruction Soft Reset LSB First SDO Active Unused
Description Note: <7:4> mirror <3:0> to ensure that this register can be accessed regardless of the state of <1> or <6> (the bit that sets LSB first). When set causes SDO to become active. When clear, the SDO pin remains in tri-state and all read data is routed to the SDIO pin. (Default = 0.) When set causes input and output data to be oriented as LSB first. Additionally, addressing increments. If this bit is clear, data is oriented as MSB first and addressing decrements. (Default = 0, MSB first.) When a 1 is written to this bit, the chip executes a soft reset, restoring default values to all of the internal registers. This bit is self-clearing. A 0 does not have to be written to clear it. When set, the instruction phase is 16 bits. When clear, the instruction phase is 8 bits. The default, and only, mode for this part is long instruction. (Default = 1.) Same as <3>. Same as <2>. Same as <1>. Same as <0>. Reserved or not used. Reserved or not used. Reserved or not used.
PLL Settings <5:0> <7:6> <4:0> <7:5> <7:0> <1:0> <2> <4:3> <6:5> LOR Enable B Counter LSBs B Counter MSBs A Counter 6-bit A counter <5:0>. Reserved or not used. 13-bit B counter (MSB) <12:8>. Reserved or not used. 13-bit B counter (LSB) <7:0>. Reserved or not used. 1 = enables the loss of reference (LOR) function; (Default = 0). Reserved or not used (default = 00). LOR Initial Lock Detect LOR initial lock detect delay. Once a lock detect is indicated, this is the number of phase Delay frequency detector (PFD) cycles that occur prior to turning on the LOR monitor. <6> <5> LOR Initial Lock Deteck Delay 0 0 1 1 07 <7> Reserved or not used 0 1 0 1 3 PFD Cycles (Default) 6 PFD Cycles 12 PFD Cycles 24 PFD Cycles
Rev. PrA | Page 30 of 41
Preliminary Technical Data
Reg. Addr. (Hex) 08 Bit(s) <1:0> Name Charge Pump Mode Description <1> 0 0 1 1 08 <5:2> PLL Mux Control <5> 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 08 08 09 09 09 09 09 <6> <7> <0> <1> <2> <3> <6:4> Charge Pump (CP) Current Setting <6> 0 0 0 0 1 1 1 1 <5> 0 0 1 1 0 0 1 1 <4> 0 1 0 1 0 1 0 1 ICP (mA) 0.62 1.25 1.87 2.50 3.12 3.75 4.37 5.00 <4> 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 <3> 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 <2> MUXOUT 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Off (Signal Goes Low) (Default) Digital Lock Detect (Active High) N Divider Output Digital Lock Detect (Active High) R Divider Output Analog Lock Detect (N Channel Open-Drain) A Counter Output Prescaler Output (NCLK) PFD Up Pulse PFD Down Pulse Loss of Reference (Active High) Tri-State Analog Lock Detect (P Channel Open-Drain) Loss of Reference or Lock Detect (Active High) Loss of Reference or Lock Detect (Active Low) Loss of Reference (Active High) <0> 0 1 0 1
AD9510
Charge Pump Mode Tri-Stated (Default) Pump Up Pump Down Normal Operation
MUXOUT is the PLL portion of the STATUS Output MUX. 0 = negative (default), 1 = positive. Phase-Frequency Detector (PFD) Polarity Reserved or not used. Reset All Counters N-Counter Reset R-Counter Reset 0 = normal (default), 1 = reset R, A, and B counters. 0 = normal (default), 1 = reset A and B counters. 0 = normal (default), 1 = reset R counter. Reserved or not used.
Rev. PrA | Page 31 of 41
AD9510
Reg. Addr. (Hex) Bit(s) Name Description Default = 000. These currents assume: CP_RSET = 5.1 k.
Preliminary Technical Data
Actual current can be calculated by: CP_lsb = 3.1875/CP_RSET. 09 0A <7> <1:0> PLL Power-Down Reserved or not used. 01 = asynchronous power-down (default). <1> 0 0 1 1 0A <4:2> Prescaler Value P/P+1 <4> 0 0 0 0 1 1 1 1 0A 0A <5> <6> B Counter Bypass <3> 0 0 1 1 0 0 1 1 <2> 0 1 0 1 0 1 0 1 Mode FD FD DM DM DM DM DM FD Prescaler Mode Divide-by-1 Divide-by-2 2/3 4/5 8/9 16/17 32/33 Divide-by-3 <0> 0 1 0 1 Mode Normal Operation Asynchronous Power-Down Normal Operation Synchronous Power-Down
DM = Dual Modulus, FD = Fixed Divide. Reserved or not used. Only valid when operating the prescaler in fixed divide (FD) mode. When this bit is set, the B counter is divide-by-1. This allows the prescaler setting to determine the divide for the N divider. Reserved or not used. R divider (MSB) <13:8>. R divider (MSB) <7:0>.
0A 0B 0C 0D
<7> <5:0> <7:0> <1:0> 14-Bit Reference Counter, MSBs 14-Bit Reference Counter, R LSBs Antibacklash PulseWidth
<1> 0 0 1 1 0D 0D <4:2> <5> Digital Lock Detect Window Reserved or not used.
<0> 0 1 0 1
Antibacklash Pulse-Width (ns) 1.3 (Default) 2.9 6.0 1.3
Digital Lock Detect Window (ns) 0 (Default) 9.5 1 3.5
<5>
Digital Lock Detect Loss of Lock Threshold (ns) 15 7
Rev. PrA | Page 32 of 41
Preliminary Technical Data
Reg. Addr. (Hex) Bit(s) Name
AD9510
Description If the time difference of the rising edges at the inputs to the PFD are less than the lock detect window time, the digital lock detect flag is set. The flag remains set until the time difference is greater than loss-of-lock threshold. 0 = normal lock detect operation (default). 1 = disable lock detect. Reserved or not used. Reserved or not used.
0D 0D 0E-33
<6> <7>
Lock Detect Disable
Unused Fine Delay Adjust <0> 34 (38) 34 (38) 35 (39) Delay Control OUT5 (OUT6) Delay block control bit. Bypasses delay block and powers it down (default = 1). Reserved or not used. Ramp Control OUT5 (OUT6)
<7:1> <2:0>
The slowest ramp (200 s) sets the longest full scale of approximately 10 ns. <2> 0 0 0 0 1 1 1 1 <1> 0 0 1 1 0 0 1 1 <0> 0 1 0 1 0 1 0 1 Ramp Current (s) 200 400 600 800 1000 1200 1400 1600
<5:3> 35 (39)
Ramp Control OUT5 (OUT6)
Selects the number of capacitors in ramp generation circuit. More capacitors => slower ramp. <5> 0 0 0 0 1 1 1 1 <4> 0 0 1 1 0 0 1 1 <3> 0 1 0 1 0 1 0 1 Number of Capacitors 4 (Default) 3 3 2 3 2 2 1
<5:0> 36 (3A)
Reference Value OUT5 (OUT6)
Sets delay within full scale of the ramp. There are 64 steps to control the reference value for the comparator. 000000 => zero delay (default). 111111 => maximum delay. The delay fine tune slightly increases or decreases the ramp current (-8% to +13%) to negate the process variation of the caps. Defaults to 100, which is the midpoint.
<2:0> 37 (3B)
Delay Fine Tune OUT5 (OUT6)
Rev. PrA | Page 33 of 41
AD9510
Reg. Addr. (Hex) Bit(s) <1:0> Name Power Down LVPECL OUT0 (OUT1) (OUT2) (OUT3) Description
Preliminary Technical Data
3C (3D) (3E) (3F)
Mode ON PD1 PD2
<1> 0 0 1
<0> 0 1 0
Description
Output
Normal operation ON Test only--do not OFF use Safe power-down OFF Partial powerdown; use if output has load resistors OFF Total powerdown Use only if output has no load resistors
PD3
1
1
<3:2> 3C (3D) (3E) (3F)
Output Level LVPECL OUT0 (OUT1) (OUT2) (OUT3)
This sets output single-ended voltage levels for LVPECL outputs
<3> 0 0 1 1 3C (3D) (3E) (3F) 40 (41) (42) (43) <7:4> Reserved or not used.
<2> 0 1 0 1
Output Voltage (mV) 490 330 805 (Default) 650
<0>
Power-Down LVDS/CMOS OUT4 (OUT5) (OUT6) (OUT7) Output Current Level LVDS OUT4 (OUT5) (OUT6) (OUT7)
Power-down bit for both output and LVDS driver. 0 = LVDS/CMOS on (default). 1 = LVDS/CMOS power-down.
40 (41) (42) (43)
<2:1>
Rev. PrA | Page 34 of 41
Preliminary Technical Data
Reg. Addr. (Hex) Bit(s) Name Description <2> 0 0 1 1 40 (41) (42) (43) <3> LVDS/CMOS Select OUT4 (OUT5) (OUT6) (OUT7) Inverted CMOS Driver OUT4 (OUT5) (OUT6) (OUT7) 0 = LVDS (default). 1 = CMOS.
AD9510
<1> 0 1 0 1
Current (mA) 1.75 3.5 (Default) 5.25 7
Termination () 100 100 50 50
<4> 40 (41) (42) (43) 40 (41) (42) (43) 44 45 45 45 45 45 45 45 46 47 48 (4A) (4C) (4E) (50) (52) (54) (56) <7:5>
Affects output only when in CMOS mode. 0 = disable inverted CMOS driver (default). 1 = enable inverted CMOS driver.
Reserved or not used.
<7:0> <0> <1> <2> <3> <4> <5> <7:6> <7:0> <7:0> <3:0> Divider High OUT0 (OUT1) (OUT2) (OUT3) (OUT4) (OUT5) (OUT6) (OUT7) Clock Select CLK1 Power-Down CLK2 Power-Down
Reserved or not used. 0: CLK2 drives distribution section. 1: CLK1 drives distribution section (default). 1 = CLK1 input is powered down (default = 0). 1 = CLK2 input is powered down (default = 0).
Prescaler Clock Power- 1 = shut down clock signal to PLL prescaler (default = 0). Down REFIN Power-Down 1 = power-down REFIN (default = 0). All Clock Inputs Power- 1 = power-down CLK1 and CLK2 inputs and associated bias and internal clock tree; Down (default = 0). Reserved or not used. Reserved or not used. Reserved or not used. Number of clock cycles divider output stays high.
Rev. PrA | Page 35 of 41
AD9510
Reg. Addr. (Hex) 48 (4A) (4C) (4E) (50) (52) (54) (56) <3:0> 49 (4B) (4D) (4F) (51) (53) (55) (57) <4> 49 (4B) (4D) (4F) (51) (53) (55) (57) <5> 49 (4B) (4D) (4F) (51) (53) (55) (57) <6> 49 (4B) (4D) (4F) (51) (53) (55) (57) Bit(s) <7:4> Name Divider Low OUT0 (OUT1) (OUT2) (OUT3) (OUT4) (OUT5) (OUT6) (OUT7) Phase Offset OUT0 (OUT1) (OUT2) (OUT3) (OUT4) (OUT5) (OUT6) (OUT7) Start OUT0 (OUT1) (OUT2) (OUT3) (OUT4) (OUT5) (OUT6) (OUT7) Force OUT0 (OUT1) (OUT2) (OUT3) (OUT4) (OUT5) (OUT6) (OUT7) Nosync OUT0 (OUT1) (OUT2) (OUT3) (OUT4) (OUT5) (OUT6) (OUT7) Description Number of clock cycles divider output stays low.
Preliminary Technical Data
Phase offset (default = 0000).
Selects start high or start low. (Default = 0).
Forces individual outputs to the state specified in start (above). This function requires that Nosync (below) also be set. (Default = 0).
Ignore chip-level sync signal (default = 0).
Rev. PrA | Page 36 of 41
Preliminary Technical Data
Reg. Addr. (Hex) 49 (4B) (4D) (4F) (51) (53) (55) (57) 58 58 58 <0> <1> <2> Bit(s) <7> Name Bypass Divider OUT0 (OUT1) (OUT2) (OUT3) (OUT4) (OUT5) (OUT6) (OUT7) Other SYNC Detect Enable SYNC Select Soft SYNC Description Bypass and power-down divider logic; route clock directly to output (default = 0).
AD9510
1 = enable SYNC detect (default = 0). 1 = raise flag if slow clocks are out-of-sync by 0.5 to 1 high speed clock cycles. 0 (default) = raise flag if slow clocks are out-of-sync by 1 to 1.5 high speed clock cycles. Soft SYNC bit works the same as the FUNCTION pin when in SYNCB mode, except that this bit's polarity is reversed. That is a High level forces selected outputs into a known state, and a High > Low transition triggers a sync (default = 0). 1 = power-down the references for the distribution section (default = 0). 1 = power-down the SYNC (default = 0).
58 58 58
<3> <4> <6:5>
Dist Ref Power Down SYNC Power Down FUNCTION Pin Select
<6> 0 0 1 1 58 59 5A <7> <7:0> <0> Update Registers Reserved or not used. Reserved or not used.
<5> 0 1 0 1
Function RESETB (Default) SYNCB Test Only; Do Not Use PDB
5A
<7:1> END
A 1 written to this bit updates all registers and transfers all serial control port register buffer contents to the control registers on next rising SCLK edge. This is a self-clearing bit. A 0 does not have to be written in order to clear it. Reserved or not used.
Rev. PrA | Page 37 of 41
AD9510 APPLICATIONS
USING THE AD9510 OUTPUTS FOR ADC CLOCK APPLICATIONS
Any high speed analog-to-digital converter (ADC) is extremely sensitive to the quality of the sampling clock provided by the user. An ADC can be thought of as a sampling mixer; and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the A/D output. Clock integrity requirements scale with the analog input frequency and resolution, with higher analog input frequency applications at >= 14-bit resolution being the most stringent. The theoretical SNR of an ADC is limited by the ADC resolution and the jitter on the sampling clock. Considering an ideal ADC of infinite resolution where the step size and quantization error can be ignored, the available SNR is can be expressed approximately by
Preliminary Technical Data
CMOS CLOCK DISTRIBUTION
The AD9510 provides four clock outputs (OUT4 to OUT7) which are selectable as either CMOS or LVDS levels. When selected as CMOS, these outputs provide a way to drive devices requiring CMOS level logic at their clock inputs. Due to factors inherent to CMOS logic, the jitter performance of these outputs cannot equal that of the LVPECL and LVDS outputs. However, for many clocking needs within a system, CMOS clock levels are appropriate. Whenever single-ended CMOS clocking is used, some of the following general guidelines should be followed. Point-to-point nets should be designed such that a driver only has one receiver on the net, if possible. This allows for simple termination schemes and minimize ringing due to possible mismatched impedances on the net. Series termination at the source is generally required to provide transmission line matching and/or to reduce current transients at the driver. The value of the resistor is dependent on board design and timing requirements (typically 10 to 100 is used). CMOS outputs are also limited in terms of the capacitive load or trace length that they can drive, typically trace lengths less than 3 inches are recommended to preserve signal rise/fall times and preserve signal integrity. Simulation results for the AD9510 CMOS outputs with a 1-inch and 3-inch trace load are shown in Figure 26. In this example, the series resistor is 10 and the trace impedance is 60 . Signal integrity, in this example, has started to degrade already at a 3-inch trace length.
1 SNR = 20 x log 2ft J where f is the highest analog frequency being digitized, and tj is the rms jitter on the sampling clock. The figure below shows required sampling clock jitter as function of analog frequency and effective number of bits (ENOB)
Figure 24. ENOB and SNR vs. Analog Input Frequency
(See Application Note AN-501 at www.analog.com for more information). Many high performance ADC's feature differential clock inputs to simplify the task of providing the required low jitter clock on a noisy PCB. (Distributing a single-ended clock on a noisy PCB can result in coupled noise on the sample clock. Differential distribution has inherent common-mode rejection that can provide superior clock performance in a noisy environment.) The AD9510 features both LVPECL and LVDS outputs that provide differential clock outputs, which enable clock solutions that maximize converter SNR performance. The input requirements of the ADC (differential or single-ended, logic level, termination) should be considered when selecting the best clocking/converter solution.
Rev. PrA | Page 38 of 41
Figure 25. Series Termination of CMOS Output
Preliminary Technical Data
AD9510
Because of the limitations of single-ended CMOS clocking, consider using differential outputs when driving high speed signals over long traces. The AD9510 offers both LVPECL and LVDS outputs that are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters.
LVPECL CLOCK DISTRIBUTION
The low voltage positive emitter coupled logic (LVPECL) outputs of the AD9510 provide the lowest jitter clock signals available from the AD9510. The LVPECL outputs (because they are open emitter) require a dc termination to bias the output transistors. A simplified equivalent circuit in Figure 29 shows the LVPECL output stage.
3.3V
Figure 26. CMOS Output Waveforms
Termination at the far end of the PCB trace is a second option. The CMOS outputs of the AD9510 do not supply enough current to provide a full voltage swing with a low impedance resistive, far-end termination, as shown in Figure 28. The far end termination network should match the PCB trace impedance and provide the desired switching point. The reduced signal swing may still meet receiver input requirements in some applications. This can be useful when driving long trace lengths on less critical nets.
Vpullup=3.3V
Out+ Out-
100 10
CMOS
GND
50
3pF
Figure 29. Simplified LVPECL Output Stage
OUT4, OUT5, OUT6, OUT7 selected as CMOS
100
In most applications, a standard LVPECL far-end termination is recommended, as shown in Figure 30. The resistor network is designed to match the transmission line impedance (50 ) and the desired switching threshold (1.3 V). Figure 32 shows a typical LVPECL clock waveform.
3.3V
Figure 27. CMOS Output with Far-End Termination
127
3.3V
50
single-ended (not oupled) c
127
3.3V
LVPECL LVPECL
50
LVPECL LVPECL
Vt=Vcc - 1.3V
83
83
Figure 30. LVPECL Far-End Termination Figure 28. Far-End Termination of CMOS Output Waveform
Rev. PrA | Page 39 of 41
AD9510
3.3V
Preliminary Technical Data
0.1nF 0.1nF differential (coupled) 100
3.3V
A typical LVDS output waveform is shown in Figure 34. (See Application Note AN-586 at www.analog.com for more information on LVDS).
LVPECL
LVPECL
200
200
Figure 31 LVPECL with Parallel Transmission Line
Figure 34. Typical LVDS Output Waveforms
POWER AND GROUNDING CONSIDERATIONS, AND POWER SUPPLY REJECTION
Figure 32. Typical LVPECL Outputs
LVDS CLOCK DISTRIBUTION
Low voltage differential signaling (LVDS) is a second differential output option for the AD9510. LVDS provides clock signals with jitter performance nearly as good as that obtainable from LVPECL, and better than CMOS. LVDS uses a currentmode output stage with several user-selectable current levels. A 3.5 mA output current yields 350 mV output swing across a standard LVDS output termination of 100 , meeting ANSI 644 requirements. A recommended termination circuit is shown for the LVDS outputs in Figure 33.
3.3V 3.3V
Many applications seek high speed and performance under less than ideal operating conditions. In these application circuits, the implementation and construction of the PCB is as important as the circuit design. Proper RF techniques must be used for device selection, placement, and routing, as well as power supply bypassing and grounding to ensure optimum performance.
LVDS
100
differential (coupled)
100
LVDS LVDS
Figure 35. Differential LC Filter for Single 3.3 V Applications Figure 33. LVDS Output Termination
Rev. PrA | Page 40 of 41
Preliminary Technical Data OUTLINE DIMENSIONS
9.00 BSC SQ 0.60 MAX 0.60 MAX
49 48
AD9510
0.30 0.25 0.18
64 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
8.75 BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
4.85 4.70 SQ* 4.55
0.45 0.40 0.35
33 32
16 17
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC
7.50 REF
SEATING PLANE
0.20 REF
*COMPLIANT TO JEDEC STANDARDS MO-220-VMMD EXCEPT FOR EXPOSED PAD DIMENSION
Figure 36. 64-Lead Frame Chip Scale Package [LFCSP] 9 mm x 9 mm Body (CP-64-1) Dimensions shown in millimeters
ORDERING GUIDE
Model AD9510 AD9510PCB Temperature Range -40C to +85C Package Description 64-Lead Chip Scale Package (LFCSP) Evaluation Board Package Options CP-64-1
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05046-0-11/04(PrA)
Rev. PrA | Page 41 of 41
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