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| AS2702 AS-Interface Slave IC DATA SHEET General Description AS2702 (SAP4.1) is a new generation AS-Interface slave device, which supports AS-Interface bus systems with up to 62 slave modules. Each slave module is equipped with an AS2702 device, which interfaces the module to the unshielded 2-wire ASInterface bus for serial bidirectional data communication and power extraction. Data communication over the AS-Interface takes place in master slave fashion, which foresees that all slave devices AS2702 connected to the bus are sequentially and cyclicly addressed by a single, central master unit. Data on the ASInterface bus are Manchester encoded and can be found as sin2-pulses with a Vpp of between 3V and 8V on top of the bus' dc voltage of nominally 30V. AS2702 regulates the nominal dc bus voltage of 30V internally down to 5V to supply it's internal circuitry including a 16 x 8 bits EEPROM, as well as down to a nominal supply level 24V with a max. loading of 35mA for the actuators and sensors connected to it at the field side. Each slave device AS2702 may interface to up to 4 sensors or 3 actuators. An AS-Interface bus system based on AS2702 may hence link as many as 248 sensors and 186 actuators to a single master unit. Slave device AS2702 (SAP4.1) is system compatible with predecessor device AS2701A (ISA3+): slave modules equipped with AS2702 (SAP4.1) will run in existing AS-Interface bus systems based on AS2701A (ISA3+). The AS-Interface concept is well established as a standardized digital bus system for industrial automation. Key Features * * Interface device to connect actuators and sensors to an AS-Interface bus Flexible system solution offering 2 package options: SOIC 20 for full functionality; SOIC 16 for applications not requiring the parameter port DC power extraction from the AS-Interface bus Serial bidir. data communication with the bus Data communication watchdog 4-bit bidir. data port plus strobe to poll the sensors and control the actuators connected 4-bit parameter port plus strobe to provide settings to the sensors and actuators 24V power supply for the sensors and actuators Periphery fault input to signal hardware failure of the sensors and actuators Integrated 16 x 8 bit EEPROM to store (5 + 1)-bit slave address and settings 2 LED outputs to optically flag slave unit operation status Operating temperature Ta: - 25C ... + 85C Operating supply voltage/bus DC voltage: typ. 30V Operating current (Osc. on, outputs idle): 6mA * Supply for sensors/actuators: typ. 24V, 35mA * * * * * * * * * * * * Revision 1.2, 26-Jul-04 Page 1 of 13 AS2702 - AS-Interface Slave IC Block Diagram CDC LTGP VLTGP-6V + THERMODETECTOR UOUT U5R U5R U5R U5R OSC1 OSCILLATOR OSC2 RECEIVE TRANSMIT JABBER INHIBIT RESET threshold 11 U5R IMP_POS IMP_NEG LTGN LOGIC BLOCK POR BANDGAP + - U5R 16 x 8 BIT SERIAL E2PROM PFAULT D0...D3 LED2 LED1 SDA SCL 4 4 P0...P3 DSTBn PSTBn TRIMMING Figure 1 Block diagram Pin Assignment and Description SOIC 20 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 SOIC 16 Pin No. 1 2 3 4 5 6 7 8 9 10 11 P1 P0 D1 D0 DSTBn LED1 OSC2 OSC1 U5R LTGN LTGP CDC UOUT I/O, digital, pull-up 1, 2 I/O, digital, pull-up 1, 2 I/O, digital I/O, digital I/O, digital, pull-up 1 I/O, digital, pull-up 1 O, analog I, analog O, power I, power I, power I/O, analog O, power Bidir. parameter port bit 1 Bidir. parameter port bit 0 Bidir. data port bit 1 Bidir. data port bit 0 Data port strobe output; reset-input LED output 1 (IC test input) Output to quartz crystal Input from quartz crystal Nom. 5V power supply output Neg. supply pin, connected to neg. AS-Interface bus line, ground reference Pos. supply pin, connected to pos. AS-Interface bus line Pin for ext. buffer capacitor Nom. 24V power supply output Name Type Note Description Revision 1.2, 26-Jul-04 Page 2 of 13 AS2702 - AS-Interface Slave IC SOIC 20 14 15 16 17 18 19 20 SOIC 16 12 13 14 15 16 - Name PFAULT LED2 PSTBn D3 D2 P3 P2 Type I, digital, pull-up Note 1 Description Low-active input to flag failure of the sensors/actuators circuitry connected LED output 2 (IC test input) Parameter port strobe output (IC test input) Bidir. data port bit 3 Bidir. data port bit 2 Bidir. parameter port bit 3 Bidir. parameter port bit 2 I/O, digital, pull-up 1 I/O, digital, pull-up 1 I/O, digital I/O, digital I/O, digital, pull-up 1, 2 I/O, digital, pull-up 1, 2 Notes: 1 The pull-up structure is a passive high-side current source with a nom. 10A current. 2 The passive pull-up current source as per note 1 on these parameter port pins is off, if the slave device is programmed with I/O-configuration code 7 and a master data call is present. Functional, Electrical and Timing Characteristics All voltages are referenced to ground pin LTGN. Timing is valid for a quartz crystal frequency of 5.333MHz. Absolute Maximum Ratings Symbol VLTGP VCDC VU5R IIN ESD1 ESD2 STG LEAD PTOT RTHJA RTHJA Parameter Voltage at the positive supply pin Voltage at pin for ext. buffer capacitor Voltage at pins U5R, OSC1, OSC2 Input current at any pin, except for LTGP, CDC Electrostatic discharge voltage Electrostatic discharge voltage Storage temperature Solder temperature Max. power dissipation Thermal resistance SOIC 16 Thermal resistance SOIC 20 61.2 58.5 Min -0.3 -0.3 -0.3 -50 1500 300 -55 125 240 1 74.8 71.5 Max 40 VLTGP + 0.3V 7 50 Unit V V V mA V V V C W K/W K/W 5 6 7 7 2 3 4 Note 1 Notes: 1 50V during t > 50s; repetition rate < 0.5Hz 2 Latch-up immunity test. Please observe max. power dissipation allowed 3 Human body model: R = 1.5kOhm; C = 100pF 4 Machine model; applies only for LTGP 5 240C during 10s (reflow and wave soldering); Twofold reflow soldering is acceptable. 6 Free convection, see Figure 2 7 No forced cooling. PCB-surface: 21 cm 2 ; still air volume around the device. 10 cm 3 Revision 1.2, 26-Jul-04 Page 3 of 13 AS2702 - AS-Interface Slave IC Pv/ W 1 Pv/ W 1 0.5 0.5 50 100 t/ C 50 100 t/ C SOIC16 Figure 2 Max. acceptable power dissipation relative to ambient temperature SOIC20 Recommended Operating Conditions Symbol VLTGP ILTG OA FC Parameter Positive supply voltage/dc portion Supply current consumption Ambient temperature Quartz frequency Sensitivity against moisture - 25 25 5.333333 Min 22.5 Nom Max 34 6 85 Unit V mA C MHz Note 1 2 3 4 5 Notes: 1 False-poling protection diode to be inserted between pos. AS-Interface bus line and LTGP-pin. LTGP-pin to be protected furthermore with a voltage clamp between LTGP and LTGN. 2 Oscillator on; data transmission stage off; no loads connected 3 Power dissipation restrictions as per Figure 2 to be observed 4 AS-Interface Quartz 5 Level 5 acc. to JEDEC-standard JESD22-A112 Supply Pin LTGP Positive supply pin connected to positive AS-Interface bus line and clamped relative to neg. supply pin/ground LTGN as described under Recommended Operating Conditions. VLTGP and ILTG specified under Recommended Operating Conditions as well. Symbol VSIG Z Parameter VPP of sin2-data-pulses on top of dc supply voltage Input impedance between 50kHz and 300kHz 18 50 Min 3 Nom Max 8 40 Unit V pF kOhm mH CCDC = 100nF Note Revision 1.2, 26-Jul-04 Page 4 of 13 AS2702 - AS-Interface Slave IC Buffer Pin CDC An external buffer capacitor with a recommended value of 100nF should be connected to this pin to ensure a sufficiently high input impedance Z at power supply pin LTGP. Voltage at this pin can be as high as VLTGP. Nom. 24V Power Supply Output UOUT The supply output voltage at UOUT is directly derived from VLTGP and regulated to a level with an offset of about -6V relative to VLTGP. UOUT provides bias to the sensors and actuators circuitry connected to the slave device as well as to the LEDs connected to outputs LED1 and LED2. UOUT is equipped with a thermal overload protection, which foresees that VUOUT is switched off as soon as the slave device's substrate temperature TJ passes a threshold value in the range of (155 20)C. After TJ has come down and has passed a temperature threshold about (15 5)C lower than (155 20)C and after a consecutive minimum delay time of 1s has elapsed, VUOUT is switched on again. Symbol VUOUT IUOUT Parameter Power supply output voltage Load current 9.5 10 below which data transmission is inhibited CUOUT Buffer capacitor F 2 Min VLTGP - 6.3V Max VLTGP - 5.3V 50 10.5 Unit V mA V 1 Note VCOMOFF UOUT voltage level Notes: 1 In case IUOUT >40mA and presence of sin2-data pulses on LTGP with VSIG >3V, VUOUT may drop as much as 1V below it's level in unloaded condition 2 Electrolytic and rf filter capacitor in parallel Nom. 5V Power Supply Output U5R The voltage at U5R is derived from the voltage present at UOUT, as long as UOUT is not switched off due to overload. In the latter case U5R is derived from an alternative voltage out of the UOUT voltage regulator, which is more or less similar to VUOUT in non switched off condition of UOUT. As a result VU5R is not affected by overload condition at UOUT and will remain. Symbol VU5R IU5R CU5R Parameter Power supply output voltage Load current Buffer capacitor 470 Min 4.85 Max 5.15 1 Unit V mA nF Oscillator Pins OSC1 and OSC2 The only component to be connected to these pins is a quartz crystal with a resonance frequency of 5.333333 MHz (AS-Interface quartz crystal). Symbol CX2 Parameter Stray capacitance Min Max 10 Unit pF Revision 1.2, 26-Jul-04 Page 5 of 13 AS2702 - AS-Interface Slave IC Data Port Pins D3, ..., D0 and Data Strobe Pin DSTBn Basically data port D3, ..., D0 is designed for bidirectional data transfer out of and into the slave device. Each data port pin is equipped with both a low-side open-drain output stage as well as an input stage to this purpose. Depending on the so-called IO-configuration code, written and stored in the slave device, each data port pin is individually set to behave as * * * output, or output/input, or input. The timing of the data transfer is presented in Figure 3. Strobe signal DSTBn flags and governs the data transfer as follows: a) data port pin is set `output': output data become valid upon the HL-edge of the strobe and will remain so until the next HL-edge, hence during the entire strobe cycle; b) data port pin is set `output/input': output data become valid upon the HL-edge of the strobe and will remain so until it's LH-edge; input data to be valid within a specific time window relative to the HL-edge, after completion of the strobe's L-phase; c) data port pin is set `input': input data to be valid within a specific time window relative to the HL-edge of the strobe, after completion of the strobe's L-phase. If necessary, output data as per a) and b) can be easily latched with the LH-edge of strobe DSTBn as they will remain valid for about 0.4s beyond as a minimum. Care must be taken however, that signal delay added by external circuitry is lower for the strobe than for the data. Dx t Dx t Data out DSTBn Data in + 0.4 s STB Data out t DSTBn Data in + tOUTOFF DSTBn t DSTBn t INPmin t INPmax Figure 3 Timing of data transfer at data port D3, ..., D0 relative to strobe DSTBn The following table specifies the timing parameters relating to Figure 3: Symbol tSTB tDSTBn tOUTOFF tINP Parameter Delay DSTBn HL-edge to Dx output data valid DSTBn strobe width Delay DSTBn LH-edge to Dx output off Input data valid time window 6 0.2 10.5 Min Max 1.5 6.8 1 12.5 Unit s s s s 1 2 3 Note Revision 1.2, 26-Jul-04 Page 6 of 13 AS2702 - AS-Interface Slave IC Notes: 1 Pulse width depends substantially on value of external pull-up resistor 2 Applies only to data port pins set to 'output/input' operation 3 Timing reference is DSTBn HL-edge. Applies only to data port pins set to either 'output/input' or 'input' operation The dc-parameters of the data port pins D3, ..., D0 are specified as follows: Symbol IOUTLO IOUTHI VSCHLT VIN Parameter Sink current @ output L Leakage current @ output off Input threshold voltage Acceptable input voltage @ output off Min 10 -1 2.5 -0.3 1 3.5 40 Max Unit mA A V V Note VOUT = 1V 1 2 Notes: 1 Output stage is low-side open-drain; ext. pull-up resistor required as no pull-up structure on chip 2 No hysteresis implemented To govern the data transfer at data port D3, ...,D0 strobe pin DSTBn is equipped with a low-side open-drain output switch plus a passive high-side current source with a nom. 10A pull-up current capability. However a second function is assigned to the DSTBn pin which requires it to be input as well: if a low-pulse is imposed on DSTBn by external means with a pulse width of at least 50 to 100ms, the slave device will be put in RESET condition, as described in section "Reset". The dc-and timing parameters of strobe pin DSTBn are specified as follows: Symbol IOUTLO IOUTHI IINLO VSCHLT VIN tNORESET tRESET CPINEXT Parameter Sink current @ output L Leakage current @ output off Input current @ VIN = 1V Input threshold voltage Acceptable input voltage @ output off DSTBn L-phase width, not triggering RESET DSTBn L-phase width, triggering RESET Max. stray capacity 100 20 Min 10 -10 -5 1.5 -0.3 10 -20 3.5 40 50 Max Unit mA A A V V ms ms pF Note VOUT = 1V VOUT = 5V 1 2 Notes: 1 DSTBn is equipped with an on-chip pull-up current source, which ensures a sufficiently fast LH-edge upon output switch-off in open-pin condition, to prevent erroneous RESET triggering. If DSTBn has an external load connected to it, an additional external pull-up resistor may be needed to prevent erroneous RESET triggering upon output switch-off. 2 No hysteresis implemented Parameter Port Pins P3, ..., P0 and Parameter Strobe Pin PSTBn (Note that parameter port pins P3, ..., P0 are only available on AS2702 package option SOIC 20, not on the SOIC 16 option.) The transfer of data at P3, ..., P0 and the supporting strobe action at pin PSTBn takes place similarly as at D3, ..., D0 resp. DSTBn. Each parameter port pin P3, ..., P0 is equipped with both a low-side open-drain output switch plus a passive, but switchable highside current source with a nom. 10 A pull-up current capability, and with an input stage. Though equipped for bidirectional data transfer as D3, ..., D0, the parameter port is nevertheless less flexible than the data port. Basically the parameter port is set to behave portwise as Revision 1.2, 26-Jul-04 Page 7 of 13 AS2702 - AS-Interface Slave IC * output, or * input depending on the IO-configuration code, written and stored in the slave device. The timing of the data transfer is presented in Figure 4. Strobe signal PSTBn flags and governs the data transfer as follows: a) parameter port is set `output': output data become valid upon the HL-edge of the strobe and will remain so until the next HL-edge, hence during the entire strobe cycle; b) parameter port is set `input': input data to be valid within a specific time window relative to the HL-edge of the strobe, after completion of the strobe's Lphase. Output data as per a) could be easily latched with the LH-edge of strobe PSTBn, if at all necessary. Px t STB Parameter out Parameter out Px t PSTBn t PSTBn PSTBn Data in + tOUTOFF t INPmin t INPmax Figure 4 Timing of data transfer at parameter port P3, ..., P0 relative to strobe PSTBn The following table specifies the timing parameters relating to Figure 4: Symbol tSTB tPSTBn tINP Parameter Delay PSTBn HL-edge to Px output data valid PSTBn strobe width Input data valid time window 6 10.5 Min Max 1.5 6.8 12.5 Unit s s s 1 2 Note Notes: 1 Pulse width depends substantially on value of external pull-up resistor 2 Timing reference is PSTBn HL-edge. Applies only to parameter port set to 'input' operation The dc-parameters of the parameter port pins P3, ..., P0 are specified as follows: Symbol IOUTLO IOUTHI IOUTHI7 IINLO Parameter Sink current @ output L Leakage current @ output off Leakage current @ output off; pull-up current source off Input current @ VIN = 1V Min 10 -10 -1 -5 10 1 -20 Max Unit Note mA A A A VOUT = 1V VOUT = 5V VOUT = 5V; IO-conf. = 7 1 Revision 1.2, 26-Jul-04 Page 8 of 13 AS2702 - AS-Interface Slave IC Symbol VSCHLT VIN Parameter Input threshold voltage Acceptable input voltage @ output off Min 2.5 -0.3 Max 3.5 40 Unit Note V V 2 Notes: 1 The passive high-side current-source provides an about constant input current @ 0V <= VIN <= 4V 2 No hysteresis implemented Though equipped for bidirectional data transfer as D3, ..., D0, the parameter port is nevertheless less flexible than the data port. Note the following differences: a) The parameter port is set portwise, the data port bitwise by the IO-configuration code; b) The parameter port can only be set to either `output' or `input'. A bidirectional behaviour within a strobe cycle is not possible; c) The parameter port is set to `output' as a rule; the only exception occurs in case of IO-configuration 7 and a master data request, which set it to `input'. To govern the data transfer at the parameter port P3, ..., P0 strobe pin PSTBn is equipped with a low-side open-drain output switch plus a passive high-side current source with a nom. 10A pull-up current capability. Typically the PSTBn-strobe width is about 6s see Figure 4. (However to simplify and shorten the component test time of the slave device, the PSTBn pin is also used as an input. Input low pulses of more than 50s each will step and cycle the device through 3 different test modes beyond the regular operation as described in this datasheet.) The dc- and timing parameters of strobe pin PSTBn are specified as follows: Symbol IOUTLO IOUTHI IINLO VSCHLT VIN tNOTM tTM CPINEXT Parameter Sink current @ output L Leakage current @ output off Input current @ VIN = 1V Input threshold voltage Acceptable input voltage @ output off PSTBn L-phase width, not triggering test mode PSTBn L-phase width, triggering test mode Stray capacitance 50 20 Min 10 -10 -5 1.5 -0.3 10 -20 3.5 40 35 Max Unit Note mA A A V V s s pF VOUT = 1V VOUT = 5V 1 2 Notes: 1 PSTBn is equipped with an on-chip pull-up current source, which ensures a sufficiently fast LH-edge upon output switch-off in open-pin condition, to prevent erroneous test mode triggering. If PSTBn has an external load connected to it, an additional external pull-up resistor may be needed to prevent erroneous test mode triggering upon output switch-off 2 No hysteresis implemented Revision 1.2, 26-Jul-04 Page 9 of 13 AS2702 - AS-Interface Slave IC Operation Status Pins LED1 and LED2 Pins LED1 and LED2 are both equipped with a low-side open-drain output switch plus a passive high-side current source with a nom. 10A pull-up current capability. They will each have an LED load connected to UOUT, which will flag the operation staus of the slave device, according to the following table: Output LED1 (green LED connected) off on off Output LED2 (red LED connected) off off of 4 Flagging Priority (1 = highest, ..., 4 = lowest) Slave Device Operation Status Supply voltage off Regular operation No data communication Regular, non-zero slave address coded; data comm. watchdog triggered Slave address = default zero Input PFAULT = L DSTBn = L to RESET, or UOUT switched-off due to overload No supply voltage Reason blinks blinks off on blinks (alternating with LED1) blinks 3 2 1 No regular slave address coded Hardware failure in sensor/actuator circuitry External RESET or overload at UOUT pin (LED1 and LED2 both also feature an input stage, to simplify component test and shorten test time of the slave device.) The dc- and timing parameters of pins LED1 and LED2 are specified as follows: Symbol ILED IOUTHI VIN fBLINK Parameter Sink current @ output L Leakage current @ output off Acceptable input voltage @ output off Blinking frequency Min 10 -10 -0.3 2 10 40 3 Max Unit Note mA A V Hz VOUT = 1V VOUT = 5V Data Communication Watchdog AS2702 is equipped with a watchdog timer to supervise data communication by monitoring the strobe signals at pins DSTBn and PSTBn. If a parameter or data strobe is not followed by a consecutive strobe within a time period of 50 ... 100ms, the watchdog is triggered and initiates a `soft' reset, see section Reset. Reset There are 2 categories of reset-events, leading to 2 slightly different reset-conditions of the slave device: 1 A `hard' reset taking place at power-up and power-down of supply-voltages U5R and UOUT. At power-up the slave device leaves reset-condition as soon as U5R has passed 3.75V and UOUT has passed VCOMOFF = nom. 10V. At power-down the slave device is forced into reset-condition as soon as U5R drops below 3.75V. 2 (Tolerance of the threshold voltages referred to is 5 %) A `soft' reset, resulting from one of the following events: 2.1 Data strobe pin DSTBn is kept L for more than 100ms; 2.2 Master command `RESET SLAVE' is received; 2.3 Master command `RESET BROADCAST' is received; 2.4 The communication watchdog is triggered. Revision 1.2, 26-Jul-04 Page 10 of 13 AS2702 - AS-Interface Slave IC A `hard' reset event conditions the slave device as follows: * * * * Internal states (counters, flags, ...) are reset The slave device's receiver is desynchronized from the AS-Interface bus The low-side open-drain output stages at ports D3, ..., D0 and ports P3, ..., P0 are switched off Any test mode will be cancelled A `soft' reset has the following consequences: * * * A regular, nominal 6s L-phase strobe is generated on both the DSTBn and PSTBn pin The low-side open-drain output stages at ports D3, ..., D0 and ports P3, ..., P0 are switched off Internal states (counters, flags, ...) are rest, however the following states and operations are not affected: - the timer function which controls blinking of LED1 and LED2 - the data communication - any test mode - any EEPROM write operation Remark: If UOUT drops below VCOMOFF = nom. 10V data communication with the AS-Interface bus is aborted by the receiver or transmitter of the slave device. As long as U5R does not drop below 3.75V in this situation, no `hard' reset takes place; however the data communication watchdog will be triggered (unless disabled) and a `soft' reset will result. EEPROM AS2702 has a 16 x 8 Bits serial interface EEPROM on board to store the slave unit's address and set-up data in a non-volatile fashion. The EEPROM stores the following data: EEPROM-Address 0, 1 2 3 4 5 6 Data Slave Address Settings (EID1) Settings (IO-Conf.) Settings (ID) Settings (EID2) Settings (Control-Code) Relevant No. of Bits 5+1 4 5 5 5 5 Programmed by Master (Initialization) Master (Initialization) Slave unit manufacturer Slave unit manufacturer Slave unit manufacturer Slave unit manufacturer Note 1 Note: 1 6 Bits (A4, ..., A0 + Sel-bit) in extended address mode: 62 slaves addressable; 5 Bits (A4, ..., A0) in non-extended address mode: 31 slaves addressable Obviously the capacity of the EEPROM is only partially used. Reading and writing of the EEPROM is performed bytewise and trough temporary, volatile registers. Writing of data from the volatile register into the EEPROM takes about 10ms per byte, whereas reading takes less than 1ms per byte. Upon RESET the EEPROM info is read into temporary register, including the slave's address which has been written redundantly into EEPROM locations 0 and 1 before. The temporary registers receiving the address are compared for similarity; in case of non-similarity - which e.g. may have been caused by a supply voltage dip during address writing - the slave will flag non-regular operation status/slave address zero. Revision 1.2, 26-Jul-04 Page 11 of 13 AS2702 - AS-Interface Slave IC AS-Interface Bus Communication All slaves connected to an AS-Interface bus are sequentially and cyclicly called by the master in a string of individual transactions between the master and each slave unit. A transaction consists of a 14 bits master request, typically containing the slave's address as well as data or parameter info, and an immediate acknowledging slave response of 7 bits. The 14 bits master request - apart from Start Bit ST = 0 and End Bit EB = 1 - has the following contents: * 1 Control Bit CB: CB = 0 stands for data transfer (typ. data or parameters) CB = 1 identifies command-type requests * * * 5 Address Bits: 5 Information Bits: 1 Parity Bit PB A4, ..., A0 I4, ..., I0 (typ. data or parameters) AS2702 allows for up to 62 slaves on the same AS-Interface bus; this requires a slave address extended to 6 bits, hence an extra bit beyond A4, ..., A0. Information bit I3 is used as the 6 th address bit in this so-called extended address mode. It is called Sel-bit, as it is perceived as to select between A-slave (Sel = 0) and B-slave (Sel = 1) at address location A4, ..., A0. In non-extended address mode AS2702 is addressed with A4, ..., A0 only - for a max. total of 31 slaves per AS-Interface bus system, and is system compatible with existing slave device AS2701A. The 7 bits slave response - apart from Start Bit ST = 0 and End Bit EB = 1 - has the following contents: * * 4 Information Bits: 1 Parity Bit PB I4, ..., I0 (typ. data or parameters) Application Support For general information and documentation on the AS-Interface concept you may contact the AS-Interface Association: AS-International Association Contact: Rolf Becker Zum Taubengarten 52 D-63571 Gelnhausen Tel.: +49-6051-473212 Fax: +49-6051-473282 e-mail: info@as-interface.net http://www.as-interface.net Ordering Information AS2702-20T AS2702-16T AS2702-20 AS2702-16 Package: Package: Package: Package: SOIC SOIC SOIC SOIC 20; delivery: tape & reel 16W; delivery: tape & reel; no parameter port available 20; delivery: tubes 16W; delivery: tubes; no parameter port available Revision 1.2, 26-Jul-04 Page 12 of 13 AS2702 - AS-Interface Slave IC Contact Headquarters austriamicrosystems AG A 8141 Schloss Premstatten, Austria Phone: +43 3136 500 0 Fax: +43 3136 525 01 industry.medical@austriamicrosystems.com www.austriamicrosystems.com Sales Offices austriamicrosystems USA, Inc. 8601 Six Forks Road Suite 400 Raleigh, NC 27615, USA Phone: +1 919 676 5292 Fax: +1 509 696 2713 austriamicrosystems AG Suite 811, Tsimshatsui Centre East Wing, 66 Mody Road Tsim Sha Tsui East, Kowloon, Hong Kong Phone: +852 2268 6899 Fax: +852 2268 6799 austriamicrosystems AG AIOS Gotanda Annex 5 th Fl., 1-7-11, Higashi-Gotanda, Shinagawa-ku Tokyo 141-0022, Japan Phone: +81 3 5792 4975 Fax: +81 3 5792 4976 austriamicrosystems AG #805, Dong Kyung Bldg., 824-19, Yeok Sam Dong, Kang Nam Gu, Seoul Korea 135-080 Phone: +82 2 557 8776 Fax: +82 2 569 9823 austriamicrosystems AG Singapore Representative Office 83 Clemenceau Avenue, #02-01 UE Square 239920, Singapore Phone: +65 68 30 83 05 Fax: +65 62 34 31 20 Copyright Copyright (c) 2003 austriamicrosystems. Trademarks registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. To the best of its knowledge, austriamicrosystems asserts that the information contained in this publication is accurate and correct. Revision 1.2, 26-Jul-04 Page 13 of 13 |
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