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CMOS Static RAM 64K (16K x 4-Bit)
IDT7188S IDT7188L
x
Features
High-speed (equal access and cycle times) - Military: 25/35/45/55/70/85ns (max.) Low power consumption Battery backup operation -- 2V data retention (L version only) Available in high-density industry standard 22-pin, 300 mil ceramic DIP Produced with advanced CMOS technology Inputs/outputs TTL-compatible Military product compliant to MIL-STD-883, Class B innovative circuit design techniques, provides a cost effective approach for memory intensive applications. Access times as fast as 25ns are available. The IDT7188 offers a reduced power standby mode, ISB1, which is activated when CS goes HIGH. This capability significantly decreases power while enhancing system reliability. The low-power version (L) version also offers a battery backup data retention capability where the circuit typically consumes only 30W operating from a 2V battery. All inputs and outputs are TTL-compatible and operate from a single 5V supply. The IDT7188 is packaged in a 22-pin, 300 mil ceramic DIP providing excellent board-level packing densities. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
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Description
The IDT7188 is a 65,536-bit high-speed static RAM organized as 16K x 4. It is fabricated using IDT's high-performance, high-reliability technology -- CMOS. This state-of-the-art technology, combined with
Functional Block Diagram
A0 VCC GND 65,536-BIT MEMORY ARRAY
DECODER
A13
I/O0 I/O1 I/O2 I/O3
COLUMN I/O INPUT DATA CONTROL
,
CS WE
2989 drw 01
FEBRUARY 2001
1
(c)2000 Integrated Device Technology, Inc. DSC-2989/09
IDT7188S/L CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
Pin Configuration
A0 A1 A2 A3 A4 A5 A6 A7 A8 CS GND
1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12
Absolute Maximum Ratings(1)
Symbol Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value -0.5 to +7.0 -55 to +125 -65 to +135 -65 to +150 1.0 50 Unit V
o o
D22-1
VCC A 13 A12 A11 A10 A9 I/O 3 I/O 2 I/O 1 I/O 0 WE
2989 drw 02
VTERM TA TBIAS TSTG PT IOUT
C C C
o
W mA
2989 tbl 03
,
DIP Top View
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
(TA = +25C, f = 1.0MHz, VCC = 0V)
Symbol Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 6 Unit pF pF
2989 tbl 04
Capacitance
Pin Descriptions
Name A0 - A13 CS WE I/O0 - I/O3 VCC GND Description Address Inputs Chip Select Write Enable Data Input/Output Power Ground
2989 tbl 01
CIN CI/O
NOTE: 1. This parameter is determined by device characterization, but is not production tested.
Recommended DC Operating Conditions
Symbol VCC GND Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5(1) Typ. 5.0 0
____
Max. 5.5 0 6.0 0.8
Unit V V V V
2989 tbl 05
Truth Table
Mode Standby Read Write
(1)
VIH WE X H L I/O High-Z DOUT DIN Power Standby Active Active
2989 tbl 02
CS H L L
VIL
____
NOTE: 1. VIL (min.) = -3.0V for pulse width less than 20ns,once per cycle.
NOTE: 1. H = VIH, L = VIL, X = don't care.
Recommended Operating Temperature and Supply Voltage
Grade Military Temperature -55 C to +125 C
O O
GND 0V
Vcc 5V 10%
2989 tbl 06
2
IDT7188S/L CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
DC Electrical Characteristics
(VCC = 5.0V 10%)
IDT7188S Symbol |ILI| |ILO| VOL Parameter Input Leakage Current Output Leakage Current Output Low Voltage Test Conditions VCC = Max., VIN = GND to VCC VCC = Max., CS = VIH, VOUT = GND to VCC IOL = 10mA, VCC = Min. IOL = 8mA, VCC = Min. VOH Output High Voltage IOH = -4mA, VCC = Min. Min.
____
IDT7188L Min.
____
Max. 10 10 0.5 0.4
____
Max. 5 5 0.5 0.4
____
Unit A A V
____
____
____
____
____
____
2.4
2.4
V
2989 tbl 07
DC Electrical Characteristics(1)
Symbol ICC1 Parameter Operating Power Supply Current CS = VIL, Outputs Open VCC = Max., f = 0(2) Dynamic Operating Current CS = VIL, Outputs Open VCC = Max., f = fMAX(2) Standby Power Supply Current (TTL Level) CS > VIH, Outputs Open VCC = Max., f = fMAX(2) Full Standby Power Supply Current (CMOS Level) CS > VHC, VCC = Max., VIN > VHC or VIN < VLC, f = 0(2) Power S L S L S L S L
(VCC = 5V 10%, VLC = 0.2V, VHC = VCC - 0.2V)
7188S25 7188L25 105 80 155 120 60 40 20 1.5 7188S35 7188L35 105 80 140 115 50 40 20 1.5 7188S45 7188L45 105 80 140 110 50 35 20 1.5 7188S55 7188L55 105 80 140 110 50 35 20 1.5 7188S70 7188L70 105 80 140 110 50 35 20 1.5 7188S85 7188L85 105 80 140 105 50 35 20 1.5
2989 tbl 08
Unit mA
ICC2
mA
ISB
mA
ISB1
mA
NOTES: 1. All values are maximum guaranteed values. 2. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC. f = 0 means no input lines change.
6.42 3
IDT7188S/L CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
Data Retention Characteristics
(L Version Only) (VHC = VCC - 0.2V)
Typ. (1) VCC @ Symbol VDR ICCDR tCDR(3) tR(3) Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Input Leakage Current CS > VHC VIN > VHC or < VLC Test Condition
____
Max. VCC @ 3.0V
____
Min. 2.0
____
2.0V
____
2.0V
____
3.0V
____
Unit V A ns ns A
2989 tbl 09
10
____
15
____
600
____
900
____
0 tRC(2)
____
____
____
____
____
IILII(3)
____
____
2
2
NOTES: 1. TA = +25C. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization but is not production tested.
Low VCC Data Retention Waveform
VCC t CDR CS VIH DATA RETENTION MODE 4.5V VDR 2V VDR V IH
2989 drw 03
4.5V tR
,
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 5ns 1.5V 1.5V See Figures 1 and 2
2989 tbl 10
5V 480 DATAOUT 255 30pF*
5V 480 DATA OUT
,
2989 drw 04
255
5pF*
2989 drw 05
,
Figure 1. AC Test Load *Includes scope and jig capacitances
Figure 2. AC Test Load (for tHZ, tLZ, tWZ, tOHZ and tOW)
4
IDT7188S/L CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
AC Electrical Characteristics
7188S25 7188L25 Symbol Parameter Min. Max.
(VCC = 5.0V 10%)
7188S35 7188L35 Min. Max. 7188S45 7188L45 Min. Max. 7188S55 7188L55 Min. Max. 7188S70 7188L70 Min. Max. 7188S85 7188L85 Min. Max. Unit
Read Cycle
tRC tAA tACS tOH tLZ(1) tHZ(1) tPU(1) tPD(1) Read Cycle Time Address Access Time Chip Select Access Time Output Hold from Address Change Output Select to Output in Low-Z Chip Deselect to Output in High-Z Chip Select to Power Up Time Chip Deselect to Power Down Time 25
____ ____
35
____
-- 35 35
____
45
____
-- 45 45
____
55
____
____
70
____
____
85
____
____
ns ns ns ns ns ns ns ns
2989 tbl 11
25 25
____
55 55
____
70 70
____
85 85
____
____
____
____
____
____
____
5 5
____
5 5
____
5 5
____
5 5
____
5 5
____
5 5
____
____
____
____
____
____
____
10
____
14
____
14
____
20
____
25
____
30
____
0
____
0
____
0
____
0
____
0
____
0
____
25
35
45
55
70
85
NOTE: 1. This parameter is guaranteed by device characterization but is not production tested.
Timing Waveform of Read Cycle No. 1(1,2)
tRC (5) ADDRESS tAA tOH DATAOUT PREVIOUS DATA VALID DATA VALID
2989 drw 06
,
Timing Waveform of Read Cycle No. 2(1,3)
tRC (5) CS tACS tLZ (4) DATAOUT tPU VCC SUPPLY CURRENT ICC ISB
2989 drw 07
tHZ (4) DATA VALID tPD
HIGH IMPEDANCE
,
NOTES: 1. WE is HIGH for Read cycle. 2. CS is LOW for Read cycle. 3. Address valid prior to or coincident with CS transition LOW. 4. Transition is measured 200mV from steady state voltage. 5. All Read cycle timings are referenced from the last valid address to the first transitioning address.
6.42 5
IDT7188S/L CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
AC Electrical Characteristics
7188S25 7188L25 Symbol Parameter Min. Max.
(VCC = 5.0V 10%)
7188S35 7188L35 Min. Max. 7188S45 7188L45 Min. Max. 7188S55 7188L55 Min. Max. 7188S70 7188L70 Min. Max. 7188S85 7188L85 Min. Max. Unit
Write Cycle
tWC tCW tAW tAS tWP tWR tDW tDH tWZ(1) tOW(1) Write Cycle Time Chip Select to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Data Hold Time Write Enable to Output in High-Z Output Active from End-of-Write 20 20 20 0 20 0 13 0
____ ____
30 25 25 0 25 0 15 0
____
____
40 35 35 0 35 0 20 0
____
____
50 50 50 0 50 0 25 0
____
____
60 60 60 0 60 0 30 0
____
____
75 75 75 0 75 0 35 0
____
____
ns ns ns ns ns ns ns ns ns ns
2989 tbl 12
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7
____
10
____
15
____
25
____
30
____
40
____
5
5
5
5
5
5
NOTE: 1. This parameter is guaranteed by device characterization.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,3)
tWC ADDRESS tAW CS1, CS2 tAS WE tWZ (6) DATAOUT
(4)
tWP
tWR
tOW (6)
(4)
tDW DATAIN
tDH
,
2989 drw 08
DATA VALID
NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. During this period, I/O pins are in the output state so that the input signals should not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state. 6. Transition is measured 200mV from steady state.
6
IDT7188S/L CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,2,3,5)
tWC ADDRESS tAW CS tAS WE tDW DATAIN DATA VALID
2989 drw 09
tCW
t WR
,
tDH
NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. During this period, I/O pins are in the output state so that the input signals should not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state. 6. Transition is measured 200mV from steady state.
Ordering Information
IDT 7188 Device Type X Power XX Speed X Package X Process/ Temperature Range
B
Military (-55C to +125C) Compliant to MIL-STD-883, Class B
,
D
300 mil Ceramic DIP (D22-1)
25 35 45 55 70 85 S L
Speed in nanoseconds
Standard Power Low Power
2989 drw 10
6.42 7
IDT7188S/L CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
Datasheet Document History
11/xx/99 Pg. 2, 3, 4 Pg. 8 08/09/00 02/01/01 Updated to new format Removed commercial temperature data Added Datasheet Document History Not recommended for new designs Removed "Not recommended for new designs"
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