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| IS42S81600A, IS42LS81600A IS42S16800A, IS42LS16800A IS42S32400A, IS42LS32400A 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM FEATURES * Clock frequency: 133 100, MHz * Fully synchronous; all signals referenced to a positive clock edge * Internal bank for hiding row access/precharge * Power supply IS42LS81600A IS42LS16800A IS42LS32400A IS42S81600A IS42S16800A IS42S32400A * LVTTL interface * Programmable burst length - (1, 2, 4, 8, full page) * Programmable burst sequence: Sequential/Interleave * Extended Mode Register * Programmable Power Reduction Feature by partial array activation during Self-Refresh * Auto Refresh (CBR) * Temp. Compensated Self Refresh. * Self Refresh with programmable refresh periods * 4096 refresh cycles every 64 ms * Random column address every clock cycle * Programmable CAS latency (2, 3 clocks) * Burst read/write and burst read/single write operations capability * Burst termination by burst stop and precharge command * Industrial Temperature Availability VDDQ VDD 2.5V 1.8V (2.5V tolerant) 2.5V 1.8V (2.5V tolerant) 2.5V 1.8V (2.5V tolerant) 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V IS42LS81600A IS42S81600A 4M x8x4 Banks 54pin TSOPII ISSI (R) ADVANCED INFORMATION AUGUST 2002 OVERVIEW ISSI's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDARM is organized as follows. IS42LS16800A IS42S16800A 2M x16x4 Banks 54ball FBGA 54 pin TSOPII IS42LS32400A IS42S32400A 2M x16x4 Banks 90ball FBGA 86pin TSOPII KEY TIMING PARAMETERS Parameter Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 Row to Column Delay Time (tRCD) Row Precharge Tim (tRP) -7 7 10 133 100 5.4 6 15 15 -10 10 10 100 100 7 9 18 18 Unit ns ns Mhz Mhz ns ns ns ns Copyright (c) 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION, Rev. 00A 08/01/02 1 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A DEVICE OVERVIEW The 128Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 2.5V VDD and 1.8V VDDQ or 3.3VDD and 3.3V VDDQ memory systems containing 134,217 ,728 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 4,096 rows by 256 columns by 16 bits. The 128Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. Only partials of the memory array can be selected for SelfRefresh and the refresh period during Self-Refresh is progammable in 4 steps which drastically reduces the self refresh current, depending on the case temperature of the components in the system application. The 128Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks ISSI (R) to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The registration of an ACTIVE command begins accesses, followed by a READ or WRITE command. The ACTIVE command in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The READ or WRITE commands in conjunction with address bits registered are used to select the starting column location for the burst access. Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations or full page, with a burst terminate option. FUNCTIONAL BLOCK DIAGRAM CLK CKE CS RAS CAS WE A11 DQM COMMAND DECODER & CLOCK GENERATOR DATA IN BUFFER 16 16 MODE REGISTER 11 REFRESH CONTROLLER I/O 0-15 SELF REFRESH CONTROLLER A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0 BA1 11 DATA OUT BUFFER 16 16 Vcc/VccQ GND/GNDQ REFRESH COUNTER 4096 4096 4096 4096 ROW DECODER MULTIPLEXER MEMORY CELL ARRAY 11 ROW ADDRESS LATCH 11 ROW ADDRESS BUFFER BANK 0 SENSE AMP I/O GATE COLUMN ADDRESS LATCH 8 256K (x 16) BANK CONTROL LOGIC BURST COUNTER COLUMN DECODER COLUMN ADDRESS BUFFER 8 2 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A PIN CONFIGURATIONS 54 pin TSOP - Type II for x8 ISSI (R) VDD I/O0 VDDQ NC I/O1 VSSQ NC I/O2 VDDQ NC I/O3 VSSQ NC VDD NC WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS I/O7 VSSQ NC I/O6 VDDQ NC I/O5 VSSQ NC I/O4 VDDQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS PIN DESCRIPTIONS A0-A11 A0-A8, A10 BA0, BA1 I/O0 to I/O7 CLK CKE CS RAS CAS Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command WE DQM VDD Vss VDDQ VssQ NC Write Enable x 8 Lower Bye, Input/Output Mask Power Ground Power Supply for I/O Pin Ground for I/O Pin No Connection Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 3 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A PIN CONFIGURATIONS 54-Ball FBGA for x16 ISSI 7 8 9 (R) 1 2 3 4 5 6 A Vss B I/O14 C I/O12 D I/O10 E I/O8 F UDQM G NC/A12 H A8 J Vss A5 A4 A3 A2 Vss A7 A6 A0 A1 A10 A11 A9 BA0 BA1 CS CLK CKE CAS RAS WE NC Vss VDD LDQM I/O7 I/O9 VDDQ VssQ I/O6 I/O5 I/O11 VssQ VDDQ I/O4 I/O3 I/O13 VDDQ VssQ I/O2 I/O1 I/O15 VssQ VDDQ I/O0 VDD PIN DESCRIPTIONS A0-A11 A0-A8, A10 BA0, BA1 DQ0 to DQ15 CLK CKE CS RAS CAS Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command WE LDQM UDQM VDD Vss VDDQ VssQ NC Write Enable x16 Lower Bye, Input/Output Mask x16 Upper Bye, Input/Output Mask Power Ground Power Supply for I/O Pin Ground for I/O Pin No Connection 4 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A PIN CONFIGURATIONS 54 pin TSOP - Type II for x16 ISSI (R) VDD I/O0 VDDQ I/O1 I/O2 VSSQ I/O3 I/O4 VDDQ I/O5 I/O6 VSSQ I/O7 VDD LDQM WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS I/O15 VSSQ I/O14 I/O13 VDDQ I/O12 I/O11 VSSQ I/O10 I/O9 VDDQ I/O8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS PIN DESCRIPTIONS A0-A11 A0-A8, A10 BA0, BA1 I/O0 to I/O15 CLK CKE CS RAS CAS Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command WE LDQM UDQM VDD Vss VDDQ VssQ NC Write Enable x16 Lower Bye, Input/Output Mask x16 Upper Bye, Input/Output Mask Power Ground Power Supply for I/O Pin Ground for I/O Pin No Connection Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 5 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A PIN CONFIGURATIONS 90-Ball FBGA for x32 ISSI (R) 1 A I/O26 B I/O28 C VssQ D VssQ E VDDQ F Vss G A4 H A7 J CLK K DQM1 L VDDQ M VssQ N VssQ P I/O11 R I/O13 2 3 4 5 6 7 8 9 I/O24 VDDQ I/O27 I/O29 I/O31 DQM3 A5 A8 CKE NC I/O8 I/O10 I/O12 VDDQ I/O15 Vss VssQ I/O25 I/O30 NC A3 A6 NC A9 NC Vss I/O9 I/O14 VssQ Vss VDD VDDQ I/O22 I/O17 NC A2 A10 NC/A12 BA0 CAS VDD I/O6 I/O1 VDDQ VDD I/O23 Vss I/O20 I/O18 I/O16 DQM2 A0 BA1 CS WE I/O7 I/O5 I/O3 VssQ I/O0 I/O21 I/O19 VDDQ VDDQ Vss VDD A1 A11 RAS DQM0 VssQ VDDQ VDDQ I/O4 I/O2 PIN DESCRIPTIONS A0-A11 A0-A8, A10 BA0, BA1 I/O0 to I/O31 CLK CKE CS RAS CAS Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command WE DQM0-DQM3 VDD Vss VDDQ VssQ NC Write Enable x32 Input/Output Mask Power Ground Power Supply for I/O Pin Ground for I/O Pin No Connection 6 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A PIN CONFIGURATIONS 86 pin TSOP - Type II for x32 VDD I/O0 VDDQ I/O1 I/O2 VSSQ I/O3 I/O4 VDDQ I/O5 I/O6 VSSQ I/O7 NC VDD DQM0 WE CAS RAS CS A11 BA0 BA1 A10 A0 A1 A2 DQM2 VDD NC I/O16 VSSQ I/O17 I/O18 VDDQ I/O19 I/O20 VSSQ I/O21 I/O22 VDDQ I/O23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS I/O15 VSSQ I/O14 I/O13 VDDQ I/O12 I/O11 VSSQ I/O10 I/O9 VDDQ I/O8 NC VSS DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC I/O31 VDDQ I/O30 I/O29 VSSQ I/O28 I/O27 VDDQ I/O26 I/O25 VSSQ I/O24 VSS ISSI (R) PIN DESCRIPTIONS A0-A11 A0-A8, A10 BA0, BA1 I/O0 to I/O31 CLK CKE CS RAS CAS Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command WE DQM0-DQM3 VDD Vss VDDQ VssQ NC Write Enable x32 Input/Output Mask Power Ground Power Supply for I/O Pin Ground for I/O Pin No Connection Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 7 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A PIN FUNCTIONS Symbol A0-A11 Type Input Pin Function (In Detail) ISSI (R) Address Inputs: A0-A11 are sampled during the ACTIVE command (row-address A0-A11) and READ/WRITE command (A0-A7 with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. CAS, in conjunction with the RAS and WE, forms the device command. See the "Command Truth Table" for details on device commands. The CKE input determines whether the CLK input is enabled. The next rising edge of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW, the device will be in either power-down mode, clock suspend mode, or self refresh mode. CKE is an asynchronous input. CLK is the master clock input for this device. Except for CKE, all inputs to this device are acquired in synchronization with the rising edge of this pin. The CS input determines whether command input is enabled within the device. Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device remains in the previous state when CS is HIGH. I/O0 to I/O32 are I/O pins. I/O through these pins can be controlled in byte units using the LDQM and UDQM pins. LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to OE in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can be written to the device. When LDQM or UDQM is HIGH, input data is masked and cannot be written to the device. BA0, BA1 CAS CKE Input Pin Input Pin Input Pin CLK CS Input Pin Input Pin I/O0 to I/O32 LDQM, UDQM I/O Pin Input Pin DQM0-DQM3 DQM RAS WE VDDQ VDD VSSQ VSS Input Pin Input Pin Input Pin Input Pin Power Supply Pin Power Supply Pin Power Supply Pin Power Supply Pin RAS, in conjunction with CAS and WE, forms the device command. See the "Command Truth Table" item for details on device commands. WE, in conjunction with RAS and CAS, forms the device command. See the "Command Truth Table" item for details on device commands. VDDQ is the output buffer power supply. VDD is the device internal power supply. VSSQ is the output buffer ground. VSS is the device internal ground. 8 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A GENERAL DESCRIPTION READ The READ command selects the bank from BA0, BA1 inputs and starts a burst read access to an active row. Inputs A0-A7 provides the starting column location. When A10 is HIGH, this command functions as an AUTO PRECHARGE command. When the auto precharge is selected, the row being accessed will be precharged at the end of the READ burst. The row will remain open for subsequent accesses when AUTO PRECHARGE is not selected. DQ's read data is subject to the logic level on the DQM inputs two clocks earlier. When a given DQM signal was registered HIGH, the corresponding DQ's will be HighZ two clocks later. DQ's will provide valid data when the DQM signal was registered LOW. ISSI (R) PRECHARGE function in conjunction with a specific READ or WRITE command. For each individual READ or WRITE command, auto precharge is either enabled or disabled. AUTO PRECHARGE does not apply except in full-page burst mode. Upon completion of the READ or WRITE burst, a precharge of the bank/row that is addressed is automatically performed. AUTO REFRESH COMMAND This command executes the AUTO REFRESH operation. The row address and bank to be refreshed are automatically generated during this operation. The stipulated period (tRC) is required for a single refresh operation, and no other commands can be executed during this period. This command is executed at least 4096 times for every 64ms. During an AUTO REFRESH command, address bits are "Don't Care". This command corresponds to CBR Auto-refresh. WRITE A burst write access to an active row is initiated with the WRITE command. BA0, BA1 inputs selects the bank, and the starting column location is provided by inputs A0-A7. Whether or not AUTO-PRECHARGE is used is determined by A10. The row being accessed will be precharged at the end of the WRITE burst, if AUTO PRECHARGE is selected. If AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. A memory array is written with corresponding input data on DQ's and DQM input logic level appearing at the same time. Data will be written to memory when DQM signal is LOW. When DQM is HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/ column location. BURST TERMINATE The BURST TERMINATE command forcibly terminates the burst read and write operations by truncating either fixedlength or full-page bursts and the most recently registered READ or WRITE command prior to the BURST TERMINATE. COMMAND INHIBIT COMMAND INHIBIT prevents new commands from being executed. Operations in progress are not affected, apart from whether the CLK signal is enabled NO OPERATION When CS is low, the NOP command prevents unwanted commands from being registered during idle or wait states. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. BA0, BA1 can be used to select which bank is precharged or they are treated as "Don't Care". A10 determined whether one or all banks are precharged. After executing this command, the next command for the selected banks(s) is executed after passage of the period tRP, which is the period required for bank precharging. Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. LOAD MODE REGISTER During the LOAD MODE REGISTER command the mode register is loaded from A0-A11. This command can only be issued when all banks are idle. EXTENDED MODE REGISTER The extended mode register defines low power functions. During this command A0-A11 are data input pins. After power on, the extended mode register set command must be executed to fix low power functions. During tRSC following this command, they can not accept any other command. AUTO PRECHARGE The AUTO PRECHARGE function ensures that the precharge is initiated at the earliest valid stage within a burst. This function allows for individual-bank precharge without requiring an explicit command. A10 to enables the AUTO Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 9 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A GENERAL DESCRIPTION Continued: The extended mode register has four fields: Options: A11-A7 Drive Strength: A6-A5 Temperature Compensated self Refresh: A4-A3 Partial Array Self Refresh: A2-A0 Following extended mode register programming, no command can be issued before at least 2 CLK have elapsed. ISSI (R) ACTIVE COMMAND When the ACTIVE COMMAND is activated, BA0, BA1 inputs selects a bank to be accessed, and the address inputs on A0-A11 selects the row. Until a PRECHARGE command is issued to the bank, the row remains open for accesses. 10 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A COMMAND TRUTH TABLE Function Symbol Device deselect No operation H Burst stop Read Read with auto precharge Write Write with auto precharge Bank activate Precharge select bank Precharge all banks Mode register set Extended mode reg set CKE n-1 H x H H H H H H H H H H n x L H x x x x x x x x x CS H H L L L L L L L L L L RAS x H H H H H H L L L L L CAS x H H L L L L H H H L L WE x x L H H L L H L L L L BA1 x x x V V V V V V x L H BA0 x x x V V V V V V x L L ISSI A10 x x L H L H V L H L L (R) A11 A9 - A0 x x V V V V V x x V V Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data. DQM TRUTH TABLE Function Symbol Data write / output enable Data mask / output disable Upper byte write enable / output enable Lower byte write enable / output enable Upper byte write inhibit / output disable Lower byte write inhibit / output disable CKE n-1 H H H H H H n x x x x x x DQM U L H L x H x L L H x L x H Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 11 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A CKE TRUTH TABLE CKE Current State /Function Activating Clock suspend mode entry Any Clock suspend mode Clock suspend mode exit Auto refresh command Idle Self refresh entry Idle Power down entry Idle Deep power down entry Self refresh exit Power down exit Deep power down exit Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data. ISSI RAS x x x L L H x H H x H x x CAS x x x L L H x H H x H x x WE x x x H H H x L H x H x x Address x x x x x x x x x x x x x (R) n-1 H L L H H H H H L L L L L n L L H H L L L L H H H H H CS x x x L L L H L L H L H x 12 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A FUNCTIONAL TRUTH TABLE CS Idle H L L L L L L L L L Row Active H L L L L L L L L Read H L L L L L L L L Write H L L L L L L L L RAS CAS X H H H H L L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H L L H H L L L X H H L L H H L L X H H L L H H L L X H H L L H H L L WE X H L H L H L H L L X H L H L H L H L X H L H L H L H L X H L H L H L H L Address X X X BA, CA, A10 A, CA, A10 BA, RA A, A10 X OC, BA1=L OC, BA1=H X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X OC, BA X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X OC, BA X X X BA, CA, A10 BA, CA, A10 BA, BA, A10 X OC, BA Command DESL NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF MRS EMRS DESL NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF MRS/EMRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF MRS/EMRS DESL NOP BST READ/READA WRIT/WRITA RA ACT PRE/PALL REF MRS/EMRS Action Nop Nop Nop ILLEGAL (2) ILLEGAL(2) ISSI (R) Row activating Nop Auto refresh Mode register set Extended mode register set Nop Nop Nop Begin read Begin write ILLEGAL ILLEGAL ILLEGAL Continue burst to end to Row active Continue burst to end Row Row active Burst stop Row active Terminate burst, begin new read (5) Terminate burst, begin write (5, 6) ILLEGAL (2) Terminate burst Precharging ILLEGAL ILLEGAL Continue burst to end Write recovering Continue burst to end Write recovering Burst stop Row active Terminate burst, start read : Determine AP (5, 6) Terminate burst, new write : Determine AP (5) ILLEGAL (2) Terminate burst Precharging ILLEGAL ILLEGAL (7) (2) (3) (3) Precharge/Precharge all banks( Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 13 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A FUNCTIONAL TRUTH TABLE Continued: CS Read with auto Precharging Precharge Precharging H L L L L L L L L Write with Auto Precharge H L L L L L L L L Precharging H L L L L L L L L Row Activating H L L L L L L L L RAS CAS x H H H H L L L L x H H H H L L L L x H H H H L L L L x H H H H L L L L x H H L L H H L L x H H L L H H L L x H H L L H H L L x H H L L H H L L WE x H L H L H L H L x H L H L H L H L x H L H L H L H L x H L H L H L H L Address x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OC, BA x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OC, BA x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OC, BA x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OC, BA PRE/PALL REF MRS/EMRS DESL NOP BST READ/READA WRIT/WRITA ACT I PRE/PALL REF MRS/EMRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF MRS/EMRS ILLEGAL (2) ILLEGAL ILLEGAL Command DESL NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF MRS/EMRS DESL NOP BST READ/READA WRIT/ WRITA Action ISSI Continue burst to end Continue burst to end ILLEGAL ILLEGAL (2) ILLEGAL (2) ILLEGAL (2) ILLEGAL (2) ILLEGAL ILLEGAL Continue burst to end -Write recovering with auto precharge Continue burst to end -Write recoveringwith auto precharge ILLEGAL ILLEGAL(2) ILLEGAL (2) (R) Nop Enter idle after tRP Nop Enter idle after tRP ILLEGAL ILLEGAL (2) ILLEGAL (2) LLEGAL(2) Nop Enter idle after tRP ILLEGAL ILLEGAL Nop Enter bank active after tRCD Nop Enter bank active after tRCD ILLEGAL ILLEGAL (2) ILLEGAL (2) ILLEGAL (2,8) ILLEGAL (2) ILLEGAL ILLEGAL Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code 14 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A FUNCTIONAL TRUTH TABLE Continued: CS Write Recovering H L L L L L L L L Write Recovering with Auto Precharge H L L L L L L L L Refresh H L L L L L L L L Mode Register Accessing H L L L L L L L L RAS CAS x H H H H L L L L x H H H H L L L L x H H H H L L L L x H H H H L L L L x H H L L H H L L x H H L L H H L L x H H L L H H L L x H H L L H H L L WE x H L H L H L H L x H L H L H L H L x H L H L H L H L x H L H L H L H L Address x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OC, BA x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OC, BA x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OC, BA x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OC, BA Command DESL NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF MRS/EMRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF MRS/EMRS DESL NOP BST EAD/READA WRIT/WRITA ACT PRE/PALL REF MRS/EMRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF MRS/EMRS Action ISSI (R) Nop Enter row active after tDPL Nop Enter row active after tDPL Nop Enter row active after tDPL Begin read (6) Begin new write ILLEGAL (2) ILLEGAL (2) ILLEGAL ILLEGAL Nop Enter precharge after tDPL Nop Enter precharge after tDPL Nop Enter row active after tDPL ILLEGAL ILLEGAL (2, 6) ILLEGAL (2) ILLEGAL (2) ILLEGAL ILLEGAL Enter idle after tRC1 Nop Enter idle after tRC1 Nop Enter idle after tRC1 ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter idle after tRSC Nop Enter idle after tRSC Nop Enter idle after tRSC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 15 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A FUNCTIONAL TRUTH TABLE Continued: ISSI (R) Notes: 1. All entries assume that CKE is active (CKEn-1=CKEn=H). 2. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 3. Illegal if tRCD is not satisfied. 4. Illegal if tRAS is not satisfied. 5. Must satisfy burst interrupt condition. 6. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 7. Must mask preceding data which don't satisfy tDPL. 8. Illegal if tRRD is not satisfied. 16 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A STATE DIAGRAM ISSI (R) Extended Mode Register Set SELF EMRS SELF exit Mode Register Set MRS IDLE Self Refresh REF CBR (Auto) Refresh DPD DPD Exit Deep Power Down ACT CKE CKE Power Down CKE Row Active BST CKE BST Active Power Down th rge Write Write Read Au to Re wi ha rite W WRITE SUSPEND Au CKE WRITE CKE to Pr ec Read CKE READ CKE th wi ad arge h ec Pr Write Read READ SUSPEND POWER ON Precharge Precharge PR E (P rec ha rge WRITEA SUSPEND ter WRITEA CKE mi CKE na tio Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 RR E( Pr rge ha ec ter na mi n) tio n) CKE READA CKE READA SUSPEND Automatic sequence Manual Input 17 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A ABSOLUTE MAXIMUM RATINGS(1) Symbol VDD MAX VDDQ MAX +4.6 VIN VOUT PD MAX ICS TOPR TSTG Parameters Maximum Supply Voltage Maximum Supply Voltage for Output Buffer V Input Voltage Output Voltage Allowable Power Dissipation Output Shorted Current Operating Temperature Com. Ind. Storage Temperature Rating -0.5 to +3.6 ISSI Unit -0.5 to +4.6 V -0.5 to +3.6 -0.5 to -0.5 to +4.6 -0.5 to +4.6 1 50 0 to +70 -40 to +85 -55 to +125 V V W mA C C (R) -0.5 to +3.6 -0.5 to +3.6 1 50 0 to +70 -40 to +85 -55 to +125 Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All voltages are referenced to Vss. DC RECOMMENDED OPERATING CONDITIONS(2) (At TA = 0 to +70C) Symbol VDD VDDQ VIH(1) VIL(2) Note: 1. VIH (max) = VDDQ +1.5V (PULSE WIDTH < 5NS). 2. VIL (min) = -1.5V (PULSE WIDTH < 5NS). Parameter Supply Voltage I/O Supply Voltage Input High Voltage Input Low Voltage Min. 42LSxxxxxx Typ. Max. 2.5 2.0 -- -- 2.7 2.5 VDDQ + 0.3 +0.3 Min. 3.0 3.0 2.0 -0.3 42Sxxxxxx Typ. Max. 3.3 3.6 3.3 3.6 -- VDDQ + 0.3 -- +0.8 Unit V V V V 2.3 1.65 0.8xVDDQ -0.3 CAPACITANCE CHARACTERISTICS(1,2) (At TA = 0 to +25C, Vdd = VddQ= 3.3 0.3V, f = 1 MHz) Symbol CIN1 CIN2 CI/O Parameter Input Capacitance: A0-A11, BA0, BA1 Input Capacitance: (CLK, CKE, CS, RAS, CAS, WE, LDQM, UDQM) Data Input/Output Capacitance: I/O0-I/O15 Typ. -- -- -- Max. 3.5 3.8 6.5 Unit pF pF pss. 18 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A ISSI Speed Min. -5 -5 2.4 -- -7 -7 -10 -10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -7 -7 -10 -10 -7 -7 -10 -10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 5 5 -- 0.4 120 140 110 120 1 1 .6 .6 11 5 7 4 6 3 5 28 17 20 120 140 110 120 90 110 80 100 (R) DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.) Symbol IIL IOL VOH VOL IDD1 Parameter Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level Operating Current(1,2) Test Condition 0V VIN VDD, with pins other than the tested pin at 0V Output is disabled, 0V VOUT VDD IOUT = -2 mA IOUT = +2 mA One Bank Operation, CAS latency = 3 Burst Length=1 Com. tRC tRC (min.) Ind. IOUT = 0mA Com. Ind. CKE VIL (MAX) tCK = tCK (MIN) Com. Ind. tCK = Com. Ind. CKE VIH (MIN) tCK = tCK (MIN) tCK = Com. Ind. CKE VIL (MAX) tCK = tCK (MIN) Com. Ind. Ind. tCK = Com. Ind. CKE VIH (MIN) tCK = tCK (MIN) tCK = Com. Ind. tCK = tCK (MIN) CAS latency = 3 IOUT = 0mA Com. Ind. Com. Ind. CAS latency = 2 Com. Ind. Com. Ind. Unit A A V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA IDD2P IDD2PS IDD2N IDD2NS IDD3P IDD3PS IDD3N IDD3NS IDD4 Precharge Standby Current (In Power-Down Mode) Precharge Standby Current (In Non Power-Down Mode) Active Standby Current (In Power-Down Mode) Active Standby Current (In Non Power-Down Mode) Operating Current (In Burst Mode)(1) Notes: 1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time increases. Also note that a bypass capacitor of at least 0.01 F should be inserted between Vdd and Vss for each memory chip to suppress power supply voltage noise (voltage drops) due to these transient currents. 2. Idd1 and Idd4 depend on the output load. The maximum values for Idd1 and Idd4 are obtained with the output open state. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 19 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A ISSI Speed Min. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 330 350 300 330 330 350 300 330 0.35 0.25 0.18 0.12 0.09 0.20 0.15 0.10 0.08 0.07 0.60 0.50 0.43 0.37 0.34 10 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA A Com. Ind. Com. Ind. -7 -7 -10 -10 -7 -7 -10 -10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- (R) DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.) Symbol IDD5 Parameter Auto-Refresh Current Test Condition tRC = tRC (MIN) CAS latency = 3 CAS latency = 2 Com. Ind. Com. Ind. IDD6 IDD6 IDD6 IDD7 Self-Refresh Current PASR=000 (full) PASR=001 (2BK) PASR=010 (1BK) PASR=101 (1/2BK) PASR=110 (1/4BK) Self-Refresh Current PASR=000 (full) PASR=001 (2BK) PASR=010 (1BK) PASR=101 (1/2BK) PASR=110 (1/4BK) Self-Refresh Current PASR=000 (full) PASR=001 (2BK) PASR=010 (1BK) PASR=101 (1/2BK) PASR=110 (1/4BK) Standby Current in Deep Power Down Mode CKE 0.2V, tCSR = 00 ts < 70OC CKE 0.2V, , tCSR = 01 ts < 45OC CKE 0.2V, , tCSR = 11 ts < 85OC CKE 0.2V 20 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A AC ELECTRICAL CHARACTERISTICS Symbol Parameter tCK3 tCK2 tAC3 tAC2 tCHI tCL tOH3 tOH2 tLZ tHZ3 tHZ2 tDS tDH tAS tAH tCKS tCKH tCKA tCS tCH ns tRC tRAS tRP tRCD tRRD tDPL3 tDPL2 tDAL3 tDAL2 tT tREF Clock Cycle Time Access Time From CLK(4) CLK HIGH Level Width CLK LOW Level Width Output Data Hold Time Output LOW Impedance Time Output HIGH Impedance Time(5)CAS Latency = 3 CAS Latency = 2 Input Data Setup Time Input Data Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time CKE to CLK Recovery Delay Time Command Setup Time (CS, RAS, CAS, WE, DQM) Command Hold Time (CS, RAS, CAS, WE, DQM) Command Period (REF to REF / ACT to ACT) Command Period (ACT to PRE) Command Period (PRE to ACT) Active Command To Read / Write Command Delay Time Command Period (ACT [0] to ACT[1]) Input Data To Precharge Command Delay time CAS Latency = 3 CAS Latency = 2 Input Data To Active / Refresh CAS Latency = 3 Command Delay time (During Auto-Precharge) CAS Latency = 2 Transition Time Refresh Cycle Time (4096) 63 37 15 15 14 2CLK 2CLK CLK+tRP 2CLK+tRP 0.5 -- CAS Latency = 3 CAS Latency = 2 CAS Latency = 3 CAS Latency = 2 CAS Latency = 3 CAS Latency = 2 (1,2,3) ISSI -7 Min. 7 10 -- -- 2.5 2.5 2.5 2.5 0 -- -- 1.5 0.8 .5 0.8 1.5 0.8 1CLK+3 1.5 Max. -- -- 5.4 6 -- -- -- -- -- 6 6 -- -- -- -- -- -- -- -- 0.8 -- 120,000 -- -- -- -- -- -- -- 30 64 -10 Min. Max 10 10 -- -- 3.5 3.5 2.5 2.5 0 -- -- 2.0 1 2.0 1 2.0 1 1CLK+3 2.0 -- 70 44 18 18 15 2CLK 2CLK 2CLK+tRP 2CLK+tRP 0.5 -- -- -- 7 9 -- -- -- -- -- 7 9 -- -- -- -- -- -- -- -- 1 -- 120,000 -- -- -- -- -- -- -- 30 64 (R) Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -- ns ns ns ns ns ns ns ns ns ns ms Notes: 1. When power is first applied, memory operation should be started 100 s after Vdd and VddQ reach their stipulated voltages. Also note that the power-on sequence must be executed before starting memory operation. 2. Measured with tT = 1 ns. 3. The reference level is 0.9V when measuring input signal timing. Rise and fall times are measured between VIH (min.) and VIL (max.). 4. Access time is measured at 0.9V with the load shown in the figure below. 5. The time tHZ (max.) is defined as the time required for the output voltage to transition by 200 mV from VOH (min.) or VOL (max.) when the output is in the high impedance state. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 21 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL -- -- tCCD tCKED tPED tDQD tDQM tDQZ tDWD tDAL tDPL tBDL tCDL tRDL tMRD tROH PARAMETER Clock Cycle Time Operating Frequency READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to data mask during WRITEs DQM to data high-impedance during READs WRITE command to input data delay Data-in to ACTIVE command Data-in to PRECHARGE command Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command CL = 3 CL = 2 -7 7 133 1 1 1 0 0 2 0 5 2 1 1 2 2 3 2 ISSI -10. 10 100 1 1 1 0 0 2 0 4 2 1 1 2 2 3 2 UNITS ns MHz cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle (R) 22 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A AC TEST CONDITIONS Input Load tCK tCHI 1.6V ISSI (R) Output Load tCL Vddq 350 CLK 0.9V 0.2V tCS 1.6V tCH Z = 50 Output 30 pF 350 INPUT 0.9V 0.2V tOH OUTPUT 0.9V tAC 0.9V AC TEST CONDITIONS Parameter AC High Level Input Voltage/Low Level Input Voltage Input Rise and Fall Times Input Timing Reference Level Output Timing Measurement Reference Level Unit 1.6V to 0.2V 1 ns 0.9V 0.9V Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 23 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A FUNCTIONAL DESCRIPTION The 128Mb SDRAMs are quad-bank DRAMs which operate at 2.5V or 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-A11 select the row). The address bits (A0-A7) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. ISSI (R) Initialization SDRAMs must be powered up and initialized in a predefined manner. The 128M SDRAM is initialized after the power is applied to VDD and Vddq (simultaneously) and the clock is stable. A 200s delay is required prior to issuing any command other than a COMMAND INHIBIT or a NOP. The COMMAND INHIBIT or NOP may be applied during the 100us period and should continue at least through the end of the period. With at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied once the 100s delay has been satisfied. All banks must be precharged. This will leave all banks in an idle state where two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SRDRAM is then ready for mode register programming. The mode register and extended mode registers should be loaded prior to applying any operational command because it will power up in an unknown state. 24 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A INITIALIZE AND LOAD MODE REGISTER ISSI Tp+1 Tp+2 Tp+3 (R) T0 CLK tCK tCKS tCKH CKE tCMH tCMS COMMAND DQM/ DQML, DQMH NOP T1 Tn+1 tCH To+1 tCL tCMH tCMS PRECHARGE tCMH tCMS AUTO REFRESH NOP AUTO REFRESH NOP Load MODE REGISTER NOP ACTIVE tAS tAH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 DQ T Power-up: VCC and CLK stable T = 100s Min. tRP Precharge all banks tRFC AUTO REFRESH tRFC AUTO REFRESH tMRD Program MODE REGISTER (2, 3, 4) DON'T CARE ALL BANKS BANK CODE tAS tAH CODE ROW ROW Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 25 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A AUTO-REFRESH CYCLE ISSI Tn+1 To+1 (R) T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 DQ BANK(s) tAS tAH High-Z PRECHARGE tCK T1 tCL T2 tCH NOP Auto Refresh NOP Auto Refresh NOP ACTIVE ROW ROW BANK tRP DON'T CARE CAS latency = 2, 3 26 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A SELF-REFRESH CYCLE ISSI Tn+1 To+1 To+2 (R) T0 CLK tCK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK tAS tAH BA0, BA1 BANK PRECHARGE T1 tCH tCL T2 tCKS tRAS tCKS NOP Auto Refresh NOP NOP Auto Refresh DQ High-Z tRP Precharge all active banks Enter self refresh mode tXSR CLK stable prior to exiting Exit self refresh mode self refresh mode (Restart refresh time base) DON'T CARE CAS latency = 2, 3 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 27 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A EXTENDED MODE REGISTER SET ISSI (R) CLK CKE CS H tRSC 2 CLK (min) RAS CAS WE BA0 BA1 A10 Address Key ADD DQM DQ Hi-Z Precharge All Banks Command Extended Mode Register Set Command Activated Command is valid DON'T CARE 28 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A REGISTER DEFINITION Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS\ latency, an operating mode and a write burst mode, as shown in MODE REGISTER DEFINITION. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. ISSI (R) Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4- M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the WRITE burst mode, and M10 and M11 are reserved for future use. The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. MODE REGISTER DEFINITION A11 A10 (1) A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus Mode Register (Mx) Reserved Burst Length M2 0 0 0 0 1 1 1 1 Burst Type M3 0 1 Latency Mode M6 M5 M4 0 0 0 0 1 1 1 1 Operating Mode M8 M7 00 ---- M6-M0 Defined -- Mode Standard Operation All Other States Reserved 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved Type Sequential Interleaved M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 M3=0 1 2 4 8 Reserved Reserved Reserved Full Page M3=1 1 2 4 8 Reserved Reserved Reserved Reserved Write Burst Mode M9 0 1 Mode Programmed Burst Length Single Location Access 1. To ensure compatibility with future devices, should program M11, M10 = "0, 0" Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 29 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A BURST LENGTH Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in MODE REGISTER DEFINITION. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, mean- ISSI (R) ing that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A7 (x16) when the burst length is set to two; by A2-A7 (x16) when the burst length is set to four; and by A3-A7 (x16) when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in BURST DEFINITION table. BURST DEFINITION Burst Length 2 A1 0 4 0 1 1 A2 0 0 0 8 0 1 1 1 1 Full Page (y) n = A0-A7 (location 0-y) A1 0 0 1 1 0 0 1 1 Starting Column Address A0 0 1 A0 0 1 0 1 A0 0 1 0 1 0 1 0 1 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn + 1, Cn + 2 Cn + 3, Cn + 4... ...Cn - 1, Cn... 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not Supported 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1 1-0 0-1 1-0 Order of Accesses Within a Burst Type = Sequential Type = Interleaved 30 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in CAS Latency diagrams. The Allowable Operating Frequency table indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. ISSI (R) reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. CAS Latency Allowable Operating Frequency (MHz) Speed 7.5 10 CAS Latency = 2 100 75 CAS Latency = 3 133 100 Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are CAS LATENCY T0 CLK T1 T2 T3 COMMAND DQ READ NOP tAC NOP DOUT tLZ CAS Latency - 2 tOH T0 CLK T1 T2 T3 T4 COMMAND DQ READ NOP NOP tAC NOP DOUT tLZ CAS Latency - 3 tOH DON'T CARE UNDEFINED Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 31 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A CHIP OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be "opened." This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Activating Specific Row Within Specific Bank). After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. Minimum tRCD should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks, rounded to 3. This is reflected in the following example, which covers any case where 2 < [tRCD (MIN)/tCK] 3. (The same procedure is used to convert other specification limits from time units to clock cycles). A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD. ISSI (R) ACTIVATING SPECIFIC ROW WITHIN SPECIFIC BANK CLK HIGH CKE CS RAS CAS WE A0-A11 BA0, BA1 ROW ADDRESS BANK ADDRESS EXAMPLE: MEETING TRCD (MIN) WHEN 2 < [TRCD (MIN)/TCK] 3 T0 CLK T1 T2 T3 T4 COMMAND ACTIVE NOP tRCD NOP READ or WRITE DON'T CARE 32 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A READS READ bursts are initiated with a READ command, as shown in the READ COMMAND diagram. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent dataout element will be valid by the next positive clock edge. The CAS Latency diagram shows general timing for each possible CAS latency setting. Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Consecutive READ Bursts for CAS latencies of two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. The 64Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command. Full-speed random read accesses can be performed to the same bank, as shown in Random READ Accesses, or each subsequent READ may be performed to a different bank. Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length READ burst may be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. ISSI HIGH (R) READ COMMAND CLK CKE CS RAS CAS WE A0-A7 A8, A9, A11 AUTO PRECHARGE COLUMN ADDRESS A10 NO PRECHARGE BA0, BA1 BANK ADDRESS The DQM input is used to avoid I/O contention, as shown in Figures RW1 and RW2. The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or remain HighZ), regardless of the state of the DQM signal, provided the DQM was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in Figure RW2, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid. The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure RW1 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure RW2 shows the case where the additional NOP is needed. A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page burst may be truncated with a PRECHARGE command to the Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 33 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in the READ to PRECHARGE diagram for each possible CAS latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in the READ Burst Termination diagram for each possible CAS latency; data element n + 3 is the last desired data element of a longer burst. ISSI (R) 34 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A RW1 - READ TO WRITE ISSI T3 T4 (R) T0 CLK T1 T2 DQM COMMAND READ NOP NOP NOP WRITE ADDRESS BANK, COL n BANK, COL b DQ tHZ DOUT n DIN b tDS DON'T CARE RW2 - READ TO WRITE WITH EXTRA CLOCK CYCLE T0 CLK T1 T2 T3 T4 T5 DQM COMMAND READ NOP NOP NOP NOP WRITE ADDRESS BANK, COL n BANK, COL b DQ tHZ DOUT n DIN b tDS DON'T CARE Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 35 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A CONSECUTIVE READ BURSTS ISSI (R) T0 CLK T1 T2 T3 T4 T5 T6 COMMAND READ NOP NOP NOP READ x =1 cycle NOP NOP ADDRESS BANK, COL n BANK, COL b DQ CAS Latency - 2 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DOUT b DON'T CARE T0 CLK T1 T2 T3 T4 T5 T6 T7 COMMAND READ NOP NOP NOP READ NOP x = 2 cycles NOP NOP ADDRESS BANK, COL n BANK, COL b DQ CAS Latency - 3 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DOUT b DON'T CARE 36 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A RANDOM READ ACCESSES ISSI (R) T0 CLK T1 T2 T3 T4 T5 COMMAND READ READ READ READ NOP NOP ADDRESS BANK, COL n BANK, COL b BANK, COL m BANK, COL x DQ CAS Latency - 2 DOUT n DOUT b DOUT m DOUT x DON'T CARE T0 CLK T1 T2 T3 T4 T5 T6 COMMAND READ READ READ READ NOP NOP NOP ADDRESS BANK, COL n BANK, COL b BANK, COL m BANK, COL x DQ CAS Latency - 3 DOUT n DOUT b DOUT m DOUT x DON'T CARE Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 37 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A RW1 - READ TO WRITE ISSI (R) T0 CLK T1 T2 T3 T4 DQM COMMAND READ NOP NOP NOP WRITE ADDRESS BANK, COL n BANK, COL b DQ tHZ DOUT n DIN b tDS DON'T CARE RW2 - READ TO WRITE WITH EXTRA CLOCK CYCLE T0 CLK T1 T2 T3 T4 T5 DQM COMMAND READ NOP NOP NOP NOP WRITE ADDRESS BANK, COL n BANK, COL b DQ tHZ DOUT n DIN b tDS DON'T CARE 38 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A READ BURST TERMINATION ISSI (R) T0 CLK T1 T2 T3 T4 T5 T6 COMMAND READ NOP NOP NOP BURST TERMINATE NOP NOP x = 1 cycle ADDRESS BANK a, COL n DQ CAS Latency - 2 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DON'T CARE T0 CLK T1 T2 T3 T4 T5 T6 T7 COMMAND READ NOP NOP NOP BURST TERMINATE NOP x = 2 cycles NOP NOP ADDRESS BANK, COL n DQ CAS Latency - 3 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DON'T CARE Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 39 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A ALTERNATING BANK READ ACCESSES ISSI T6 T7 T8 (R) T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK 0 ACTIVE tCK T1 tCL T2 tCH T3 T4 T5 NOP READ tCMS tCMH NOP ACTIVE NOP READ NOP ACTIVE COLUMN m(2) ENABLE AUTO PRECHARGE ROW ROW COLUMN b(2) ENABLE AUTO PRECHARGE ROW ROW BANK 0 tLZ BANK 3 tOH DOUT m tAC tAC tOH DOUT m+1 tAC BANK 3 tOH DOUT m+2 tAC tRP - BANK 0 tRCD - BANK 3 CAS Latency - BANK 3 tOH DOUT m+3 tAC BANK 0 tOH DOUT b tAC tRCD - BANK 0 DQ tRCD - BANK 0 tRRD tRAS - BANK 0 tRC - BANK 0 CAS Latency - BANK 0 DON'T CARE 40 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A READ - FULL-PAGE BURST ISSI T6 Tn+1 Tn+2 Tn+3 Tn+4 (R) T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK ACTIVE T1 tCK tCL T2 tCH T3 T4 T5 NOP READ NOP NOP NOP NOP NOP BURST TERM NOP NOP tCMS tCMH COLUMN m(2) BANK tAC tAC DOUT m tAC DOUT m+1 tAC DOUT m+2 tOH tAC DOUT m-1 tOH tAC DOUT m tOH tHZ DOUT m+1 tOH DON'T CARE Full page Full-page burst not self-terminating. completion Use BURST TERMINATE command. UNDEFINED DQ tRCD tLZ CAS Latency tOH tOH each row (x4) has 1,024 locations Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 41 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A READ - DQM OPERATION ISSI T6 T7 T8 (R) T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL T2 tCH T3 T4 T5 NOP READ tCMS tCMH NOP NOP NOP NOP NOP NOP COLUMN m(2) ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE BANK tAC tOH DOUT m tHZ tLZ tAC tOH DOUT m+2 tAC tOH DOUT m+3 tHZ DON'T CARE UNDEFINED DQ tLZ tRCD CAS Latency 42 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A READ to PRECHARGE ISSI (R) T0 CLK T1 T2 T3 T4 T5 tRP T6 T7 COMMAND READ NOP NOP NOP PRECHARGE NOP NOP ACTIVE x = 1 cycle ADDRESS BANK a, COL n BANK (a or all) BANK a, ROW DQ CAS Latency - 2 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DON'T CARE T0 CLK T1 T2 T3 T4 T5 tRP T6 T7 COMMAND READ NOP NOP NOP PRECHARGE NOP x = 2 cycles NOP ACTIVE ADDRESS BANK, COL n BANK, COL b BANK a, ROW DQ CAS Latency - 3 DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DON'T CARE Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 43 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A WRITES WRITE bursts are initiated with a WRITE command, as shown in WRITE Command diagram. ISSI (R) WRITE COMMAND CLK HIGH CKE CS RAS CAS WE A0-A7 A8, A9, A11 AUTO PRECHARGE COLUMN ADDRESS A10 NO PRECHARGE BA0, BA1 BANK ADDRESS The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored (see WRITE Burst). A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command. 44 An example is shown in WRITE to WRITE diagram. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. The 128Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Random WRITE Cycles, or each subsequent WRITE may be performed to a different bank. Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE burst may be immediately followed by a subsequent READ command. Once the READ com mand is registered, the data inputs will be ignored, and WRITEs will not be executed. An example is shown in WRITE to READ. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a fullpage WRITE burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued tWR after the clock edge at which the last desired input data element is registered. The auto precharge mode requires a tWR of at least one clock plus time, regardless of frequency. In addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE command. An example is shown in the WRITE to PRECHARGE diagram. Data n+1 is either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in WRITE Burst Termination, where data n is the last desired data element of a longer burst. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A WRITE BURST T0 CLK T1 T2 T3 ISSI (R) COMMAND WRITE NOP NOP NOP ADDRESS BANK, COL n DQ DIN n DIN n+1 DON'T CARE WRITE TO WRITE T0 CLK T1 T2 COMMAND WRITE NOP WRITE ADDRESS BANK, COL n BANK, COL b DQ DIN n DIN n+1 DIN b DON'T CARE RANDOM WRITE CYCLES T0 CLK T1 T2 T3 COMMAND WRITE WRITE WRITE WRITE ADDRESS BANK, COL n BANK, COL b BANK, COL m BANK, COL x DQ DIN n DIN b DIN m DIN x Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 45 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A WRITE TO READ T0 CLK T1 T2 T3 T4 T5 ISSI (R) COMMAND WRITE NOP READ NOP NOP NOP ADDRESS BANK, COL n BANK, COL b DQ DIN n DIN n+1 DOUT b DOUT b+1 Latency = 2 DON'T CARE WRITE TO PRECHARGE (TWR @ TCK 15NS) T0 CLK T1 T2 T3 T4 T5 T6 DQM tRP COMMAND WRITE NOP PRECHARGE NOP NOP ACTIVE NOP ADDRESS BANK a, COL n BANK (a or all) BANK a, ROW tWR DQ DIN n DIN n+1 DON'T CARE 46 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A WRITE to PRECHARGE (tWR @ tCK < 15ns) T0 CLK T1 T2 T3 T4 T5 T6 ISSI (R) DQM tRP COMMAND WRITE NOP PRECHARGE NOP NOP ACTIVE NOP ADDRESS BANK a, COL n BANK (a or all) BANK a, ROW tWR DQ DIN n DIN n+1 DON'T CARE WRITE Burst Termination T0 CLK T1 T2 COMMAND WRITE BURST TERMINATE NEXT COMMAND ADDRESS BANK, COL n (ADDRESS) DQ DIN n (DATA) DON'T CARE Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 47 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A WRITE - FULL PAGE BURST T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK BANK tDS DQ tRCD tDH tDS tDH DIN m+1 tDS tDH DIN m+2 tDS tDH tDS tDH tDS COLUMN m(2) ACTIVE NOP WRITE NOP NOP NOP NOP ISSI T5 Tn+1 Tn+2 (R) T1 tCK tCL T2 tCH T3 T4 BURST TERM NOP tCMS tCMH tDH DIN m DIN m+3 DIN m-1 DON'T CARE Full page completed 48 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A WRITE - DQM OPERATIOON ISSI T5 T6 T7 (R) T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL T2 tCH T3 T4 NOP WRITE tCMS tCMH NOP NOP NOP NOP NOP COLUMN m(2) ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE BANK tDS tDH tDS tDH DIN m+2 tDS tDH DIN m tRCD DIN m+3 DON'T CARE DQ Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 49 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A ALTERNATING BANK WRITE ACCESS ISSI T6 T7 T8 T9 (R) T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK 0 ACTIVE tCK T1 tCL T2 tCH T3 T4 T5 NOP WRITE tCMS tCMH NOP ACTIVE NOP WRITE NOP NOP ACTIVE COLUMN m(2) ENABLE AUTO PRECHARGE ROW ROW COLUMN b(2) ENABLE AUTO PRECHARGE ROW ROW BANK 0 tDS tDH tDS tDH DIN m+1 BANK 1 tDS tDH DIN m+2 tDS tDH BANK 1 tDS tDH DIN b tDS tDH tDS tDH BANK 0 tDS tDH DQ tRCD - BANK 0 tRRD tRAS - BANK 0 tRC - BANK 0 DIN m DIN m+3 DIN b+1 DIN b+2 DIN b+3 tRCD - BANK 0 tWR - BANK 1 tWR - BANK 0 tRCD - BANK 1 tRP - BANK 0 DON'T CARE 50 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A CLOCK SUSPEND Clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, "freezing" the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. ISSI (R) Clock Suspend During WRITE Burst T0 CLK T1 T2 Any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the DQ pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (See following examples.) Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. T3 T4 T5 CKE INTERNAL CLOCK COMMAND NOP WRITE NOP NOP ADDRESS BANK a, COL n DQ DIN n DIN n+1 DIN n+2 DON'T CARE Clock Suspend During READ Burst T0 CLK T1 T2 T3 T4 T5 T6 CKE INTERNAL CLOCK COMMAND READ NOP NOP NOP NOP NOP ADDRESS BANK a, COL n DQ Qn Qn+1 Qn+2 Qn+3 DON'T CARE Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 51 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A CLOCK SUSPEND MODE ISSI T6 T7 T8 T9 (R) T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 tAS tAH BA0, BA1 BANK COLUMN m(2) tAS tAH READ tCK T1 tCL T2 tCH tCKS tCKH T3 T4 T5 NOP tCMS tCMH NOP NOP NOP NOP WRITE NOP COLUMN n(2) BANK tAC tAC DOUT m tLZ tOH DON'T CARE UNDEFINED tHZ DOUT m+1 tDS tDH DOUT e DOUT e+1 DQ CAS latency = 2, burst length = 2 52 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A PRECHARGE The PRECHARGE command (see figure) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. ISSI HIGH (R) PRECHARGE Command CLK CKE CS RAS CAS WE A0-A9, A11 ALL BANKS POWER-DOWN Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if powerdown occurs when there is a row active in either bank, this mode is referred to as active power-down. Entering powerdown deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. The device may not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting tCKS). See figure below. A10 BANK SELECT BA0, BA1 BANK ADDRESS POWER-DOWN CLK tCKS CKE tCKS COMMAND NOP Input buffers gated off NOP ACTIVE tRCD tRAS tRC DON'T CARE All banks idle Enter power-down mode Exit power-down mode less than 64ms Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 53 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A POWER-DOWN MODE CYCLE ISSI Tn+1 Tn+2 (R) T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK tAS tAH BA0, BA1 BANK PRECHARGE tCK T1 tCL T2 tCH tCKS tCKS NOP NOP NOP ACTIVE ROW ROW BANK DQ High-Z Two clock cycles Precharge all active banks All banks idle, enter power-down mode Input buffers gated off while in power-down mode All banks idle Exit power-down mode DON'T CARE CAS latency = 2, 3 54 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0). ISSI (R) Four cases where CONCURRENT AUTO PRECHARGE occurs are defined below. READ with Auto Precharge 1. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered. 2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered. CONCURRENT AUTO PRECHARGE An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. ISSI SDRAMs support CONCURRENT AUTO PRECHARGE. READ With Auto Precharge interrupted by a READ T0 CLK COMMAND NOP READ - AP BANK n T1 T2 T3 T4 T5 T6 T7 NOP READ - AP BANK m NOP NOP NOP NOP BANK n Page Active READ with Burst of 4 Interrupt Burst, Precharge tRP - BANK n Idle tRP - BANK m Precharge Internal States BANK m BANK n, COL a Page Active READ with Burst of 4 BANK m, COL b ADDRESS DQ DOUT a CAS Latency - 3 (BANK n) DOUT a+1 DOUT b DOUT b+1 DON'T CARE CAS Latency - 3 (BANK m) READ With Auto Precharge interrupted by a WRITE T0 CLK COMMAND WRITE - AP BANK n T1 T2 T3 T4 T5 T6 T7 NOP NOP NOP WRITE - AP BANK m NOP NOP NOP BANK n READ with Burst of 4 Page Active Page Active BANK n, COL a BANK m, COL b Interrupt Burst, Precharge tRP - BANK n WRITE with Burst of 4 Idle tRP - BANK m Write-Back Internal States BANK m ADDRESS DQM DQ DOUT a CAS Latency - 3 (BANK n) DIN b DIN b+1 DIN b+2 DIN b+3 DON'T CARE Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 55 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing (CAS latency) later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. ISSI (R) 4. Interrupted by a WRITE (with or without auto precharge): AWRITE to bank m will interrupt a WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m. WRITE With Auto Precharge interrupted by a READ T0 CLK T1 T2 T3 T4 T5 T6 T7 COMMAND NOP WRITE - AP BANK n NOP READ - AP BANK m NOP NOP NOP NOP BANK n Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back tWR - BANK n Precharge tRP - BANK n tRP - BANK m Precharge Internal States BANK m Page Active READ with Burst of 4 ADDRESS BANK n, COL a BANK m, COL b DQ DIN a DIN a+1 CAS Latency - 3 (BANK m) DOUT b DOUT b+1 DON'T CARE WRITE With Auto Precharge interrupted by a WRITE T0 CLK T1 T2 T3 T4 T5 T6 T7 COMMAND NOP WRITE - AP BANK n NOP NOP WRITE - AP BANK m NOP NOP NOP BANK n Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back tWR - BANK n Precharge tRP - BANK n tRP - BANK m Write-Back Internal States BANK m Page Active WRITE with Burst of 4 ADDRESS BANK n, COL a BANK m, COL b DQ DIN a DIN a+1 DIN a+2 DIN b DIN b+1 DIN b+2 DIN b+3 DON'T CARE 56 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A SINGLE READ WITH AUTO PRECHARGE ISSI T5 T6 T7 T8 (R) T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS A0-A9, A11 A10 BA0, BA1 tAH ROW tAS tAH ROW tAS tAH BANK ACTIVE T1 tCK tCL T2 tCH T3 T4 NOP NOP NOP READ NOP NOP ACTIVE NOP tCMS tCMH COLUMN m(2) ENABLE AUTO PRECHARGE ROW ROW BANK tAC tOH DOUT m tHZ tRCD tRAS tRC CAS Latency tRP BANK DQ DON'T CARE UNDEFINED Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 57 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A READ WITH AUTO PRECHARGE ISSI T6 T7 T8 (R) T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 DQ ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL T2 tCH T3 T4 T5 NOP READ tCMS tCMH NOP NOP NOP NOP NOP ACTIVE COLUMN m(2) ENABLE AUTO PRECHARGE ROW ROW BANK tAC tLZ CAS Latency tAC DOUT m tOH tAC DOUT m+1 tOH tAC DOUT m+2 tOH tRP tHZ DOUT m+3 tOH BANK tRCD tRAS tRC DON'T CARE UNDEFINED 58 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A SINGLE READ WITHOUT AUTO PRECHARGE ISSI T6 T7 T8 (R) T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 DQ ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL T2 tCH T3 T4 T5 NOP READ tCMS tCMH NOP NOP PRECHARGE NOP ACTIVE NOP COLUMN m(2) ALL BANKS ROW ROW DISABLE AUTO PRECHARGE BANK tAC tLZ CAS Latency tOH DOUT m tHZ tRCD tRAS tRC SINGLE BANK BANK BANK DON'T CARE tRP UNDEFINED Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 59 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A READ WITHOUT AUTO PRECHARGE ISSI T6 T7 T8 (R) T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 DQ ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL T2 tCH T3 T4 T5 NOP READ tCMS tCMH NOP NOP NOP PRECHARGE NOP ACTIVE COLUMN m(2) ALL BANKS ROW ROW DISABLE AUTO PRECHARGE BANK tAC tLZ CAS Latency tAC DOUT m tOH tAC DOUT m+1 tOH SINGLE BANK BANK tAC DOUT m+2 tOH tRP tHZ DOUT m+3 tOH DON'T CARE UNDEFINED BANK tRCD tRAS tRC 60 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A SINGLE READ WITH AUTO PRECHARGE ISSI T6 T7 T8 (R) T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK ACTIVE T1 tCK tCL T2 tCH T3 T4 T5 NOP NOP NOP READ NOP NOP ACTIVE NOP tCMS tCMH COLUMN m(2) ENABLE AUTO PRECHARGE ROW ROW BANK tAC tOH DOUT m tHZ tRCD tRAS tRC CAS Latency tRP BANK DQ DON'T CARE UNDEFINED Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 61 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A SINGLE WRITE - WITHOUT AUTO PRECHARGE ISSI T5 T6 T7 T8 (R) T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL T2 tCH T3 T4 NOP WRITE tCMS tCMH NOP(4) NOP(4) PRECHARGE NOP ACTIVE NOP COLUMN m(3) ROW ALL BANKS ROW DISABLE AUTO PRECHARGE SINGLE BANK BANK tDS tDH BANK BANK DQ tRCD tRAS tRC DIN m tWR(3) tRP DON'T CARE 62 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A WRITE - WITHOUT AUTO PRECHARGE ISSI T6 T7 T8 (R) T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL T2 tCH T3 T4 T5 NOP WRITE tCMS tCMH NOP NOP NOP PRECHARGE NOP ACTIVE COLUMN m(3) ALL BANKS ROW ROW DISABLE AUTO PRECHARGE BANK tDS tDH tDS tDH DIN m+1 tDS tDH DIN m+2 tDS tDH SINGLE BANK BANK BANK DQ tRCD tRAS tRC DIN m DIN m+3 tWR(2) tRP DON'T CARE Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 63 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A WRITE - WITH AUTO PRECHARGE ISSI T6 T7 T8 T9 (R) T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH tAS tAH A0-A9, A11 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK ACTIVE tCK T1 tCL T2 tCH T3 T4 T5 NOP WRITE tCMS tCMH NOP NOP NOP NOP NOP NOP ACTIVE COLUMN m(2) ENABLE AUTO PRECHARGE ROW ROW BANK tDS tDH tDS tDH DIN m+1 tDS tDH DIN m+2 tDS tDH BANK DQ tRCD tRAS tRC DIN m DIN m+3 tWR tRP DON'T CARE 64 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A ORDERING INFORMATION - VDD = 2.5V Commercial Range: 0C to 70C Frequency 133 MHz 100 MHz Speed (ns) 7 10 Order Part No. IS42LS81600A-7T IS42LS81600A-10T Package 54pin TSOPII 54pin TSOPII ISSI (R) Frequency 143 MHz 100 MHz Speed (ns) 7 10 Order Part No. IS42LS16800A-7B IS42LS16800A-7T Package 54 pin BGA 54 Pin TSOPII IS42LS16800A-10B 54 pin BGA IS42LS16800A-10T 54 Pin TSOPII Frequency 133 MHz 100 MHz Speed (ns) 7 10 Order Part No. IS42LS32400A-7B IS42LS32400A-7T Package 90 pin BGA 86-Pin TSOPII IS42LS32400A-10B 90 pin BGA IS42LS32400A-10T 86-Pin TSOPII ORDERING INFORMATION - VDD = 2.5V Industrial Range: -40C to 85C Frequency 133 MHz 100 MHz Speed (ns) 7 10 Order Part No. IS42LS81600A-7TI Package 54pin TSOPII IS42LS81600A-10TI 54pin TSOPII Frequency 133 MHz 100 MHz Speed (ns) 7 10 Order Part No. IS42LS16800A-7BI IS42LS16800A-7TI Package 54 pin BGA 54 Pin TSOPII IS42LS16800A-10BI 54 pin BGA IS42LS16800A-10TI 54 Pin TSOPII Frequency 133 MHz 100 MHz Speed (ns) 7 10 Order Part No. IS42LS32400A-7BI IS42LS32400A-7TI Package 90 pin BGA 86-Pin TSOPII IS42LS32400A-10BI 90 pin BGA IS42LS32400A-10TI 86-Pin TSOPII Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 65 IS42S81600A, IS42S16800A, IS42S32400A IS42LS81600A, IS42LS16800A, IS42LS32400A ORDERING INFORMATION - VDD = 3.3V Commercial Range: 0C to 70C Frequency 133 MHz 100 MHz Speed (ns) 7 10 Order Part No. IS42S81600A-7T IS42S81600A-10T Package 54pin TSOPII 54pin TSOPII ISSI (R) Frequency 133 MHz 100 MHz Speed (ns) 7 10 Order Part No. IS42S16800A-7B IS42S16800A-7T IS42S16800A-10B IS42S16800A-10T Package 54 pin BGA 54 Pin TSOPII 54 pin BGA 54 Pin TSOPII Frequency 133 MHz 100 MHz Speed (ns) 7 10 Order Part No. IS42S32400A-7B IS42S32400A-7T IS42S32400A-10B IS42S32400A-10T Package 90 pin BGA 86-Pin TSOPII 90 pin BGA 86-Pin TSOPII ORDERING INFORMATION - VDD = 3.3V Industrial Range: -40C to 85C Frequency 133 MHz 100 MHz Speed (ns) 7 10 Order Part No. IS42S81600A-7TI IS42S81600A-10TI Package 54pin TSOPII 54pin TSOPII Frequency 133 MHz 100 MHz Speed (ns) 7 10 Order Part No. IS42S16800A-7BI IS42S16800A-7TI IS42S16800A-10BI IS42S16800A-10TI Package 54 pin BGA 54 Pin TSOPII 54 pin BGA 54 Pin TSOPII Frequency 133 MHz 100 MHz Speed (ns) 7 10 Order Part No. IS42S32400A-7BI IS42S32400A-7TI IS42S32400A-10BI IS42S32400A-10TI Package 90 pin BGA 86-Pin TSOPII 90 pin BGA 86-Pin TSOPII 66 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 06/01/02 |
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