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E2A0046-16-X1 Semiconductor
Semiconductor
MSM7557
This version: Jan. 1998 MSM7557 Previous version: Nov. 1996
Single Chip MSK Modem with Compandor for Cordless Telephone
GENERAL DESCRIPTION
The MSM7557 is a single chip MSK modem with base band voice processor for cordless telephone. The MSM7557 voice transmit block consists of high pass filter, compressor, pre-emphasis, limiter and splatter filter. Voice receive block consists of Band pass filter, De-emphasis and Expander.
FEATURES
* Available to transmit modem signal and also transmit base band voice signal through wireless transmission path (0.3 kHz to 3.4 kHz) * Built-in compandor circuit * Upper limit of voice band (3306 Hz/3400 Hz/3500 Hz) is selectable * Modem bit rate (2400/1200 bps) is selectable * Transmit function and receive function operate separately * Emphasis mode selectable * Built-in bit synchronous detector and frame synchronous detector * Built-in limiter level generator and external limit voltage input * Dynamic range selectable * Built-in crystal oscillator circuit * Wide range power supply voltage (2.7V ~ 5.5V) * Package : 56-pin plastic QFP (QFP56-P-910-0.65-2K) (Product name : MSM7557GS-2K)
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Semiconductor
BLOCK DIAGRAM
CMPI CC1 CC2 CC3N CC3P
TVIO TVI
-
LIM
Compressor
+
HPF1
PreEmphasis
Limiter
Splatter Filter
RCLPF
TAO SEC DYN TVE ME EMP RCK1 RCK2 RD RT FD FPS BIT FDE CSH
SD ST BR VR1 VR2 VR3 BYP VDD GND SG
MOD RCLPF DEMOD SG Mix LPF Mixer DEMBPF
CONT
Flame Det
Shaper
X1 X2 RAIO
OSC
-
+
RAI
RBPF
DeEmphasis Voltage REF
HPF2
Expander
RCLPF
RVO
CE3N
PDN
PDN
CE3P
CE1 CE2
RVE
MSM7557
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PIN CONFIGURATION (TOP VIEW)
50 PDN
49 VDD
48 RVE
55 TVE
44 FPS
54 ME
46 RD
51 NC
NC ST EMP LIM NC VR1 VR2 VR3 NC TVIO CMPI TVI CC1 CC2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
43 NC 42 41 40 39 38 37 36 35 34 33 32 31 30 29
56 SD
47 RT
53 X2
52 X1
45 FD
NC BIT FDE BR BYP RCK2 RCK1 SEC CSH RAI NC RAIO CE3P NC
(VDD)
GND
DYN
CC3N
CC3P
RVO
NC
TAO
CE3N
NC
CE1
Notes: The pin 49 should be used for VDD. The pin 21 should be connected to VDD or opened. NC : No connect pin
CE2
NC
SG
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PIN DESCRIPTION
Name Transmit data input. The data on SD pin are took into MSK modulator and the data are available on the positive edge of ST. Description
ME SD input t MS SD ST
Modulator input data In order to synchronize a receive modem, more than 18bits bit-synchronous signal should be transmitted before data transmission. If S/N ratio of the receive signal is always good, more than 11bits bit-synchronous signal synchronizes the receiver. ST Transmit data timing clock output. When digital "0" is put on ME pin, ST is fixed to digital "1" level. Emphasis path selection. EMP EMP 0 1 path Pre-emphasis circuit is connected to the path Transmit side Pre-emphasis circuit is bypassed to the path De-emphasis circuit is connected to the path Receive side De-emphasis circuit is bypassed to the
Deviation limiter control. Voice signal maximum Rf modulation level is controlled by connecting external reference voltage to this pin. Input impedance of this pin is about 200 kW. When this pin is left open, internal reference voltage is used as the clamp level. LIM Internal clamp level is as follows. DYN 0 1 Internal clamp level 0.50 V 1.26 V Limiter level -9 dBV -1 dBV
This internal clamp level is made by internal reference voltage which is unrelated with VDD. Negative clamp level is made by internal operational amplifier and the voltage is reversed at VSG.
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(Continued)
Name Modulator output level control. Refer to the following figure.
R1 40 kW R2 40 kW R1 R2 R1
Description
From modulator
- +
VR1
VR1 VR2 VR3
To transmit filter - +
VR2
R2 VR3
VTAO = 20 log (R2/R1) - 9 dBV (DYN = "0" ) VTAO = 20 log (R2/R1) - 1 dBV (DYN = "1" ) This level is made from internal voltage reference, so this level doesn't depend on power supply voltage. Transmit side RC active filter input (TVI) and output (TVIO). If over 50 kHz frequency element is in the input signal, folding noise is generated from internal SCF circuit, so second order RC-active filter is needed. (fc = 10 kHz)
CMPI C19 C1 R3 R5 C3 TVI R4 C2 SG - + TVIO
Compressor R5 60 kW C1 and C19 are used for DC cut.
TVIO TVI
VTVI
Example of fc = 10 kHz and 0 dB gain R3 = R4 = R5 = 68 kW C1 = 0.22 mF, C2 = 510 pF, C3 = 110 pF
When digital "1" is applied to TVE pin, transmit voice signal comes out to TAO. CC1 CC2 CC3N CC3P Capacitor connection pins to remove for DC offset of the compressor. A 1 mF capacitor between SG pin and each pin should be connected. Capacitor connection pins for the compressor attack and recovery time. When DYN is digital "0" level, a 0.22 mF capacitor should be connected between CC3N and CC3P. And when DYN is digital "1" level, a 0.47 mF capacitor should be connected between them.
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(Continued)
Name CMPI Compressor circuit input. A 0.47 mF capacitor should be connected between CMPI and TVIO. Dynamic range control input. For an application of which VDD is always higher than 4.5 V (Base station), by setting DYN = "1", modem transmit carrier level, typical input signal level, limiter clamp level and compandor DYN standard input level are up about 8dB to improve S/N ratio. For an application of which VDD is lower than 4.5 V (Hand-set) DYN shall be digital "0". To make easier interface with the RF part, one solution is to put digital "0" on DYN pin for both Base station and Handset. Built-in analog signal ground. The DC voltage is half of VDD. SG GND To make this voltage source impedance lower and to ensure the device performance, it is necessary to put a bypass capacitor of more than 1mF between SG and VDD in close physical proximity to the device. Ground pin, (0V). Transmit analog signal output. According to control data on ME and TVE, TAO is set as follows. ME TAO 0 0 1 TVE 0 1 X Voice signal output MSK modulator output X : Don't care Receive voice signal output. RVO pin state is defined by RVE control. RVO RVE 0 1 CE1 CE2 CE3N CE3P RAIO RAI CSH Output enable RVO Output disable (potential = SG) TAO No signal output (potential = SG) Description
Capacitor connection pins to remove DC offset of the expander. A 1 mF capacitor between SG pin and each pin should be connected. Capacitor connection pins for the expander attack time and recovery time. When DYN is digital "0" level, a 0.22 mF capacitor should be connected between CE3N and CE3P. And when DYN is digital "1" level, a 0.47 mF capacitor should be connected between them. Receive side amplifier input (RAI) and output (RAIO). Second order RC-active filter is needed like TVIO and TVI. Refer to TVIO and TVI pin description. Capacitor connection pin to remove DC offset of the modem shaper circuit. A 1 mF capacitor should be connected between GND pin and CSH.
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(Continued)
Name SEC Device test input. SEC shall be connected to GND. Voice band select. RCK1 RCK2 RCK1 0 X 1 Compandor path selection. BYP BYP 0 1 Transmit side Compressor is connected to the path. Compressor is bypassed to the path. Receive side Expander is connected to the path. Expander is bypassed to the path. RCK2 1 0 1 Upper Limit of Voice Band 3306 Hz 3400 Hz 3500 Hz Function
Modem data signaling rate select pin. BR BR 0 1 Date signaling rate 1200 bps 2400 bps
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(Continued)
Name Frame synchronous signal detector control. When digital "0" is applied to this pin, FD pin is fixed to "0" level. RT and RD always work. FDE When digital "1" is applied to this pin, frame synchronous detector works, and RT and RD pins are fixed to "1" level untill synchronous signal detector detects frame synchronous signal and FD becomes "1" level. Refer to Fig.3 (receive signal timing). Bit synchronous signal detector control. When BIT and FDE pins are digital "1" level and when bit synchronous signal and frame synchronous BIT signal are detected continously, FD becomes digital "1". When BIT pin is digital "0" level and FDE pin is digital "1" level and when 16-bit frame synchronous signal is detected, FD pin becomes digital "1" level. Refer to FPS pin detection. Frame synchronous pattern control. BIT FPS 0 0 1 1 FPS 0 1 0 1 Detect pattern 1001 0011 0011 0110 (=9336H) 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 0 (=C4D6H) 1 0 1 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 0 (=A9336H) 1 0 1 0 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 0 (=AC4D6H) Receiver Handset side Base station Handset side Base station Function
(Note : This pattern is for Japanese Cordless Telephone.) Frame synchronous detector output. FD When receive data correspond to detection pattern, FD pin is held to digital "1" level. When FDE is applied to digital "0" level, FD pin is reset to digital "0" level. And at the full power down state (PDN = "1", RVE = "0" ), FD pin is reset to digital "0" level. Demodulator serial data output. RD The data are synchronized with the re-generated timing clock of RT. When FDE is digital "1" level and also FD is digital "0" level, RD is fixed to digital "1" level. Receive data timing clock output. This signal is re-generated by internal digital PLL. The falling edge of this clock output is coincident RT with the transitions of RD. The rising edge of RT can be used to latch the valid receive data. When FDE pin is applied to digital "1" level and also FD pin output digital "0" level, RT pin is fixed to digital "1" level. Refer to Fig.3. RVE Receive voice signal control. Refer to RVO pin description. Power supply. VDD This device is sensitive to power supply noises as switched capacitor tequniques are utilized. A bypass capacitor of more than 10 mF between VDD and GND pin should be connected to ensure the performance.
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(Continued)
Name Power down control. Power down state is controlled by PDN, ME, RVE, and TVE. Voice control path OFF OFF OFF ON Transmit side modem OFF OFF ON ON Receive side modem OFF ON ON ON X : Don't care Function
PDN Mode1 PDN Mode2 Mode3 Mode4 1 1 0
ME X X 1
RVE 0 1 0
TVE X X 0
others
At the mode 4, all functions are powered on. At the full power down mode(PDN = "1" and RVE = "0"), the demodulator circuit and FD pin are reset. When VDD is turned ON, the demodulator circuit and FD pin should be reset by setting Mode1. Crystal connection. X1 X2 3.6864 MHz crystal shall be connected. When an external master clock is applied, the clock should be supplied to X2 pin via a 200 pF capacitor for AC coupling and X1 should be opened. MSK moudulator output. ME When digital "1" is applied to this pin, MSK modulator is connected to the splatter filter. Refer to TAO pin description. Transmit side voice signal contorol. Refer to TAO pin description.
TVE
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ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Analog Input Voltage *1 Digital Input Voltage *2 Storage Temperature Symbol VDD VIA VID TSTG Condition Ta = 25C Refer to GND -- Rating -0.3 to +7.0 -0.3 to VDD + 0.3 -55 to +150 V C Unit
*1 : LIM, VR2, TVI, RAI, CMPI *2 : SD, EMP, DYN, SEC, RCK1, RCK2, BYP, BR, FDE, BIT, FPS, RVE, PDN, X2, ME, TVE
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature Crystal Oscillating Freq. Data Signaling Rate C4, C5, C11, C12, C15 C6, C13 C7, C8 C9, C10 C14 C19 C20, C21 Symbol VDD Top fX'TAL TS -- -- -- -- -- -- -- -- Condition from DYN = "0" GND level DYN= "1" VDD = 2.7 V to 5.5 V -- BR = 0" BR = "1" -- DYN = "0" DYN = "1" -- RL 40kW -- -- -- Min. 2.7 4.5 -30 3.6860 -- -- -- -- -- -- -- -- -- -- Typ. 3.6 5.0 +25 3.6864 1200 2400 1.0 0.22 0.47 1.0 0.22 10 0.47 20 Max. 5.5 5.5 +70 3.6868 -- -- -- -- -- -- -- -- -- -- pF mF Unit V C MHz bit/sec
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ELECTRICAL CHARACTERISTICS
DC Characteristics
DYN = "0" : VDD = 2.7 V to 5.5 V, Ta = -30C to 70C DYN = "1" : VDD = 4.5 V to 5.5 V, Ta = -30C to 70C Symbol IDD IDDS1 Power Supply Current *1 IDDS2 IDDS3 Input Leakage Current *2 Input Voltege *2 Output Voltege *3 IIL IIH IIL IIH VOL VOH Condition Normal 3.6 V mode 5.5 V (mode 4) Power down mode 1 Power down mode 2 Power down mode 3 VIN = 0 V VIN = VDD -- IOL = -20 mA IOH= 20 mA 3.6 V -- -10 0 0.7VDD 0 0.8VDD 4.6 -- -- -- -- -- 9.0 +10 0.2VDD VDD 0.1VDD VDD mA 5.5 V Min. -- -- -- -- Typ. 9.0 14.0 1.0 3.8 Max. 18 24 20 7.0 mA mA Unit mA
Parameter
V
*1 Refer to PDN pin description *2 SD, EMP, DYN, SEC, RCK1, RCK2, BYP, BR, FDE, BIT, FPS, RVE, PDN, ME, TVE *3 ST, FD, RD, RT
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AC Characteristics
Parameter Transmit Carrier Frequency Transmit Carrier Level Receive Carrier Input Level 1200 Bit Error Rate bps 2400 bps BER Defined at RAIO Symbol fM1 fS1 fM2 fS2 VOX VIR Condition SD = "1" SD= "0" SD = "1" SD= "0" R1 = R2 BR = "0" ME= "1" BR = "1" ME= "1"
DYN = "0" : VDD = 2.7 V to 5.5 V, Ta = -30C to 70C DYN = "1" : VDD = 4.5 V to 5.5 V, Ta = -30C to 70C Min. 1199 1799 1199 2399 -11 -3 -32 8 dB 10 dB 11 dB 13 dB Number of data bits required for the PLL to be locked in within the phase difference of 22.5 or less Number of data bits required for the PLL to be locked in within the phase difference of 90 or less -- -- -- -- Typ. 1200 1800 1200 2400 -9 -1 -- 1 10-3 5 10-5 1 10-3 5 10-5 Max. 1201 1801 1201 2401 -7 +1 -2 -- -- -- -- -- dBV Hz Unit
DYN = "0" DYN = "1"
--
--
18 bit
Number of PLL Lock-in Data Bits *1
VIR
--
--
11
*1 Receive MSK signal is bit synchronous signal (modulated signal of alternating "0", "1" pattern).
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Voice Signal Interfaces
Parameter RVO Maximum Output Signal Level Limiter Clamp Level Transmit Output Distortion Receive Output Distortion Transmit Gain Receive Gain Transmit Idle Noise Receive Idle Noise RCV.AETran. Cross Talk Tran.AERCV. Symbol VOUT VLIM HDT HDR GT GR HIT HIR CTT CTR FT1 Transmit Filter Response FT3 FT25 FT34 FT60 FR1 Receive Filter Response FR3 FR25 FR34 FR60 Condition fIN = 1 kHz BYP = "0" *1 fIN = 1 kHz LIM = open
DYN = "0" : VDD = 2.7 V to 5.5 V, Ta = -30C to 70C DYN = "1" : VDD = 4.5 V to 5.5 V, Ta = -30C to 70C Min. -- -- -10 -2 -- -- -1.5 -1.5 -- -- *2 100 Hz 300 Hz 2.5 kHz 3.4 kHz 6 kHz 100 Hz 300 Hz 2.5 kHz 3.4 kHz 6 kHz -- -- -- -12.5 +6.5 +8.5 -- +1.5 +8.0 -9.5 -12.5 -- Typ. -- -- -9 -1 -40 -40 -0.2 -0.2 -51 -85 -75 -80 -28 -10.5 +8.0 +10.5 -40 +3.0 +9.5 -8.0 -10.5 -40 Max. -6 +2 -8 0 -- -- +1 +1 -- -- -60 -60 -23 -8.5 +9.5 +12.5 -30 +4.5 +11.0 -6.5 -8.5 -30 dB dBV dB dBV Unit DYN = "0" DYN = "1" DYN = "0" DYN = "1"
fIN = 1 kHz, -12 dBV BYP = "0", EMP = "1" fIN = 1 kHz, BYP = EMP = "1" fIN = 1 kHz, BYP = EMP = "1" BYP = "0" EMP = "1" RAIO = -2 dBV TVIO = -2 dBV EMP = "1" BYP = "1" RCK2 = "0" Ref. = 1 kHz EMP = "1" BYP = "1" RCK2 = "0" Ref. = 1 kHz
*1 S/D 20 dB *2 fIN = 1 kHz, BYP = EMP = "1"
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(Continued)
DYN = "0" : VDD = 2.7 V to 5.5 V, Ta = -30C to 70C DYN = "1" : VDD = 4.5 V to 5.5 V, Ta = -30C to 70C Parameter Standard Input Level Maximum Input Level Output Level *3 Attack Time Recovery Time Standard Input Level Maximum Symbol VICS fIN = 1 kHz VICM GC2 GC4 GC5 TAT1 TAT2 TRE1 TRE2 VIES fIN = 1 kHz VIEM GE1 GE2 GE3 TAT3 TAT4 TRE3 TRE4 fIN = 1 kHz *3 fIN = 1 kHz Condition DYN = "0" DYN = "1" DYN = "0" DYN = "1" -20 dB -40 dB -60 dB DYN = "0", C6 = 0.22 mF DYN = "1", C6 = 0.47 mF DYN = "0", C6 = 0.22 mF DYN = "1", C6 = 0.47 mF *4 *5 *6 DYN = "0" DYN = "1" -10 dB -20 dB -30 dB DYN = "0", C13 = 0.22 mF DYN = "1", C13 = 0.47 mF DYN = "0", C13 = 0.22 mF DYN = "1", C13 = 0.47 mF Min. -16.1 -7.1 -- -- -10.6 -21.0 -- -- -- -- -- -12.9 -13.3 -4.7 -- -- -21.5 -42.2 -- -- -- -- -- Typ. -13.7 -5.5 -- -- -9.9 -19.8 -29.5 3.4 3.5 17 16 -10.8 -11.2 -3.1 -- -- -20 -40 -59 3.4 3.5 17 16 Max. -11.3 -3.9 -7 +1.0 -9.2 -18.6 -- -- -- -- -- -8.7 -9.1 -1.5 -6 +2 -18.3 -37.5 -- -- -- -- -- ms dB dBV ms dB dBV Unit
Compressor Expander
Output Level Output Level Attack Time Recovery Time
*3 0 dB is defined as the input level and the output level when the standard input level is input. *4 VDD = 3.6 V, DYN = "0" *5 VDD = 5.0 V, DYN = "0" *6 VDD = 5.0 V, DYN = "1"
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Common Characteristics
Parameter Input Resistance Symbol RIA RIC ROX1 Output Resistance ROX2 ROX3 Output Load Resistance RXL1 RXL2 VSG Output DC Voltage VAO TAO, RVO Condition TVI, RAI, VR2 LIM TAO
DYN = "0" : VDD = 2.7 V to 5.5 V, Ta = -30C to 70C DYN = "1" : VDD = 4.5 V to 5.5 V, Ta = -30C to 70C Min. -- -- -- -- -- *1 TVIO SG 40 60 VDD - 0.1 2 VDD - 0.15 2 Typ. 10 200 1750 600 100 -- -- VDD 2 VDD 2 2 VDD + 0.15 2 Max. -- -- -- -- -- -- -- VDD + 0.1 V kW W Unit MW kW
VR1, VR3, RVO TVIO, RAIO S/D 20 dB
*1 VR1, VR3, TAO, RVO, RAIO
Digital Timing Characteristics
Parameter Transmit Data Set-up Time Transmit Data Hold Time Receive Data Output Delay Sync-signal Output Delay (MEAEST) Symbol tS Refer to Fig. 1 tH tD tMS Refer to Fig. 1 Refer to Fig. 1 Condition
DYN = "0" : VDD = 2.7 V to 5.5 V, Ta = -30C to 70C DYN = "1" : VDD = 4.5 V to 5.5 V, Ta = -30C to 70C Min. 1 1 -300 0 Typ. -- -- -- -- Max. -- ms -- 300 834 ns ms Unit
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TIMING DIAGRAM
ST
50%
SD
50%
tS
tH
Figure 1 Input Data Timing
RT 50%
FD,RD
50%
tD
Figure 2 Output Data Timing
FDE
RT
Internal RD
N-2
N-1
N
D1
D2
D3
FD
RD
D1
D2
D3
N-2, N-1, N : Frame shnchronous signal
Figure 3 Receive Signal Timing
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MSM7557
OPERATION DESCRIPTION
Limiter Circuit
A R12 R11 LIM - + R11 : 1 kW R12 : 200 kW
Reverse
HPF1 or PRE - EMPHASIS
Limiter
Splatter filter
DYN = "0" DYN = "1"
: Clamp level = VSG 0.50 V : Clamp level = VSG 1.26 V
2. In case of using external voltage reference LIM pin shall be supplied over VSG voltage. Notes 1 ) R11 is protection resister from external extra voltage. 2 ) Resistor value of R11 and R12 changes 0.7 to 1.3 times from the typical value by lot variation and temperature variation.
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Frame Detector Frame detection pattern is defined by BIT and FPS.
BIT 0 0 1 1 FPS 0 1 0 1 Sync-pattern 9336H C4D6H A9336H AC4D6H Receiver S.H. M.T. S.H. M.T. Note Frame synchronous Frame synchronous Bit + Frame synchronous Bit + Frame synchronous
M.T. = Master telephone S.H. = Slave handset
Fig 3 shows detection timing First, put digital "0" level to FDE pin more than 1 ms, then FD pin is reset to "0" level. Next, put digital "1" level to FDE pin, then RT and RD output digital "1" level until frame synchronous signal detected. When synchronous pattern is detected, FD pin is held to digital "1" level. At the full power down state (PDN = "1", RVE = "0"), FD pin becomes reset state. In order to detect frame synchronous signal certainly, receive side PLL should be locked in sufficiently. When a modem starts data transmittion, the bit-synchronous signal of more than 18 bits should be transmitted before frame pattern of the upper table.
Frame detection signal Internal RT
D CK
Q Q
FD
FDE
D CK
Q Q RT
Internal RD Full power down signal (Internal signal)
RD
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Application Circuit
MSM7557GS-2K
Transmit data Transmit data timing clock Emphasis path select Limiter circuit clamp voltage input
SD ST EMP LIM VR1 R1 R2 VR2
C19
TVE ME X2 C20
Transmit voice output control MSK modulator control 3.6864 MHz
X1 C21 PDN VDD Power down control Power supply C14 Receive voice output control Receive timing clock
+ -
R5 C3
VR3 CMPI TVIO
RVE RT
Transmit voice input
C1
R3 C2
TVI R4 CC1 C4 CC2 C5 CC3N C6 CC3P Dynamic range select DYN SG C8 C7 GND VDD C9 TAO C10 RVO CE1 C11 CE2 C12 CE3N C13 CE3P
RD FD FPS BIT
Receive data Frame synchronous detector output Synchronous pattern select Bit synchronus detector control
FDE BR
Frame synchronous detector control Modem data signaling rate select
BYP
Compandor path select
Transmit signal output Receive voice output
RCK1 Voice band select RCK2 SEC CSH RAI C16 RAIO C17 R7 Receive signal input + C15 - R6 R8 C18
Note : An arrow mark of ( ) indicates connection to the SG pin.
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MSM7557 Filter Characteristics MSM7557 has wide band filters (0.3 kHz to 3.4 kHz) as follows. Pre-Emphasis ........................................................................................................ Fig. 4 Splatter Filter ........................................................................................................ Fig. 5 RBPF ....................................................................................................................... Fig. 6 De-Emphasis ......................................................................................................... Fig. 7 Transmit Total (HPF1 + Pre-Emphasis + Splatter) ......................................... Fig. 8 Receive Total (RBPF + De-Emphasis) ............................................................... Fig. 9 Transmit and Receive Total ................................................................................ Fig. 10 Fig. 4 to Fig. 10 show the filter characteristics when RCK2 is digital "0". When RCK1 is digital "0" and RCK2 is digital "1", the filter characteristics change 0.972 times on the frequency axis. (pass-band becomes narrow) When RCK1 is digital "1" and RCK2 is digital "1", the filter characteristics change 1.029 times on the frequency axis. (pass-band becomes wide)
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10
0
100
1k
10k FREQ [Hz]
-10
-20
-30 Figure 4 MSM7557 Pre-Emphasis
LEVEL [dB] 100
1k
10k FREQ [Hz]
0 -10 -20 -30 -40 -50 -60 -70 -80 Figure 5 MSM7557 Splatter Filter Fcut(-0.2 dB) = 3.4 kHz
LEVEL [dB]
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0 -10 -20 -30 -40 -50
LEVEL [dB]
100
1k
10k FREQ [Hz]
Fcut(-0.2 dB) = 3.4 kHz
-60 -70 -80
Figure 6 MSM7557 RBPF
20
10
100 0
1k
10k FREQ [Hz]
-10
-20 Figure 7 MSM7557 De-Emphasis
LEVEL [dB]
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10 0 -10 -20 -30 -40 100 1k 10k FREQ [Hz]
-60 -70
Figure 8 MSM7557 Transmit Total (HPF1 + Pre-Emphasis+Splatter)
10 100 0 FREQ [Hz] -10 -20 -30 -40
LEVEL [dB]
LEVEL [dB]
-50
1k
10k
-50 -60 -70
Figure 9 MSM7557 Receive Total (RBPF + De-Emphasis)
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100 0
1k
10k FREQ [Hz]
-10 -20 -30 -40 -50
LEVEL [dB]
-60 -70 -80
Figure 10 MSM7557 Transmit and Receive Total
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PACKAGE DIMENSIONS
(Unit : mm)
QFP56-P-910-0.65-2K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.43 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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