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a
FEATURES Fault and Overvoltage Protection up to 40 V Signal Paths Open Circuit with Power Off Signal Path Resistance of RON with Power On 44 V Supply Maximum Ratings Low On Resistance 80 Typ 1 nA Max Path Current Leakage @ +25 C Low Power Dissipation 0.8 W Typ Latchup-Proof Construction APPLICATIONS ATE Equipment Sensitive Measurement Equipment Hot-Insertion Rack Systems ADC Input Channel Protection
VIN
Single Channel Protector in an SOT-23 Package ADG465
FUNCTIONAL BLOCK DIAGRAM
VDD VD1 VSS VS1
VIN
VOUT VOUT
ADG465
VDD
VDD
OUTPUT CLAMPED @ VDD - 1.5V
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG465 is a single channel protector in an SOT-23 package. The channel protector is placed in series with the signal path, and will protect sensitive components from voltage transience in the signal path whether or not the power supplies are present. Because the channel protection works regardless of the presence of the supplies, the channel protectors are ideal for use in applications where correct power sequencing cannot always be guaranteed to protect analog inputs (e.g., hot-insertion rack systems). This is discussed further, and some example circuits are given, in the Applications section of this data sheet. A channel protector consists of an n-channel MOSFET, a p-channel MOSFET and an n-channel MOSFET, connected in series. The channel protector behaves like a series resistor during normal operation, i.e., (VSS + 2 V) < VIN < (VDD - 1.5 V). When a channel's analog input exceeds the power supplies (including VDD and VSS = 0 V), one of the MOSFETs will switch off, clamping the output to either VSS + 2 V or VDD - 1.5 V. Circuitry and signal source protection is provided in the event of an overvoltage or power loss. The channel protectors can withstand overvoltage inputs from -40 V to +40 V. See the Circuit Information section of this data sheet. The ADG465 can operate from both bipolar and unipolar supplies. The channels are normally on when power is connected, and open circuit when power is disconnected. With power supplies of 15 V, the on-resistance of the ADG465 is 80 typ, with a leakage current of 1 nA max. When power is disconnected, the input leakage current is approximately 5 nA typ. The ADG465 is available in a 6-lead plastic surface mount SOT-23 package, and an 8-lead SOIC package. REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
1. Fault Protection. The ADG465 can withstand continuous voltage inputs from -40 V to +40 V. When a fault occurs due to the power supplies being turned off, or due to an overvoltage being applied to the ADG465, the output is clamped. When power is turned off, current is limited to the nanoampere level. 2. Low Power Dissipation. 3. Low RON 80 typ. 4. Trench Isolation Latchup-Proof Construction. A dielectric trench separates the p- and n-channel MOSFETs thereby preventing latchup.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
ADG465-SPECIFICATIONS
Dual Supply1 (V
Parameter FAULT PROTECTED CHANNEL Fault-Free Analog Signal Range2 RON RON LEAKAGE CURRENTS Channel Output Leakage, IS(ON) (Without Fault Condition) Channel Input Leakage, ID(ON) (With Fault Condition) Channel Input Leakage, ID(OFF) (With Power Off and Fault) Channel Input Leakage, ID(OFF) (With Power Off and Output S/C) POWER REQUIREMENTS IDD ISS VDD/VSS 80 95 4
DD
= +15 V, VSS = -15 V, GND = 0 V, unless otherwise noted)
+25 C B VSS + 1.2 VDD - 0.8 115 5 Units V min V max typ max max Test Conditions/Comments Output Open Circuit -10 V VS +10 V, IS = 1 mA -5 V VS +5 V VS = VD = 10 V nA typ nA max nA typ nA max nA typ nA max A typ A max A typ A max A typ A max V min V max VS = 25 V VD = Open Circuit VDD = 0 V, VSS = 0 V VS = 35 V VD = Open Circuit VDD = 0 V, VSS = 0 V VS = 35 V, VD = 0 V
0.1 1 0.2 2 0.5 2 0.005 0.015 0.05 0.5 0.05 0.5 0 20
1 5 0.4 5 2 10 0.1 0.5
5 5 0 20
NOTES 1 Temperature range is as follows: B Version: -40C to +85C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
-2-
REV. A
ADG465
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25C unless otherwise noted)
PIN CONFIGURATIONS (RT-6)
VD1 1 NC 2 6 VDD
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 V VS, VD, Analog Input Overvoltage with Power ON2 . . . . . . . . . . . . . . . . . . . . . . . . . VSS - 20 V to VDD + 20 V VS, VD, Analog Input Overvoltage with Power OFF2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -35 V to +35 V Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 20 mA Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA (Pulsed at 1 ms, 10% Duty Cycle Max) Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +125C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150C SOT-23 Package JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . 230C/W SOIC Package JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . 205C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at S or D will be clamped by the channel protector, see Circuit Information section of the data sheet.
(RM-8)
NC 1 VDD 2 8 NC
ADG465
TOP VIEW VSS 3 (Not to Scale) 4 VS1 NC = NO CONNECT
5 NC
7 VD1 TOP VIEW VS1 3 (Not to Scale) 6 VSS NC 4 5 NC
ADG465
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Pin Pin RT-6 RM-8 Pin Description 1 7 VD1, this is one terminal of the channel protector. The channel protector is bidirectional so this terminal may be used as an input or an output. NC, this is a no connect pin. VSS, Negative Power Supply (0 V to -20 V). The clamping point for a negative overvoltage is also defined by VSS, see Overvoltage Protection section. VS1, this is one terminal of the channel protector. The channel protector is bidirectional so this terminal may be used as an output or an input. NC, this is a no connect pin. VDD, Positive Power Supply (0 V to 20 V). The clamping point for a positive overvoltage is also defined by VDD, see Overvoltage Protection section.
2 3
1, 4 6
4
3
5 6
5, 8 2
ORDERING GUIDE
Model ADG465BRT ADG465BRM
Temperature Range -40C to +85C -40C to +85C
Package Descriptions 6-Lead Plastic Surface Mount SOT-23 8-Lead SOIC
Brand S1B S1B
Package Options RT-6 RM-8
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG465 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
-3-
ADG465 --Typical Performance Characteristics
140 TEMP = +25 C 130 120 110 100 90 80 70 60 50 -10 -5 0 VD, VS - Volts 5 10 VDD = +10V VSS = -10V VDD = +5V VSS = -5V 15 10 POSITIVE OVERVOLTAGE ON INPUT RLOAD = 100k CLOAD = 100pF -5V TO +15V VDD = +10V STEP INPUT VSS = -10V
RON -
Volts
5 0 -5 CHANNEL PROTECTOR OUTPUT
VDD = +16.5V VSS = -16.5V
Ch1
5.00V
Ch2
5.00V
M50.0ns
Ch1
500mV
Figure 1. On Resistance as a Function of VDD and VD (Input Voltage)
Figure 3. Positive Overvoltage Transience Response
125 115 105 Volts 95
RON -
VDD = +15V VSS = -15V
NEGATIVE OVERVOLTAGE ON INPUT 5 0 +125 C +80 C -5
RLOAD = 100k CLOAD = 100pF VDD = +10V VSS = -10V
CHANNEL PROTECTOR OUTPUT
85 75 65 55 45 -10
-10 -15
+25 C
5V TO -15V STEP INPUT
-5
0 VD, VS - Volts
5
10
Ch1
5.00V
Ch2
5.00V
M50.0ns
Ch1
500mV
Figure 2. On Resistance as a Function of Temperature and VD (Input Voltage)
Figure 4. Negative Overvoltage Transience Response
10V TO +10V INPUT
RLOAD = 100k VDD = +5V VSS = -5V
10
20V
VCLAMP = 4.5V
OUTPUT 20
VCLAMP = 4V Ch1 5.00V Ch2 5.00V M100ns Ch1 500mV
Figure 5. Overvoltage Ramp
-4-
REV. A
ADG465
CIRCUIT INFORMATION
Figure 6 below shows a simplified schematic of a channel protector circuit. The circuit is comprised of four MOS transistors--two NMOS and two PMOS. One of the PMOS devices does not lie directly in the signal path, but is used to connect the source of the second PMOS device to its backgate. This has the effect of lowering the threshold voltage and increasing the input signal range of the channel for normal operation. The source and backgate of the NMOS devices are connected for the same reason. During normal operation the channel protectors have a resistance of 80 typ. The channel protectors are very low power devices; even under fault conditions the supply current is limited to sub-microampere levels. All transistors are dielectrically isolated from each other using a trench isolation method. This makes it impossible to latch up the channel protectors. For an explanation, see Trench Isolation section.
VSS - VTP where VTP is the threshold voltage of the PMOS device (2 V typ). If the input voltage exceeds these threshold voltages, the output of the channel protector (no load) is clamped at these threshold voltages. However, the channel protector output will clamp at a voltage inside these thresholds if the output is loaded. For example, with an output load of 1 k, VDD = 15 V and a positive overvoltage. The output will clamp at VDD - VTN - V = 15 V - 1.5 V - 0.6 V = 12.9 V where V is due to I. R voltage drops across the channels of the MOS devices (see Figure 8). As can be seen from Figure 8, the current during fault condition is determined by the load on the output (i.e., VCLAMP/RL). However, if the supplies are off, the fault current is limited to the nanoampere level. Figures 7, 9 and 10 show the operating conditions of the signal path transistors during various fault conditions. Figure 7 shows how the channel protectors operate when a positive overvoltage is applied to the channel protector.
VDD - VTN* (+13.5V)
VSS
PMOS NMOS NMOS
POSITIVE OVERVOLTAGE (+20V)
NMOS
PMOS
NMOS
SATURATED
PMOS VDD VSS VDD
NONSATURATED VSS (-15V)
NONSATURATED VDD (+15V)
VDD (+15V)
*VTN = NMOS THRESHOLD VOLTAGE (+1.5V)
Figure 6. The Channel Protector Circuit
Overvoltage Protection
Figure 7. Positive Overvoltage on the Channel Protector
When a fault condition occurs on the input of a channel protector, the voltage on the input has exceeded some threshold voltage set by the supply rail voltages. The threshold voltages are related to the supply rails as follows: for a positive overvoltage, the threshold voltage is given by VDD - VT where VTN is the threshold voltage of the NMOS transistor (1.5 V typ). In the case of a negative overvoltage the threshold voltage is given by
VD (+20V) VG (VDD = +15V) VS
The first NMOS transistor goes into a saturated mode of operation as the voltage on its Drain exceeds the Gate voltage (VDD) - the threshold voltage (VTN). This situation is shown in Figure 8. The potential at the source of the NMOS device is equal to VDD -VTN. The other MOS devices are in a nonsaturated mode of operation.
V (+13.5V) PMOS NMOS RL VCLAMP
OVERVOLTAGE OPERATION (SATURATED)
N+
EFFECTIVE SPACE CHARGE REGION P-
N+ N-CHANNEL (VG - VT = 13.5V)
N+
NONSATURATED OPERATION IOUT
VT = 1.5V
Figure 8. Positive Overvoltage Operation on the Channel Protector
REV. A
-5-
ADG465
When a negative overvoltage is applied to the channel protector circuit, the PMOS transistor enters a saturated mode of operation as the drain voltage exceeds VSS - VTP. See Figure 9 below. As in the case of the positive overvoltage, the other MOS devices are nonsaturated.
NEGATIVE OVERVOLTAGE (-20V) NEGATIVE OVERVOLTAGE (-20V) NMOS PMOS VSS - VTP* (-13V) NMOS
TRENCH ISOLATION
The MOS devices that make up the channel protector are isolated from each other by an oxide layer (trench) (see Figure 11). When the NMOS and PMOS devices are not electrically isolated from each other, there exists the possibility of "latchup" caused by parasitic junctions between CMOS transistors. Latchup is caused when P-N junctions that are normally reverse biased, become forward biased, causing large currents to flow. This can be destructive. CMOS devices are normally isolated from each other by Junction Isolation. In Junction Isolation, the N and P wells of the CMOS transistors form a diode that is reverse biased under normal operation. However, during overvoltage conditions, this diode becomes forward biased. A Silicon-Controlled Rectifier (SCR) type circuit is formed by the two transistors, causing a significant amplification of the current that, in turn, leads to latchup. With Trench Isolation, this diode is removed; the result is a latchup-proof circuit.
VG VS VD VS VG VD
NONSATURATED VDD (+15V)
SATURATED VSS (-15V)
NONSATURATED VDD (+15V)
*VTP = PMOS THRESHOLD VOLTAGE (+2V)
Figure 9. Negative Overvoltage on the Channel Protector
The channel protector is also functional when the supply rails are down (e.g., power failure) or momentarily unconnected (e.g., rack system). This is where the channel protector has an advantage over more conventional protection methods such as diode clamping (see Applications Information). When VDD and VSS equal 0 V, all transistors are off and the current is limited to microampere levels (see Figure 10).
(0V)
T R E N C H
P+
P-CHANNEL
P+
N-
T R E N C H
N+
N-CHANNEL
N+
P-
T R E N C H
BURIED OXIDE LAYER
POSITIVE OR NEGATIVE OVERVOLTAGE
NMOS
PMOS
NMOS
SUBSTRATE (BACKGATE)
OFF VDD (0V)
OFF VSS (0V)
OFF VDD (0V)
Figure 11. Trench Isolation
Figure 10. Channel Protector Supplies Equal to Zero Volts
-6-
REV. A
ADG465
APPLICATIONS INFORMATION Overvoltage and Power Supply Sequencing Protection
The ADG465 is ideal for use in applications where input overvoltage protection is required and correct power supply sequencing cannot always be guaranteed. The overvoltage protection ensures that the output voltage of the channel protector will not exceed the threshold voltages set by the supplies (see Circuit Information section) when there is an overvoltage on the input. When the input voltage does not exceed these threshold voltages, the channel protector behaves like a series resistor (80 typ). The resistance of the channel protector does vary slightly with operating conditions (see Typical Performance Graphs). The power sequencing protection is afforded by the fact that when the supplies to the channel protector are not connected, the channel protector becomes a high resistance device. Under this condition all transistors in the channel protector are off and the only currents that flow are leakage currents, which are at the A level.
EDGE CONNECTOR VDD +5V VSS -5V
channel protectors. In this way, the outputs of the channel protectors are clamped well below VDD and VSS until the capacitors are charged. The diodes ensure that the supplies on the channel protector never exceed the supply rails of the board when it is being disconnected. Again, this ensures that signals on the inputs of the CMOS devices never exceed the supplies. High Voltage Surge Suppression The ADG465 are not intended for use in high voltage applications such as surge suppression. The ADG465 has breakdown voltages of VSS - 20 V and VDD + 20 V on the inputs when the power supplies are connected. When the power supplies are disconnected, the breakdown voltages on the input of the channel protector are 35 V. In applications where inputs are likely to be subject to overvoltages exceeding the breakdown voltages quoted for the channel protectors, transient voltage suppressors (TVSs) should be used. These devices are commonly used to protect vulnerable circuits from electric overstress such as that caused by electrostatic discharge, inductive load switching and induced lightning. However, TVSs can have a substantial standby (leakage) current (300 A typ) at the reverse standoff voltage. The reverse standoff voltage of a TVS is the normal peak operating voltage of the circuit. In addition, TVSs offer no protection against latchup of sensitive CMOS devices when the power supplies are off. To provide the best leakage current specification and circuit protection, the best solution is to use a channel protector in conjunction with a TVS. Figure 13 shows an input protection scheme that uses both a TVS and channel protector. The TVS is selected with a reverse standoff voltage much greater than the operating voltage of the circuit (TVSs with higher breakdown voltages tend to have better standby leakage current specifications), but inside the breakdown voltage of the channel protector. This circuit protects the circuitry whether or not the power supplies are present.
VDD = +5V VSS = -5V
ANALOG IN -2.5V TO +2.5V
ADC
ADG465
LOGIC LOGIC GND CONTROL LOGIC
Figure 12. Overvoltage and Power Supply Sequencing Protection
Figure 12 shows a typical application requiring overvoltage and power supply sequencing protection. The application shows a Hot-Insertion rack system. This involves plugging a circuit board or module into a live rack via an edge connector. In this type of application it is not possible to guarantee correct power supply sequencing. Correct power supply sequencing means that the power supplies should be connected prior to any external signals. Incorrect power sequencing can cause a CMOS device to "latch up," see Trench Isolation section. This is true of most CMOS devices, regardless of the functionality. RC networks are used on the supplies of the channel protector (Figure 12) to ensure that the rest of the circuitry is powered up before the
ADG465 ADC
TVSs BREAKDOWN VOLTAGE = 20V
Figure 13. High Voltage Protection
REV. A
-7-
ADG465
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
6-Lead Plastic Surface Mount SOT-23 Package (RT-6)
0.122 (3.10) 0.106 (2.70)
0.071 (1.80) 0.059 (1.50) PIN 1
6 1
5 2
4 3
0.118 (3.00) 0.098 (2.50)
0.037 (0.95) BSC 0.075 (1.90) BSC 0.051 (1.30) 0.035 (0.90) 0.006 (0.15) 0.000 (0.00) 0.057 (1.45) 0.035 (0.90) 0.020 (0.50) SEATING 0.010 (0.25) PLANE 10 0.009 (0.23) 0 0.003 (0.08) 0.022 (0.55) 0.014 (0.35)
8-Lead SOIC (RM-8)
0.122 (3.10) 0.114 (2.90)
8
5
0.122 (3.10) 0.114 (2.90)
1 4
0.199 (5.05) 0.187 (4.75)
PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.006 (0.15) 0.002 (0.05) SEATING PLANE 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.94) 0.011 (0.28) 0.003 (0.08) 33 27 0.028 (0.71) 0.016 (0.41) 0.120 (3.05) 0.112 (2.84)
-8-
REV. A
PRINTED IN U.S.A.
C2217a-0-9/98

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