 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| a Preliminary Technical Data FEATURES Voltage-Controlled Amplifier/Attenuator Operating Frequency 1 MHz to 3 GHz Optimized for Controlling Output Power High Linearity: OIP3 31 dBm @ 900 MHz Output Noise Floor -150 dBm/Hz @ 900 MHz Fully-Balanced Differential Signal Path Differential Input at 50 Wide Gain-Control Range: -34 dB to +22 dB @ 900 MHz Linear-in-dB Gain Control Function, 20 mV/dB Single Supply 4.75 - 6 V GAIN ENBL 1 MHz - 3 GHz VGA with 60dB Gain Control Range ADL5330 VPS2 VPS2 VPS2 VPS2 VPS2 VPS1 GAIN CONTROL COM1 COM2 INHI RF 50 RF input,I/P INLO Input gm Stage Continuously Variable Attenuator O/P OPHI (TZ) Stage OPLO BALUN RF to PA COM1 APPLICATIONS Output Power Control for Wireless Infrastructure BIAS & VREF COM2 VPS1 VREF VPS2 IPBS OPBS COM2 COM2 COM2 Figure 1. Functional Block Diagram PRODUCT DESCRIPTION The ADL5330 is a high-performance voltage-controlled variablegain amplifier/attenuator, for use up to 3 GHz. The signal path is fully differential; the balanced structure minimizes distortion, and reduces the risk of spurious feed-forward at low gains and high frequencies due to substrate coupling. While operation between a balanced source and load is recommended, a single-sided input is internally converted to differential from. The input impedance is 50- from INHI to INLO. The outputs will usually be coupled into a 50- grounded load via a 1:1 balun. However, the output pins, OPHI and OPLO, may also be used separately, with some noise degradation. A single supply of 4.75 to 6 V is required. With a 2140 MHz W-CDMA 3GPP forward path signal, the ADL5330 is capable of producing greater than -3 dBm output power while maintaining ACPR greater than 55 dB, and an output noise floor less than -144 dBm/Hz. Three cascaded sections are used. The 50- input system converts the applied voltage to a pair of differential currents with high linearity and good common rejection if driven by a single-sided source. The signal currents are then applied to a proprietary voltage-controlled attenuator, which provides precise definition of the overall gain, under the control of the Linear-in-dB interface. Pin GAIN accepts a voltage from 0 V at minimum gain to 1.4 V at full gain. The scaling factor is 20 mV/dB. Optional external control of the input-stage and/or output-stage biasing is provided using pins IPBS and OPBS respectively. The output of the high-accuracy wideband attenuator is applied to a differential trans-impedance output stage. Higher output power is attainable at the lower operating frequencies by raising the supply voltage to 6 V. When powered-down by a logic LO input on the ENBL pin, the current consumption is < TBD A. The ADL5330 is available in a 24-lead (4 x 4mm) CSP package and is specified for operation from ambient temperatures of -40C to +85C. Multiple Patents Pending Rev. PrK Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 World Wide Web Site: http://www.analog.com (c)2004 Analog Devices, Inc. All Rights Reserved Preliminary Technical Data ADL5330 SPECIFICATIONS ADL5330 Table 1. VS = 5 V; TA = 25C; 800 MHz < f < 2.2GHz.1:1 balun at input and output for single-ended 50 match Parameter General Usable Frequency Range Nominal Input Impedance Nominal Output Impedance 100 MHz Gain Control Span Max Gain Min Gain Gain Control Slope Input Compression Point Output Compression Point - P1dB Third-Order Intercept - OIP3 900 MHz Gain Control Span Max Gain Min Gain Gain Control Slope Input Compression Point Output Compression Point - P1dB Third-Order Intercept - OIP3 Output Noise Floor 1900 MHz Gain Control Span Max Gain Min Gain Gain Control Slope Input Compression Point Output Compression Point - P1dB Third-Order Intercept - OIP3 Output Noise Floor 2200 MHz Gain Control Span Max Gain Min Gain Gain Control Slope Input Compression Point Output Compression Point - P1dB Third-Order Intercept - OIP3 GAIN CONTROL INPUT Gain Control Voltage Range Incremental Input Resistance Full-Scale Response Time POWER SUPPLIES Voltage Current, Nominal Active Current, Disabled Conditions Min 0.001 Typ Max 3 Unit GHz dB dB dB mV/dB via 1:1 Single-Sided to Differential Balun via 1:1 Differential to Single-Sided Balun +/-3 dB Gain Law Conformance VGAIN = 1.4 V VGAIN = 0.1 V VGAIN = 1.3 V VGAIN = 1.3 V VGAIN = 1.3 V +/-3 dB Gain Law Conformance VGAIN = 1.4 V VGAIN = 0.1 V VGAIN = 1.3 V VGAIN = 1.3 V VGAIN = 1.3 V 20 MHz Carrier Offset, VGAIN = 1.3 V, Pout = -2 dBm +/-3 dB Gain Law Conformance VGAIN = 1.4 V VGAIN = 0.5 V VGAIN = 1.3 V VGAIN = 1.3 V VGAIN = 1.3 V 20 MHz Carrier Offset, VGAIN = 1.3 V, Pout = -7 dBm +/-3 dB Gain Law Conformance VGAIN = 1.4 V VGAIN = 0.5 V VGAIN = 1.3 V VGAIN = 1.3 V VGAIN = 1.3 V Pin GAIN Pin GAIN to COM1 VGN 0 - 1.6V, to within 0.25 dB of final gain Pins VPS1, VPS2, COM1, COM2, ENBL VGN = 0 V VGN = 1.4 V ENBL = LO 0 TBD 50 50 58 +23 -35 21 +2 +22 +36 52 22 -34 20 +3 +22 +31 -144 dBm dBm dBm dB dB dB mV/dB dBm dBm dBm dBm/Hz 47 19 -27 18 +1 +17 +24 -148 dB dB dB mV/dB dBm dBm dBm dBm/Hz 48 17 -31 17 +1 +14 +20 1.4 500 4.75 5 dB dB dB mV/dB dBm dBm dBm V M ns V mA mA A 6 TBD 240 TBD TBD REV. PrK | Page 2 of 5 Preliminary Technical Data Table 2. Pin Function Description Pin 1,6 2,5 3, 4 7 8 Name VPS1 COM1 INHI,INLO VREF IPBS ADL5330 9 OPBS 10,11,12,14, 17 13,18,19,20, 21,22 15 16 23 24 COM2 VPS2 OPLO OPHI ENBL GAIN Description Positive Supply for input stage. Nominally equal to 5 V Common for input stage Differential inputs Voltage reference output of 1.5 volts Input bias, normally no connection. This function is subject to change. PCB designs should include the possibility to connect a capacitor between Pin 8 and Pin 9. Output bias, normally no connection. This function is subject to change. PCB designs should include the possibility to connect a capacitor between Pin 8 and Pin 9. Common for output stage Positive Supply for output stage. Nominally equal to 5 V Low side of differential output, bias to VP with RF chokes High side of differential output, bias to VP with RF chokes Device enable, apply logic high for normal operation. Enable Threshold = 1.6 V Gain-control voltage input. Nominal Range 0 to 1.4 V. VPOS VPOS C2 0.1 uF R2 0 R13 10k C1 100 pF VPOS C14 0.1 uF R12 0 C13 100 pF L1 120 nH ENBL VPS2 VPS2 VPS2 GND VP R1 0 J1 Enable J2 Gain SW1 R3 0 VPOS 50 ohm microstrip J3 Input C8 0.1 uF R5 0 C7 100 pF GAIN VPS1 VPS2 VPS2 COM2 OPHI L2 120 nH C11 100 pF T2 50 ohm microstrip T1 C5 100 pF COM1 INHI ADL5330 INLO OPLO COM2 COM2 COM2 OPBS IPBS J7 Output 25 ohm microstrip (both sides of caps) VPOS C3 0.1 uF J4 VREF J5 IPBS J6 OPBS C6 100 pF R4 0 C4 100 pF COM1 VPS1 VREF C12 100 pF 25 ohm microstrip C10 100 pF VPOS R6 0 C9 0.1 uF VPS2 COM2 R15 R8 R14 open open 0 R7 0 R10 1nF R9 0 R11 1nF Figure 2. ADL5330 Evaluation Board Schematic REV. PrK | Page 3 of 5 Preliminary Technical Data Typical Performance Characteristics . 40 30 20 10 0 -10 -20 -30 -40 0 0.2 0.4 0.6 0.8 1 Vgain - Volts 1.2 1.4 1.6 Gain 100 MHz Gain 900 MHz Gain 1900 MHz 2200 MHz Error 100 MHz Gain Error 900 MHz Error 1900 Error 2200 MHz ADL5330 . 20.00 15.00 10.00 Error - dB 5.00 0.00 -5.00 -10.00 -15.00 -20.00 50 40 30 20 Gain - dB OIP3 10 0 100 MHz 900 MHz 1900 MHz 2200 MHz -10 -20 -30 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Vgain - V Figure 3. Gain and Gain Law Conformance vs. Vgain 5 Figure 5. OIP3 vs. Gain 30 4 20 3 2 Input Referred P1dB - dB 10 Output P1dB - dBm 1 0 -1 100 MHz 900 MHz 1900 MHz 2200 MHz 0 -10 -2 100Mhz 900Mhz 1900Mhz 2200Mhz -20 -3 -4 -30 -5 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Vgain - V -40 0 0.2 0.4 0.6 0.8 Vgain - V 1 1.2 1.4 1.6 Figure 4. Input Referred Compression Point vs. Gain 10.00 -90.00 Figure 7. Output Referred Compression Point vs. Gain 0.00 -100.00 0.00 Pout vs. Vin Noise - 20 MHz offset -100.00 Pout vs. Vin -10.00 . N o is e - 2 0 M H z C a rrie r O ffs e t - d B m /H z -110.00 . N o is e - 2 0 M H z C a r r ie r O ffs e t - d B m /H z -10.00 O u tp u t P o w e r - d B m -110.00 Noise - 20 MHz offset -20.00 O u tp u t P o w e r - d B m -120.00 -20.00 -120.00 -30.00 -130.00 -30.00 -130.00 -40.00 -140.00 -40.00 -140.00 -50.00 -150.00 -50.00 -60.00 0.00 -160.00 1.60 -150.00 0.20 0.40 0.60 0.80 VGAIN 1.00 1.20 1.40 -60.00 0.00 0.20 0.40 0.60 0.80 VGAIN 1.00 1.20 1.40 -160.00 1.60 Figure 8. Pout and Noise Floor vs. Gain, 900 MHz. Pin = 21 dBm Figure 8. Pout and Noise Floor vs. Gain 1.9 GHz. Pin = -22 dBm REV. PrK | Page 4 of 5 Preliminary Technical Data OUTLINE DIMENSIONS ADL5330 REV. PrK | Page 5 of 5 PR05134-0-12/04(PrK) |
Price & Availability of ADL5330
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |