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BU9817FV
Multimedia ICs
4-channel temperature sensor IC for PCs with I2C BUS interface
BU9817FV
The BU9817FV is a 4-channel, 8-bit, A / D converter / overvoltage detector that is perfect for temperature sensors with built-in I2C BUS interfaces. The host can access the BU9817FV anytime for the voltage data.
!Applications Notebook computers, desktop computers, household electric appliances
!Features 1) By attaching a thermistor, a maximum four-channel temperature sensor is possible. 2) Can set comparison voltages independently. 3) Built-in I2C BUS interface. 4) Detection level and operating mode settings are programmable.
5) Extremely low operating current perfect for portable equipment. 6) Operating voltage of VDD = 3V to 5.5V.
!Absolute maximum ratings (Ta = 25C)
Parameter Power supply voltage Power dissipation Operating temperature Storage temperature Voltage applied to pins Symbol VDD Pd Topr Tstg VIN Limits 7.0 350 - 15 ~ + 75 - 55 ~ +125 GND - 0.5 ~ VDD + 0.5 Unit V mW C C V
* Reduced by 3.5mW for each increase in Ta of 1C over 25C.
!Recommended operating conditions (Ta = 25C)
Parameter Operating power supply voltage Symbol VDD Min. 3.0 Typ. -- Max. 5.5 Unit V
Note) I2C BUS is a registered trademark philips.
BU9817FV
Multimedia ICs
!Block diagram
SDA
1 I2C BUS Interface
14
VDD
Vdl Register SCL 2
Pointer Register
Configuration Register 13 STOPB
Vul Register
Reset & Shutdown
OD1
3
Reset Voltage Hysteresis Comparator
Reset Shutdown ADV Register
12
AD1
OD2
4
Reset Voltage Hysteresis Comparator
11 ADV Register
AD2
Sel
8bit A/D
Sel
OD3
5
Reset Voltage Hysteresis Comparator
10 ADV Register
AD3
OD4
6
Reset Voltage Hysteresis Comparator
9
AD4
ADV Register
GND
7
8
CLK
BU9817FV
Multimedia ICs
!Pin descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin name SDA SCL OD1 OD2 OD3 OD4 GND CLK AD4 AD3 AD2 AD1 STOPB VDD I2C BUS Serial Data Line Function
I2C BUS Serial Clock Input Open Drain Output 1 Open Drain Output 2 Open Drain Output 3 Open Drain Output 4 Ground Clock for Logic Input Analog-to-Digtal Converter Input 4 Analog-to-Digtal Converter Input 3 Analog-to-Digtal Converter Input 2 Analog-to-Digtal Converter Input 1 Reset & Power save mode set Supply Voltage 3.0V to 5.5V
BU9817FV
Multimedia ICs
!Input / output equivalent circuits
Pin. No Pin name Input / output circuits Function
1
SDA
I2C BUS serial data input / output. When only input address accords slave address (BU9817FV's), register data is inputted or outputted.
2
SCL
I2C BUS serial clock input.
3 4 5 6
OD1 OD2 OD3 OD4
Open-drain output corresponds to AD1 to AD4 input. Connect this pin a pull-up resister. The pull-up resister should be above VDD / 4mA ().
7
GND
Ground terminal.
8
CLK
Clock input for ADC block. Input clock is 32.768kHz. AD converter and voltage hysteresis comparator use this clock to operate.
BU9817FV
Multimedia ICs
!Input / output equivalent circuits
Pin. No Pin name Input / output circuits Function
9 10 11 12
AD1 AD2 AD3 AD4
AD input. Each channel is converted in order. (AD1, AD2, AD3, AD4, AD1,AD2...)
13
STOPB
Reset and power save mode setting. High: Operation mode Operation follows the setting of configuration register. Low : Reset & Power save mode Reset the all internal circuit and stop the ADC operation. Go into power save mode. Be sure to set STOPB pin low for initial reset of the internal circuit, when the BU9816FV is power up.
14
VDD
Power supply. Supply voltage 3.0V to 5.5V.
BU9817FV
Multimedia ICs
!Electrical characteristics (unless otherwise noted, VDD = 5.0V, Ta = 25C)
Parameter Circuit current (normal) Symbol ICC Min. 0.2 Typ. 0.75 Max. 2.0 Unit mA Conditions SDA, SCL = "H" CLK = 32.768kHz SDA, SCL = "H" CLK = 32.768kHz Mode setting or STOPB = Low -- -- -- -- -- loL = 4.0mA loL = 6.0mA CL = 400pF loL = 6.0mA --
Circuit current (shutdown / reset / STOPB) Input high level voltage Input low level voltage Input high level current Input low level current Input capacity Open drain output low level voltage SDA output low level voltage SDA output fall time STOPB minimum pulse width STOPB minimum pulse width VDD
ICC.sd
-- VDD x 0.7 - 0.5 -- - 1.0 -- 0.0 0.0 -- 10
1.0
2.0
A V V A A pF V V ns s
ViH ViL IiH IiL Ci VoLod VoLsda tfsda pwstopb
VDD 0.0 0.0 0.0 -- 0.2 0.2 -- --
VDD + 0.5 VDD x 0.3 1.0 -- 10 0.6 0.6 250 --
GND
0.3VDD Minimum pulse width
A / D AD resolution Non-linearity error Differential non-linearity error 1-channel conversion time Input range RES Nle Ndle Tc Ai -- -2 -1 -- GND 8 -- -- 305 -- -- 2 1 -- VDD bits LSB LSB s V 2 points connected fCLK = 32.768kHz -- -- --
BU9817FV
Multimedia ICs
!Measurement circuit
820
820
820 I2C BUS Controller
A
2
13
820
3
12
1.2k
4
11
1.2k
5
10
1.2k
6 1.2k
9
32.768kHz
7
8
A
Fig.1
N
N
N
N
A
A
A
1
V V V V V V
14
BU9817FV
Multimedia ICs
!Circuit operation Explanation of operating mode
Operating mode Normal mode Interval High mode Interval Low mode Shutdown mode Reset mode Configuration register settings 000000b 001100b 001000b 000001b 001b ADC operation conversion interval 1.221ms 1 second intervals 4 second intervals Stopped Stopped Open drain operation timing 10th clock after A / D conversion 10th clock after A / D conversion 10th clock after A / D conversion Hold status Reset fixed at high Register status Normal operation Normal operation Normal operation Hold data Data reset Current consumption (typ.) 0.75mA Note: average less than 3A Note: average less than 2A Less than 1A Less than 1A
The asterisk can be either 0 or 1. Conversion time is for fCLK = 32.768kHz. These mode setting bits (bit 0 and bits 3 to 5) are common for each channel, the last setting of bits (bit0 and bits3 to 5) is effective for all channels. Furthermore, bits 1 and 2 are independent and can be set for each channel. Note: These parameters are reference values derived through calculations and are not guaranteed characteristic values.
Explanation of ADC / open drain operation
(Normal mode) Tad = 1.221ms, 40 clock 10 clock ADC operation 4ch OD1 OD2 OD3 OD4 (Interval mode) Tin = 1s, 4s Tc = 1.831ms, 60 clock 10 clock 10 clock ADC operation OD1 OD2 OD3 OD4 1ch 2ch 3ch 4ch 1ch 10 clock 1ch 2ch 3ch 1ch 2ch 3ch 4ch 1ch 2ch 3ch 4ch 1ch
BU9817FV
Multimedia ICs
!Circuit operation Explanation of I2C BUS interface
* Slave address 1
MSB
0
0
1
1
1
1
R/W
LSB
* Conforms to I2C BUS standards Parameter SCL clock frequency Start condition hold time Start condition setup time Data setup time Data hold time Stop condition setup time Symbol f SCL t HD: STA t SU: STA t SU: DAT t HD: DAT t SU: STO Min. 0 0.6 0.6 100 0 0.6 Max. 400 -- -- -- 0.9 -- Unit kHz s s ns s s
(Start conditions)
SCL
SDA t SU: STA (Data conditions) t HD: STA
SCL
SDA t SU: DAT (Stop conditions) t HD: DAT
SCL
SDA t SU: STO
BU9817FV
Multimedia ICs
!Circuit operation OD output voltage response diagram
(Example: open-drain output is set active low)
Vul
AD pin voltage waveform
Vdl
OD Output (Comparator Mode)
OD Output (Interrupt Mode)
Read
Read
Read Time
* Note: Resetting OD output under interrupt mode occurs at only shutdown mode or reset mode or STOPB or when data read generated from host. Except for these cases, OD output is kept setting.
BU9817FV
Multimedia ICs
!Circuit operation Register structure
1ch Configuration Register 1ch Vdl Register 1ch Vul Register 1ch ADV Register
2ch Configuration Register 2ch Vdl Register 2ch Vul Register 2ch ADV Register SDA SCL I C BUS Interface
2
Pointer Register (Register select)
3ch Configuration Register 3ch Vdl Register 3ch Vul Register 3ch ADV Register
4ch Configuration Register 4ch Vdl Register 4ch Vul Register 4ch ADV Register
I2C Bus data structure (1) Write Mode
S Address -- W A Pointer reg. Byte A Write Data Byte A P
(2) Read Mode 1) Pointer register set
S Address -- W A Pointer reg. Byte A -- AP
Sr
Address
R
A
Read Data Byte
2) Preset pointer register
S Address R A Read Data Byte -- AP
S: Start condition P: Stop condition Sr: Restart condition A: acknowledge -- A: acknowledge bar
BU9817FV
Multimedia ICs
Mode settings table 1 / 2 (1) Pointer register (selects which registers will be read from or written to)
D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0
Channel Select
Register Select
D4 to D7: These bits are used for test mode and must be kept zero for normal operation. Channel Select D3 0 0 1 1 D2 0 1 0 1 Channel Channel 1 Channel 2 Channel 3 Channel 4
Register Select D1 0 0 1 1 D0 0 1 0 1 Register ADV Register (Read only) (Power on Reset default) Configuration Register (Read / Write) Vdl Register (Read / Write) Vul Register (Read / Write)
(2) ADV Register (Read only)
Channel 1 ch 2 ch 3 ch 4 ch D7 MSB MSB MSB MSB D6 bit6 bit6 bit6 bit6 D5 bit5 bit5 bit5 bit5 D4 bit4 bit4 bit4 bit4 D3 bit3 bit3 bit3 bit3 D2 bit2 bit2 bit2 bit2 D1 bit1 bit1 bit1 bit1 D0 LSB LSB LSB LSB
D0 to D7: Voltage data The defaults for the power-on-reset and reset modes are 1 for all bits.
(3) Configuration Register (Read / Write)
Channel 1 ch 2 ch 3 ch 4 ch D7 0 0 0 0 D6 0 0 0 0 Interval Mode Interval Speed D5 D4 D3 D2 Opendrain Polarity Opendrain Polarity Opendrain Polarity Opendrain Polarity D1 Comp. / Int. Comp. / Int. Shutdown Comp. / Int. Comp. / Int. D0
Reset
The defaults for the power-on-reset and reset modes are 0 for all bits.
BU9817FV
Multimedia ICs
Mode settings table 2 / 2 D0 : Shutdown "0" - Operation mode. "1" - The BU9817FV stops A / D operation and goes into low power shutdown mode. D0 bit of each channel is common bit. D1 : Comparator / Interrupt mode "0" - Comparator mode. "1" - Interrupt mode. D2 : Open Drain Polarity "0" - active low. "1" - active high. D3 : Reset "0" - Operation mode. "1" - Reset any bits except D3 bit of the configuration register, any registers, the A / D converter, and the voltage hysteresis comparator. D3 bit of each channel is common bit. D4 : Interval Speed Set the conversion cycle time of the 8bit A / D and the voltage hysteresis comparator when D5 bit (Interval Mode) is "1". "0" - conversion cycle time is 4s. "1" - conversion cycle time is 1s. D4 bit of each channel is common bit. D5 : Interval Mode "0" - normal mode. "1" - Interval mode. D5 bit of each channel is common bit.
(4) Vul and Vdl Register (Read / Write)
Channel 1 ch 2 ch 3 ch 4 ch D7 MSB MSB MSB MSB D6 bit6 bit6 bit6 bit6 D5 bit5 bit5 bit5 bit5 D4 bit4 bit4 bit4 bit4 D3 bit3 bit3 bit3 bit3 D2 bit2 bit2 bit2 bit2 D1 bit1 bit1 bit1 bit1 D0 LSB LSB LSB LSB
D0 to D7: Voltage limit data of Vul and Vdl. Default after power on reset and reset mode is Vul = 80h, Vdl = 66h.
BU9817FV
Multimedia ICs
!Application example
VDD
SDA
1
14
From system controller
SCL
2
13
STOPB Input (From Reset IC) Power on Reset
VDD
RS OD1 Output 3 12 AD1 Input VDD RTH Thermal Zone
RS OD2 Output 4 11 AD2 Input RTH Thermal Zone
OD3 Output
5
10
AD3 Input RTH: NTC Thermistor
OD4 Output
6
9
AD4 Input
7
8
CLK Input (fCLK = 32.768kHz)
Fig.2
BU9817FV
Multimedia ICs
!Explanation for external components (1) AD input pin (example when used as a temperature sensor) To the AD input pin, input a voltage with divided resistance from a resistor and NTC thermistor. For the sensor to measure the temperature, the NTC thermistor is used. The thermistor is a p-type semiconductor and as the temperature increases, the resistance value becomes lower. In other words, the resistance temperature coefficient is negative, and so the AD input pin voltage temperature characteristics are also negative.
Put nearby BU9817FV VCC ADx BU9817FV NTC thermistor
Put nearby measured object GND is required common and stability.
!External dimensions (Units : mm)
5.0 0.2 14 8
6.4 0.3
4.4 0.2
1.15 0.1
1
7
0.1
0.65
0.22 0.1
0.3Min. 0.1
SSOP-B14
0.15 0.1

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