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HMD4M64D16V
32Mbyte(4Mx64) Fast Page Mode 4K Ref. 3.3V, DIMM 168 pin Part No. HMD4M64D16V
GENERAL DESCRIPTION
The HMD4M64D16V is a 4Mx64bits Dynamic RAM high density memory module. The HMD4M64D16V consists of sixteen CMOS 4Mx4bits DRAMs in SOJ/TSOP 400mil packages mounted on a 168-pin glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The HMD4M64D16EV is a Dual Inline Memory Module and is intended for mounting into 168 pin edge connector sockets
FEATURES
SPEED w Part Identification HMD4M64D16V --- 4KCycles/64ms Ref, Gold Plate Lead w High-density 32MByte design w New JEDEC standard proposal without buffer w CAS-before-RAS Refresh capability w RAS-only and Hidden refresh capability w Single +3.3 0.3V power supply w Fast Page mode operation. w LVTTL compatible inputs and outputs w FR4-PCB design w Access times : 50, 60ns -5 -6
PERFORMANCE RANGE
tRAC 50ns 60ns tCAC 15ns 17ns tRC 84ns 104ns tHPC 20ns 25ns
w Timing 50ns access 60ns access w Packages 168-pin DIMM D -5 -6
PIN NAMES
Pin Name A0-A11 A0-A12 Function Address Input (4k ref) Address Input (8k ref) Pin Name /RAS0, /RAS2 /CAS0 - /CAS7 Function Row Address Strobe Column Strobe /W0,/W2 /OE0,/OE2 Read/Write Enable Output Enable SCL DU Serial Clock Don't use Vcc SDA Power (+3.3V) Serial Address /Data I/O SA0 - SA2 Address in EEPROM CB0 - CB7 Check Bit DQ0-DQ63 Data In/Out Address Pin Name Vss NC Function Ground No Connection
l
When Used to Parity, SA0-SA2,SCL,CB0-CB7,SDA is setting. This Model not used.
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HMD4M64D16V
PIN ASSIGNMENT
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Symbol Vss DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 Vss DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 NC NC Vss NC NC Vcc /WE0 /CAS0
PIN 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
Symbol /CAS1 /RAS0 /OE0 Vss A0 A2 A4 A6 A8 A10 NC Vcc Vcc NC Vss /OE2 /RAS2 /CAS2 /CAS3 /WE2 Vcc NC NC NC NC Vss DQ16 DQ17
PIN 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
Symbol DQ18 DQ19 Vcc DQ20 NC NC NC Vss DQ21 DQ22 DQ23 Vss DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 Vss NC NC NC SDA SCL Vcc
PIN 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112
Symbol Vss DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 DQ40 Vss DQ41 DQ42 DQ43 DQ44 DQ45 Vcc DQ46 DQ47 NC NC Vss NC NC Vcc NC /CAS4
PIN 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140
Symbol /CAS5 /RAS1 NC Vss A1 A3 A5 A7 A9 A11 NC Vcc NC NC Vss NC /RAS3 /CAS6 /CAS7 NC Vcc NC NC NC NC Vss DQ48 DQ49
PIN 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
Symbol DQ50 DQ51 Vcc DQ52 NC NC NC Vss DQ53 DQ54 DQ55 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 Vss NC NC SA0 SA1 SA2 Vcc
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FUNCTIONAL BLOCK DIAGRAM
DQ 0-63
/CAS0 /RAS0 /OE0 /CAS /RAS /OE /W DQ0-3 /CAS4 /RAS2 /OE2 /CAS /RAS /OE /W
HMD4M64D16V
DQ32-35
U1
A0 -A11
U11
A0 -A11
/CAS /RAS /OE /W
DQ4-7
U2
A0 -A11
/CAS /RAS /OE /W
DQ36-39
U12
A0 -A11
/CAS1
/CAS /RAS /OE /W
DQ8-11
/CAS5
U3
A0 -A11
/CAS /RAS /OE /W
DQ40-43
U13
A0 -A11
/CAS /RAS /OE /W
DQ12-15
U4
A0 -A11 /CAS6
/CAS /RAS /OE /W
DQ44-47
U14
A0 -A11
/CAS2
/CAS /RAS /OE /W
DQ16-19
/CAS /RAS /OE /W
DQ48-51
U6
A0 -A11
U16
A0 -A11
/CAS /RAS /OE /W /CAS3
DQ20-23
U7
A0 -A11
/CAS /RAS /OE /W
DQ52-55
U17
A0 -A11
/CAS /RAS /OE /W
DQ24-27
/CAS
U8
A0 -A11
/CAS /RAS /OE /W
DQ56-59
U18
A0 -A11
/CAS /RAS /OE /W
DQ28-31
U9
A0 -A11
/CAS /RAS /OE /W
DQ60-63
U19
A0 -A11
/WE0 A(0:11)
/WE2
Vcc
0.1uF or 0.22uF Capacitor To all DRAMs
Vss
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ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN ,OUT Vcc PD TSTG
HMD4M64D16V
RATING -0.5V to 4.6V -0.5V to 4.6V 16W -55oC to 150oC
Short Circuit Output Current IOS 50mA w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
( Voltage reference to VSS, TA=0 to 70 o C ) PARAMETER Supply Voltage Ground Input High Voltage Input Low Voltage SYMBOL Vcc Vss VIH VIL MIN 3.0 0 2.0 -0.3 TYP. 3.3 0 MAX 3.6 0 Vcc+0.3 0.8 UNIT V V V V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted) HMD16M64D16EV (4K REF) SYMBOL SPEED MIN MAX -5 ICC1 -6 ICC2 ICC3 -6 -5 ICC4 -6 ICC5 ICC6 -6 Icc7 Iccs L L 1600 4000 3200 mA A A Don't care -5 1280 8 1870 mA MA mA 1600 1440 mA mA Don't care -5 1600 16 1870 mA MA mA 1870
UNITS
mA
ICC1 : Operating Current * (/RAS , /CAS , Address cycling @t RC=min.) ICC2 : Standby Current ( /RAS=/CAS=VIH )
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ICC3 : /RAS Only Refresh Current * ( /CAS=V IH, /RAS, Address cycling @tRC=min ) ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min ) ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V ) ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min ) IIL : Input Leakage Current (Any input 0V VIN 4.5V, all other pins not under test = 0V) IOL : Output Leakage Current (Data out is disabled, 0V VOUT 3.3V VOH : Output High Voltage Level (IOH= -2mA ) VOL : Output Low Voltage Level (IOL = 2mA )
HMD4M64D16V
* NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle.
o
CAPACITANCE
( TA=25 C, Vcc = 3.3V, f = 1Mz ) SYMBOL CIN1 C IN2 CIN3 CIN4 CDQ1
o
DESCRIPTION Input Capacitance (A0-A11) Input Capacitance (/W0,/W1,/OE0,/OE2) Input Capacitance (/RAS0,/RAS2) Input Capacitance (/CAS0-/CAS7) Input/Output Capacitance (DQ0-63)
MIN -
MAX 20 20 73 20 17
UNITS pF pF pF pF pF
AC CHARACTERISTICS
( 0 C TA 70oC , Vcc = 3V10%, See notes 1,2.) -5 -6 UNIT MIN MAX MIN 104 140 50 13 25 3 3 3 2 30 50 13 38 8 20 15
-5-
STANDARD OPERATION Random read or write cycle time Read-modify-write cycle time Access time from /RAS Access time from /CAS Access time from column address /CAS to output in Low-Z /OE to output in Low-Z Output buffer turn-off delay from /CAS Transition time (rise and fall) /RAS precharge time /RAS pulse width /RAS hold time /CAS hold time /CAS pulse width /RAS to /CAS delay time /RAS to column address delay time
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SYMBOL MAX tRC tRWC tRAC tCAC tAA tCLZ tOLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD 84 116
ns ns 60 15 30 ns ns ns ns ns 13 50 ns ns ns 10K ns ns ns 10K 45 30 ns ns ns
3 3 13 50 3 2 40 10K 60 15 45 10K 37 25 10 20 15
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/CAS to /RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address hold referenced to /RAS Column Address to /RAS lead time Read command set-up time Read command hold referenced to /CAS Read command hold referenced to /RAS Write command hold time Write command pulse width Write command to /RAS lead time Write command to /CAS lead time Data-in set-up time Data-in hold time Refresh period Write command set-up time /CAS to /W delay time /RAS to /W delay time Column address to /W delay time /CAS precharge to /W delay time /CAS setup time (/CAS-before /RAS refresh) /CAS hold time(/CAS-before-/RAS refresh) /RAS to /CAS precharge time Access time from /CAS precharge Hyper page mode cycle time Hyper page mode read-modify write cycle time /CAS precharge time(Hyper page cycle) /RAS pulse width (Hyper page cycle) /RAS hold time from /CAS precharge /OE access time /OE to date delay Output buffer tune off delay time from /OE /OE command hold time tCP tRASP tRHCP tOEA tOED tOEZ tOEH 13 3 13 13 8 50 30 13 15 3 13 200K 10 60 35 tCHR tRPC tCPA tHPC tHPRWC 20 47 10 5 28 25 56 10 5 tCRP tASR tRAH tASC tCAH tRRH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS tDH tREF tWCS tCWD tRWD tAWD tCPWD tCSR 0 30 67 42 47 5 5 0 10 0 8 0 25 0 0 0 10 10 13 8 0 8 32 0 34 79 49 54 5 5 0 10 0 10 0 30 0 0 0 10 10 15 10 0 10
HMD4M64D16V
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 32 ms ns ns ns ns ns ns
ns ns 35 ns ns ns
ns 200K ns ns 15 ns ns 15 ns ns
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Output data hold time Output buffer turn off delay from /RAS Output buffer turn off delay from /W /WE to data delay /OE to /CAS hold time /CAS hold time to /OE /OE precharge time /WE pulse width (Hyper page cycle) tDOH tREZ tWEZ tWED tOCH tCHO tOEP tWPE 10 3 3 15 5 5 5 5 13 13 10 3 3 15 5 5 5 5
HMD4M64D16V
ns 15 15 ns ns ns ns ns ns ns
NOTES
1.An initial pause of 200s is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.Input voltage levels are VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times
are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3.Measured with a load equivalent to 1TTL loads and 100pF 4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD
is greater than the specified tRCD(max) limit, then access time is controlled exclusively by t CAC.
5.Assumes that tRCD tRCD(max)
6.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH or VOL. 7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter. They are included in the data sheet as electrical characteristic only. If t WCS tWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle the data output will contain the data read from the selected address. If neither of the above conditions are satisfied, The condition of the data out is indeternimated. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA. 10. If /RAS goes to high before /CAS high going, the open circuit condition of the output is achieved by /CAS high going. If /Cas goes to high before /RAS high going, the open circuit condition of the output is achieved by /RAS high going. 11.tASC 6ns
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TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE
HMD4M64D16V
/RAS
/CAS
A
/W
/OE
DQ
TIMING WAVEFORM OF WRITE CYCLE (EARLY WRITE)
/RAS
/CAS
A
/W
/OE
DQ
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TIMING WAVEFORM OF WRITE CYCLE (/OE CONTROLLED WRITE) NOTE : Dout = OPEN
HMD4M64D16V
/RAS
/CAS
A /W
/OE
DQ
READ MODIFY WRITE CYCLE
/RAS
/CAS
A
/W
/OE
DQ
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HYPER PAGE READ CYCLE
HMD4M64D16V
/RAS
/CAS
A
/W
/OE
DQ
HYPER PAGE WRITE CYCLE (EARLY WRITE) /RAS
/CAS
A
/W
/OE
DQ
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HYPER PAGE READ MODIFY WRITE CYCLE /RAS
HMD4M64D16V
/CAS
A /W
/OE
DQ
HYPER PAGE READ AND WRITE MIXED CYCLE
/RAS
/CAS
A
/W
/OE
DQ
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/RAS ONLY REFRESH CYCLE NOTE: /W,/OE,Din = Don't care Dout = OPEN
HMD4M64D16V
/RAS
/CAS
A
/CAS BEFORE /RAS REFRESH CYCLE NOTE: /OE, A = Don't care
/RAS
/CAS
A
DQ
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HIDDEN REFRESH CYCLE ( READ)
HMD4M64D16V
/RAS
/CAS
A
/W
/OE
DQ
HIDDEN REFRESH CYCLE ( WRITE ) NOTE: Dout = OPEN
/RAS
/CAS
A
/W
/OE
DQ
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/CAS BEFORE /RAS REFRESH COUNTER TEST CYCLE /RAS
HMD4M64D16V
/CAS
A READ CYCLE
/W
/OE
DQ WRITE CYCLE /W
/OE
DQ
READ-MODIFY-WRITE /W
/OE
DQ
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/CAS BEFORE /RAS SELF REFRESH CYCLE NOTE : /OE, A = Don't care
HMD4M64D16V
/RAS
/CAS
DQ
/W
TEST MODE IN CYCLE NOTE: /OE, A = Don't care
/RAS
/CAS
/W
DQ
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PACKAGING INFORMATION
(FRONT VIEW)
HMD4M64D16V
3.69mm MAX
0.25 mm MAX
2.54 mm MIN
1.27
Gold : 1.00mm
1.270.1 mm
ORDERING INFORMATION
Part Number Density Org. Package Component Number 16EA 16EA Vcc MODE SPEED
HMD4M64D16V-5 HMD4M64D16V-6
32Byte 32Byte
X64 x 64
168 Pin-DIMM 168 Pin-DIMM
3.3V 3.3V
FP FP
50ns 60ns
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