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TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES
MSM832 - 020/025/35
PRODUCT MAY BE MADE OBSOLETE WITHOUT NOTICE: November 1998 ISSUE 4.3
32K x 8 SRAM
MSM832 - 020/025/35
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear NE29 8SE, England Tel. +44 (0)191 2930500 Fax. +44 (0) 191 2590997
Issue 5.0 : April 2001
Description The MSM832 is a high speed Static RAM organised as 32K x 8 available with access times of 20 25 or 35 ns. It features completely static operation with a low power standby mode and is 3.0V battery back-up compatible. It is directly TTL compatible and has common data inputs and outputs. The device may be screened in accordance with MIL-STD-883.
32,768 x 8 CMOS High Speed Static RAM Features * Fast Access Times of 20/25/35 ns. * JEDEC Standard footprint. * Operating Power 1 W (max) * Low Power Standby 13 mW (max) -L version. * Low Voltage Data Retention. * Directly TTL compatible. * Completely Static Operation.
Block Diagram
Pin Definitions
A1 14 A2 12 A3 7 A4 6 A5 5 A6 4 A7 3 A8 2 A9 1 A 10 0 D 11 0 D 12 1 D 13 2 G D 14 N
A3 A4 A5 A6 A7 A8 A12 A13 A14
X Address Buffer
Row Decoder
Memory Array
512 X 512
V,T PACKAGE TOP VIEW
D0 D7
I/O Buffer
Column I/O Column Decoder
WE OE
Y Address Buffer
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC W E A13 A8 A9 A11 OE A10 CS D7 D6 D5 D4 D3
A0 A1 A2 A9 A10 A11
CS
Package Details Pin Count 28 28 28 Description Package Type V T S
0.1" Vertical-in-LIne (VILTM) 0.3" Dual-in-line (SKINNY DIP) 0.6" Dual-in-line
Pin Functions A0-A14 Address inputs D0-7 Data Input/Output CS Chip Select OE Output Enable WE Write Enable V CC Power(+5V) GND Ground
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ISSUE 4.3 : November 1998
MSM832 - 020/025/35
DC OPERATING CONDITIONS Absolute Maximum Ratings (1) Voltage on any pin relative to VSS (2) Power Dissipation Storage Temperature VT PT TSTG -0.5V to +7 1 -65 to +150 V W
o
C
Notes : (1) Stresses above those listed may cause permanent damage. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply Voltage Input High Voltage Input Low Voltage Operating Temperature
Symbol
V CC VIH VIL TA TAL TAM
min
4.5 2.2 -0.5 0 -40 -55
typ
5.0 -
max
5.5 VCC+0.5 0.8 70 85 125
Unit
V V V
o o
C C ( Suffix I ) C ( Suffix M, MB )
o
DC Electrical Characteristics (VCC = 5.0V10%, TA=-55C to +125C)
Parameter
Input Leakage Current Output Leakage Current Average Supply Current Standby Supply Current
Symbol Test Condition
ILI ILO ICC ISB1 ISB2 VOL VOH
VIN=0V to VCC CS=VIH or OE=VIH ,VI/O= VSS to VCC ,WE=VIL CS=VIL,II/O=0mA, Min. Cycle, Duty=100% CS=VIH ,Min Cycle. CSVCC-0.2V, 0.2VVINVCC-0.2V IOL= 8.0 mA IOH= -4.0 mA
min
-2 -2 2.4
typ
-
max
2 2 182 44 2.3 0.4 -
Unit
A A mA mA mA V V
-L Version Output Voltage
Capacitance (VCC=5V10%,TA=25C)
Parameter
Input Capacitance I/O Capacitance
Note:
Symbol Test Condition
CIN CI/O VIN = 0V VI/O= 0V
min
-
typ
-
max
7 8
Unit
pF pF
This parameter is not 100% tested.
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MSM832 - 020/025/35
ISSUE 4.3 : November 1998
Operating Modes The table below shows the logic inputs required to control the MSM832 SRAM.
Mode
Not Selected OutputDisable Read Write
CS
1 0 0 0
OE
X 1 0 X 1 = VIH,
WE
X 1 1 0
VCC Current
ISB1,ISB2 ICC ICC ICC 0 = VIL,
I/O Pin Reference Cycle
High Z High Z DOUT DIN Read Cycle Write Cycle Power Down
X = Don't Care
Low Vcc Data Retention Characteristics - L Version Only ( TA=-55C to +125C)
Parameter
VCC for Data Retention Data Retention Current -L Version Chip Deselect to Data Retention Time Operation Recovery Time Notes (1) tRC = Read Cycle Time
Symbol
VDR ICCDR2 t CDR tR
Test Condition
CSVCC-0.2V, VIN0V See Retention Waveform See Retention Waveform
min
2.0 0 t RC
(1)
typ
-
max
5.5 350 -
Unit
V A ns ns
VCC=2.0V, CSVCC-0.2V, VIN0V -
AC Test Conditions * Input pulse levels: 0V to 3.0V * Input rise and fall times: 3ns * Input and Output timing reference levels: 1.5V * Output load: see diagram * Vcc=5V10%
Output Load
I/O Pin 166 1.76V 30pF
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ISSUE 4.3 : November 1998
MSM832 - 020/025/35
AC OPERATING CONDITIONS Read Cycle
20 Parameter
Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Output Hold from Address Change Chip Selection to Output in Low Z Output Enable to Output in Low Z Chip Deselection to Output in High Z Output Disable to Output in High Z
(3) (3)
25 max
20 20 9 9 9
35 max
25 25 12 12 12
Symbol min
t RC tAA tACS tOE tOH tCLZ tOLZ t CHZ tOHZ 20 5 6 0 0 0
min
25 5 6 0 0 0
min
35 5 6 0 0 0
max
35 35 15 15 15
Unit
ns ns ns ns ns ns ns ns ns
Write Cycle
Parameter
Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write
20 Symbol min. max
t WC t CW tAW tAS tWP t WR t WHZ t DW t DH t OW 20 15 15 0 15 0 0 15 0 5 15 -
min.
25 20 20 0 15 0 0 20 0 5
25 max
15 -
35 min
35 30 30 0 20 0 0 20 0 5
max
18 -
Unit
ns ns ns ns ns ns ns ns ns ns
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MSM832 - 020/025/35
ISSUE 4.3 : November 1998
Read Cycle 1 Timing Waveform
(1)
t
RC
Address
t AA
OE
t OE t OLZ t OH
CS
t CLZ t ACS t CHZ(3) t OHZ(3)
Dout
High-Z
Data Valid
Read Cycle 2 Timing Waveform
(1) (2) (4)
t RC
Address
t AA t OH t OH
Dout
Data Valid
Notes: (1) WE is High for Read Cycle. (2) Device is continuously selected, CS=VIL. (3) tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. These parameters are sampled and not 100% tested. (4) OE=VIL.
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ISSUE 4.3 : November 1998
MSM832 - 020/025/35
Write Cycle No.1 Timing Waveform
t WC
Address
t AS(3) t AW t CW(4)
(6)
OE
tWR
(2)
CS
t WP(1)
WE
t OHZ(3,9) High-Z t DW High-Z t OW t DH
Dout
Din
Data Valid
Write Cycle No.2 Timing Waveform
(5)
t WC Address tCW CS
(6) (4)
t AW t WP(1) WE t AS(3) t WHZ(3,9) Dout High-Z t DW Din High-Z Data Valid t OW
t WR(2)
t OH
(8) (7)
tDH
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MSM832 - 020/025/35
ISSUE 4.3 : November 1998
Data Retention Waveform
Vcc
4.5V
DATA RETENTION MODE
4.5V
t CDR VDR
CS
0V
tR
2.2V
CS>Vcc-0.2V
AC Write Characteristics Notes (1) (2) (3) (4) (5) (6) (7) (8) (9) A write occurs during the overlap (tWP) of a low CS and a low WE. tWR is measured from the earlier of CS or WE going high to the end of write cycle. During this period, I/O pins are in the output state. Input signals out of phase must not be applied. If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition, outputs remain in a high impedance state. OE is continuously low. (OE=VIL) Dout is in the same phase as written data of this write cycle. Dout is the read data of next address. If CS is low during this period, I/O pins are in the output state. Input signals out of phase must not be applied to I/O pins. tWHZ and tOHZ is defined as the time at which the outputs achieve the open circuit conditions and is not referenced to output voltage levels. This parameter is sampled and not 100% tested.
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ISSUE 4.3 : November 1998
MSM832 - 020/025/35
PACKAGE DETAILS dimensions in mm (inches) 28 pin 0.6" Dual-In-Line (DIL) - 'S' Package
35.94 (1.415) 35.18 (1.385)
1.54 (0.060) 1.02 (0.040) 4.00 (0.157) 3.00 (0.117) 2.67 (0.105) 2.41 (0.095) 0.51 (0.020) 0.41 (0.016) 4.45 (0.175) 3.43 (0.135)
28 pin 0.3" Dual-in-Line (SKINNY)
35.94 (1.415) 35.18 (1.385)
15.56 (0.610)
1.54 (0.060) 1.02 (0.040) 4.00 (0.157) 3.00 (0.117) 2.67 (0.105) 2.41 (0.095) 0.51 (0.020) 0.41 (0.016)
8
15.05 (0.590)
7.87 (0.310) 7.37 (0.290) 4.30 (0.170) 3.30 (0.130)
MSM832 - 020/025/35
ISSUE 4.3 : November 1998
28 pin 0.1" Vertical-In-Line (VIL) - 'V' Package
35.94 (1.415) 35.18 (1.385) 11.43 (0.450) 10.41 (0.410)
3.18 (0.125) 2.67 (0.105)
4.00 (0.157) 3.00 (0.117) 1.54 (0.060) 1.02 (0.040) 2.54 (0.100) 0.51 (0.020) 0.41 (0.016) 2.54 (0.100)
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ISSUE 4.3 : November 1998
MSM832 - 020/025/35
SCREENING Military Screening Procedure The Component Screening Flow for high reliability parts in accordance with Mil-883 method 5004 is shown below:
MB COMPONENT SCREENING FLOW
SCREEN
Visual and Mechanical Internal visual Temperature cycle Constant acceleration Pre-Burn-in electrical Burn-in Final Electrical Tests Static (dc) Functional Switching (ac) Percent Defective allowable (PDA) Hermeticity Fine Gross External Visual 2010 Condition B or manufacturers equivalent 1010 Condition C (10 Cycles,-65C to +150C) 2001 Condition E (Y, only) (30,000g) Per applicable device specifications at TA=+25C Method 1015,Condition D,TA=+125C,160hrs min Per applicable Device Specification a) @ TA=+25C and power supply extremes b) @ temperature and power supply extremes a) @ TA=+25C and power supply extremes b) @ temperature and power supply extremes a) @ TA=+25C and power supply extremes b) @ temperature and power supply extremes Calculated at post-burn-in at TA=+25C 1014 Condition A Condition C 2009 Per vendor or customer specification 100% 100% 100% 100% 100% 100% 100% 100% 100% 5% 100% 100% 100% 100% 100%
TEST METHOD
LEVEL
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MSM832 - 020/025/35
ISSUE 4.3 : November 1998
ORDERING INFORMATION
MSM832VLMB - 35
Speed 020 025 35 Blank I M MB = 20 ns = 25 ns = 35 ns = Commercial = Industrial = Military = Screened in accordance with MIL-STD-883
Temp. range/screening
Power Option
Blank = Standard Power L = Low Power S V T = 28 pin DIP (0.6") = 28 pin 0.1" VIL = 28 pin 0.3" SKINNY DIP
Package
Memory Organisation
832
= 32K x 8 SRAM
THESE DEVICES ARE NOT RECOMMENDED FOR NEW DESIGNS AND MAY BE MADE OBSOLETE WITHOUT NOTICE....
Although this data is believed to be accurate, the information contained herein is not intended to, and does not create any warranty of merchantability or fitness for a particular purpose. Our products are subject to a constant process of development. Data may be changed at any time without notice. Our products are not authorised for use as critical components in life support devices, or systems without the express written approval of a company director.
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