View TDA6612-2_397309.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TV-Stereo-Sound
Preliminary Data
TDA 6612-2
Bipolar IC
Features The TDA 6612-2 represents a complete TV-stereo system controlled by the I2C Bus according to German TV-Stereo standard.
q All functions inclusive matrix adjustment are I2C Bus q q q q q q q q q
controlled Inputs for AM sound or NICAM SCART-interface Independent headphones Universal clock generation circuit build-in Clipping detector build-in Volume control High signal-to-noise ratio Extremely low total harmonic distortions High security for the detection of the identification signals because of the digital interference suppression and the very narrow bandwidth
P-DIP-28-3
P-DSO-28-1
Type TDA 6612-2 TDA 6612-2X
Ordering Code Q67000-A5097 Q67000-A5194
Package P-DIP-28-3 P-DSO-28-1
Semiconductor Group
1
08.94
TDA 6612-2
The IC is divided into three functional blocks 1 Stereo Sound Processing with High Performance (exceeds DIN 45500; suitable for NICAM and CD) a) Matrix for G-standard with crosstalk compensation controlled via the I2C Bus b) Additional single channel AF input (for e.g. AF signal according to L-standard) c) Stereo SCART interface according to FTZ-official specification d) Stereo loudspeaker signal section with Ch1/Ch2 switch, bass/treble control, quasi stereo/stereo base width expansion and separate loudspeaker volume control for left and right (balance) e) Separate stereo head phone signal section with Ch1/Ch2 switch and volume control 2 TV-Sound Identification Signal Decoder Consisting of: a) Active pilot signal filter b) Phase independent rectifier with very narrow bandwidth for evaluation of the identification signal c) Digital integrator to reduce interferences by noise d) Multiplexer for cyclical switch over between "stereo" or "dual" evaluation e) Reference signal generation with externally synchronized PLL
* synchronization with external H-sync pulse or 62.5-kHz clock * build-in crystal oscillator and external 4-MHz crystal * external 4-MHz (or 1-MHz) clock signal
3 Control Section for: a) I2C Bus interface with listen/talk function b) Control of the complete AF-sound signal detector c) Read access to the clipping detector d) Control of the identification signal decoder e) Reading of the status of the identification signal decoder f) Test modes
Semiconductor Group
2
TDA 6612-2
Circuit Description Signal Section The audio signal processing in the matrix and the switch-over for multi channel TV-sound signals according to the two carrier system used in Germany takes place in the matrix and switching sections. Crosstalk compensation is carried out in the sound 1 input stage. The crosstalk compensation range has an adjustment range of 3 dB with a step width of 0.2 dB. In addition to the two inputs for the demodulated sound carrier a two channel SCART-input and an additional mono input (e.g. for demodulated L-standard sound) are provided. The two AF (pin 1 and pin 2) inputs can be bypassed internally in such a way that decoded stereo sound of other audio systems (NICAM) can be processed. The switching section includes also the SCART-output with the possibility to select the sound 1 or 2 during the "dual" mode. The Ch1/Ch2-switches for the loudspeaker and headphone outputs are independently switchable. In the signal path for the volume control unit output there is the Ch1/Ch2-switch followed by two different volume control units. The first has a control range from 0 to - 15 dB with a step width of 1.25 dB. In conjunction with the main volume control after bass and treble control a high immunity against overdriving the output stage is reached. The first volume control is used as a "pre-stage" of the main volume control in conjuntion with the clipping detector. This section is followed by a switchable quasi stereo stage which provides a stereophonic audio effect with mono signals due to a 180 phase shift at medium frequencies (about 1 kHz) in one channel. The following bass control has a control range of +15/-12 dB with a step width of 3 dB. The cut-off frequency for each channel is set with an external capacitor. The implemented switchable circuit for stereo base width expansion provides a three dimensional aural reception. This is realized with a 50% frequency dependent crosstalk with opposite phase of the signal between both channels. The circuit operates with the same cut-off frequency as the bass control, but the function is widely independent. The treble control has a step width of 3 dB with an control range of +/-12 dB. The cut-off frequency of the treble control is derived from one capacitor for each channel. The loudspeaker signal path is terminated with the loudspeaker control, independently adjustable for left and right. With 57 steps of 1.25 dB the adjustment range is 70 dB, where step 57 activates the "MUTE" function. Functions such as "balance" or "loudness" are realized by software and adjustment of the appropriate tone and volume controls. In the volume control unit there is a clipping detector. The status of the clipping detector can be evaluated via the I2C Bus. Therefore it is possible to implement an automatic volume control using the clipping detector and software implemented into the controller. After every evaluation the clipping bit is reset. Therefore after a read access to the clipping bit a new evaluation of the clipping detector status is possible. The signal path for the headphones contains a volume control after the Ch1/Ch2-switch with a common adjustment for left and right. Thirty two steps of 2 dB give an adjustment range of 62 dB (31 x 2 dB = 62 dB, the 32nd step is MUTE). Identification Signal Decoder The input of the identification signal decoder consists of an op-amp for the pilot signal with its side bands. An external LC-circuit is used. The signal is then passed to a phase independent active band-pass filter with a very narrow bandwidth (adjustable externally). This filter detects whether the lower side band of the pilot carrier, which is modulated with the identification signal, is present. The
Semiconductor Group
3
TDA 6612-2
center frequency of the filter is switched between "dual" and "stereo" by a multiplexer. The multiplexing frequency is adjustable by software. If a side band is detected, the multiplexer stops. The interferences on the first "detected" criterion are suppressed by a digital integrator with a following comparator and can be read out via I2C Bus (talk mode) as the "stereo" or "dual" mode. The control of the corresponding signal can be either directly internally or through the C. All the necessary clock signal are derived from a fast setting PLL which is synchronized by a reference frequency. This reference frequency must be sufficiently close to the horizontal frequency, but a rigid phase coupling is not required. Therefore, alternatively the use of a crystal controlled 62.5kHz frequency commonly found in PLL-tuning systems is possible. A further alternative for the clock signal generation is a build-in crystal oscillator with an external 4-MHz crystal or the use an external 1- or 4-MHz clock frequency. Control Section All functions are controlled via an I2C Bus interface with "listen" / "talk" functions. The data bytes currently used are stored in a block of latches. The telegram structure is formed in the following manner: start condition - chip address - any number of bytes - stop condition The following conditions apply to the data bytes: Before the actual data byte (with the adjustment information), always an I2C Bus sub-address byte has to be transmitted. The I2C Bus interface however is interpreting this sub-address byte as a data byte. Example: The headphone volume is to be increased in a number of steps.
Right Start condition Chip address 84 (Hex) Sub-addr. vol. HP 03 (Hex) Vol. step 8 08 (Hex) Sub-addr. vol. HP 03 (Hex) Vol. step 9 09 (Hex) Sub-addr. vol. HP 03 (Hex) Vol. step 10 0A (Hex) Stop condition
Wrong Start condition Chip address 84 (Hex) Sub-addr. vol. HP 03 (Hex) Vol. step 8 08 (Hex) Vol. step 9 09 (Hex) Vol. step 10 0A (Hex) Stop condition
Within a telegram (i.e. without a new start condition) any different sub-addresses can be accessed. The changeover between "listen" and "talk" access to the IC however must always occur using the following sequence: stop condition - start condition - chip address. Before each read access always a start condition and chip address (talk) must be transmitted. The data to be read out are then loaded into the I2C Bus interface and can be transferred to the C.
Semiconductor Group
4
TDA 6612-2
Chip Address MSB 1 * 0 * 0 * 0 * 0 * 1 * 0 LSB R/W
R/W = 0 Read (Listen) R/W = 1 Write (Talk) Subaddress Bytes MSB * Volume input control Volume of left speaker Volume of right speaker Volume of headphones Treble / bass Switch byte I Switch byte II Crosstalk adjustment X X X X X X X X X X X X X X X X * X X X X X X X X * X X X X X X X X * X X X X X X X X * 1 0 0 0 1 1 0 1 * 0 0 1 1 0 1 0 1 LSB 0 1 0 1 1 1 0 0
Control Bytes a) Volume Input Control MSB Maximum volume Max - 1 Min + 1 Minimum volume Power ON Qu-H = 0 Qu-H = 1 Qu-H Qu-H Qu-H Qu-H 0 * Ch1/Ch2EN Ch1/Ch2EN Ch1/Ch2EN Ch1/Ch2EN 0 * Ch1/Ch2SC Ch1/Ch2SC Ch1/Ch2SC Ch1/Ch2SC 0 * 0 0 1 1 0 * 0 0 0 1 0 * 0 0 1 0 0 * 0 1 1 0 0 LSB MUTE III MUTE III MUTE III MUTE III 1
PLL synchronization with H-pulse; power ON PLL synchronization with crystal oszillator, additionally the bit "H-pulse" has to be set to "H" in switch byte ll
Semiconductor Group
5
TDA 6612-2
Ch1/Ch2EN 0 0 1 1
Ch1/Ch2SC 0 1 0 1
SCART output pin 9 sound 1 sound 2 sound 1 sound 2
SCART output pin 10 sound 2 sound 1 sound 1 sound 2
Ch1/Ch2EN, Ch1/Ch2SC are only activated if the matrix is in the dual mode (switch byte ll: matrix 0 = 1 and matrix 1 = 0 or matrix 0 = 1 , matrix 1 = 1 and the identification decoder is in the mode "dual") MUTE lll = 0 MUTE lll = 1 SCART output are muted. SCART output ON; power ON (will be overwritten by MUTE 1 = 0 equal to all audio outputs muted) MUTE lll is "or" wired with MUTE l.
b) Volume of Left / Right Loudspeaker MSB Maximum volume Max -1 Max -15 Max -55 MUTE MUTE MUTE Power ON X X X X X X X 0 * X X X X X X X 0 * 1 1 1 0 0 0 0 0 * 1 1 1 0 0 0 0 0 * 1 1 0 1 0 0 0 0 * 1 1 0 0 1 0 X 0 * 1 1 0 0 1 0 X 0 LSB 1 0 0 0 1 0 X 1
c) Volume of Headphones MSB Maximum volume Max -1 Max -15 Max -31 MUTE Power ON T2 T2 T2 T2 T2 0 * T1 T1 T1 T1 T1 0 * T0 T0 T0 T0 T0 0 * 1 1 1 0 0 0 * 1 1 0 0 0 0 * 1 1 0 0 0 0 * 1 1 0 0 0 0 LSB 1 0 0 1 0 1
T0, T2 are test bits; these must be set to 0 for normal operation
Semiconductor Group
6
TDA 6612-2
d) Crosstalk Compensation Matrix (sound 1) MSB Max. amplification Max -1 Gain 0 dB Min. gain Min. gain Power ON 0 0 0 0 0 0 * 0 0 0 0 0 0 * 0 0 0 0 0 0 * 1 1 1 0 0 0 * 1 1 0 0 0 0 * 1 1 0 0 0 0 * 1 1 0 0 0 0 LSB 1 0 0 1 X 1
e) Treble/Bass MSB Linear Max. treble, lin. bass Max. treble, lin. bass Min. treble, lin. bass Min. treble, lin. bass Lin. treble, max. bass Lin. treble, max. bass Lin. treble, max. bass Lin. treble, min. bass Lin. treble, min. bass Max. treble, max. bass Min. treble, min. bass Power ON 1 1 1 0 0 1 1 1 1 1 1 0 0 MSB treble * 0 1 1 1 0 0 0 0 0 0 1 0 0 * 0 0 X 0 X 0 0 0 0 0 X X 0 * 0 0 X 0 X 0 0 0 0 0 X X 0 LSB treble * 1 1 1 1 1 1 1 1 0 0 1 0 0 MSB bass * 0 0 0 0 0 1 1 1 1 0 1 0 0 * 0 0 0 0 0 0 X 1 0 X X X 0 LSB 0 0 0 0 0 1 1 X 0 X 1 X 1 LSB bass
Semiconductor Group
7
TDA 6612-2
f) Switch Byte I MSB MUTE I MUTE l MUTE l MUTE ll MUTE ll * MUTE II =0 =1 =0 =1 * CH1/CH2LS * CH1/CH2KH * Mono * SCART * SCART-D LSB AM
All AF-outputs are muted (speakers, headphones, SCART); power ON All AF-outputs ON Loudspeaker outputs muted; power ON Loudspeaker outputs ON
MUTE l and MUTE ll are OR gated with respect to the loudspeaker outputs MUTE l and MUTE llI are OR gated with respect to the SCART output
MUTE I 0 0 0 0 1 1 1 1 Ch1/Ch2LS Ch1/Ch2LS Ch1/Ch2KH Ch1/Ch2KH
MUTE II 0 0 1 1 0 0 1 1 = = = = 0 1 0 1
MUTE III 0 1 0 1 0 1 0 1
Loudspeaker output muted muted muted muted muted muted ON ON
Headphone output muted muted muted muted ON ON ON ON
SCART output muted muted muted muted muted ON muted ON
Sound 1 on the loudspeaker outputs; power ON Sound 2 on the loudspeaker outputs Sound 1 on the headphone outputs; power ON Sound 2 on the headphone outputs
Ch1/Ch2LS and Ch1/Ch2KH are only effective if the matrix is set to the position "dual sound". Mono Mono SCART SCART = = = = 0 1 0 1 identification signal decoder is set to the position mono and held; power ON normal operation if ID-signal decoder normal TV-operation; power ON SCART playback; connection of SCART inputs - AF - outputs SCART = 1 has priority over AM = 1 (loudspeaker and headphones)
SCART-playback stereo (mono); power ON Enable for the Ch1/Ch2 switch during SCART playback. (only effective when SCART = 1) AM = 0 Normal operation (G-standard) AM = 1 AM AF-input is activated; power ON AM = 1 has priority over bypass = 1 Qu-H, Ch1/Ch2EN, Ch1/Ch2SC MUTE lll see chapter Control Bytes a). Semiconductor Group 8
SCART-D SCART-D
= =
0 1
TDA 6612-2
g) Switch Byte II MSB MPX0 MPX0 0 0 1 * MPX1 MPX1 0 1 0 * Quasi-st MPX-period 2s 4s 8s * BS * H-pulse * Matrix 0 * Matrix 1 LSB Bypass
recommended C 25, 26 permissible crystal tolerance power ON 1 F 2.2 F 4.7 F 40 ppm 70 ppm
special for crystal operation recommended adjustments: 0 0 2s 470 nF 0 1 4s 330 nF
MPX period = 2 s signifies: ID-signal decoder searches 1 second dual and 1 second stereo. It is inprinciple permitted to make with given C 25, 26 the MPX-period higher than indicated, but not lower. Quasi stereo Quasi stereo Bb Bb H-pulse H-pulse = = = = = = 0 1 0 1 0 1 Quasi stereo OFF; power ON Quasi stereo ON Stereo base width expansion OFF; power ON Stereo base width expansion ON; ID-signal decoder synchronization with f H = 15.625 kHz; power ON ID-synchronization with 4 x f H (has to be set to 1 during operation with crystal or 4-MHz reference frequency) Matrix status mono power ON stereo dual automatic according to ID-signal decoder
Matrix 0 0 0 1 1 Bypass = Bypass =
Matrix1 0 1 0 1 0 1
Normal operations (G-standard) Matrix is bridge so that left/right signals can be fed; power ON (AM = 1 has priority over bypass = 1)
Semiconductor Group
9
TDA 6612-2
Priority List of Setting Bits 1. MUTE l 2. MUTE ll (only with regard to the loudspeaker output) 3. SCART 4. AM 5. Bypass 6. Matrix 0, 1
h) Talk Mode MS St 0 1 0 1 CL = 1 * D 0 * T3 * T4 * T5 * CL * X LSB X
decoder detects mono
0 decoder detects stereo 1 decoder detects dual 1 internally inhibited The signal path for the loudspeaker reached the clipping level (The bit CL is automatical reset)
T3 - T5 are test bits
Semiconductor Group
10
TDA 6612-2
Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Function AF-input mono, left, sound 1 (may be balanced) Bias for AF-operating point AF-input right, sound 2 54-kHz input 54-kHz filter AF-input (L-standard) AF-input SCART left (sound 1) AF-input SCART right (sound 2) AF-output SCART (mono, sound 1, left) AF-output SCART (mono, sound 2, right) Phase shifter quasi stereo Phase shifter quasi stereo Cut-off frequency bass (base width) left Cut-off frequency bass (base width) right AF-output, loudspeaker right AF-output, loudspeaker left Cut-off frequency treble left Cut-off frequency treble right AF-output, headphones right AF-output, headphones left + VS (supply voltage) I2C Bus SCL I2C Bus SDA Input H-pulse (4 x H-pulse), crystal oscillator Filter ID-signal decoder Filter ID-signal decoder PLL-filter ID-signal decoder Ground
Semiconductor Group
11
TDA 6612-2
Block Diagram Semiconductor Group 12
TDA 6612-2
PLL Filter ID-Signal Decoder (Pin 27)
Filter ID-Signal Decoder (Pin 25/26)
Semiconductor Group
13
TDA 6612-2
H-Pulse/Crystal Oscillator (Pin 24)
I2C Bus SDA (Pin 23)
Semiconductor Group
14
TDA 6612-2
I2C Bus SCL (Pin 22)
AF-Outputs Headphones (Pin 19/20) Loudspeaker (Pin 15/16) SCART (Pin 9/10) Semiconductor Group 15
TDA 6612-2
Cut-Off Frequency Treble (Pin 17/18)
Cut-Off Frequency Bass (Pin 13/14)
Semiconductor Group
16
TDA 6612-2
Phase Advancer Quasi Stereo (Pin 11/12)
Semiconductor Group
17
TDA 6612-2
AF-Inputs SCART (Pin 7/8)
AF-Input AM (Pin 6)
Semiconductor Group
18
TDA 6612-2
54-kHz Filter (Pin 4/5)
AF-Input (Pin 3)
Semiconductor Group
19
TDA 6612-2
Input for AF-Unit Bias Blocking Capacitor (Pin 2)
AF-Input (Pin 1)
Semiconductor Group
20
TDA 6612-2
Absolute Maximum Ratings TA = 0 to 70 oC; all voltages relatives to Vss Parameter Supply voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-current Max. DC-current Max. DC-current Max. DC-current Max. DC-current Max. DC-current Max. DC-current Max. DC-current Symbol min. V21 V1 V2 V3 V4 V6 V7 V8 V11 V12 V13 V14 V17 V18 V22 V23 V24 V25 V26 I5 I9 I10 I15 I16 I19 I20 I27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Limit Values max. 14 V21 V21 V21 V21 V21 V21 V21 V21 V21 V21 V21 V21 V21 V21 V21 V21 V21 V21 2 2 2 2 2 2 2 1 V V V V V V V V V V V V V V V V V V V mA mA mA mA mA mA mA mA Unit Remarks
Semiconductor Group
21
TDA 6612-2
Absolute Maximum Ratings (cont'd) Parameter ESD-voltage ESD-voltage Junction temperature Storage temperature Thermal resistance system ambient Operating Range Supply voltage Ambiente temperature Input frequency range V6 TA fI 10 0 0.01 13.2 70 20 V
oC
Symbol min. VESD -2
Limit Values max. 2 6 150 - 40 125 53
Unit kV kV
oC oC
Remarks HBM (R = 1.5 k, C = 100 pF) HBM (R = 1.5 k, C = 100 pF)
VESD7,8,9,10 - 6 Tj Tstg R th SA
K/W
kHz
Semiconductor Group
22
TDA 6612-2
Characteristics
VS = 12 V; TA = 25 oC, audio reference level 0 dB-250 mVrms, if not differently defined.
I2C Bus preset: start - 84 - 01,3F - 0 2,3F - 04,00 - 0 3,1F - 0 5,88 - 0 6,10 - 07,C8 - 00,01 - stop Chip address - Vol LSI 63 - Vol LSr 63 - Vol VLs - Vol HP 31 - Sound lin Adjust 0dB - MUTE I, MUTE II, Mono - Bypass The basic setting for each point in the specification is always preset; only settings which deviate from this are given in the test conditions. Details in italics only provide explanation of the hexadecimal codes. If switch byte are mentioned only the bit status and activated features are indicated. Parameter Symbol Limit Values min. Current consumption I21 Signal Section Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain typ. 58. -2 -2 -2 -2 -2 -2 -2 -2 4 4 -2 -2 -2 -2 -2 -2 -2 -2 0 0 0 0 0 0 0 0 6 6 0 0 0 0 0 0 0 0 max. 80 2 2 2 2 2 2 2 2 8 8 2 2 2 2 2 2 2 2 mA dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Unit Test Condition (in accordance with test circuit 1)
V16-1 V15-3 V20-1 V19-3 V16-3 V15-3 V20-3 V19-3 V16-1 V20-1 V16-7 V15-8 V20-7 V19-8 V16-6 V15-6 V20-6 V19-6
00,02; V1 = 01 Matrix: Stereo 00,02; V1 = 01 Matrix: Stereo 00,02; V1 = 0 Matrix: Stereo 00,02; V1 = 0 Matrix: Stereo 00,02; V3 = 0 Matrix: Stereo 00,02; V3 = 0 Matrix: Stereo 07,CC, SCART 07,CC, SCART 07,CC, SCART 07,CC, SCART 07,C9, AM 07,C9, AM 07,C9, AM 07,C9, AM
Semiconductor Group
23
TDA 6612-2
Characteristics (cont'd) Parameter Gain Gain Gain Gain Gain Gain Gain Min. gain Main control Min. gain Main control Min. gain 1st. control Min. gain 1st. control Min. gain Min. gain Symbol Limit Values min. typ. 0 0 0 0 6 0 0 - 70 - 70 - 17 - 17 - 15 - 15 - 62 - 62 max. 2 2 2 2 8 2 2 - 65 - 65 - 13 - 13 - 57 - 57 dB dB dB dB dB dB dB dB dB dB dB dB dB 00,02; V1 = 0 Matrix: Stereo 00,02; V1 = 0 Matrix: Stereo 00,02; V1 = 0 Matrix: Stereo 07,C9, AM 01,08-02,08 Vol LSi 8 - Vol LSr 8 01,08-02,08 Vol LSi 8 - Vol LSr 8 04,18 Vol VLS 24 04,18 Vol VLS 24 03,01, Vol HP 1 03,01, Vol HP 1 -2 -2 -2 -2 4 -2 -2 Unit Test Condition
V9-1 V10-3 V9-3 V10-3 V9-1 V10-6 V9-6 V16-1 V15-3 V16-1 V15-3 V20-1 V19-3
Semiconductor Group
24
TDA 6612-2
Characteristics (cont'd) Parameter Symbol Limit Values min. Channel tracking error Channel tracking error Step width Vol 15 Step width Vol 16 Step width Vol 15 Step width Vol 16 Step width Vol 19 Step width Vol 20 Matrix adjustment Matrix adjustment Matrix adjustment Matrix adjustment Matrix adjustment Matrix adjustment Adjust. step width V15-16 typ. max. 2 dB 01,3F to 01,24 02,3F to 02,24 Vol LSl 63-36 - Vol LSr 63-36 03,1F to 03,13 Vol HP 31-19 01,X-01,(X 1) Vol LSI X - Vol LSI (X 1) 02,X-02,(X 1) Vol LSr X - Vol LSr (X 1) 04,X-04,(X 1) Vol VLS X - Vol VLS (X 1) 04,X-04,(X 1) Vol VLS X - Vol VLS (X 1) 03,X-03,(X 1) Vol HP X - Vol HP (X 1) 03,X-03,(X 1) Vol HP X - Vol HP (X 1) 06,1F, Adjust. max 06,1F, Adjust. max 06,1F, Adjust. max 06,01, Adjust. min 06,01, Adjust. min 06,1F, Adjust. max 06,X-06,(X 1) Adjust. X - adjust. (X 1) Unit Test Condition
Analogous values are valid for feed in at the pins 6, 7 and 8
V19-26 V15 V16 V15 V16 V19 V20 0 0 0 0 0 0 2.5 2.5 2.5 - 3.5 - 3.5 - 3.5 0.1 1.25 1.25 1.25 1.25 2 2 3 3 3 -3 -3 -3 0.2
2 2.5 2.5 2.5 2.5 4 4 3.5 3.5 3.5 - 2.5 - 2.5 - 2.5 0.3
dB dB dB dB dB dB dB dB dB dB dB dB dB dB
V16-1 V20-1 V9-1 V16-1 V20-1 V9-1
V16
Semiconductor Group
25
TDA 6612-2
Characteristics (cont'd) Parameter Adjust. step width Adjust. step width Bass boost Bass boost Bass cut Bass cut Step width bass Step width bass Symbol V20 V9 0.1 0.1 13 13 Limit Values min. typ. 0.2 0.2 15 15 - 12 - 12 1 1 3 3 5 5 max. 0.3 0.3 dB dB dB dB dB dB dB dB 06,X-06,(X 1) Adjust. X - adjust. (X 1) 06,X-06,(X 1) Adjust. X - adjust. (X 1) 05,8 F; fI = 40 Hz Bass max, treble lin. 05,8 F; fI = 40 Hz Bass max, treble lin. 05,8 F; fI = 40 Hz Bass max, treble lin. 05,8 F; fI = 40 Hz Bass max, treble lin. 05,8X-05,8 (X 1) Bass X - bass (X 1) 05,8X-05,8 (X 1) Bass X - bass (X 1) Unit Test Condition
V16-1 V15-3 V16-1 V15-3
V15 V16
Semiconductor Group
26
TDA 6612-2
Characteristics (cont'd) Parameter Treble boost Treble boost Treble cut Treble cut Step width bass Step width bass Linearity sound Symbol Limit Values min. typ. 12 12 - 12 - 12 1 1 3 3 5 5 2 max. dB dB dB dB dB dB dB 05,8 F; fI = 15 Hz Treble max, bass lin. 05,8 F; fI = 15 Hz Treble max, bass lin. 05,8 F; fI = 15 Hz Treble max, bass lin. 05,8 F; fI = 15 Hz Treble max, bass lin. 05,X8-05 (X 1)8 Treble X - treble (X 1) 05,X8-05 (X 1)8 Treble X - treble (X 1) 05,88; fI = 40 Hz - 15 kHz Treble, bass lin. 05,88; fI = 40 Hz - 15 kHz Treble, bass lin. 05,8 F; fI = 40 Hz Treble lin, bass max. 01,2F - 02,2F Vol LSl 47 - Vol LSr 47 10 10 Unit Test Condition
V16-1 V15-3 V16-1 V15-3
V15 V16 V15
Linearity sound
V16
2
dB
Detection level of the clipping detector
V1
580
mVrms
The same values are valid if the test signals are applied at pin 3, 6, 7 or 8 Channel separation Channel separation of the clipping Channel separation Cross talk attenuation switch V15-16 V19-20 V9-10 I interf / Q rms 60 dB 50 50 50 dB dB dB
V3 or V8 = 600 mVrms V3 or V8 = 600 mVrms V3 or V8 = 600 mVrms VI rms = 0 VI Interf, 3,6 = 600 mVrms VI Interf, 7,8 = 2 Vrms
Semiconductor Group
27
TDA 6612-2
Characteristics (cont'd) Parameter Attenuation MUTE Symbol 1-16 80 Limit Values min. typ. max. dB 01,00 - 02,00 Vol LSI 0 - Vol LSr 0 V1 = 600 mVrms 07,48; V1 = 600 mVrms MUTE I: 0 07,88; V1 = 600 mVrms MUTE II: 0 01,00 - 02,00 Vol LSI 0 -Vol LSr 0 V3 = 600 mVrms 07,48; V3 = 600 mVrms MUTE I: 0 07,88; V3 = 600 mVrms MUTE II: 0 03,00; V1 = 600 mVrms Vol HP 0 07,48; V1 = 600 mVrms MUTE I: 0 Unit Test Condition
Attenuation MUTE
1-16
80
dB
Attenuation MUTE
1-16
80
dB
Attenuation MUTE
3-15
80
dB
Attenuation MUTE
3-15
80
dB
Attenuation MUTE
3-15
80
dB
Attenuation MUTE
1-20
80
dB
Attenuation MUTE
1-20
80
dB
Semiconductor Group
28
TDA 6612-2
Characteristics (cont'd) Parameter Attenuation MUTE Symbol 3-19 80 Limit Values min. typ. max. dB 03,00; Unit Test Condition
V3 = 600 mVrms
Attenuation MUTE 3-19 80 dB
MUTE I: 0 07,48; V1 = 600 mVrms MUTE I: 0
07,48; V3 = 600 mVrms MUTE I: 0 07,48; V1 = 600 mVrms MUTE I: 0 07,49; V6 = 600 mVrms MUTE I: 0, AM 07,49; V6 = 600 mVrms MUTE I: 0, AM
Analogous values are valid for feed in at pins 6, 7, 8; V7,8 = 2 Vrms; V6 = 600 mVrms Attenuation MUTE 3-10 80 dB
Attenuation MUTE
1-9
80
dB
Attenuation MUTE
6-10
80
dB
Attenuation MUTE
6-9
80
dB
Max. input voltage Max. input voltage Max. input voltage Max. input voltage Max. input voltage*) Max. input voltage*)
V6 V3 V3 V1 V7 V8
600 600 600 300 2 2
mVrms mVrms mVrms mVrms Vrms Vrms
THD15, 16 = 1% THD15 = 1% THD16 = 1% THD16 = 1%; 00,02 Matrix; Stereo THD16 = 3%; 07, CC, Scart THD15 = 1%; 07, CC, Scart
*) The tone control is possible over the full functional range if 04, 18, Vol VLS 24
Semiconductor Group
29
TDA 6612-2
Characteristics (cont'd) Parameter Distortion Distortion Distortion Distortion Symbol Limit Values min. typ. 0.01 0.01 0.01 0.01 max. 0.1 0.1 0.1 0.1 % % % % Unit Test Condition
THD19 THD20 THD19 THD20
V3 = 250 mVrms V1 = 250 mVrms V3 = 250 mVrms;
03,15 Vol HP 21 V3 = 250 mVrms; 03,15 Vol HP 21
Analogous values are valid for feed in at pins 6, 7, 8; V7,8 = 600 Vrms; V6 = 250 mVrms Distortion Distortion Distortion
THD16 THD15 THD15
0.01 0.01 0.01
0.1 0.1 0.2
% % %
V1 = 250 mVrms; V3 = 250 mVrms V1 = 250 mVrms;
01,2F-02,2F Vol LSI 47 Vol LSr 47 V3 = 250 mVrms; 01,2F-02,2F Vol LSI 47 Vol LSr 47 V1 = 250 mVrms; 05,XX any sound V3 = 250 mVrms; 05,XX any sound
Distortion
THD15
0.01
0.2
%
Distortion
THD16
0.1
0.4
%
Distortion
THD15
0.1
0.4
%
Analogous values are valid for feed in at pins 6, 7, 8; V7,8 = 600 mVrms; V6 = 250 mVrms Distortion Distortion Distortion Distortion
THD10 THD9 THD10 THD9
0.01 0.01 0.01 0.01
0.1 0.1 0.1 0.1
% % % %
V3 = 250 mVrms V1 = 250 mVrms V6 = 250 mVrms;
07,C9,AM V6 = 250 mVrms; 07,C9,AM
Semiconductor Group
30
TDA 6612-2
Characteristics (cont'd) Parameter Symbol Limit Values min. Anti-phase cross talk Base width V16-15 Anti-phase cross talk Base width V
15-16
Unit
Test Condition
typ. 0.55 0.55
max.
0.5 0.5
V3 = 600 mVrms f I = 2 kHz; 00, 11
Base width V1 = 600 mVrms f I = 2 kHz; 00, 11 Base width
210 deg
Base width phase
16-15
150
180
V1 = 600 mVrms f = 2 kHz; 00, 11
Base width V3 = 600 mVrms f = 2 kHz; 00, 11 Base width
Base width phase
15-16
150
180
210
deg
Phase rotation quasi stereo Phase rotation quasi stereo Phase rotation quasi stereo Signal-to-noise ratio Signal-to-noise ratio Signal-to-noise ratio
16-15
0
10
40
deg
V3,1 = 600 mVrms f = 40 kHz; 00, 21
Quasi stereo V3,1 = 600 mVrms f = 700 kHz; 00, 21 Quasi stereo V3,1 = 600 mVrms f = 15 kHz; 00, 21 Quasi stereo
16-15
130
180
230
deg
16-15
- 30
10
0
deg
S/N16 S/N15 S/N16
85 85 60
94 94 70
dB dB dB
VN rms 20 Hz-20 kHz; V1 = 0.6 Vrms VN rms 20 Hz-20 kHz; V3 = 0.6 Vrms VN rms 20 Hz-20 kHz; V1 = 0.6 Vrms
01,27-02,27 Vol LSI 39-Vol LSr 39
Signal-to-noise ratio
S/N15
60
70
dB
VN rms 20 Hz-20 kHz; V3 = 0.6 Vrms
01,27-02,27 Vol LSI 39 - Vol LSr 39
Semiconductor Group
31
TDA 6612-2
Characteristics (cont'd) Parameter Symbol Limit Values min. Output noise voltage VN16 typ. 12 max. 33 Vrms Unit Test Condition
VN rms 20 Hz-20 kHz;
01,00-02,00 Vol LSI 0-Vol LSr 0
Output noise voltage VN15
12
33
Vrms
VN rms 20 Hz-20 kHz;
01,00-02,00 Vol LSI 0-Vol LSr 0
Signal-to-noise ratio Signal-to-noise ratio Signal-to-noise ratio
S/N20 S/N19 S/N20
85 85 65
94 94 70
dB dB dB
VN rms 20 Hz-20 kHz; V1 = 0.6 Vrms VN rms 20 Hz-20 kHz; V3 = 0.6 Vrms VN rms 20 Hz-20 kHz; V1 = 0.6 Vrms
03, 10, Vol HP 16
Signal-to-noise ratio
S/N19
65
70
dB
VN rms 20 Hz-20 kHz; V3 = 0.6 Vrms
03, 10, Vol HP 16
Output noise voltage VN20 Output noise voltage VN19 Signal-to-noise ratio Signal-to-noise ratio S/N9 S/N10 90 90
12 12 97 97
33 33
Vrms Vrms dB dB
VN rms 20 Hz-20 kHz;
03, 00, VolHP 0
VN rms 20 Hz-20 kHz;
03, 00, Vol HP 0
VN rms 20 Hz-20 kHz; V1 = 0.6 Vrms VN rms 20 Hz-20 kHz; V1 = 0.6 Vrms
Semiconductor Group
32
TDA 6612-2
Characteristics (cont'd) Parameter DC/pop 1 Bit DC/pop 1 Bit DC/pop 1 Bit DC/pop 1 Bit DC/pop 1 Bit DC/pop 1 Bit DC/pop 1 Bit DC/pop 1 Bit Design-Related Data Input resistance Input resistance Input resistance Input resistance Input resistance Output resistance Output resistance Output resistance Output resistance Output resistance Output resistance R7 R8 R6 R3 R1 R 19 R 20 R 15 R 16 R9 R 10 35 35 20 22 22 70 70 70 70 70 70 k k k k k Symbol V16 V15 V16 V15 V16 V15 V19 V20 Limit Values min. typ. max. 4 4 4 4 2 2 4 4 mV mV mV mV mV mV mV mV 01, X-01, X 1 Vol LSI X - Vol LSI (X 1) 02, X-02, X 1 Vol LSr X - Vol LSr (X 1) 04, X-04, X 1 Vol VLS X - Vol VLS (X 1) 04, X-04, X 1 Vol VLS X - Vol VLS (X 1) 05, X-05, X 1 ToneX - Tone (X 1) 05, X-05, X 1 ToneX - Tone (X 1) 03, X-03, X 1 Vol HP X - Vol HP (X 1) 03, X-03, X 1 Vol HP X - Vol HP (X 1) Unit Test Condition
Semiconductor Group
33
TDA 6612-2
Characteristics (cont'd) Parameter Symbol Limit Values min. ID-Signal Decoder Gain filter OP-amplif. Max. input voltage VCO-voltage PLL VCO-voltage PLL VCO-voltage PLL VCO-voltage PLL V5 V5 V27 V27 V27 V27 1.3 13 600 1.3 2 3 4 4.7 14 15 dB mVpp V V V V typ. max. Unit Test Condition Test Circuit
VIF = 80 mVpp
Function f 24 = 14.6 kHz; V24 = 2.5 V f 24 = 15.625 kHz; V24 = 2.5 V f 24 = 16.6 kHz; V24 = 2.5 V f 24 = 58.4 kHz; V24 = 2.5 V 00,08, H-pulse f 24 = 66.4 kHz; V24 = 2.5 V 00,08, H-pulse 00,08 - 04.81 H-pulse; quartz cont. function
1 2 2 2 2 2
VCO-voltage PLL
V27
4.7
V
2
VCO-voltage PLL
V27
2
3
4
V
4
V Filter
gain
( V 25 - V 25 * ) 2 + ( V 26 - V 26 * ) = ----------------------------------------------------------------------------------V25 or V26 when V5 = 0 V5 V25* or V26* when V5 = 100 mVpp; m = 50%
VKT Filter 3.4 6.8 V f 5 = pilot signal dual; I2C-talk: dual f 5 = pilot signal stereo; I2C-talk: stereo 2
2
ID-filter gain
ID-filter gain
VKT Filter
3.4
6.8
V
2
V5 test = V 25 (V5 = 0) V25; V26 test = V 26 (V5 = 0) V26
Semiconductor Group
34
TDA 6612-2
Characteristics (cont'd) Parameter Detection threshold Detection threshold Detection threshold Detection threshold Mono threshold Mono threshold Mono threshold Mono threshold Symbol V25 - V25 V26 - V26 V25 - V25 V26 - V26 900 900 900 900 0 0 0 0 1/4 Response of detection t det 1/4 1/2 100 100 100 100 1/2 Limit Values min. typ. max. mV mV mV mV mV mV mV mV I2C-talk: stereo or dual I2C-talk: stereo or dual I2C-talk: stereo or dual I2C-talk: stereo or dual I2C-talk: mono I2C-talk: mono I2C-talk: mono I2C-talk: mono I2C-talk: stereo or dual; V25 = 1 V I2C-talk: stereo or dual; V26 = 1 V Unit Test Condition Test Circuit 3 3 3 3 3 3 3 3 3 3
Response of detection t det
t MPX t MPX
Semiconductor Group
35
TDA 6612-2
Characteristics (cont'd) Parameter Switching threshold f REF-input Switching threshold f REF-input Amplitude crystal oscillator Ext. 1- or 4 MHzclock signal Crystal current Multiplexer clock Multiplexer clock Multiplexer clock Design-Related Data Filter output resistance f REF-input resistance Input impedance crystal oscillator Crystal serial resistance Crystal serial resistance Spurious wave spacing (fundamental wave to harmonic and nonharmonic signals) R 25,26 R 24 Z 24 110 800 - 600 - 500 - 400 100 300 20 k dB Symbol VH in L VH in L V24 V24 0 3.5 0.3 2 0.29 0.35 2.17 4.34 8.68 0.42 Limit Values min. typ. max. 1.5 V21 V V Vpp Vpp mArms RC = 40 s 09,08, MPX = 2 s s 09,48, MPX = 4 s s 09,88, MPX = 8 s f0 = 4.00000 MHz Serial resonance Unit Test Condition Test Circuit 2 2 4 3
IC
t MPX t MPX t MPX
RC1 RC3
Ptot = 1 W,
fundamental
Ptot = 1 W
3rd harmonic
Ptot = 1 W f < 15 MHz
Semiconductor Group
36
TDA 6612-2
Characteristics (cont'd) Parameter I2C Bus (SCL, SDA) SCL, SDA edges Rise time Fall time Shift register clock pulse SCL Frequency H-pulse width L-pulse width Start Set-up time Hold time Stop Set-up time Bus free time Data transfer Set-up time Hold time Input SCL, SDA Input voltage Input current Output SDA (Open collector) Output voltage VQH VQL 5.4 0.4 V V RL = 2.5 k IQL = 3 mA tR tF 1 300 s ns Symbol Limit Values min. typ. max. Unit Test Condition
f SCL t HIGH t LOW t SUSTA t HDSTA t SUDAT t HDDAT t SUDAT t HDDAT VQH VQL VQH VQL
0 4 4 4 4 1 1 1 600 3
100
kHz s s s s s s s ns
5.5 1.5 50 100
V V A A
Semiconductor Group
37
TDA 6612-2
Test Circuit 1 Semiconductor Group 38
TDA 6612-2
Test Circuit 2 Semiconductor Group 39
TDA 6612-2
Test Circuit 3 Semiconductor Group 40
TDA 6612-2
Test Circuit 4 Semiconductor Group 41
TDA 6612-2
Application Circuit 1 Semiconductor Group 42
TDA 6612-2
Application Circuit 2 Semiconductor Group 43
TDA 6612-2
Application Circuit 3 Semiconductor Group 44
TDA 6612-2
I2C Bus Timing Diagram
tSUSTA tHDSTA tHIGH tLOW tSUDAT tHDDAT tSUSTO tBUF tF tR
Setup time (start) Hold time (start) H-pulse width (clock) L-pulse width (clock) Setup time (data transfer) Hold time (data transfer) Setup time (stop) Bus free time Fall time Rise time
All times referred to VIH and VIL values.
Semiconductor Group
45
TDA 6612-2
Package Outlines Plastic Package, P-DIP-28-1 (Plastic Dual In-Line Package)
Semiconductor Group
46
GPD05037
TDA 6612-2
Plastic Package, P-DSO-28.350 (SMD) (Plastic Dual Small Outline)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Semiconductor Group 47
Dimensions in mm
GPS05182

▲Up To Search▲

Price & Availability of TDA6612-2

	To Download TDA6612-2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .