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IRLR/U2905PbF
l l l l l l l l
PD- 95084A
Logic-Level Gate Drive Ultra Low On-Resistance Surface Mount (IRLR2905) Straight Lead (IRLU2905) Advanced Process Technology Fast Switching Fully Avalanche Rated Lead-Free
HEXFET(R) Power MOSFET
D
VDSS = 55V RDS(on) = 0.027
G S
ID = 42A
Description
Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. The D-PAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 watts are possible in typical surface mount applications.
D-Pak TO-252AA I-Pak TO-251AA
Absolute Maximum Ratings
Parameter
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds
Max.
42 30 160 110 0.71 16 210 25 11 5.0 -55 to + 175 300 (1.6mm from case )
Units
A W W/C V mJ A mJ V/ns C
Thermal Resistance
Parameter
RJC RJA RJA Junction-to-Case Case-to-Ambient (PCB mount)** Junction-to-Ambient
Typ.
--- --- ---
Max.
1.4 50 110
Units
C/W
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** When mounted on 1" square PCB (FR-4 or G-10 Material ) . For recommended footprint and soldering techniques refer to application note #AN-994
1
12/7/04
IRLR/U2905PbF
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
V(BR)DSS
V(BR)DSS/TJ
Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance
RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss
Min. Typ. Max. Units Conditions 55 --- --- V VGS = 0V, ID = 250A --- 0.070 --- V/C Reference to 25C, I D = 1mA --- --- 0.027 VGS = 10V, ID = 25A --- --- 0.030 W VGS = 5.0V, ID = 25A --- --- 0.040 VGS = 4.0V, ID = 21A 1.0 --- 2.0 V VDS = VGS, ID = 250A 21 --- --- S VDS = 25V, ID = 25A --- --- 25 VDS = 55V, VGS = 0V A --- --- 250 VDS = 44V, VGS = 0V, TJ = 150C --- --- 100 VGS = 16V nA --- --- -100 VGS = -16V --- --- 48 ID = 25A --- --- 8.6 nC VDS = 44V --- --- 25 VGS = 5.0V, See Fig. 6 and 13 --- 11 --- VDD = 28V --- 84 --- ID = 25A ns --- 26 --- RG = 3.4, VGS = 5.0V --- 15 --- RD = 1.1, See Fig. 10 Between lead, 4.5 nH 6mm (0.25in.) G from package --- 7.5 --- and center of die contact --- 1700 --- VGS = 0V --- 400 --- pF VDS = 25V --- 150 --- = 1.0MHz, See Fig. 5
D
S
Source-Drain Ratings and Characteristics
IS
ISM
VSD trr Qrr ton Notes:
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol --- --- 42 showing the A G integral reverse --- --- 160 S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 25A, VGS = 0V --- 80 120 ns TJ = 25C, IF = 25A --- 210 320 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
max. junction temperature. ( See fig. 11 ) VDD = 25V, starting TJ = 25C, L =470H RG = 25, IAS = 25A. (See Figure 12) ISD 25A, di/dt 270A/s, VDD V(BR)DSS, TJ 175C Pulse width 300s; duty cycle 2%.
Repetitive rating; pulse width limited by
Caculated continuous current based on maximum allowable This is applied for I-PAK, LS of D-PAK is measured between
lead and center of die contact. junction temperature; Package limitation current = 20A.
Uses IRLZ44N data and test conditions.
2
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IRLR/U2905PbF
1000
VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP
1000
ID , Drain-to-Source Current (A)
100
ID , Drain-to-Source Current (A)
VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP
100
10
10
2.5V
2.5V 20s PULSE WIDTH T J = 25C
1 10
1 0.1
100
A
1 0.1
20s PULSE WIDTH T J = 175C
1 10
100
A
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
3.0
R DS(on) , Drain-to-Source On Resistance (Normalized)
I D = 41A
I D , Drain-to-Source Current (A)
2.5
TJ = 25C
100
2.0
TJ = 175C
1.5
10
1.0
0.5
1 2.0 3.0 4.0 5.0
V DS= 25V 20s PULSE WIDTH
6.0 7.0 8.0 9.0
A
0.0 -60 -40 -20 0 20 40 60
VGS = 10V
80 100 120 140 160 180
A
VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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3
IRLR/U2905PbF
2800
2400
Ciss
VGS , Gate-to-Source Voltage (V)
V GS = 0V, f = 1MHz C iss = Cgs + C gd , Cds SHORTED C rss = C gd C oss = Cds + C gd
15
I D = 25A V DS = 44V V DS = 28V
12
C, Capacitance (pF)
2000
1600
9
1200
Coss
6
800
Crss
400
3
0 1 10 100
A
0 0 10 20 30
FOR TEST CIRCUIT SEE FIGURE 13
40 50 60 70
A
VDS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000
1000
ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY R DS(on)
I D , Drain Current (A)
100
10s
100
100s
TJ = 175C TJ = 25C
10
1ms
10 0.4 0.8 1.2 1.6
VGS = 0V
2.0
A
1 1
TC = 25C TJ = 175C Single Pulse
10
10ms
2.4
100
A
VSD , Source-to-Drain Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRLR/U2905PbF
50
LIMITED BY PACKAGE
40
V DS VGS RG 5V
Pulse Width 1 s Duty Factor 0.1 %
RD
D.U.T.
+
ID , Drain Current (A)
-VDD
30
20
Fig 10a. Switching Time Test Circuit
10
VDS 90%
0
25
50
75
100
125
150
175
TC , Case Temperature ( C)
Fig 9. Maximum Drain Current Vs. Case Temperature
10% VGS
td(on) tr t d(off) tf
Fig 10b. Switching Time Waveforms
10
Thermal Response (Z thJC )
1
D = 0.50 0.20 0.10 PDM SINGLE PULSE (THERMAL RESPONSE) t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1
0.1
0.05 0.02 0.01
0.01 0.00001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRLR/U2905PbF
E AS , Single Pulse Avalanche Energy (mJ)
500
TOP
400
15V
BOTTOM
ID 10A 17A 25A
VDS
L
DRIVER
300
RG
20V
D.U.T
IAS tp
+ V - DD
A
200
0.01
Fig 12a. Unclamped Inductive Test Circuit
100
0
VDD = 25V
25 50 75 100 125 150
A
175
V(BR)DSS tp
Starting TJ , Junction Temperature (C)
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
50K
QG
12V
.2F .3F
10 V
QGS
QGD
VGS
3mA
D.U.T.
+ V - DS
VG
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
6
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IRLR/U2905PbF
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS
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7
IRLR/U2905PbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFR120 WITH AS S EMBLY LOT CODE 1234 AS S EMBLED ON WW 16, 1999 IN THE AS S EMBLY LINE "A" Note: "P" in as sembly line pos ition indicates "Lead-Free" INTERNATIONAL RECTIFIER LOGO AS S EMBLY LOT CODE PART NUMBER
IRFU120 12 916A 34
DAT E CODE YEAR 9 = 1999 WEEK 16 LINE A
OR
INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER
IRFU120 12 34
DATE CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) YEAR 9 = 1999 WEEK 16 A = AS S EMBLY S ITE CODE
8
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IRLR/U2905PbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFU120 WIT H AS S EMBLY LOT CODE 5678 AS S EMBLED ON WW 19, 1999 IN T HE AS S EMBLY LINE "A" Note: "P" in assembly line position indicates "Lead-Free" INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER
IRF U120 919A 56 78
DAT E CODE YEAR 9 = 1999 WEEK 19 LINE A
OR
INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER
IRFU120 56 78
DAT E CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) YEAR 9 = 1999 WEEK 19 A = AS S EMBLY S IT E CODE
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9
IRLR/U2905PbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR TRR TRL
16.3 ( .641 ) 15.7 ( .619 )
16.3 ( .641 ) 15.7 ( .619 )
12.1 ( .476 ) 11.9 ( .469 )
FEED DIRECTION
8.1 ( .318 ) 7.9 ( .312 )
FEED DIRECTION
NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. Data and specifications subject to change without notice. 12/04
10
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