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| DRAM MODULE KMM5321204C2W/C2WG 1Mx32 DRAM SIMM (1MX16 Base) Revision 0.0 November 1997 -1- Rev. 0.0 (Nov. 1997) DRAM MODULE Revision History Version 0.0 (November 1997) * Changed module PCB from 6-Layer to 4-Layer. KMM5321204C2W/C2WG * Changed Module Part No. from KMM5321200CW/CWG to KMM5321200C2W/C2WG caused by PCB revision . -2- Rev. 0.0 (Nov. 1997) DRAM MODULE KMM5321204C2W/C2WG KMM5321204C2W/C2WG Fast Page Mode with Extended Data Out 1M x 32 DRAM SIMM using 1Mx16 , 1K Refresh, 5V GENERAL DESCRIPTION The Samsung KMM5321204C2W is a 1Mx32bits Dynamic RAM high density memory module. The Samsung KMM5321204C2W consists of two CMOS 1Mx16bits DRAMs in 42-pin SOJ package mounted on a 72-pin glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The KMM5321204C2W is a Single In-line Memory Module with edge connections and is intended for mounting into 72 pin edge connector sockets. FEATURES * Part Identification - KMM5321204C2W(1024 cycles/16ms Ref, SOJ, Solder) - KMM5321204C2WG(1024 cycles/16ms Ref, SOJ, Gold) * Fast Page Mode with Extended Data Out * CAS-before-RAS refresh capability * RAS-only and hidden refresh capability * TTL compatible inputs and outputs * Single +5V 10% power supply * JEDEC standard PDPin & pinout * PCB : Height(750mil), single sided component PERFORMANCE RANGE Speed -5 -6 tRAC 50ns 60ns tCAC 15ns 17ns tRC 90ns 110ns tHPC 25ns 30ns PIN CONFIGURATIONS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Symbol VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 Vcc NC A0 A1 A2 A3 A4 A5 A6 Res(A10) DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 A7 Res(A11) Vcc A8 A9 Res(RAS1) RAS0 NC NC Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Symbol NC NC Vss CAS0 CAS2 CAS3 CAS1 RAS0 Res(RAS1) NC W NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 Vcc DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC Vss PIN NAMES Pin Name A0 - A9 DQ0 - DQ31 W RAS0 CAS0 - CAS3 PD1 -PD4 Vcc Vss NC Res Function Address Inputs Data In/Out Read/Write Enable Row Address Strobe Column Address Strobe Presence Detect Power(+5V) Ground No Connection Reserved Pin PRESENCE DETECT PINS (Optional) Pin PD1 PD2 PD3 PD4 50NS Vss Vss Vss Vss 60NS Vss Vss NC NC * Pin connection changing available SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. -3- Rev. 0.0 (Nov. 1997) DRAM MODULE FUNCTIONAL BLOCK DIAGRAM KMM5321204C2W/C2WG RAS0 RAS CAS0 LCAS U0 CAS1 UCAS OE W A0-A9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 RAS CAS2 LCAS CAS3 UCAS U1 OE W A0-A9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 W A0-A9 Vcc .1 or .22uF Capacitor for each DRAM Vss To all DRAMs -4- Rev. 0.0 (Nov. 1997) DRAM MODULE ABSOLUTE MAXIMUM RATINGS * Item Voltage on any pin relative to V SS Voltage on V CC supply relative to V SS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN, VOUT VCC Tstg Pd IOS KMM5321204C2W/C2WG Rating -1 to +7.0 -1 to +7.0 -55 to +150 2 50 Unit V V C W mA * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for in tended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to V SS, TA = 0 to 70C) Item Supply Voltage Ground Input High Voltage Input Low Voltage *1 : VCC+2.0V/20ns, Pulse width is measured at VCC. *2 : -2.0V/ 20ns, Pulse width is measured at VSS. Symbol VCC VSS VIH VIL Min 4.5 0 2.4 -1.0 *2 Typ 5.0 0 Max 5.5 0 VCC+1*1 0.8 Unit V V V V DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) Symbol ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 II(L) IO(L) VOH VOL ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 II(L) IO(L) VOH VOL Speed -5 -6 Dont care -5 -6 -5 -6 Dont care -5 -6 Dont care Dont care KMM5321204C2W/C2WG Min - Max 300 280 4 300 280 240 220 2 300 280 10 5 0.4 Unit mA mA mA mA mA mA mA mA mA mA uA uA V V -10 -5 2.4 - : Operating Current * ( RAS, CAS, Address cycling @ tRC=min) : Standby Current ( RAS=CAS=W=VIH) : RAS Only Refresh Current * ( CAS=VIH, RAS cycling @ tRC=min) : EDO Mode Current * ( RAS=VIL, CAS cycling : tHPC=min) : Standby Current ( RAS=CAS=W=Vcc-0.2V) : CAS-Before-RAS Refresh Current * ( RAS and CAS cycling @ tRC=min) : Input Leakage Current (Any input 0 VINVcc+0.5V, all other pins not under test=0 V) : Output Leakage Current(Data Out is disabled, 0V VOUTVcc) : Output High Voltage Level (I OH = -5mA) : Output Low Voltage Level (I OL = 4.2mA) * NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In I CC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one EDO mode cycle, tHPC. -5- Rev. 0.0 (Nov. 1997) DRAM MODULE CAPACITANCE (TA = 25C, VCC=5V, f = 1MHz) Item Input capacitance[A0-A9] Input capacitance[ W] Input capacitance[ RAS0] Input capacitance[ CAS0 - CAS3] Input/Output capacitance[DQ0-31] Symbol CIN1 CIN2 CIN3 CIN4 CDQ1 Min - KMM5321204C2W/C2WG Max 30 30 25 20 20 Unit pF pF pF pF pF AC CHARACTERISTICS (0CTA70C, VCC=5.0V10%. See notes 1,2.) Test condition : Vih/Vil=2.4/0.8V, V oh/Vol=2.0/0.8V, Output loading CL=100pF Parameter Random read or write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay from CAS Transition time(rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold time referenced to CAS Read command hold time referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in set-up time Data-in hold time Refresh period Write command set-up time CAS setup time( CAS-before-RAS refresh) CAS hold time( CAS-before-RAS refresh) RAS precharge to CAS hold time Access time from CAS precharge Symbol -5 Min 90 50 15 25 3 3 2 30 50 13 40 8 20 15 5 0 10 0 8 25 0 0 0 10 10 13 13 0 8 16 0 5 10 5 30 0 5 10 5 35 10K 37 25 10K 13 50 3 3 2 40 60 17 50 10 20 15 5 0 10 0 10 30 0 0 0 10 10 15 10 0 10 16 10K 45 30 10K 15 50 Max Min 110 60 17 30 -6 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns 3 7 9 9 8 8 13 4 10 3,4,10 3,4,5 3,10 3 6,11,12 2 Note tRC tRAC tCAC tAA tCLZ tCEZ tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS tDH tREF tWCS tCSR tCHR tRPC tCPA -6- Rev. 0.0 (Nov. 1997) DRAM MODULE Test condition : Vih/Vil=2.4/0.8V, V oh/Vol=2.0/0.8V, Output loading CL=100pF Parameter Hyper page mode cycle time CAS precharge time(Hyper page cycle) RAS pulse width(Hyper page cycle) RAS hold time from CAS precharge W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) Output data hold time Output buffer turn off delay from RAS Output buffer turn off delay from W W to data delay W pulse width (Hyper Page Cycle) Symbol -5 Min 25 8 50 30 10 10 5 3 3 15 5 13 13 200K Max KMM5321204C2W/C2WG AC CHARACTERISTICS (0CTA70C, VCC=5.0V10%. See notes 1,2.) -6 Min 30 10 60 35 10 10 5 3 3 15 5 15 15 200K Max Unit ns ns ns ns ns ns ns ns ns ns ns 6,11,12 6,11 Note 13 tHPC tCP tRASP tRHCP tWRP tWRH tDOH tREZ tWEZ tWED tWPE NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. VIH(min) and V IL(max) are reference levels for measuring timing of input signals. Transition times are measured between V IH(min) and V IL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCDtRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH or VOL. 7. tWCS is non-restrictive operating parameter. It is included in the data sheet as electrical characteristic s only. If tWCStWCS(min), the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameter are referenced to the CAS leading edge in early write cycles and to the W leading edge in read-write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 11. tCEZ(max), tREZ(max), tWEZ(max) and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced to output voltage level. 12. If RAS goes to high before CAS high going, the open circuit condtion of the output is achieved by CAS high going. If CAS goes to high before RAS high going, the open circuit condition of the output is achieved by RAS high going. 13. tASCtCP min -7- Rev. 0.0 (Nov. 1997) DRAM MODULE READ CYCLE KMM5321204C2W/C2WG tRC tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tRAD tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tRCS W VIH VIL - tRCH tRRH tAA tCEZ tRAC OPEN tCAC tCLZ tREZ DATA-OUT tWEZ DQ VOH VOL - Dont care Undefined -8- Rev. 0.0 (Nov. 1997) DRAM MODULE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN KMM5321204C2W/C2WG tRC tRAS RAS VIH VIL - tRP tCSH tCRP CAS VIH VIL - tRCD tRAD tRSH tCAS tCRP tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL tWCS W VIH VIL - tWCH tWP tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined -9- Rev. 0.0 (Nov. 1997) DRAM MODULE HYPER PAGE READ CYCLE KMM5321204C2W/C2WG tRASP RAS VIH VIL o tRP tCSH tCRP CAS VIH VIL - tRHCP tHPC tCP tHPC tCAS tCP tHPC tCAS tCP tCAS tRCD tCAS tRAD tASR A VIH VIL - tRAH tASC ROW ADDR tCAH tASC tCAH tASC tCAH COLUMN ADDR tASC tCAH tREZ COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS tRRH tRCS W VIH VIL - tRCH tCPA tCAC tAA tCAC tAA tCPA tAA tCAC tRAC tDOH VALID DATA-OUT tCAC tAA tCPA tDOH VALID DATA-OUT tDOH VALID DATA-OUT VALID DATA-OUT DQ VOH VOL - tCLZ Dont care Undefined - 10 - Rev. 0.0 (Nov. 1997) DRAM MODULE HYPER PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN KMM5321204C2W/C2WG tRASP RAS VIH VIL o tRP tRHCP tCRP CAS VIH VIL - tHPC tRCD tCAS tRAD tCSH tASC tCP tCAS o tHPC tCP tRSH tCAS tASR A VIH VIL - tRAH tCAH tASC tCAH o tASC tCAH ROW ADDR. COLUMN ADDRESS COLUMN ADDRESS o COLUMN ADDRESS tWCS W VIH VIL - tWCH tWCS tWCH tWP tCWL o tWCS tWCH tWP tCWL tRWL tWP tCWL tDS DQ VIH VIL - tDH VALID DATA-IN tDS tDH o VALID DATA-IN tDS tDH o VALID DATA-IN Dont care Undefined - 11 - Rev. 0.0 (Nov. 1997) DRAM MODULE RAS - ONLY REFRESH CYCLE* NOTE : W, OE, DIN = Don't care DOUT = OPEN tRC RAS VIH VIL - KMM5321204C2W/C2WG tRP tRAS tCRP tRPC tCRP CAS VIH VIL - tASR A VIH VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE , A = Don't care tRP RAS VIH VIL - tRC tRAS tRP tRPC tCP tCSR tCHR tRPC CAS VIH VIL - tWRP W VIH VIL - tWRH tCEZ DQ VOH VOL - OPEN Dont care Undefined * In RAS-only refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off. - 12 - Rev. 0.0 (Nov. 1997) DRAM MODULE HIDDEN REFRESH CYCLE ( READ ) KMM5321204C2W/C2WG tRC RAS VIH VIL - tRP tRC tRAS tRP tRAS tCRP CAS VIH VIL - tRCD tRSH tCHR tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tRCS W VIH VIL - tRRH tWRH tWRP tAA tCAC tCLZ tRAC DQ VOH VOL - tCEZ tREZ tWEZ DATA-OUT OPEN Dont care Undefined - 13 - Rev. 0.0 (Nov. 1997) DRAM MODULE HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN KMM5321204C2W/C2WG tRC RAS VIH VIL - tRP tRC tRAS tRP tRAS tCRP tRCD tRSH tCHR CAS VIH VIL - tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tWCS W VIH VIL - tWRP tWCH tWP tWRH tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined - 14 - Rev. 0.0 (Nov. 1997) DRAM MODULE CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE KMM5321204C2W/C2WG tRP RAS VIH VIL VIH VIL - tRAS tCPT tCHR tRSH tCAS tRAL tASC tCAH tCSR CAS A VIH VIL - COLUMN ADDRESS READ CYCLE W VIH VIL - tWRP tWRH tAA tRCS tCAC tRRH tRCH tWEZ tCLZ DATA-OUT tCEZ tREZ DQ VOH VOL - WRITE CYCLE W VIH VIL - tWRP tWRH tWCS tRWL tCWL tWCH tWP tDS tDH DATA-IN DQ VIH VIL - Dont care Undefined NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules. - 15 - Rev. 0.0 (Nov. 1997) DRAM MODULE CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Dont care KMM5321204C2W/C2WG tRP RAS VIH VIL - tRASS tRPS tRPC tCP tCSR tCHS tRPC CAS VIH VIL - tCEZ DQ VOH VOL - OPEN W VIH VIL - tWRP tWRH TEST MODE IN CYCLE NOTE : OE , A = Dont care tRC tRAS tRPC tCP CAS VIH VIL - tRP RAS VIH VIL - tRP tRPC tCSR tCHR tWTS W VIH VIL - tWTH tCEZ DQ VOH VOL - OPEN Dont care Undefined - 16 - Rev. 0.0 (Nov. 1997) DRAM MODULE PACKAGE DIMENSIONS KMM5321204C2W/C2WG Units : Inches (millimeters) 4.250(107.95) 3.984(101.19) .133(3.38) R.062(1.57) .125 DIA.002(3.18.051) .400(10.16) .750(19.05) .250(6.35) .080(2.03) .250(6.35) .250(6.35) 3.750(95.25) R.062.004(R1.57.10) .125(3.17) MIN ( Front view ) ( Back view ) Gold & Solder Plating Lead .200(5.08) MAX .010(.25)MAX .100(2.54) MIN .050(1.27) .041.004(1.04.10) .054(1.37) .047(1.19) Tolerances : .005(.13) unless otherwise specified NOTE : The used device is 1Mx16 DRAM DRAM Part No. : KMM5321204C2W/C2WG -- KM416C1204CJ (400 mil) Revision History Rev 0.0 : Nov. 1997 - 17 - Rev. 0.0 (Nov. 1997) |
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