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APA0710/0711
1.1W Mono Low-Voltage Audio Power Amplifier
Features * * * * * *
Operating Voltage : 2.6V-5.5V APA0710 Compatible with TPA711 APA0711 Compatible with TPA751 Bridge-Tied Load (BTL) or Single-Ended (SE) Modes Operation (for APA0710 only) Supply Current - IDD=1.3mA at VDD=5V ,BTL mode - IDD=0.9mA at VDD=3.3V ,BTL mode Low Shutdown Current - IDD=0.1A Low Distortion - 630mW, at VDD=5V, BTL, RL=8 THD+N=0.15% - 280mW, at VDD=3.3V, BTL, RL=8 THD+N=0.15%
General Description
The APA0710 is a bridged-tied load (BTL) or singledended (SE) audio power amplifier developed especially for low-voltage applications where internal speakers and external earphone operation are required. The APA0711 is a only BTL audio power amplifier developed especially for low-voltage applications where internal speakers are required. Operating with a 5V supply, the APA0710/1 can deliver 1.1W of continuous power into a BTL 8 load at 10% THD+N throughout voice band frequencies. Although this device is characterized out to 20kHz,its operation is optimized for narrow band applications such as wireless communications. The BTL configuration eliminates the need for external coupling capacitors on the output in most applications, which is particularly important for small battery-powered equipment. A unique feature of the APA0710 is that it allows the amplifier to switch from BTL to SE on the fly when an earphone drive is required. This eliminates complicated mechanical switching or auxiliary devices just to drive the external load. This device features a shutdown mode for power-sensitive applications with special depop circuitry to eliminate speaker noise when exiting shutdown mode. The APA0710/1 are available in an 8-pin SOP and 8-pin MSOP-P with enhanced thermal pad.
*
Output Power at 1% THD+N - 900mW, at VDD=5V, BTL, RL=8 - 400mW, at VDD=3.3V, BTL, RL=8 at 10% THD+N -1.1W at VDD=5V, BTL, RL=8 -480mW at VDD=3.3V, BTL, RL=8
* * * *
Depop Circuitry Integrated Thermal Shutdown Protection and Over Current Protection Circuitry High supply voltage ripple rejection Surface-Mount Packaging - 8 pin MSOP-P (with enhanced thermal pad) power package available - SOP-8 package
Applications * * * *
Mobil Phones PDAs Digital Camera Portable Electronic Devices
*
Lead Free Available (RoHS Compliant)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 1 www.anpec.com.tw
APA0710/0711
Pin Description
APA0710
Shutdown Bypass SE/BTL IN
1 8
APA0711
VOGND VDD VO+ Shutdown Bypass IN+ IN1 8
VOGND VDD VO+
2
7
2
7
3
6
3
6
4
5
4
5
SOP-8 APA0710
Shutdown Bypass SE/BTL IN
1 8
SOP-8 APA0711
VOGND VDD VO+ Shutdown Bypass IN+ IN1 8
VOGND VDD VO+
2
7
2
7
3
6
3
6
4
5
4
5
MSOP-8-P NC = No internal connection
MSOP-8-P
= Thermal Pad (connected to GND plane for better heat dissipation)
Ordering and Marking Information
APA0710/1 Lead Free Code Handling Code Temp. Range Package Code APA0710/1 K : APA0710/1 XA : APA0710/1 XXXXX A0710/1 XXX XX Package Code K : SOP-8 XA : MSOP-8-P Temp. Range I : -40 to 85 C Handling Code TR : Tape & Reel Lead Free Code L : Lead Free Device Blank : Original Device XXXXX - Date Code XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature.
Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Oct., 2005
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APA0710/0711
Block Diagram
RF Audio Input VDD RI VDD/2 4 IN Bypass
_
6
VDD Cs
Vo+ CI 2
+
5 CC
CB
_
Vo+
8
From System Control From HP Jack
1 3
Shutdown SE/BTL Bias Control GND
7
APA0710
RF Au d i o In p u t VDD RI 4 CI 3 2 CB IN IN + Bypass VDD /2 6
VDD Cs
_ +
Vo+ 5
_
Vo8
+
From S ys te m C o n t r o l 1 Shutdown Bias C o n trol GND 7
APA0711
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APA0710/0711
Absolute Maximum Ratings
(Over operating free-air temperature range unless otherwise noted.)
Symbol VDD VIN TA TJ TSTG TS VESD PD
Note: 1.APA0710/1 integrated internal thermal shutdown protection when junction temperature ramp up to 170C 2.Human body model: C=100pF, R=1500, 3 positives pulses plus 3 negative pulses 3.Machine model: C=200pF, L=0.5F, 3 positive pulses plus 3 negative pulses
Parameter Supply Voltage Input Voltage Range, Shutdown, SE/BTL Operating Ambient Temperature Range Maximum Junction Temperature Storage Temperature Range Soldering Temperature, 10 seconds Electrostatic Discharge Power Dissipation
Rating -0.3 to 6 -0.3 to VDD+0.3 -40 to 85 Internally Limited* -65 to +150 260 -2000 to 2000*
2 1
Unit V V C C C C V W
Internally Limited
Recommended Operating Conditions
Symbol VDD VIH VIL Parameter Supply Voltage High-Level Voltage Low-Level Voltage Shutdown, Shutdown SE/BTL Shutdown, Shutdown SE/BTL Test Conditions Min. 2.6 2.2 0.9VDD 0.4 0.9VDD-1 Max. 5.5 Unit V V V
Thermal Characteristics
Symbol RTHJA Parameter Thermal Resistance from Junction to Ambient in Free Air MSOP-8-P* SOP-8 50 160 C/W Value Unit
* 3.42in 2 printed circuit board with 20z trace and copper through 6 vias of 12mil diameter vias. The thermal pad on the MSOP-8-P package with solder on the printed circuit board.
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APA0710/0711
Electrical Characteristics
Electrical Characteristics at Specified Free - Air Temperature
VDD = 3.3V, TA = 25C (unless otherwise noted)
Symbol VOO IDD IDD(SD)
Parameter Output Offset Voltage Supply Current Supply Current, Shutdown Mode
Test Conditions RL = 8, R F = 10k BTL mode, RF = 10k SE mode, RF = 10k RF = 10k Shutdown, VI = V DD
APA0710/1 Min. Typ. Max. 20 0.9 0.55 0.1 1.8 1.1 2 1 1 1 1 1 1 400 40 0.15 20 2 74 61 28 380
Unit mV mA A
|IH|
Shutdown, VI = V DD SE/BTL, VI = VDD Shutdown, VI = 0V
A
|IL|
Shutdown, VI = 0V SE/BTL, VI = 0V
A
Operating characteristic, VDD = 3.3V, T A = 25C, RL = 8 PO THD+N Bom B1 PSRR Vn T WU Output Power (Note 1) THD = 1%, BTL mode, RL = 8 THD = 1%, SE mode, RL = 32 Total Harmonic Distortion PO = 280mW, BTL mode, R L = 8 Plus Noise (Note 1) Maximum Output Power Gain = 2, THD+N = 2% Bandwidth Unity-Gain Bandwidth Open Loop Power Supply Rejection Ratio (Note1) Noise Output Voltage Wake-up time CB = 1F, BTL mode, RL = 8 CB = 1F, SE mode, RL = 8 Gain = 1, CB = 0.1F CB = 1F mW % kHz MHz dB V(rms) ms
VDD= 5V, TA = 25C (unless otherwise noted)
Symbol VOO IDD IDD(SD)
Parameter Output Offset Voltage Supply Current Supply Current , Shutdown Mode
Test Conditions RL = 8, R F = 10k BTL mode, RF = 10k SE mode, RF = 10k RF = 10k
APA0710/1 Min. Typ. Max. 20 1.3 0.75 0.1 2.6 1.5 2
Unit mV mA A
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APA0710/0711
Electrical Characteristics(Cont.)
Electrical Characteristics at Specified Free - Air Temperature (Cont.)
VDD= 5V, TA= 25C (unless otherwise noted)
Symbol
Parameter
Test Conditions Shutdown, VI = VDD
APA0710/1 Min. Typ. Max. 1 1 1 1 1 1 900 94 0.15 20 2 74 61 28 400
Unit
|IH|
Shutdown, VI = VDD SE/BTL, VI = VDD Shutdown, VI = 0V
A
|IL|
Shutdown, VI = 0V SE/BTL, VI = 0V
A
Operating characteristic, VDD = 5V, TA = 25C, RL = 8 THD = 1%, SE mode, RL = 32 Total Harmonic Distortion PO = 630mW, BTL mode, THD+N (Note 1) Plus Noise RL = 8 Maximum Output Power Bom Gain = 2, THD+N = 2% Bandwidth B1 Unity-Gain Bandwidth Open Loop PSRR Vn Twu Power Supply Rejection (Note1) Ratio Noise Output Voltage Wake-up time CB = 1F, BTL mode, RL = 8 CB = 1F, SE mode, RL = 8 Gain = 1, CB = 0.1F CB = 1F PO Output Power
(Note 1)
THD = 1%, BTL mode, RL = 8
mW % kHz MHz dB V(rms) ms
Note1 : Output power is measured at the output terminals of device at f=1KHz.
Pin Description
APA0710
Pin Name Shutdown Bypass SE/BTL IN VO+ VDD GND VONo 1 2 3 4 5 6 7 8 O I/O I I I I Description Shutdown mode control signal input, place entire IC in shutdown mode when held high. Bypass pin When SE/BTL is held low, the APA0710 is in BTL mode. When SE/BTL is held high, the APA0710 is in SE mode In is the audio input terminal Supply voltage input pin Ground connection for circuitry VO- is the negative output in BTL mode and a high-impedance output in SE mode
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O VO+ is the positive output for BTL and SE modes
Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Oct., 2005
APA0710/0711
Pin Description
APA0711
Pin Name Shutdown Bypass IN+ INVO+ VDD GND VONo 1 2 3 4 5 6 7 8
I/O I I I I
Description Shutdown mode control signal input, place entire IC in shutdown mode when held low. Bypass pin IN+ is the non-inverting input. IN+ is typically tied to the Bypass terminal. IN- is the inverting input. IN- is typically used as the audio input terminal. Supply voltage input pin. Ground connection for circuitry.
O VO+ is the positive BTL output.
O VO- is the negative BTL output.
Typical Application Circuit
for APA0710 Application
RF
1 0k
Audio Input
VDD VDD/2 4 IN Bypass
6 CC 330 F
VDD Cs 1 F
RI 10k
_
Vo+ 5
CI 0.47 F CB 1 F
2
+
1k
_
Vo1 3 0.1 F VDD 100k 100k Shutdown SE/BTL Bias Control 8
+
7 GND
From System Control
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APA0710/0711
Typical Application Circuit (Cont.)
for APA0711 Application
RF
1 0 k
VDD VDD/2 4 3 ININ+
Audio Input
6
VD D Cs
RI 1 0k
_
Vo+ 5
1 F
CI 0.47 F
+
2 CB 1 F
Byp a s s
_
Vo8
+
From S ystem Control 1 Shutdown Bias Control 7 GND
for APA0711 Differential Input Application
RF
1 0 k
VD D VDD/2 4 3 ININ+
_
6
VD D Cs 1 F
Audio C I RI Input- 0.47 F 1 0k
Vo+
+
5
Audio Input+
RI 10k R F
1 0 k
2
Bypass
CI 0.47 F
CB 1 F
_
Vo+
8
From S ys tem Control
1
Shutdown
Bias Control
7 GND
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APA0710/0711
Typical Characteristics
PSRR vs. Frequency
+0
PSRR vs. Frequency
+0
Ripple Rejection Ration (dB)
No-Capacitor
-20
Ripple Rejection Ration (dB)
No-Capacitor
-20
-40
CB=1F
CB=0.1F
-40
CB=1F
CB=0.1F
-60
-60
CB=2.2F
-80
CB=2.2F
-80
VDD=3.3V RL=8 SE
20 100 1k 10k 20k
VDD=5V RL=8 SE
100 1k 10k 20k
-100
-100 20
Frequency (Hz)
Frequency (Hz)
PSRR vs. Frequency
+0 T RL=8 CB=1F -20 BTL
1600
Supply Current vs. Supply Voltage
RF=10k
1400
Ripple Rejection Ration (dB)
Supply Current (A)
1200
BTL(SE/BTL=0.1VDD)
1000 800 600 400 200 0
-40
-60
VDD=3.3V
-80
SE(SE/BTL=0.9VDD)
VDD=5V
-100 20
100
1k
10k 20k
2.5
3
3.5
4
4.5
5
5.5
Frequency (Hz)
Supply Voltage(V)
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APA0710/0711
Typical Characteristics (Cont.)
Supply Current vs. Supply Voltage
0.12
Output Power vs. Supply Voltage
1200
RF=10k
1000
THD+N=1% f=1kHz BTL
Supply Current (uA)
Output Power (mW)
0.11
800
0.1
600
RL=8
400
0.09
200
RL=32
0.08 2.5 3 3.5 4 4.5 5 5.5
0 2.5
3
3.5
4
4.5
5
5.5
Supply Voltage(V)
Supply Voltage(V)
Output Power vs. Supply Voltage
400 350
1000
Output Power vs. Load Resistance
THD+N=1% f=1kHz BTL
THD+N=1% f=1kHz SE
900 800
Output Power (mW)
Output Power (mW)
300 250 200 150 100 50 0 2.5
700 600 500 400 300 200 100 0
RL=8
VDD=5V
RL=32
VDD=3.3V
3
3.5
4
4.5
5
5.5
8
16
24
32
40
48
56
64
Supply Voltage(V)
Load Resistance()
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APA0710/0711
Typical Characteristics (Cont.)
Output Power vs. Load Resistance
350 300 250
THD+N vs. Frequency
10
THD+N=1% f=1kHz SE
1
VDD=3.3V Po=250mW RL=8 BTL
AV=-20V/V
Output Power (mW)
200 150
VDD=5V
100 50 0 8 16 24 32 40 48 56 64
THD+N (%)
AV=-10V/V
0.1
AV=-2V/V
VDD=3.3V
0.01 20
100
1k
10k 20k
Load Resistance()
Frequency (Hz)
THD+N vs. Frequency
10
THD+N vs. Output Power
10
VDD=3.3V RL=8 AV=-2V/V BTL Po=50mW Po=125mW
1
VDD=3.3V f=1kHz AV=-2V/V BTL
THD+N (%)
THD+N (%)
1
RL=8
0.1
0.1
Po=250mW
0.01 20
0.01
100 1k 10k 20k
0
0.1
0.2
0.3
0.4
0.5
0.6
Frequency (Hz)
Output Power (W)
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APA0710/0711
Typical Characteristics (Cont.)
THD+N vs. Output Power
10
THD+N vs. Frequency
10
f=10kHz
1
VDD=5V Po=700mW RL=8 BTL AV=-20V/V
f=20kHz
1
THD+N (%)
THD+N (%)
AV=-10V/V
f=1kHz
0.1
f=20Hz
VDD=3.3V RL=8 CB=1F AV=-2V/V BTL
1
0.1
AV=-2V/V
0.01 0.01
0.01
0.1
20
100
1k
10k
20k
Output Power (W)
Frequency (Hz)
THD+N vs. Frequency
10 R R
THD+N vs. Output Power
10
VDD=5V RL=8 AV=-2V/V BTL Po=50mW Po=700mW
1
VDD=5V f=1kHz AV=-2V/V BTL
1
THD+N (%)
THD+N (%)
RL=8
0.1
0.1
Po=350mW
0.01 20 100 1k 10k 20k
0.01 0.1 0.3 0.5 0.7 0.9 1.1 1.2
Frequency (Hz)
Output Power (W)
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APA0710/0711
Typical Characteristics (Cont.)
THD+N vs. Output Power
10
10
THD+N vs. Frequency
VDD=3.3V Po=30mW RL=32 SE AV=-10V/V
f=10kHz
1
1
f=20kHz
THD+N (%)
THD+N (%)
AV=-5V/V
0.1
f=1kHz
0.1
VDD=5V RL=8 CB=1F AV=2V/V BTL
0.01 0.01
f=20Hz
AV=-1V/V
0.1
1
0.001 20
100
1k
10k 20k
Output Power (W)
Frequency (Hz)
THD+N vs. Frequency
10 R VDD=3.3V
10
THD+N vs. Output Power
VDD=3.3V f=1kHz RL=32 AV=-1V/V 1 SE
RL=32 AV=-1V/V SE
1
THD+N (%)
Po=10mW
0.1
THD+N (%)
10k 20k
0.1
Po=15mW
0.01
Po=30mW
0.01
0.001
20
100
1k
0.001 0.02
0.025
0.03
0.035
0.04
0.045
0.05
Frequency (Hz)
Output Power (W)
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APA0710/0711
Typical Characteristics (Cont.)
THD+N vs. Output Power
10
THD+N vs. Frequency
10 T T TTTTT T TTTTTTTT T TTTTTTTT TT T T T TTTTTT TT TT
VDD=3.3V RL=32 AV=-1V/V SE
1
1
VDD=5V Po=60mW RL=32 SE AV=-10V/V
f=20Hz
THD+N (%)
THD+N (%)
0.1
AV=-5V/V
0.1
f=20kHz f=10kHz
0.01
f=1kHz
0.01
AV=-1V/V
0.001 0.002
0.01
0.1
0.001 20
100
1k
10k
20k
Output Power (W)
Frequency (Hz)
THD+N vs. Frequency
10 R R R R
THD+N vs. Output Power
10
VDD=5V RL=32 AV=-1V/V SE
1
1
VDD=5V f=1kHz RL=32 AV=-1V/V SE
THD+N (%)
0.1
Po=15mW Po=30mW
THD+N (%)
10k 20k
0.1
0.01
Po=60mW
0.01
0.001 20
100
1k
0.02
0.04
0.06
0.08
0.1
0.12
0.14
Frequency (Hz)
Output Power (W)
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APA0710/0711
Typical Characteristics (Cont.)
THD+N vs. Output Power
10
THD+N vs. Frequency
T
10
VDD=5V RL=32 AV=-1V/V SE
1
VDD=3.3V Po=0.1mW RL=10k SE
1
THD+N (%)
THD+N (%)
f=20kHz f=20Hz
AV=-2V/V
0.1
0.1
AV=-1V/V
0.01
f=10kHz
AV=-5V/V
0.01 0.002
f=1kHz
0.01 0.1 0.2
20 100 1k 10k 20k
Output Power (W)
Frequency (Hz)
THD+N vs. Frequency
10
THD+N vs. Output Power
10
VDD=3.3V RL=10k AV=-1V/V SE
1
THD+N (%)
VDD=3.3V f=1kHz RL=10k AV=-1V/V SE
1
THD+N (%)
0.1
Po=0.1mW Po=0.05mW
0.1
0.01 20
Po=0.13mW
100 1k 10k 20k
0.01 50 75 100 125 150 175 200
Frequency (Hz)
Output Power (W)
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APA0710/0711
Typical Characteristics (Cont.)
THD+N vs. Output Power
10
THD+N vs. Frequency
10 T T T T
VDD=3.3V RL=10k AV=-1V/V SE
VDD=5V Po=0.3mW RL=10k SE
T
1
1
THD+N (%)
f=20Hz f=20kHz
THD+N (%)
0.1
AV=-5V/V
0.1
0.01
AV=-1V/V AV=-2V/V
0.01 50
f=1kHz
100
f=10kHz
0.001 20
200
300
400 500
100
1k
10k
20k
Output Power (W)
Frequency (Hz)
THD+N vs. Frequency
10
THD+N vs. Output Power
10
VDD=5V RL=10k AV=-1V/V SE
1
THD+N (%)
1
VDD=5V f=1kHz RL=10k AV=-1V/V SE
0.1
THD+N (%)
0.1
Po=0.2mW Po=0.1mW
0.01
0.01
Po=0.3mW
0.001 20 100 1k 10k 20k
0.001 50 500
100
150
200
250
300
350
400
450
Frequency (Hz)
Output Power (W)
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APA0710/0711
Typical Characteristics (Cont.)
THD+N vs. Output Power
10
Close Loop Gain and Phase vs. Frequency
+28 +24 +220
VDD=5V RL=10k AV=-1V/V SE
Close Loop Gain (dB)
1
+180 +20 +16 +12
Phase
+140
THD+N (%)
f=20Hz
0.1
f=20kHz f=10kHz
0.01
+100
Gain
+8 +4 -0
f=1kHz
0.001 10
VDD=3.3V RL=8 AV=-4V/V Po=250mW BTL
10 100 1k 10k 100k
+60
+20
100
500
Output Power (W)
Frequency (Hz)
Close Loop Gain and Phase vs. Frequency
+28 +220 +24
Close Loop Gain and Phase vs. Frequency
+10 +8 +300
Gain Phase
+260 +220 +180
Close Loop Gain (dB)
+20
Close Loop Gain (dB)
+180
+6 +4 +2 +0 -2 -4 -6 -8 -10 +100
Phase()
+16 +12
Phase
+140
+100
Gain
+8 +4
-0 10 100 1k
VDD=5V RL=8 AV=-4V/V Po=700mW BTL
10k 100k
+60
+20
VDD=3.3V RL=32 AV=-2V/V Po=30mW SE
10 100 1k 10k 100k
+60 +20
Frequency (Hz)
Frequency (Hz)
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Phase()
+140
Phase()
APA0710/0711
Typical Characteristics (Cont.)
Close Loop Gain and Phase vs. Frequency
+10 +8 +300
100
Noise Floor vs. Frequency
Close Loop Gain (dB)
+6 +4 +2 +0 -2 -4 -6 -8 -10 10 100 1k
Gain
+260
RL= 8, BTL
+180
Phase
+140 +100
Noise Floor (Vrms)
+220
Phase()
10
RL= 32, SE
VDD=5V RL=32 AV=-2V/V Po=60mW SE
10k 100k
+60 +20
1 20 100
VDD=3.3V BW=22Hz to 22kHz AV=-1V/V
1k 10k 20k
Frequency (Hz)
Frequency (Hz)
Noise Floor vs. Frequency
100
350 300 250 200 150 100
Power Dissipation vs. Output Power
RL= 8, BTL
10
RL= 32, SE
Power Dissipation (mW)
RL=8
Noise Floor (Vrms)
RL=32
50 0
VDD=5V BW=22Hz to 22kHz AV=-1V/V
1 20 100 1k 10k 20k
VDD=3.3V BTL
0 200 400 600
Frequency (Hz)
Output Power (mW)
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APA0710/0711
Typical Characteristics (Cont.)
Power Dissipation vs. Output Power
100 90
800 700
Power Dissipation vs. Output Power
Power Dissipation (mW)
80 70 60 50 40 30 20 10 0 0 50
RL=8
Power Dissipation (mW)
RL=8
600 500 400 300 200 100 0
RL=32
RL=32 VDD=5V BTL
0 200 400 600 800 1000
VDD=3.3V SE
100 150
Output Power (mW)
Output Power (mW)
Power Dissipation vs. Output Power
200 180
RL=8
Power Dissipation (mW)
160 140 120 100 80 60 40 20 0 0 50 100 150 200 250 300
RL=32 VDD=5V SE
Output Power (mW)
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APA0710/0711
Application Descriptions
BTL Operation supply, no need DC voltage exists across the load. This eliminates the need for an output coupling capacitor which is required in a single supply, SE configuration. Single-Ended Operation
RL Vo-
Vo+
OP1
Vbias
OP2
Figure1: APA0710/1 power amplifier internal configuration The power amplifier OP1 gain is setting by external gain setting, while the second amplifier OP2 is internally fixed in a unity-gain, inverting configuration. Figure 1 shows that the output of OP1 is connected to the input to OP2, which results in the output signals of with both amplifiers with identical in magnitude, but out of phase 180. Consequently, the differential gain for each channel is 2X (Gain of SE mode). By driving the load differentially through outputs Vo+ and Vo-, an amplifier configuration commonly referred to as bridged mode is established. BTL mode operation is different from the classical single-ended SE amplifier configuration where one side of its load is connected to ground. A BTL amplifier design has a few distinct advantages over the SE configuration, as it provides differential drive to the load, thus doubling the output swing for a specified supply voltage. Four times the output power is possible as compared to a SE amplifier under the same conditions. A BTL configuration, such as the one used in APA0710, also creates a second advantage over SE amplifiers. Since the differential outputs, Vo+, Vo- are biased at halfCopyright (c) ANPEC Electronics Corp. Rev. A.5 - Oct., 2005
Consider the single-supply SE configuration shown Application Circuit. A coupling capacitor is required to block the DC offset voltage from reaching the load. These capacitors can be quite large (approximately 33F to 1000F) so they tend to be expensive, occupy valuable PCB area, and have the additional drawback of limiting low-frequency performance of the system (refer to the Output Coupling Capacitor). The rules described still hold with the addition of the following relationship : 1 1 1 << (1) Cbypassx 80kO (RI + RF) x CI RLCC Output SE/BTL Operation (for APA0710 only) The ability of the APA0710 to easily switch between BTL and SE modes is one of its most important costs saving features. This feature eliminates the requirement for an additional headphone amplifier in applications where internal speakers are driven in BTL mode but external headphone or speakers must be accommodated. Internal to the APA0710, two separate amplifiers drive Vo+ and Vo- (see Figure 2). The SE/BTL input controls the operation of the follower amplifier that drives Vo-. * When SE/BTL is held low, the OP2 is turn on and the APA0710 is in the BTL mode. * When SE/BTL is held high, the OP2 is in a high output impedance state, which configures the APA0710 as SE driver from Vo+. IDD is reduced by approximately one-half in SE mode. Control of the SE/BTL input can be a logic-level TTL
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APA0710/0711
Application Descriptions (Cont.)
Output SE/BTL Operation (for APA0710 only) source or a resistor divider network or the mono headphone jack with switch pin as shown in Application Circuit. The value of Ci is important to consider as it directly affects the low frequency performance of the circuit. Consider the example where Ri is 100k and the specification calls for a flat bass response down to 40Hz. Equation is reconfigured as follow : Ci=
1k VDD 100k SE/BTL 100k
Headphone Jack Control Pin
vo+
1 2RifC
(3)
Consider to input resistance variation, the Ci is 0.04F so one would likely choose a value in the range of 0.1F to 1.0F. A further consideration for this capacitor is the leakage path from the input source through the input network (Ri+Rf, Ci) to the load. This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the DC level there is held at VDD/2, which is likely higher that the source DC level. Please note that it is important to confirm the capacitor polarity in the application. Effective Bypass Capacitor, Cbypass As other power amplifiers, proper supply bypassing is critical for low noise performance and high power supply rejection. The capacitors located on the bypass and power supply pins should be as close to the device as possible. The effect of a larger half supply bypass capacitor will improve PSRR due to increased halfsupply stability. Typical application employ a 5V regulator with 1.0F and a 0.1F bypass as supply filtering. This does not eliminate the need for bypassing the supply nodes of the APA0710/1. The selection of
Figure 2: SE/BTL input selection by phonejack plug In Figure 2, input SE/BTL operates as follows : When the phonejack plug is inserted, the 1k resistor is disconnected and the SE/BTL input is pulled high and enables the SE mode. When this input goes high level, the Vo- amplifier is shutdown causing the speaker to mute. The Vo+ amplifier then drives through the output capacitor (CC) into the headphone jack. When there is no headphone plugged into the system, the contact pin of the headphone jack is connected from the signal pin, the voltage divider set up by resistors 100k and 1k. Resistor 1k then pulls low the SE/BTL pin, enabling the BTL function. Input Capacitor, Ci In the typical application an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the minimum input impedance Ri form a high-pass filter with the corner frequency determined in the follow equation : 1 (2) FC(highpass)= 2RiCi
Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Oct., 2005
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APA0710/0711
Application Descriptions (Cont.)
Effective Bypass Capacitor, Cbypass (Cont.) bypass capacitors, especially Cbypass, is thus dependent upon desired PSRR requirements, click and pop performance. To avoid start-up pop noise occurred, the bypass voltage should rise slower than the input bias voltage and the relationship shown in equation (4) should be 1 maintained.1 << (4) (R I + R F) x C I Cbypass x 80kO The bypass capacitor is fed from a 80k resistor inside the amplifier. Bypass capacitor, Cbypass, values of 0.1F to 2.2F ceramic or tantalum low-ESR capacitors are recommended for the best THD and noise performance. The bypass capacitance also effects to the start up time. It is determined in the following equation : Tstart up = 5 x (Cbypass x 80k) (5) Power Supply Decoupling, Cs The APA0710/1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents the oscillations causing by long lead length between the amplifier and the speaker. The optimum decoupling is achieved by using two different type capacitors that target on different type of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1F placed as close as possible to the device VDD lead works best. For filtering lowerfrequency noise signals, a large aluminum electrolytic capacitor of 10F or greater placed near the audio power amplifier is recommended. Optimizing Depop Circuitry Circuitry has been included in the APA0710/1 to minimize the amount of popping noise at power-up and when coming out of shutdown mode. Popping occurs whenever a voltage step is applied to the speaker. In order to eliminate clicks and pops, all capacitors must be fully discharged before turn-on. Rapid on/off switching of the device or the shutdown function will cause the click and pop circuitry. The value of Ci will also affect turn-on pops (refer to Effective Bypass Capacitance). The bypass voltage rise up should be slower than input bias voltage. Although the bypass pin current source cannot be modified, the size of Cbypass can be changed to alter the device turn-on time and the amount of clicks and pops. By increasing the value of Cbypass, turn-on pop can be reduced. However, the tradeoff for using a larger bypass capacitor is to increase the turn-on time for this device. There is a linear relationship between the
Output Coupling Capacitor, Cc (for APA0710 only) In the typical single-supply (SE) configuration on a APA0710, an output coupling capacitor (Cc) is required to block the DC bias at the output of the amplifier thus preventing DC currents in the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high-pass filter governed by equation. FC(highpass)= 1 2RLCC (6)
For example, a 330F capacitor with an 8 speaker would attenuate low frequencies below 60.6Hz. The main disadvantage, from a performance standpoint, is the load impedance is typically small, which drives the low-frequency corner higher degrading the bass response. Large values of CC are required to pass low frequencies into the load.
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APA0710/0711
Application Descriptions (Cont.)
Optimizing Depop Circuitry (Cont.) size of Cbypass and the turn-on time. In a SE configuration, the output coupling capacitor, CC, is of particular concern. This capacitor discharges through the internal 10k resistors. Depending on the size of CC, the time constant can be relatively large. In the most cases, choosing a small value of Ci in the range of 0.33F to 1F, Cbypass being equal to 1F should produce a virtually clickless and popless turn-on. A high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain. So it is advantageous to use low-gain configurations. Shutdown Function In order to reduce power consumption while not in use, the APA0710/1 contains a shutdown function to externally turn off the amplifier bias circuitry. This shutdown feature turns the amplifier off when a logic high is placed on the Shutdown pin for APA0710 and a logic low on the Shutdown pin for APA0711. The trigger point between a logic high and logic low level is typically 0.4VDD. It is best to switch between ground and the supply voltage VDD to provide maximum device performance. By switching the Shutdown/Shutdown pin to high level/ low level, the amplifier enters a low-current state, IDD for APA0710/1. APA0710/1 are in shutdown mode. On normal operating, APA0710' Shutdown pin pull to low s level and APA0711' Shutdown pin should pull to high s level to keeping the IC out of the shutdown mode. The Shutdown/Shutdown pin should be tied to a definite voltage to avoid unwanted state changes. BTL Amplifier Efficiency An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power supply to the power delivered to the load. The following equations are the basis for calculating amplifier efficiency. Efficiency = Where : PO = VO,RMS = VO,RMS x VO,RMS RL VP 2 = VPxVP 2RL (8) (9) PO PSUP (7)
PSUP = VDD x IDD,AVG = VDDx 2VP RL Efficiency of a BTL configuration : PO VPxVP ) / (VDD x2VP ) = VP =( 4VDD PSUP RL 2RL
Po (W) 0.125 0.25 0.375 Efficiency (%) 33.6 47.6 58.3 VP(V) 1.41 2.00 2.45*
(10)
PD (W) 0.26 0.29 0.28
*High peak voltages cause the THD to increase. Table 1. Efficiency Vs Output Power in 3.3V/8 BTL Systems.
Table 1 employs equation10 to calculate efficiencies for three different output power levels when load is 8. The efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a mono 900mW audio system with 8 loads and a 5V supply, the maximum draw on the
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Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Oct., 2005
APA0710/0711
Application Descriptions (Cont.)
BTL Amplifier Efficiency (Cont.) power supply is almost 1.5W. A final point to remember about linear amplifiers (either SE or BTL) is how to manipulate the terms in the efficiency equation to utmost advantage when possible. Note that in equation10, V DD is in the denominator. This indicates that as VDD goes down, efficiency goes up. In other words, use the efficiency analysis to choose the correct supply voltage and speaker impedance for the application. Power Dissipation Whether the power amplifier is operated in BTL or SE modes, power dissipation is a major concern. In equation11 states the maximum power dissipation point for a SE mode operating at a given supply voltage and driving a specified load. VDD 2 SE mode : PD,MAX= (11) 22RL In BTL mode operation, the output voltage swing is doubled as in SE mode. Thus the maximum power dissipation point for a BTL mode operating at the same given conditions is 4 times as in SE mode.
2 BTL mode : PD,MAX= 4VDD 2 2 RL
thermal pad, the thermal resistance (JA) is equal to 50C/W and 160C/W, respectively. Since the maximum junction temperature (TJ,MAX) of APA0710/1 are 170C and the ambient temperature (T A) is defined by the power system design, the maximum power dissipation which the IC package is able to handle can be obtained from equation13. Once the power dissipation is greater than the maximum limit (PD,MAX), either the supply voltage (VDD) must be decreased, the load impedance (RL) must be increased or the ambient temperature should be reduced. Thermal Pad Considerations The thermal pad must be connected to ground. The package with thermal pad of the APA0710/1 requires special attention on thermal design. If the thermal design issues are not properly addressed, the APA0710/1 8 will go into thermal shutdown when driving a 8 load. The thermal pad on the bottom of the APA0710/1 should be soldered down to a copper pad on the circuit board. Heat can be conducted away from the thermal pad through the copper plane to ambient. If the copper plane is not on the top surface of the circuit board, 6 to 10 vias of 12 mil or smaller in diameter should be used to thermally couple the thermal pad to the bottom plane. For good thermal conduction, the vias must be plated through and solder filled. The copper plane used to conduct heat away from the thermal pad should be as large as practical. If the ambient temperature is higher than 25C, a larger copper plane or forced-air cooling will be required to keep the APA0710/1 junction temperature below the thermal shutdown temperature (170C). In higher ambient temperature, higher airflow rate and/or larger copper area will be required to keep the IC out of thermal shutdown.
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(12)
Since the APA0710/1 is a mono channel power amplifier, the maximum internal power dissipation is equal to the both of equations depending on the mode of operation. Even with this substantial increase in power dissipation, the APA0710/1 does not require extra heatsink. The power dissipation from equation12, assuming a 5V-power supply and an 8 load, must not be greater than the power dissipation that results from the equation13 : TJ,MAX - TA (13) PD,MAX= JA For MSOP-8-P package with and SOP-8 without
Copyright (c) ANPEC Electronics Corp. Rev. A.5 - Oct., 2005
APA0710/0711
Packaging Information
SOP-8 pin ( Reference JEDEC Registration MS-012)
E
H
e1 D
e2
A1
A
1 L
0.004max.
Dim A A1 D E H L e1 e2 1
Millimeters Min. 1.35 0.10 4.80 3.80 5.80 0.40 0.33 1.27BSC 0 8 0 Max. 1.75 0.25 5.00 4.00 6.20 1.27 0.51 Min. 0.053 0.004 0.189 0.150 0.228 0.016 0.013
0.015X45
Inches Max. 0.069 0.010 0.197 0.157 0.244 0.050 0.020 0.50BSC 8
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APA0710/0711
Packaging Information
MSOP-8-P
e1
E
H1
E1 GAUGE PLANE
D1 L
C e
0.25
L1
A1 A3
A2
Dim A1 A2 A3 C e e1 E E1 D1 H1 L L1
Millimeters Min. 0.06 0.86 TYP 0.25 0.13 0.65 TYP 2.90 4.8 2.90 2.146 REF 1.740 REF 0.9 0.45 6 1.0 0.65 0.036 0.018 3.1 5.0 3.1 0.114 0.189 0.114 0.4 0.23 0.01 0.005 Max. 0.15 Min. 0.002
Inches Max. 0.006 0.34 TYP 0.0126 0.009 0.0256 TYP 0.122 0.197 0.122 0.0845 REF 0.0685 REF 0.039 0.026 6
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APA0710/0711
Physical Specifications
Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
TP
(IR/Convection or VPR Reflow)
tp Critical Zone T L to T P
Ramp-up
Temperature
TL Tsmax
tL
Tsmin Ramp-down ts Preheat
25
t 25 C to Peak
Time
Classificatin Reflow Profiles
Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classificatioon Temperature (Tp) Time within 5C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly 3C/second max. 100C 150C 60-120 seconds 183C 60-150 seconds See table 1 10-30 seconds Pb-Free Assembly 3C/second max. 150C 200C 60-180 seconds 217C 60-150 seconds See table 2 20-40 seconds
6C/second max. 6C/second max. 6 minutes max. 8 minutes max. Time 25C to Peak Temperature Notes: All temperatures refer to topside of the package .Measured on the body surface.
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APA0710/0711
Classificatin Reflow Profiles(Cont.)
Table 1. SnPb Entectic Process - Package Peak Reflow Temperature s Package Thickness Volume mm 3 Volume mm 3 <350 350 <2.5 mm 240 +0/-5C 225 +0/-5C 2.5 mm 225 +0/-5C 225 +0/-5C
Table 2. Pb-free Process - Package Classification Reflow Temperatures Package Thickness Volume mm 3 Volume mm 3 Volume mm 3 <350 350-2000 >2000 <1.6 mm 260 +0C* 260 +0C* 260 +0C* 1.6 mm - 2.5 mm 260 +0C* 250 +0C* 245 +0C* 2.5 mm 250 +0C* 245 +0C* 245 +0C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0C. For example 260C+0C) at the rated MSL level.
Reliability Test Program
Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245C, 5 SEC 1000 Hrs Bias @125C 168 Hrs, 100%RH, 121C -65C~150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA
Carrier Tape & Reel Dimensions
t P P1 D
Po E
F W
Bo
Ao
Ko D1
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APA0710/0711
Carrier Tape & Reel Dimensions(Cont.)
T2
J C A B
T1
Application
A 3301
B 62 1.5 D
M/SOP-8
F 5.5 0.1
C 12.75 + 0.1 5 D1
J 2 + 0.5 Po
T1 12.4 +0.2 P1 2.0 0.1
T2 2 0.2 Ao 6.4 0.1
W 12 + 0.3 - 0.1 Bo 5.2 0.1
P 8 0.1 Ko
E 1.75 0.1 t
1.550.1 1.55+ 0.25 4.0 0.1
2.1 0.1 0.30.013
(mm)
Cover Tape Dimensions
Application SOP- 8 MSOP- 8 Carrier Width 12 12 Cover Tape Width 9.3 9.3 Devices Per Reel 2500 3000
Customer Service
Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369
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