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19-2717; Rev 1; 7/03
KIT ATION EVALU BLE AVAILA
Compact 155Mbps to 3.2Gbps Limiting Amplifier
General Description Features
o SFP Reference Design Available o 16-Pin QFN Package with 3mm 3mm Footprint o Single +3.3V Supply Voltage o 86ps Rise and Fall Time o Loss of Signal with Programmable Threshold o RSSI Interface (with MAX3744 TIA) o Output Disable o Polarity Select o 8.5psP-P Deterministic Jitter (3.2Gbps)
MAX3748/MAX3748A
The MAX3748/MAX3748A multirate limiting amplifier functions as a data quantizer for SONET, Fibre Channel, and Gigabit Ethernet optical receivers. The amplifier accepts a wide range of input voltages and provides constantlevel current-mode logic (CML) output voltages with controlled edge speeds. A received-signal-strength indicator (RSSI) is available when the MAX3748/MAX3748A is combined with the MAX3744 SFP transimpedance amplifier (TIA). A receiver consisting of the MAX3744* and the MAX3748/ MAX3748A can provide up to 19dB RSSI dynamic range. Additional features include a programmable loss-of-signal (LOS) detect, an optional disable function (DISABLE), and an output signal polarity reversal (OUTPOL). Output disable can be used to implement squelch. The combination of the MAX3748/MAX3748A and the MAX3744 allows for the implementation of all the smallform-factor SFF-8472 digital diagnostic specifications using a standard 4-pin TO-46 header. The MAX3748/ MAX3748A is packaged in a 3mm 3mm 16-pin QFN package with an exposed pad.
*Future product--contact factory for availability.
Ordering Information
PART MAX3748ETE MAX3748AETE TEMP RANGE -40C to +85C -40C to +85C PINPACKAGE 16 QFN-EP* 16 QFN-EP* PACKAGE CODE T1633-3 T1633-3
*EP = Exposed pad. Functional Diagram and Pin Configuration appear at end of data sheet.
Applications
Gigabit Ethernet SFF/SFP Transceiver Modules Fibre Channel SFF/SFP Transceiver Modules Multirate OC-3 to OC-48-FEC SFF/SFP Transceiver Modules
Typical Operating Circuits
SFP OPTICAL RECEIVER SUPPLY FILTER HOST BOARD HOST FILTER VCC_RX OUTPOL VCC CAZ1 CAZ2
4-PIN TO HEADER
0.1F
0.1F IN+
MAX3744 TIA*
OUT+ 0.1F
50 SERDES 50
IN-
OUT-
MAX3748/ MAX3748A
RSSI DS1858 3-INPUT DIAGNOSTIC MONITOR R1 3k C1 0.1F TH RTH GND DISABLE LOS 4.7k TO 10k VCC_HOST LOS *FUTURE PRODUCT.
Typical Operating Circuits continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Compact 155Mbps to 3.2Gbps Limiting Amplifier MAX3748/MAX3748A
ABSOLUTE MAXIMUM RATINGS
Power-Supply Voltage (VCC) .................................-0.5V to +6.0V Voltage at IN+, IN- ..........................(VCC - 2.4V) to (VCC + 0.5V) Voltage at DISABLE, OUTPOL, RSSI, CAZ1, CAZ2, LOS, TH............................-0.5V to (VCC + 0.5V) Current into LOS ...................................................-1mA to +9mA Differential Input Voltage (IN+ - IN-) .....................................2.5V Continuous Current at CML Outputs (OUT+, OUT-) ...............................................-25mA to +25mA Continuous Power Dissipation (TA = +70C) 16-Pin QFN (derate 17.7mW above +70C) ....................1.4W Operating Junction Temperature Range (TJ) ....-55C to +150C Storage Ambient Temperature Range (Ts)........-55C to +150C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 2.97V to 3.63V, ambient temperature = -40C to +85C, CML output load is 50 to VCC, CAZ = 0.1F, typical values are at +25C, VCC = 3.3V, unless otherwise specified. The data input transition time is controlled by a 4th-order Bessel filter with f-3dB = 0.75 2.667GHz for all data rates of 2.667Gbps and below, and with f-3dB = 0.75 3.2GHz for a data rate of 3.2Gbps.)
PARAMETER Single-Ended Input Resistance Input Return Loss Input Sensitivity Input Overload Single-Ended Output Resistance Output Return Loss Differential Output Voltage Differential Output Signal when Disabled Outputs AC-coupled, VIN-MAX applied to input (Note 2) K28.5 pattern at 3.2Gbps Deterministic Jitter (Notes 2, 3) DJ 2 - 1 PRBS equivalent pattern at 2.7Gbps (Note 4) K28.5 pattern at 2.1Gbps 2 - 1 PRBS equivalent pattern at 155Mbps Random Jitter (Note 5) Data Output Transition Time Input-Referred Noise Low-Frequency Cutoff Power-Supply Current Power-Supply Noise Rejection LOS Hysteresis LOS Assert/Deassert Time Low LOS Assert Level Low LOS Deassert Level Medium LOS Assert Level ICC PSNR CAZ = open CAZ = 0.1F (Note 6) LOS disabled f < 2MHz 10log (VDEASSERT/VASSERT) (Note 8) RTH = 20k RTH = 20k RTH = 280 10.3 1.25 2 2.8 4.1 6.7 15.2 11.6 26 2.2 100 Input = 5mVP-P Input = 10mVP-P 20% to 80% (Note 2)
23 23
SYMBOL
CONDITIONS Single ended to VCC Differential, f < 3GHz, DUT is powered on
MIN 42
TYP 50 13
MAX 58 5
UNITS dB mVP-P mVP-P dB mVP-P mVP-P
VIN-MIN VIN-MAX
(Note 1) (Note 1) Single ended to VCC Differential, f < 3GHz, DUT is powered on 600 1200 42 50 10 780
58 1200 10
8.5 9.3 7.8 25 6.5 3 86 185 70 0.8 32
25 30 25 50 psRMS 115 ps VRMS kHz 49 37 mA dB dB s mVP-P mVP-P mVP-P psP-P
LOSS OF SIGNAL at 2.5Gbps (Notes 2, 7)
2
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Compact 155Mbps to 3.2Gbps Limiting Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.97V to 3.63V, ambient temperature = -40C to +85C, CML output load is 50 to VCC, CAZ = 0.1F, typical values are at +25C, VCC = 3.3V, unless otherwise specified. The data input transition time is controlled by a 4th-order Bessel filter with f-3dB = 0.75 2.667GHz for all data rates of 2.667Gbps and below, and with f-3dB = 0.75 3.2GHz for data rate of 3.2Gbps.)
PARAMETER Medium LOS Deassert Level High LOS Assert Level High LOS Deassert Level LOSS OF SIGNAL at 155Mbps (Note 7) LOS Hysteresis LOS Assert/Deassert Time Low LOS Assert Level Low LOS Deassert Level Medium LOS Assert Level Medium LOS Deassert Level High LOS Assert Level High LOS Deassert Level RSSI RSSI Current Gain (Note 9) Input-Referred RSSI Current Stability TTL/CMOS I/O LOS Output High Voltage LOS Output Low Voltage LOS Output Current DISABLE Input High DISABLE Input Low DISABLE Input Current VIH VIL RLOS = 4.7k to 10k to VCC_host VOH VOL RLOS = 4.7k to10k to VCC_host (3V) RLOS = 4.7k to10k to VCC_host (3.6V) RLOS = 4.7k to10k to VCC_host (3.3V); IC is powered down 2.0 0.8 10 2.4 0.4 40 V V A V V A ARSSI ARSSI = IRSSI/ICM_RSSI IRSSI/ARSSI (Note 10) ICM_INPUT < 6.6mA ICM_INPUT > 6.6mA -31 -73 0.03 +33 +90 A 10log (VDEASSERT/VASSERT) (Note 8) RTH = 20k RTH = 20k RTH = 280 RTH = 280 RTH = 80 RTH = 80 2.1 20 3.5 5.6 13.3 21.2 33.3 55.5 dB s mVP-P mVP-P mVP-P mVP-P mVP-P mVP-P SYMBOL RTH = 280 RTH = 80 RTH = 80 22.8 CONDITIONS MIN TYP 25 38.3 65.2 99.3 MAX 38.6 UNITS mVP-P mVP-P mVP-P
MAX3748/MAX3748A
Note 1: Note 2: Note 3: Note 4:
Note 5: Note 6: Note 7: Note 8: Note 9: Note 10:
Between sensitivity and overload, all AC specifications are met. Guaranteed by design and characterization. The deterministic jitter caused by this filter is not included in the DJ generation specifications (input). 223 - 1 PRBS pattern was substituted by K28.5 pattern to determine the high-speed portion of the deterministic jitter. The low-speed portion of the DJ (baseline wander) was obtained by measuring the eye width difference between outputs generated using K28.5 and 223 - 1 PRBS patterns. Random jitter was measured without using a filter at the input. The supply current measurement excludes the CML output currents by connecting the CML outputs to a separate VCC (see Figure 1). Unless otherwise specified, the pattern for all LOS detect specifications is 223 - 1 PRBS. The signal at the input is switched between two amplitudes, Signal_ON and Signal_OFF, as shown in Figure 2. ICM_INPUT is the input common mode. IRSSI is the current at the RSSI output. Stability is defined as variation over temperature and power supply with respect to the typical gain of the part.
_______________________________________________________________________________________
3
Compact 155Mbps to 3.2Gbps Limiting Amplifier MAX3748/MAX3748A
Typical Operating Characteristics
(TA = +25C and VCC = +3.3V, unless otherwise specified.)
SUPPLY CURRENT vs. TEMPERATURE
MAX3748 toc01
TRANSFER FUNCTION
MAX3748 toc02
RANDOM JITTER vs. TEMPERATURE (INPUT LEVEL 10mVP-P)
9 8 RANDOM JITTER (psRMS) 7 6 5 4 3 2 1 0
MAX3748 toc03
100 90 80 70 CURRENT (mA) 60 50 40 30 20 10 0
900 800 DIFFERENTIAL OUTPUT (mVP-P) 700 600 500 400 300 200 100 0 OUTPUT VOLTAGE vs. INPUT VOLTAGE
10
-40 -30-20 -10 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (C)
1
2
3
4
5
6
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (C)
DIFFERENTIAL INPUT (mVP-P)
RANDOM JITTER vs. INPUT AMPLITUDE
MAX3748 toc04
BIT-ERROR RATIO vs. INPUT VOLTAGE
MAX3748 toc05
DETERMINISTIC JITTER vs. INPUT COMMON-MODE VOLTAGE (VCC TO VCC - 0.8V)
24 DETERMINISTIC JITTER (psP-P) 22 20 18 16 14 12 10
MAX3748 toc06
10 9 8 RANDOM JITTER (psRMS) 7 6 5 4 3 2 1 0 0 10 20 30
1200 1000 BIT-ERROR RATIO (10-12) 800 600 400 200 0
40
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 COMMON-MODE VOLTAGE (VCC + x)
DIFFERENTIAL INPUT AMPLITUDE (mVP-P)
INPUT VOLTAGE (mVP-P)
OUTPUT EYE DIAGRAM (MINIMUM INPUT)
MAX3748 toc07
OUTPUT EYE DIAGRAM (MAXIMUM INPUT)
MAX3748 toc08
OUTPUT EYE DIAGRAM (MINIMUM INPUT)
MAX3748 toc09
3.2Gbps, 223 - 1 PRBS, 5mVP-P
3.2Gbps, 223 - 1 PRBS, 1200mVP-P
2.7Gbps, 223 - 1 PRBS, 5mVP-P
100mV/div
100mV/div
100mV/div
50ps/div
50ps/div
100ps/div
4
_______________________________________________________________________________________
Compact 155Mbps to 3.2Gbps Limiting Amplifier
Typical Operating Characteristics (continued)
(TA = +25C and VCC = +3.3V, unless otherwise specified.)
MAX3748/MAX3748A
OUTPUT EYE DIAGRAM WITH MAXIMUM INPUT (DATA RATE OF 2.6667Gbps)
MAX3748 toc10
OUTPUT EYE DIAGRAM AT +100C (MINIMUM INPUT)
MAX3748 toc11
ASSERT/DEASSERT LEVELS vs. RTH
MAX3748 toc12
2.7Gbps, 223 - 1 PRBS, 1200mVP-P
3.2Gbps, 223 - 1 PRBS, 5mVP-P ASSERT/DEASSERT (mVP-P)
100
DEASSERT
100mV/div
100mV/div
10 ASSERT
1 50ps/div 50ps/div 0.01 0.1 1 RTH (k) 10 100
INPUT RETURN GAIN vs. FREQUENCY (SDD11) (INPUT SIGNAL LEVEL = -40dBm)
MAX3748 toc13
OUTPUT RETURN GAIN vs. FREQUENCY (SDD22) (INPUT SIGNAL LEVEL = -40dBm)
MAX3748 toc14
DETERMINISTIC JITTER vs. INPUT OFFSET VOLTAGE (2.667Gbps, K28.5)
18 DETERMINISTIC JITTER (psP-P) 16 14 12 10 8 6 4 2 0
MAX3748 toc15
30 20 10 GAIN (dB) 0 -10 -20 -30 -40 100M OUTPUT DISABLED
30 20 10 GAIN (dB) 0 -10 -20 -30 -40 100M
20
1G FREQUENCY (Hz)
10G
1G FREQUENCY (Hz)
10G
-6
-4
-2
0
2
4
6
INPUT OFFSET VOLTAGE (mVP-P)
LOS HYSTERESIS vs. TEMPERATURE (2.667bps, 210 - 1 PRBS)
MAX3748 toc16
RSSI CURRENT GAIN vs. INPUT TIA CURRENT (MAX3744 AND MAX3748)
MAX3748 toc17
6 10LOG (DEASSERT/ASSERT) (dB) 5 4 3 2 1 0 RTH = 280 RTH = 20k RTH = 80
700 600 OUTPUT RSSI CURRENT (A) 500 400 300 200 100 0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (C)
0 100 200 300 400 500 600 700 800 900 1000 INPUT TIA CURRENT (A)
_______________________________________________________________________________________
5
Compact 155Mbps to 3.2Gbps Limiting Amplifier MAX3748/MAX3748A
Pin Description
PIN 1, 4, 12 2 3 5 NAME VCC IN+ INTH Supply Voltage Noninverted Input Signal, CML Inverted Input Signal, CML Loss-of-Signal Threshold Pin. Resistor to ground (RTH) sets the LOS threshold. Connecting this pin to VCC disables the LOS circuitry and reduces power consumption. Disable Input, CMOS/TTL. The data outputs are held static when this pin is asserted high. The LOS function remains active when the outputs are disabled, CMOS. On the MAX3748, this pin does not include ESD protection. If routed through the DS1858/DS1859 controller IC, no additional ESD protection is required. On the MAX3748A, this pin has ESD protection. Noninverted Loss-of-Signal Output. LOS is asserted high when the signal drops below the assert threshold set by the TH input. The output is open collector (Figure 5). On the MAX3748, this pin does not include ESD protection. If routed through the DS1858/DS1859 controller IC, no additional ESD protection is required. On the MAX3748A, this pin has ESD protection. Supply Ground Output Polarity Control Input. Connect to GND for an inversion of polarity through the limiting amplifier and connect to VCC for normal operation. Inverted Data Output, CML Noninverted Data Output, CML Received-Signal-Strength Indicator. This current output can be used to obtain a ground-referenced voltage proportional to photodiode current with the MAX3744 by connecting an external resistor between this pin and GND. Offset Correction Loop Capacitor Connection. A capacitor connected between this pin and CAZ1 extends the time constant of the offset correction loop. Typical value of CAZ is 0.1F. The offset correction is disabled when the CAZ1 and CAZ2 pins are shorted together. Offset Correction Loop Capacitor Connection. A capacitor connected between this pin and CAZ2 extends the time constant of the offset correction loop. Typical value of CAZ is 0.1F. The offset correction is disabled when the CAZ1 and CAZ2 pins are shorted together. Connect the exposed paddle to board ground for optimal electrical and thermal performance. FUNCTION
6
DISABLE
7
LOS
8, 16 9 10 11 13
GND OUTPOL OUTOUT+ RSSI
14
CAZ2
15
CAZ1 Exposed paddle
EP
Detailed Description
The limiting amplifier consists of an input buffer, a multistage amplifier, offset correction circuitry, an output buffer, power-detection circuitry, and signal-detect circuitry (see Functional Diagram).
VCC ICC (SUPPLY CURRENT) IOUT (CML OUTPUT CURRENT) 50
50
Input Buffer
The input buffer is shown in Figure 3. It provides 50 termination for each input signal IN+ and IN-. The MAX3748/MAX3748A can be DC- or AC-coupled to a TIA (TIA output offset degrades receiver performance if DC-coupled). The CML input buffer is optimized for the MAX3744 TIA.
MAX3748/ MAX3748A RTH
Gain Stage
The high-bandwidth gain stage provides approximately 53dB of gain.
6 Figure 1. Power-Supply Current Measurement
_______________________________________________________________________________________
Compact 155Mbps to 3.2Gbps Limiting Amplifier MAX3748/MAX3748A
VIN SIGNAL ON 1dB MAX DEASSERT LEVEL
IN+ 0.25pF 50 50 VCC
6dB
POWER-DETECT WINDOW
IN-
75k
MIN DEASSERT LEVEL
0.25pF
ESD STRUCTURES
0V
SIGNAL OFF TIME
Figure 2. LOS Deassert Threshold Set 1dB Below the Minimum by Receiver Sensitivity (for Selected RTH)
Figure 3. CML Input Buffer
Offset Correction Loop
The MAX3748/MAX3748A is susceptible to DC offsets in the signal path because it has high gain. In communication systems using NRZ data with a 50% duty cycle, pulse-width distortion present in the signal or generated in the transimpedance amplifier appears as an input offset and is reduced by the offset correction loop. For Gigabit Ethernet and Fibre Channel applications, no capacitor is required. For SONET applications, CAZ = 0.1F is recommended. This capacitor determines the lower 3dB frequency of the data path.
VCC
50
50 OUT+ OUT-
Q3 DISABLE
Q4
Q1
Q2 ESD STRUCTURES
CML Output Buffer
The MAX3748/MAX3748A limiting amplifier's CML output provides high tolerance to impedance mismatches and inductive connectors. The output current is approximately 18mA. The output is disabled by connecting the DISABLE pin to VCC. If the LOS pin is connected to the DISABLE pin, the outputs OUT+ and OUT- are at a static voltage (squelch) whenever the input signal level drops below the LOS threshold. The output buffer can be AC- or DC-coupled to the load (Figure 4).
DATA
18mA
18mA
DISABLE
DISABLE
Figure 4. CML Output Buffer
Power-Detect and Loss-of-Signal Indicator
The MAX3748/MAX3748A is equipped with an LOS circuitry, which indicates when the input signal is below a programmable threshold, set by resistor RTH at the TH pin (see Typical Operating Characteristics for appropriate resistor sizing). An averaging peak-power detector compares the input signal amplitude with this threshold and feeds the signal detect information to the LOS output, which is open collector. Two control voltages, VASSERT and VDEASSERT, define the LOS assert and
deassert levels. To prevent LOS chatter in the region of the programmed threshold, approximately 2dB of hysteresis is built into the LOS assert/deassert function. Once asserted, LOS is not deasserted until the input amplitude rises to the required level (V DEASSERT ) (Figure 5).
Design Procedure
Program the LOS Assert Threshold
External resistor RTH programs the LOS threshold. See the Assert/Deassert Levels vs. RTH graph in the Typical Operating Characteristics to select the appropriate resistor.
7
_______________________________________________________________________________________________________
Compact 155Mbps to 3.2Gbps Limiting Amplifier MAX3748/MAX3748A
VCC
LOS
ESD STRUCTURE
GND
Figure 5. MAX3748 LOS Output Circuit
The MAX3744 preamp measures the average photodiode current and provides the information to the output common mode. The MAX3748/MAX3748A RSSI detect block senses the common-mode DC level of input signals IN+ and IN- and provides a ground-referenced output signal (RSSI) proportional to the photodiode current. The advantage of this implementation is that it allows the TIA to be packaged in a low-cost conventional 4-pin TO46 header. The MAX3748/MAX3748A RSSI output is connected to an analog input channel of the DS1858/DS1859 SFP controller to convert the analog information into a 16-bit word. The DS1858/DS1859 provide the receive-power information to the host board of the optical receiver through a 2-wire interface. The DS1859 allows for internal calibration of the receive-power monitor. The MAX3744 and the MAX3748/MAX3748A have been optimized to achieve RSSI stability of 2.5dB within the range of 6A to 500A of average input photodiode current. To achieve the best accuracy, Maxim recommends receive power calibration at the low end (6A) and the high end (500A) of the required range; see the RSSI Current Gain graph in the Typical Operating Characteristics.
Select the Coupling Capacitor
When AC-coupling is desired, coupling capacitors CIN and COUT should be selected to minimize the receiver's deterministic jitter. Jitter is decreased as the input lowfrequency cutoff (fIN) is decreased: fIN = 1 / [2(50)(CIN)] For ATM/SONET or other applications using scrambled NRZ data, select (CIN, COUT) 0.1F, which provides fIN < 32kHz. For Fibre Channel, Gigabit Ethernet, or other applications using 8B/10B data coding, select (CIN, COUT) 0.01F, which provides fIN < 320kHz. Refer to Application Note HFAN-1.1: Choosing ACCoupling Capacitors.
Connecting to the DS1858/DS1859
For best use of the RSSI monitor, capacitor C1 and resistor R1 shown in the first Typical Application Circuit need to be placed as close as possible to the Dallas diagnostic monitor with the ground of C1 and R1 the same as the DS1858/DS1859 ground. Capacitor C1 suppresses system noise on the RSSI signal. R1 = 3k and C1 = 0.1F is recommended.
Select the Offset-Correction Capacitor
The capacitor between CAZ1 and CAZ2 determines the time constant of the signal path DC offset cancellation loop. To maintain stability, it is important to keep a onedecade separation between fIN and the low-frequency cutoff (fOC) associated with the DC offset cancellation circuit. For ATM/SONET or other applications using scrambled NRZ data, fIN < 32kHz, so fOCMAX < 3.2kHz. Therefore, CAZ = 0.1F (fOC = 2kHz). For Fibre Channel or Gigabit Ethernet applications, leave pins CAZ1 and CAZ2 open.
VCC
RSSI Implementation
The SFF-8472 Digital Diagnostic specification requires monitoring of input receive power. The MAX3748/ MAX3748A and MAX3744 receiver chipset allows for the monitoring of the average receive power by measuring the average DC current of the photodiode.
GND
LOS
ESD STRUCTURE
Figure 6. MAX3748A LOS Output Circuit 8 _______________________________________________________________________________________
Compact 155Mbps to 3.2Gbps Limiting Amplifier
Typical Operating Circuits (continued)
SFP OPTICAL RECEIVER VCC (+3.3V OR APD REFERENCE VOLTAGE) VCC (+3.3V) 0.1F 5-PIN TO HEADER OUTPOL VCC CAZ1 CAZ2 SUPPLY FILTER HOST BOARD HOST FILTER VCC_RX
MAX3748/MAX3748A
PIN OR APD
MAX3744 TIA
0.1F IN+ OUT+ 0.1F INMAX3748/ MAX3748A RSSI TH RTH LOS R1 3k C1 0.1F GND DISABLE LOS 4.7k TO 10k VCC_HOST OUT50 50 SERDES
DS1858 3-INPUT DIAGNOSTIC MONITOR
SFP OPTICAL RECEIVER VCC (+3.3V OR APD REFERENCE VOLTAGE) HIGH-SIDE CURRENT SENSE 5-PIN TO HEADER OUTPOL CIN 0.1F IN+
MAX3744 TIA
HOST BOARD
VCC (+3.3V) 0.1F VCC CAZ1 CAZ2 COUT 0.1F OUT+ 50 SERDES INCIN 0.1F MAX3748/ MAX3748A RSSI TH RTH LOS GND DISABLE LOS OUTCOUT 0.1F 4.7k TO 10k VCC_HOST 50 SUPPLY FILTER HOST FILTER VCC_RX
PIN OR APD
DS1858 3-INPUT DIAGNOSTIC MONITOR
_______________________________________________________________________________________
9
Compact 155Mbps to 3.2Gbps Limiting Amplifier MAX3748/MAX3748A
Functional Diagram
CAZ VCC VCC
50
50
CAZ1
CAZ2
MAX3748/ MAX3748A
50
50
OFFSET CORRECTION
OUTOUT+
IN+ IN-
18mA DISABLE RSSI DETECT RSSI TH POWER DETECT LOS OUTPOL
Pin Configuration
GND 16 VCC IN+ INVCC 1 2 3 4 5 6 7 8 GND MAX3748/ MAX3748A CAZ1 CAZ2 15 14 RSSI 13 12 VCC 11 OUT+ 10 OUT9 OUTPOL
Chip Information
TRANSISTOR COUNT: 1468 PROCESS: SiGe Bipolar
TH DISABLE LOS
3mm x 3mm QFN
10
______________________________________________________________________________________
Compact 155Mbps to 3.2Gbps Limiting Amplifier
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
12x16L QFN THIN.EPS
MAX3748/MAX3748A
D2 b
0.10 M C A B
D D/2
D2/2
E/2
E2/2
C L
-A-
E
(NE - 1) X e
E2
L
-B-
e
k (ND - 1) X e
C L
C L
0.10 C 0.08 C
C L
A A2 A1 L L
e
e
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 12 & 16L, QFN THIN, 3x3x0.8 mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0136
1 2
C
EXPOSED PAD VARIATIONS
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 12 & 16L, QFN THIN, 3x3x0.8 mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0136
2 2
C
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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