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Military 5.0V pASIC 1 Family
Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA
Military 5.0V pASIC 1 Family
DEVICE HIGHLIGHTS
Device Highlights Features
s
FEATURES
Total of 180 I/O pins
s s s
Very High Speed
s
ViaLink" metal-to-metal programmable technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns at 5V, and over 80 MHz at 3.3V operation.
-172 Bidirectional Input/Output pins -6 Dedicated Input/High-Drive pins -2 Clock/Dedicated input pins with fanoutindependent, low-skew clock networks -PCI 2.1 Compliant I/Os
High Usable Density
s
s s s s
Up to a 24-by-32 array of 768 logic cells provides 22,000 usable PLD gates in 208-pin PQFP and 208-pin CQFP packages.
Input + logic cell + output delays under 6 ns Chip-to-chip operating frequencies up to 110 MHz Internal state machine frequencies up to 150 MHz Clock skew < 0.5 ns Input hysteresis provides high noise immunity Built-in scan path permits 100% factory testing of logic and I/O cells and functional testing with Automatic Test Vector Generation (ATVG) software after programming 208 pin PQFP pin for pin compatible with the 208 CQFP 0.65 CMOS process with ViaLink programming technology
PCI-Output Drive
s
s s s
Fully PCI 2.1 compliant input/output capability. (including drive current)
s
s
Device
ASIC Gates
PLD Gates
Package
Max I/O
Qualification Level
SMD 5962-
QL8x12B QL12x16B QL16x24B QL24x32B
1,000 2,000 4,000 8,000
2,000 4,000 7,000 14,000
68CPGA 84CPGA 144CPGA 160 CQFP 208CQFP 208PQFP
64 76 122 122 180 180
M M, /883 M, /883 M, /883 M, /883 M
96836 95599 95599 96837
M = Military Temperature (-55 to +125 degrees C) /883 = MIL-STD-883 qualified
TABLE 1: Selector Table
Rev B
8-7
Military 5.0V pASIC 1 Family
PRODUCT SUMMARY
Product Summary
The pASIC 1 Family is a very-high-speed CMOS user-programmable ASIC devices. The 768 logic cell field-programmable gate array (FPGA) features 22,000 usable PLD gates of high-performance general-purpose logic in a 208-pin PQFP and CQFP package. Low-impedance, metal-to-metal, ViaLink interconnect technology provides nonvolatile custom logic capable of operating above 150 MHz. Logic cell delays under 2 ns, combined with input delays of under 1.5 ns and output delays under 3 ns, permit
high-density programmable devices to be used with today's fastest microprocessors and DSPs. Designs can be entered using QuickLogic's QuickWorks Toolkit or most popular third-party CAE tools. QuickWorks combines Verilog/VHDL design entry and simulation tools with device-specific place & route and programming software. Ample on-chip routing channels allow fast, fully automatic place and route of designs using up to 100% of the logic and I/ O cells, while maintaining fixed pin-outs.
PINOUT DIAGRAM 68-PIN CPGA
Pinout Diagram 68-Pin CPGA
PIN B10 A10 B9 A9 B8 A8 B7 A7 B6 A6 B5 A5 B4 A4 B3 A3 A2
FUNC IO IO IO IO IO IO I/(SCLK) I/CLK/(SM) VCC I I IO IO IO IO IO IO
PIN B2 B1 C2 C1 D2 D1 E2 E1 F2 F1 G2 G1 H2 H1 J2 J1 K1
FUNC IO IO IO IO IO IO IO IO GND IO IO IO IO IO IO IO IO
PIN K2 L2 K3 L3 K4 L4 K5 L5 K6 L6 K7 L7 K8 L8 K9 L9 L10
FUNC IO IO IO IO IO IO I/(SI) I/CLK VCC I I/(SO) IO IO IO IO IO IO
PIN K10 K11 J10 J11 H10 H11 G10 G11 F10 F11 E10 E11 D10 D11 C10 C11 B11
FUNC IO IO IO IO IO IO IO IO GND IO IO IO IO IO IO IO IO
TABLE 2: CPGA 68 Function/Connector Pin Table
8-8 8
Preliminary
Military 5.0V pASIC 1 Family
PINOUT DIAGRAM 84-PIN CPGA
Pinout Diagram 84-pin CPGA
PIN B10 B9 A10 A9 B8 A8 A7 C7 A6 B7 C6 B6 B5 C5 A5 A4 B4 A3 A2 B3 A1
FUNC IO IO IO IO IO IO IO GND IO I/(SCLK) I/CLK/(SM) I(P) I VCC IO IO IO IO IO IO IO
PIN B2 C2 B1 C1 D2 D1 E1 E3 E2 F1 F2 F3 G1 G3 G2 H1 H2 J1 K1 J2 L1
FUNC IO IO IO IO IO IO IO GND IO IO IO IO IO VCC IO IO IO IO IO IO IO
PIN K2 K3 L2 L3 K4 L4 L5 J5 L6 K5 J6 K6 K7 J7 L7 L8 K8 L9 L10 K9 L11
FUNC IO IO IO IO IO IO IO GND IO I/(SI) I/CLK I I/(SO) VCC IO IO IO IO IO IO IO
PIN K10 J10 K11 J11 H10 H11 G11 G9 G10 F11 F10 F9 E11 E9 E10 D11 D10 C11 B11 C10 A11
FUNC IO IO IO IO IO IO IO GND IO IO IO IO IO VCC IO IO IO IO IO IO IO
TABLE 3: CPGA 84 Function/Connector Pin Table
8-9
Military 5.0V pASIC 1 Family
PINOUT DIAGRAM 144-PIN CPGA
Pinout Diagram 144-pin CPGA
PIN A2 B3 C4 A3 B4 A4 C3 B5 A5 C6 B6 A6 A7 B7 C5 A8 B8 C8 C7 A9 B9 C11 A10 A11 B10
FUNC IO IO IO IO IO IO VCC IO IO IO IO IO IO IO GND IO I/(SCLK) I/CLK/(SM) VCC I/(P) I VCC IO IO IO
PIN B15 C14 D13 C15 D14 E13 D15 E14 E15 F13 F14 F15 G15 C13 G14 H15 H14 G13 H13 J15 J14 J13 K15 L15 K14
FUNC IO IO IO IO IO VCC IO IO IO IO IO IO IO GND IO IO IO GND IO IO IO VCC IO IO IO
PIN R14 P13 N12 R13 P12 R12 N13 P11 R11 N10 P10 R10 R9 P9 N11 R8 P8 N8 N9 R7 P7 N5 R6 R5 P6
FUNC IO IO IO IO IO IO VCC IO IO IO IO IO IO IO GND IO I/(SI) I/CLK VCC I I/(SO) VCC IO IO IO
PIN P1 N2 M3 N1 M2 L3 M1 L2 L1 K3 K2 K1 J1 N3 J2 H1 H2 J3 H3 G1 G2 G3 F1 E1 F2
FUNC IO IO IO IO IO VCC IO IO IO IO IO IO IO GND IO IO IO GND IO IO IO VCC IO IO IO
TABLE 4: CPGA 144 Function/Connector Table (Cont'd on next page)
8-10 10
Preliminary
Military 5.0V pASIC 1 Family
CPGA 144 Function/Connector Table (Cont'd)
A12 B11 C10 A13 C9 B12 A14 B13 C12 A15 B14 IO IO IO IO GND IO IO IO IO IO IO M15 L14 K13 N15 L13 M14 P15 N14 M13 R15 P14 IO IO IO IO GND IO IO IO IO IO nc R4 P5 N6 R3 N7 P4 R2 P3 N4 R1 P2 IO IO IO IO GND IO IO IO IO IO IO D1 E2 F3 C1 E3 D2 B1 C2 D3 A1 B2 IO IO IO IO GND IO IO IO IO IO nc
PINOUT DIAGRAM 160-PIN CPGA
QL16x24B-1CF160M
8-11
Military 5.0V pASIC 1 Family
PINOUT DIAGRAM 208-PIN CPGA
Pinout Diagram 208-pin CPGA
Pin #157 Pin #1
pASIC QL24X32B-1PQ208M
Pin #53
Pin #105
8-12 12
Preliminary
Military 5.0V pASIC 1 Family
PQFP/CQFP 208 FUNCTION/CONNECTOR TABLE
PQFP/CQFP 208 Function/Connector Table
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
FUN I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/Sck I/Clk
PIN 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
FUN VCC I/P I VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O
PIN 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78
FUN I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND
PIN 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
FUN I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O
PIN 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130
FUN I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/SI I/Clk
PIN 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156
FUN VCC I I/SO VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O
PIN 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182
FUN I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND
PIN 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
FUN I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O
8-13
Military 5.0V pASIC 1 Family
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ........................-0.5 to 7.0V Input Voltage................ -0.5 to VCC +0.5V ESD Pad Protection.................... 2000V DC Input Current .......................20 mA Latch-up Immunity .................. 200 mA Storage Temperature .......-65C to +150C Lead Temperature ...........................300C
5 Volt OPERATING RANGE
Symbol VCC TA TC K Supply Voltage Ambient Temperature Case Temperature Delay Factor Parameter Military Min Max 4.5 5.5 -55 125 0.39 1.82 0.39 1.56 Unit V C C
-0 Speed Grade -1 Speed Grade
DC CHARACTERISTICS over 5V operating range
Symbol VIH VIL VOH VOL II IOZ CI IOS ICC Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input Leakage Current 3-State Output Leakage Current Input Capacitance [1] Output Short Circuit Current [2] D.C. Supply Current [3] Conditions Min 2.0 3.7 2.4 VCC-0.1 0.4 0.1 10 10 10 -90 160 20 Max 0.8 IOH = -4 mA IOH = 16 mA IOH = -10 A IOL = 8 mA IOL = 10 A VI = VCC or GND VI = VCC or GND VO = GND VO = VCC VI, VIO = VCC or GND Unit V V V V V V V A A pF mA mA mA
-10 -10 -10 40
Notes: [1] Capacitance is sample tested only. CI = 20 pF max on I/(SI). [2] Only one output at a time. Duration should not exceed 30 seconds. [3] Maximum Icc for military grade is 20 mA. For AC conditions use the formula described in the databook, Section 9 - Power vs Operating Frequency. [4] Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. [5] These limits are derived from a representative selection of the slowest paths through the pASIC logic cell including net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.
8-14 14
Preliminary
Military 5.0V pASIC 1 Family
QL8X12B
QL8X12B
AC CHARACTERISTICS at VCC = 5V, TA = 25C (K = 1.00)
Logic Cell
Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Parameter Combinatorial Delay [5] Setup Time [5] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1 1.7 2.1 0.0 1.0 2.0 2.0 1.7 1.5 1.9 1.8 Propagation Delays (ns) Fanout 2 3 4 2.1 2.6 3.0 2.1 2.1 2.1 0.0 0.0 0.0 1.5 1.9 2.3 2.0 2.0 2.0 2.0 2.0 2.0 2.1 2.6 3.0 1.8 2.2 2.5 1.9 1.9 1.9 1.8 1.8 1.8
8 4.8 2.1 0.0 4.2 2.0 2.0 4.8 3.9 1.9 1.8
Input Cells
Symbol tIN tINI tIO tGCK tGCKHI tGCKLO Parameter High Drive Input Delay [6] High Drive Input, Inverting Delay [6] Input Delay (bidirectional pad) Clock Buffer Delay [7] Clock Buffer Min High [7] Clock Buffer Min Low [7] 1 2.1 2.1 1.4 2.7 2.0 2.0 Propagation Delays (ns) [4] 2 2.2 2.2 1.8 2.7 2.0 2.0 3 2.3 2.3 2.2 2.8 2.0 2.0 4 2.4 2.5 2.6 2.9 2.0 2.0 6 2.6 2.8 3.4 3.0 2.0 2.0 8 2.9 3.1 4.2
Output Cell
Symbol tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Parameter Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-state [8] Output Delay Low to Tri-state [8] 30 2.7 2.8 4.0 3.6 2.9 3.3 Propagation Delays (ns) [4] Output Load Capacitance (pF) 50 75 100 3.4 4.2 5.0 3.7 4.7 5.6 4.9 6.1 7.3 4.2 5.0 5.8 150 6.7 7.6 9.7 7.3
Notes: [6] See High Drive Buffer Table for more information. [7] Clock buffer fanout refers to the maximum number of flip flops per half column. The number of half columns used does not affect clock buffer delay. [8] The following loads are used for tPXZ:
8-15
Military 5.0V pASIC 1 Family
High Drive Buffer
Symbol Parameter Clock Drivers Wired Together 1 2 3 4 1 2 3 4 Propagation Delays (ns) [4] Fanout 12 24 48 72 96 4.0 4.9 3.5 5.0 4.0 4.8 5.6 4.1 4.8 4.2 5.1 3.7 5.2 4.2 5.0 5.8 4.3 5.0
tIN
High Drive Input Delay
tINI
High Drive Input, Inverting Delay
[4] Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range.
8-16 16
Preliminary
Military 5.0V pASIC 1 Family
QL12x16B
QL12X16B
AC CHARACTERISTICS at VCC = 5V, TA = 25C (K = 1.00)
Logic Cell
Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Parameter Combinatorial Delay [5] Setup Time [5] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1 1.7 2.1 0.0 1.0 2.0 2.0 1.7 1.5 1.9 1.8 Propagation Delays (ns) Fanout 2 3 4 2.2 2.6 3.2 2.1 2.1 2.1 0.0 0.0 0.0 1.5 1.9 2.5 2.0 2.0 2.0 2.0 2.0 2.0 2.1 2.6 3.2 1.9 2.2 2.7 1.9 1.9 1.9 1.8 1.8 1.8
8 5.2 2.1 0.0 4.6 2.0 2.0 5.2 4.3 1.9 1.8
Input Cells
Symbol tIN tINI tIO tGCK tGCKHI tGCKLO Parameter High Drive Input Delay [6] High Drive Input, Inverting Delay [6] Input Delay (bidirectional pad) Clock Buffer Delay [7] Clock Buffer Min High [7] Clock Buffer Min Low [7] 1 2.4 2.5 1.4 2.7 2.0 2.0 Propagation Delays (ns) [4] 2 2.5 2.6 1.9 2.8 2.0 2.0 3 2.6 2.7 2.2 2.8 2.0 2.0 4 2.7 2.8 2.8 2.9 2.0 2.0 6 3.0 3.1 3.7 2.9 2.0 2.0 8 3.3 3.4 4.6 3.0 2.0 2.0
Output Cell
Symbol tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Parameter Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-state [8] Output Delay Low to Tri-state [8] 30 2.7 2.8 4.0 3.6 2.9 3.3 Propagation Delays (ns) [4] Output Load Capacitance (pF) 50 75 100 3.4 4.2 5.0 3.7 4.7 5.6 4.9 6.1 7.3 4.2 5.0 5.8 150 6.7 7.6 9.7 7.3
Notes: [6] See High Drive Buffer Table for more information. [7] Clock buffer fanout refers to the maximum number of flip flops per half column. The number of half columns used does not affect clock buffer delay. [8] The following loads are used for tPXZ:
8-17
Military 5.0V pASIC 1 Family
High Drive Buffer
Symbol Parameter Clock Drivers Wired Together 1 2 3 4 1 2 3 4 Propagation Delays (ns) [4] Fanout 12 24 48 72 96 4.5 5.4 3.9 5.6 4.5 5.3 6.3 4.6 5.3 4.7 5.6 4.0 5.8 4.6 5.5 6.4 4.8 5.5
tIN
High Drive Input Delay
tINI
High Drive Input, Inverting Delay
[4] Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range.
8-18 18
Preliminary
Military 5.0V pASIC 1 Family
QL16x24B
QL16X24B
AC CHARACTERISTICS at VCC = 5V, TA = 25C (K = 1.00)
Logic Cell
Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Parameter Combinatorial Delay [5] Setup Time [5] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1 1.7 2.1 0.0 1.0 2.0 2.0 1.7 1.5 1.9 1.8 Propagation Delays (ns) Fanout 2 3 4 2.2 2.6 3.2 2.1 2.1 2.1 0.0 0.0 0.0 1.5 1.9 2.6 2.0 2.0 2.0 2.0 2.0 2.0 2.2 2.6 3.2 1.9 2.2 2.7 1.9 1.9 1.9 1.8 1.8 1.8
8 5.3 2.1 0.0 4.7 2.0 2.0 5.3 4.4 1.9 1.8
Input Cells
Symbol tIN tINI tIO tGCK tGCKHI tGCKLO Parameter High Drive Input Delay [6] High Drive Input, Inverting Delay [6] Input Delay (bidirectional pad) Clock Buffer Delay [7] Clock Buffer Min High [7] Clock Buffer Min Low [7] 1 2.8 3.0 1.4 2.7 2.0 2.0 Propagation Delays (ns) [4] 2 2.9 3.1 1.9 2.8 2.0 2.0 3 3.0 3.2 2.2 2.9 2.0 2.0 4 3.1 3.3 2.9 3.0 2.0 2.0 6 4.0 4.1 4.7 3.1 2.0 2.0 8 5.3 5.7 6.5 3.3 2.0 2.0
Output Cell
Symbol tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Parameter Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-state [8] Output Delay Low to Tri-state [8] 30 2.7 2.8 4.0 3.6 2.9 3.3 Propagation Delays (ns) [4] Output Load Capacitance (pF) 50 75 100 3.4 4.2 5.0 3.7 4.7 5.6 4.9 6.1 7.3 4.2 5.0 5.8 150 6.7 7.6 9.7 7.3
Notes: [6] See High Drive Buffer Table for more information. [7] Clock buffer fanout refers to the maximum number of flip flops per half column. The number of half columns used does not affect clock buffer delay. [8] The following loads are used for tPXZ:
8-19
Military 5.0V pASIC 1 Family
High Drive Buffer
Symbol Parameter Clock Drivers Wired Together 1 2 3 4 1 2 3 4 Propagation Delays (ns) [4] Fanout 12 24 48 72 96 5.3 6.7 4.5 6.6 5.3 6.2 7.2 5.4 6.2 5.7 7.2 4.6 6.8 5.5 6.4 7.4 5.6 6.4
tIN
High Drive Input Delay
tINI
High Drive Input, Inverting Delay
[4] Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range.
8-20 20
Preliminary
Military 5.0V pASIC 1 Family
QL24x32B
QL24X32B
AC CHARACTERISTICS at VCC = 5V, TA = 25C (K = 1.00)
Logic Cell
Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Parameter Combinatorial Delay [5] Setup Time [5] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1 1.7 2.1 0.0 1.0 2.0 2.0 1.7 1.5 1.9 1.8 Propagation Delays (ns) Fanout 2 3 4 2.1 2.7 3.3 2.1 2.1 2.1 0.0 0.0 0.0 1.5 1.9 2.7 2.0 2.0 2.0 2.0 2.0 2.0 2.2 2.7 3.3 1.9 2.3 2.8 1.9 1.9 1.9 1.8 1.8 1.8
8 5.5 2.1 0.0 4.9 2.0 2.0 5.5 4.6 1.9 1.8
Input Cells
Symbol tIN tINI tIO tGCK tGCKHI tGCKLO Parameter High Drive Input Delay [6] High Drive Input, Inverting Delay [6] Input Delay (bidirectional pad) Clock Buffer Delay [7] Clock Buffer Min High [7] Clock Buffer Min Low [7] 1 3.1 3.3 1.4 2.7 2.0 2.0 Propagation Delays (ns) [4] 2 3.2 3.4 1.9 2.8 2.0 2.0 3 3.3 3.5 2.3 2.9 2.0 2.0 4 3.4 3.6 3.0 3.0 2.0 2.0 8 4.4 4.6 4.8 3.1 2.0 2.0 12 5.8 6.0 6.7 3.3 2.0 2.0 16 6.5 6.7 8.5 3.4 2.0 2.0
Output Cell
Symbol tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Parameter Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-state [8] Output Delay Low to Tri-state [8] 30 2.7 2.8 2.1 2.6 2.9 3.3 Propagation Delays (ns) [4] Output Load Capacitance (pF) 50 75 100 3.3 3.8 4.3 3.6 4.5 5.3 2.6 3.1 3.7 3.3 4.1 4.9 150 5.4 6.9 4.8 6.5
Notes: [6] See High Drive Buffer Table for more information. [7] Clock buffer fanout refers to the maximum number of flip flops per half column. The number of half columns used does not affect clock buffer delay. [8] The following loads are used for tPXZ:
8-21
Military 5.0V pASIC 1 Family
High Drive Buffer
Symbol Parameter Clock Drivers Wired Together 1 2 3 4 1 2 3 4 Propagation Delays (ns) [4] Fanout 12 24 48 72 96 5.8 7.2 5.0 7.1 5.8 6.7 7.7 5.9 6.8 6.0 7.4 5.2 7.3 6.0 6.9 7.9 6.1 7.0
tIN
High Drive Input Delay
tINI
High Drive Input, Inverting Delay
[4] Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range.
AC Performance
Propagation delays depend on routing, fanout, load capacitance, supply voltage, junction temperature, and process variation. The AC Characteristics are a design guide to provide initial timing estimates at nominal conditions. Worst case estimates are obtained when nominal propagation delays are multiplied by the appropriate Delay Factor, K, as specified in the Delay Factor table (Operating Range). The effects of voltage and temperature variation are illustrated in the graphs on the following pages, K Factor versus Voltage and Temperature. The pASIC Development Tools incorporate data sheet AC Characteristics into the QDIF database for pre-place-and-route timing analysis. The SpDE Delay Modeler extracts specific timing parameters for precise path analysis or simulation results following place and route.
ORDERING INFORMATION
QL 24x32B - 1 CF208 M
QuickLogic pASIC device Operating Range M = Military M/883C = MIL STD 883
pASIC device part number B = 0.65 micron CMOS 8x12B 12x16B 16x24B 24x32B Speed Grade 0 = fast 1 = faster
Package Code CG68 = 68-pin CPGA CG84 = 84-pin CPGA CG144 = 144-pin CPGA CF160 = 160-pin CQFD PQ208 = 208-pin PQFP CF208 = 208-pin CQFP
8-22 22
Preliminary

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