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ACT15530
CMOS Manchester Encoder / Decoder
Features
* MIL-STD-1553 Compatible
CIRCUIT TECHNOLOGY
* 1.25 Megabit/sec Maximum Data Rate * Sync Identification and Lock-in * Clock Recovery * Manchester II Encode / Decode * Separate Encoder and Decoder Sections * Low Operating Power * Military Temperature Range -55C to +125C * Monolithic - Single Chip - Construction
Valid Word Encoder Shift Clock Take Data Serial Data Out Decoder Clock Bipolar Zero In Bipolar One In Unipolar Data In Decoder Shift Clock Command/Data Sync Decoder Reset VSS
1 2 3 4 5 6 7 8 9 10 11 12
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24 23 22 21 20 19 18 17 16 15 14 13
VDD Encoder Clock Send Clock In Send Data Sync Select Encoder Enable Serial Data In Bipolar One Out Output Inhibit Bipolar Zero Out / 6 Out Master Reset
Figure 1: Pin Assignments (24-Pin DIP/Flat Package - See Figure 18 for LCC Pkg)
* Available in Commercial and Industrial Temperature Ranges * Several Package and Quality Options (Consult Factory for Details) * Direct Replacement for the Obsolete Harris HD15530-9/-2/8 and GEC Plessey Marconi MA15530 / MAS15530 parts
1
General Description
The ACT15530 is a high performance CMOS integrated circuit used to implement MIL-STD-1553 and similar Manchester II encoded, time division multiplexed, serial data protocols. The device is divided into two independent sections, encoder and decoder, with a common master reset. The function of the encoder section is to produce the sync pulse and parity bit, and encode the data bits. The decoder section recognizes the sync pulse, decodes the data bits and checks for parity. The ACT15530 is fully guaranteed to support the 1 MHz data rate of MIL-STD-1553 over the full temperature and supply voltage ranges. The device interfaces with CMOS, TTL or N-Channel support circuitry and operates from a standard 5 volt supply. The circuit can also be used in many party line digital data communications applications where high reliability command and control signals are required. Using Aeroflex transceivers products (4400 Series) the Bit Error Rates (BER) and Word Error Rates (WER) of MIL-STD-1553 can be achieved (Refer to MIL-STD-1553 Multiplex Applications Handbook "MIL-HDBK-1553"). eroflex Circuit Technology - Data Bus Modules For The Future (c) SCD15330 REV B 7/28/99
12 13 22 14
Vss Master Reset Send Clock In VDD Output Inhibit
24 16
/ 6 Out /2 /6
Character Former
17 15
Bipolar One Out Bipolar Zero Out
23
Encoder Clock Bit Counter
21
Send Data
2
18
19
20
Sync Select
Send Data In Encoder Enable
Encoder Shift Clock
Note: All Pin designations are for 24-Pin DIP & Flatpak
Figure 2: Encoder Block Diagram
Unipolar Data In Bipolar One In Bipolar Zero In
8 7 6
Transition Finder Character Identifier
3 10 4
Take Data Command / Data Sync Serial Data Out
Decoder Clock
5
Synchronizer
Bit Rate Clock
Parity Check
1
Valid Word
Master Reset
13
9
Decoder Shift Clock
Decoder Reset
11
Bit Counter
Note: All Pin designations are for 24-Pin DIP & Flatpak
Figure 3: Decoder Block Diagram
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Pin Designations
Pin
1 2 3 4 5 6 7 8 9 10
Input
Output
Enc
Dec
Function
Valid word Encoder Shift Clock
Comment
A 'high' signals the receipt of a valid word Shifts data into the encoder on a 'low' to 'high' transition 'high' during data reception after the sync pulse is identified NRZ output of received data Clock for the transition finder and synchronizer which generates the clock for the rest of the decoder Should be 'high' when the bus is in a negative state. Must be tied 'high' when the unipolar input is used Should be 'high' when the bus is in a positive state. Must be tied 'low' when the unipolar input is used Input for unipolar data to the transition finder. Must be tied 'low' when not used Provides the DECODER CLOCK divided by 12, synchronized by the recovered serial data This output indicates the type of synchronizing character received as follows: If a data synchronizing character was received, this pin is low while the data is decoded. If a command synchronizing character was received, this pin is high during data decoding A 'high' during a DECODER SHIFT CLOCK rising edge resets the bit counter Ground A 'high" clears the counters in both sections Provides the ENCODER CLOCK divided by 6 Provides an active 'low' output to the zero or negative sense of a bipolar line driver A 'low' inhibits the BIPOLAR ZERO OUT and BIPOLAR ONE OUT by forcing them to inactive, 'high', states Provides an active 'low' output to the one or positive sense of a bipolar line driver Receives serial data at the rate of the ENCODER SHIFT CLOCK A 'high' starts the encode cycle provided that the previous cycle is complete A 'high' selects the command sync and a 'low' selects the data sync Provides an active 'high' to enable the external serial data source Clock input at 2 times the data rate Input to the divide by 6 circuit Positive Supply

Take Data Serial Data Out Decoder clock Bipolar Zero In Bipolar One In Unipolar Data In Decoder Shift Clock Command/Data Sync
11 12 13 14 15 16
- -

-
Decoder Reset VSS Master Reset

/ 6 Out
Bipolar Zero Out Output Inhibit
17 18 19 20 21 22 23 24
Bipolar One Out Serial Data In Encoder Enable Sync Select Send Data Send Clock In Encoder Clock

-
VDD
Figure 4: Pin Designations (24-Pin Dip/FlatPack)
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DC Characteristics and Ratings Absolute Maximum Ratings
Parameter
VDD Input Voltage Operating Temperature Storage Temperature
Min
3 Vss - 0.3 -55 -65
Max
7 VDD + 0.3V +125 +150
Units
V V C C
Figure 5: Absolute Maximum Ratings
DC Characteristics
Sym
VIH VIL VIHC VILC IIL VOH VOL IDDSB
Parameter
Logic "1" Input Voltage Logic "0" Input Voltage Logic "1" Input Voltage (Clock) Logic "0" Input Voltage (Clock) Input Leakage Current Logic "1" Output Voltage Logic "0" Output Voltage Standby Supply Current
Min
70%VDD VDD - 0.5V -1.0 2.4 -
Typ
-
Max
30%VDD VSS + 0.5V +1.0
Units
V V V V A V V mA
Test Conditions
0V < VIN < VDD IOH = -3 mA IOL = 1.8 mA Output Open VIN = VDD = 5.5V VDD = 5.5V, f = 1MHz
0.5
0.4 2.0
IDDOP CIN COUT
Operating Supply Current Input Capacitance Output Capacitance
-
8.0 5.0 8.0
10.0 7.0 10.0
mA pF pF
VDD = 5V 10%, over full operating temperature range.
Figure 6: DC Characteristics
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AC Characteristics
Sym
fEC fESC tECR tECF fED tMR tE1 tE2 tE3 tE4 tE5 tE6 tE7 tE8 tE9
Parameter Encoder clock frequency Send clock frequency Encoder clock rise time Encoder clock fall time Data rate Master reset pulse width Shift clock delay Serial data setup time Serial data hold time Enable setup time Enable pulse width Sync setup time Sync pulse width Send data delay Bipolar output delay
Min
0 0 0 150 75 75 90 100 55 150 0 -
Limits Max
15 2.5 8 8 1.25 125 50 130
Units
MHz MHz ns ns MHz ns ns ns ns ns ns ns ns ns ns Figure 7: Encoder Electrical Characteristics
1. VDD = 5V 10%, over full operating temperature range. 2. CL=50pF.
Sym
fDC tDCR tDCF fDD tDR tDRS tMR tD1 tD2 tD3 tD4 tD5 tD6 tD7 tD8 tD9 tD10 tD11
Parameter Decoder clock frequency Decoder clock rise time Decoder clock fall time Data rate Decoder reset pulse width Decoder reset setup time Master reset pulse width Bipolar data pulse width Sync transition span One-Zero overlap Short data transition span Long data transition span Sync delay (on) Take data delay (on) Serial data out delay Sync delay (off) Take data delay (off) Valid word delay
Limits Min
0 0 150 75 150 tDC + 10 -20 0 0 0 0
Typ
18tDC 6tDC 12tDC -
Max
15 8 8 1.25 tDC - 10 110 110 80 110 110 110
Units
MHz MHz ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 8: Decoder Electrical Characteristics
1. VDD = 5V 10%, over full operating temperature range. 2. CL=50pF. 3. tDC = Decoder clock period = 1/fDC
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Encoder Operation
The Encoder requires a single clock with a frequency of twice the desired data rate applied at the SEND CLOCK input. An auxiliary divide by six counter is provided on chip which can be utilised to produce the SEND CLOCK by dividing the DECODER CLOCK. The Encoder's cycle begins when ENCODER ENABLE is high during a failing edge of ENCODER SHIFT CLOCK x. This cycle lasts for one word length or twenty ENCODER SHIFT CLOCK periods. At the next low-to-high transition of the ENCODER SHIFT CLOCK, a high at SYNC SELECT input actuates a command sync or a low will produce a data sync for that word y. When the Encoder is ready to accept data, the SEND DATA output will go high and remain high for sixteen ENCODER SHIFT CLOCK periods z. During these sixteen periods the data should be clocked into the SERIAL DATA input with every low-high transition of the ENCODER SHIFT CLOCK z - {. After the sync and the Manchester II coded data are chip transmitted through the BIPOLAR ONE and BIPOLAR ZERO outputs, the Encoder adds on an additional bit which is the parity for that word |. At any time a low in OUTPUT INHIBIT input will force both bipolar outputs to a high state but will not affect the Encoder in any other way. To abort the Encoder transmission a positive pulse must be applied at MASTER RESET. Anytime after or during this pulse, a low to high transition on SEND CLOCK clears the internal counters and initializes the Encoder for a new word.
Timing
01
2
3
4
5
6
7
15 16 17 18 19
Send Clock Encoder Shift Clock Encoder Enable
Don't Care
Sync Select
Valid
Don't Care
Send Data
Serial Data In Bipolar One Out
15 14 13 12 11 10
32
1
0
1st
2nd
15 14 13 12 11
3
2
1
0
P
Half Half Bipolar Zero Out
Sync Sync 15 14 13 12 11
3
2
1
0
P
1
2
3
4
5
Figure 9: Encoder Operation
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Decoder Operation
The Decoder requires a single clock with a frequency of 12 times the desired data rate applied at the DECODER CLOCK input. The Manchester II coded data can be presented to the Decoder in one of two ways. The BIPOLAR ONE and BIPOLAR ZERO inputs will accept data from a comparator sensed transformer coupled bus as specified in MIL-STD-1553. The UNIPOLAR DATA input can only accept non-inverted Manchester II coded data (e.g.from BIPOLAR ZERO OUT of an Encoder). The Decoder is free running and continuously monitors its data input lines for a valid sync character and two valid Manchester data bits to start an output cycle.. When a valid sync is recognized x, the type of sync is indicated on COMMAND/DATA SYNC output. if the sync character was a command sync, this output will go high y and remain high for sixteen DECODER SHIFT CLOCK periods z, otherwise it will remain low. The TAKE DATA output will go high and remain high y - z while the Decoder is transmitting the decoded data through SERIAL DATA OUT. The decoded data available at SERIAL DATA OUT is in a NRZ format. The DECODER SHIFT CLOCK is provided so that the decoded bits can get shifted into an external register on every low-to-high transition of this clock y - z. After all sixteen decoded bits have been transmitted z the data is checked for odd parity. A high on VALID WORD output { indicates a successful reception of a word without any Manchester or parity errors. At this time the Decoder is looking for a new sync character to start another output sequence. At any time in the above sequence, a high input on DECODER RESET during a low-to-high transition of DECODER SHIFT CLOCK will abort transmission and initialize the Decoder to start looking for a new sync character.
Timing
0
12
3
4
5
6
7
8
16 17 18 19
Decoder Shift Clock Bipolar One In Bipolar Zero In 1st 2nd 15 14 13 12 11 10 Half Half
Sync Sync 15 14 13 12 11 10
2
1
0
P
2
1
0
P
Take Data Command/Data Sync
Serial Data Out
Undefined
15 14 13 12
4
3
2
1
0
Valid Word
(From Previous Reception)
1
2
3
4
Figure 10: Decoder Operation
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Send Clock
tE1
Encoder Shift Clock
tE2
Serial Data In Valid Valid
tE3
Send Clock
tE1
Encoder Shift Clock
tE4 tE6
Encoder Enable
tE5
Sync Select Valid
tE8
Encoder Shift Clock
tE7
Send Clock
tE9
Send Clock Bipolar One Out or Bipolar Zero Out
Figure 11: Encoder Timing Diagram
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ONE BIT PER.
ZERO BIT PER.
ONE BIT PER.
1/ Bipolar One In Command Sync 1/ Bipolar Zero In
tD1
tD2
tD3
tD3
tD2 tD1
1/ Bipolar One In Data Sync 1/ Bipolar Zero In
tD2
tD3
tD3
tD1
1/ Bipolar One In
tD2 tD3 tD3
tD3
1/ Bipolar Zero In
tD3
tD3
tD3
tD4
tD1 tD5
tD5
tD1 tD4 tD2
2/ Unipolar In Command Sync 2/ Unipolar In Data Sync 2/ Unipolar In
tD2
tD2
tD2 tD4
tD4
ONE
tD5
ZERO
tD5
ONE
tD4
ONE
Notes: 1. Unipolar In = 0 2. Bipolar One In = 0 Bipolar Zero In = 1
Figure 12: Decoder Timing Diagram
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tD7 tD6
Decoder Shift Clock
Command / Data Sync
Take Data
Decoder Shift Clock
tD8
Serial Data Out Data Bit
Decoder Shift Clock
tD9
Command / Data Sync
tD10 tD11
Take Data
Valid Word
Decoder Shift Clock
tDRS
Decoder Reset
tDR
Figure 13: Decoder Timing Details
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Command Sync
Data Sync Bit Period Bit Period Bit Period
Logical One Data
Logical Zero Data
Figure 14: Character Formats
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Command Word (From Controller to Terminal) 5 1 5 5 1
Sync
Terminal Address
R/T
Subaddress Mode
Data Word Count
P
Data Word (Sent Either Direction) 16 1
Sync
Data Word
P
Status Word (From Terminal to Controller) 5 1 9 1 1
Sync
Terminal Address
ME
Code for Failure Modes
TF
P
Figure 15: Word Formats
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D
Pin 1 Notch
e
W
ME
Seating Plane A A1 H 0-15 Alernative Pin Shapes b c e1 0-15
Valid Word Encoder Shift Clock Take Data Serial Data Out Decoder Clock Bipolar Zero In Bipolar One In Unipolar Data In Decoder Shift Clock Command/Data Sync Decoder Reset VSS
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VDD Encoder Clock Send Clock In Send Data Sync Select Encoder Enable Serial Data In Bipolar One Out Output Inhibit Bipolar Zero Out / 6 Out Master Reset
Ref.
A A1
Min. 0.38 (0.015) 0.35 (0.014) 0.20 (0.008) 4.71 (0.185) -
Nom. 2.54 (0.100) Typ 15.24 (0.600) Typ -
Max. 5.60 (0.220) 1.53 (0.060) 0.59 (0.023) 0.36 (0.014) 30.79 (1.212) 5.38 (0.212) 15.90 (0.626) 1.53 (0.060)
b c D e e1 H ME W
Dimensions in mm (inches)
Figure 16: 24-Lead Ceramic DIL (Solder Seal) - Package Style C
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M
b
D
Z e L A c
ME
A1
Ref.
A A1
Min. 0.25 (0.010) 0.38 (0.015) 0.10 (0.004) 14.86 (0.585) 6.73 (0..265) 9.91 (0.390) 7.6 (0.30) 0.13 (0.005)
Nom. 1.275 (0.050) -
Max. 2.67 (0.105) 1.02 (0.040) 0.48 (0.019) 0.18 (0.007) 15.62 (0615) 7.75 (0.305) 10.41 (0.410) 1.14 (0.045)
b c
Pin 1 Index
D e L M ME Z
Dimensions in mm (inches)
VDD Encoder Clock Send Clock In Send Data Sync Select Encoder Enable Serial Data In Bipolar One Out Output Inhibit Bipolar Zero Out / 6 Out Master Reset
24 23 22 21 20 19 18 17 16 15 14 13
1 2 3 4 5
Bottom View
6 7 8 9 10 11 12
Valid Word Encoder Shift Clock Take Data Serial Data Out Decoder Clock Bipolar Zero In Bipolar One In Unipolar Data In Decoder Shift Clock Command/Data Sync Decoder Reset VSS
Figure 17: 24-Lead Ceramic Flatpack (Solder Seal) - Package Style CF
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TOP VIEW
ENCODER SHIFT CLK
SERIAL DAA OUT
ENCODER CLK
4 DECODER CLK 5 NC 6 NC 7 BIPOLAR ZERO IN 8 BIPOLAR ONE IN 9 UNIPOLAR DATA IN 10 DECODER SHIFT CLOCK 11 12 COMMAND / DATA SYNC
3
2
1
28 27 26 25 SEND DATA 24 NC 23 NC 22 SYNC SELECT 21 ENCODER ENABLE 20 SERIAL DATA IN 19 BIPOLAR ONE OUT
13 14 15 16 17 18 DECODER RESET MASTER RESET OUTPUT INHIBIT 6 OUT BIPOLAR ZERO OUT GROUND
BOTTOM VIEW
.003 .015 .075 .095
.006 .022 .442 .458 .022 .028 .045 .055 .015
MIN
.050
/
SEND CLK IN
VALID WORD
TAKE DATA
Vcc
BSC
.442 .458 .090
MAX
.074 .088
Figure 18: 28-Leadless Ceramic Chip Carrier - Package Style L
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CIRCUIT TECHNOLOGY
Ordering Information
Model Number
ACT15530XX
Part Number
See Below or Contact Factory
Part Number Breakdown
ACT15530 X X
Package Type C Ceramic DIL (Figure 16) CF Flatpack (Figure 17) L LCC (Figure 18) N Naked Die * P Plastic DIP *
Rel Level B Class B Operating Temperature (Figure 5) -55C to +125C C Commercial (0C to+70C) I Industrial (-40C to +85C) S Space *
* Contact Factory for Details
Aeroflex Circuit Technology 35 South Service Road Plainview New York 11803
Specifications subject to change without notice.
Aeroflex Circuit Technology
Telephone: (516) 694-6700 FAX: (516) 694-6715 Toll Free Inquiries: 1-(800)THE-1553
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