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| w w at .D w Sh a ee 4U t omAgilent HPFC-5000 Tachyon .c Fibre Channel Interface Controller Product Brief Internal Block Diagram The Internal Block Diagram in Figure 1 below shows the high-level chip architecture for Tachyon. Inbound Message Queue Inbound Data MFS SFS Buffer Buffer Queue Queue Outbound Host-Based Data Structures Command Queue SCSI Exchange State Table High-Priority Command Queue Backplane Interface Inbound Block Mover Inbound Message Channel Inbound SFS and MFS Buffer Channels SCSI Read/Write Channel Inbound Data Manager Inbound Data FIFO Receive w Inbound Sequence Manager w .D w SCSI Buffer Manager ACKs ACKs Loop/N_Port State Machine FCP Assists SCSI Exchange Manager t a ACK FIFO Outbound Message Channel S a Outbound Sequence Manager High Priority Message Channel e h Outbound Data t e U 4 Description Tachyon is a fundamental building block compatible with Agilent Technologies' Fibre Channel solution which includes interface controllers, physical link modules, adapters, switches and disk drives. .c m o The Tachyon architecture supports both networking and mass storage connections to provide a low cost, high performance solution with low host overhead. Specifications * System clock frequency: 20 - 40 MHz backplane operation * Testability: Full internal scan path IEEE Standard 1149.1 boundary scan * Packaging: 208-pin metal quad flat pack * Standards: Intended to be compliant with ANSI standards and FCSI/FCA profile definitions Outbound Block Mover Sequence Management Outbound Frame FIFO Transmit OS/CRC Generator 16B/20B Encoder 20B/10B MUX OS Processor CRC Checker Elastic Store/ Smoothing Buffer 20B/16B Decoder 10B/20B De-MUX Link Figure 1. w w w .D a aS t ee h 4U t om .c Features * Single chip Fibre Channel interface (no I/O processor required) * Supports 1062, 531 and 266 Mbaud links * Supports 3 topologies - direct connect, fabric and Fibre Channel Arbitrated Loop (FC-AL) * Supports Fibre Channel Class 1, 2 and 3 services * Supports up to 2 Kbyte frame payload for all classes of service * Sequence segmentation/reassembly in hardware * Automatic ACK frame generation and processing * On-chip support of FCP for SCSI initiators and targets * Supports up to 16384 concurrent SCSI I/O transactions * Compliant with Internet MIB-II network management * Direct interface to industry standard 10 and 20-bit Gigabit Link Module (GLM) * Hardware assists for TCP/UDP/IP networking * Parity protection on internal data path * Eight internal DMA channels * Full duplex internal architecture that allows Tachyon to process inbound and outbound data simultaneously Pin-out Block Diagram Figure 2 below shows the pin-out block diagram for Tachyon. TACHYON Backplane Interface TAD [31..0] PARITY AVCS_L RBC TYPE [2..0] READY_L COM_DET L_UNUSE LCKREF_L Gigabit Link Module Interface PAR_ID [1..0] RX [19..0] Gigabit Link Module Receive Backplane PREFETCH_L RETRY_L ERROR_L INT_L RESET_L TBR_L [1..0] TBG_L SCLK EWRAP FAULT TX [19..0] Transmit Scan Test Interface TDI TDO TCK TRST TMS TBC TXCLK_SEL Clock Generator Figure 2. System Adapter Card Block Diagram Figure 3 below shows an example of a Tachyon on a generic host bus adapter. Backplane Interface TACHYON Gigabit Link Module CLK Figure 3. www.semiconductor.agilent.com Data subject to change. Copyright (c) 2001 Agilent Technologies, Inc. Obsoletes 5965-1215 April 25, 2001 5988-2605EN |
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