View KMM372C803CK_424201.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DRAM MODULE
KMM372C80(8)3CK/CS
KMM372C80(8)3CK/CS Fast Page Mode 8Mx72 DRAM DIMM with ECC Using 8Mx8, 4K & 8K Refresh, 5V
GENERAL DESCRIPTION
The Samsung KMM372C80(8)3C is a 8Mx72bits Dynamic RAM high density memory module. The Samsung KMM372C80(8)3C consists of nine CMOS 8Mx8bits DRAMs in SOJ/TSOP-II 400mil packages and two 16 bits driver IC in TSSOP package mounted on a 168-pin glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The KMM372C80(8)3C is a Dual In-line Memory Module and is intended for mounting into 168 pin edge connector sockets.
FEATURES * Part Identification
Part number KMM372C803CK KMM372C803CS KMM372C883CK KMM372C883CS * * * * * * * * PKG SOJ TSOP SOJ TSOP 8K 4K/64ms 8K/64ms Ref. 4K CBR Ref. ROR Ref. 4K/64ms
PERFORMANCE RANGE
Speed -5 -6
tRAC
50ns 60ns
tCAC
18ns 20ns
tRC
90ns 110ns
tPC
35ns 40ns
Fast Page Mode Operation CAS-before-RAS Refresh capability RAS-only and Hidden refresh capability TTL compatible inputs and outputs Single 5V10% power supply JEDEC standard pinout & Buffered PDpin Buffered input except RAS and DQ PCB : Height(1250mil), single sided component
PIN CONFIGURATIONS
Pin Front Pin Front Pin Front 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 DQ16 DQ17 VSS RSVD RSVD VCC W0 CAS0 29 *CAS2 57 30 RAS0 58 31 OE0 59 60 VSS 32 61 A0 33 62 A2 34 63 A4 35 64 A6 36 A8 65 37 66 A10 38 67 A12 39 68 VCC 40 41 RFU 69 42 RFU 70 71 43 VSS OE2 72 44 45 RAS2 73 46 CAS4 74 47 *CAS6 75 76 48 W2 77 49 VCC 50 RSVD 78 51 RSVD 79 52 DQ18 80 53 DQ19 81 82 54 VSS 55 DQ20 83 56 DQ21 84 DQ22 DQ23 VCC DQ24 RFU RFU RFU RFU DQ25 DQ26 DQ27 VSS DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 DQ35 VSS PD1 PD3 PD5 PD7 ID0 VCC Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS DQ36 DQ37 DQ38 DQ39 VCC DQ40 DQ41 DQ42 DQ43 DQ44 VSS DQ45 DQ46 DQ47 DQ48 DQ49 VCC DQ50 DQ51 DQ52 DQ53 VSS RSVD RSVD VCC RFU *CAS1 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back *CAS3 *RAS1 RFU VSS A1 A3 A5 A7 A9 A11 *A13 VCC RFU B0 VSS RFU *RAS3 *CAS5 *CAS7 PDE VCC RSVD RSVD DQ54 DQ55 VSS DQ56 DQ57 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back DQ58 DQ59 VCC DQ60 RFU RFU RFU RFU DQ61 DQ62 DQ63 VSS DQ64 DQ65 DQ66 DQ67 VCC DQ68 DQ69 DQ70 DQ71 VSS PD2 PD4 PD6 PD8 ID1 VCC
PIN NAMES
Pin Names A0, B0, A1 - A11 A0, B0, A1 - A12 DQ0 - DQ71 W0, W2 OE0, OE2 RAS0, RAS2 CAS0, CAS4 VCC VSS NC PDE PD1 - 8 ID0 - 1 RSVD RFU Function Address Input(4K ref.) Address Input(8K ref.) Data In/Out Read/Write Enable Output Enable Row Address Strobe Column Address Strobe Power(+5V) Ground No Connection Presence Detect Enable Presence Detect ID bit Reserved Use Reserved for Future Use
Pins marked * are not used in this module.
PD & ID Table
Pin PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0 50NS 1 0 1 1 0 0 0 0 0 60NS 1 0 1 1 0 1 1 0 0 0
NOTE : A12 is used for only KMM372C883CK/CS (8K Ref.)
ID1 0 PD Note :PD & ID Terminals must each be pulled up through a resistor to VCC at the next higher level assembly. PDs will be either open (NC) or driven to VSS via on-board buffer circuits. PD : 0 for Vol of Drive IC & 1 for N.C ID Note : IDs will be either open (NC) or connected directly to VSS without a buffer. ID : 0 for Vss & 1 for N.C
DRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
RAS0 W0 OE0 CAS0 A0 A1-A11(A12) DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 RAS2 W2 OE2 CAS4 B0 A1-A11(A12)
KMM372C80(8)3CK/CS
U0
U5
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
U1
U6
U2
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
U7
U3
U8
DQ64 DQ65 DQ66 DQ67 DQ68 DQ69 DQ70 DQ71
Vcc 0.1 or 0.22uF Capacitor under each DRAM Vss To all DRAMs
U4
NOTE : A12 is used for only KMM372C880CK/CS(8K Ref.)
A0 B0 A1-A11(A12) W0, OE0 W2, OE2
U0-U4 U5-U8 U0-U8 U0-U4 U5-U8
DRAM MODULE
ABSOLUTE MAXIMUM RATINGS *
Item Voltage on any pin relative VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN, VOUT VCC Tstg PD IOS
KMM372C80(8)3CK/CS
Rating -1 to +7.0 -1 to +7.0 -55 to +125 9 50 Unit V V C W mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70C)
Item Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.4 -1.0*2 Typ 5.0 0 Max 5.5 0 VCC*1 0.8 Unit V V V V
*1 : VCC+2.0V at pulse width20ns, which is measured at VCC. *2 : -2.0V at pulse width20ns, which is measured at VSS.
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
Symbol ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 II(L) IO(L) VOH VOL Speed -5 -6 Dont care -5 -6 -5 -6 Dont care -5 -6 Dont care Dont care KMM372C803CK/CS Min
--
KMM372C883CK/CS Min -10 -5 2.4 Max 810 720 100 810 720 540 450 30 810 720 10 5 0.4
Max 1080 990 100 1080 990 630 540 30 1080 990 10 5 0.4
Unit mA mA mA mA mA mA mA mA mA mA uA uA V V
-10 -5 2.4 -
ICC1*: Operating Current * (RAS, CAS, Address cycling @tRC=min) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3*: RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min) ICC4*: Fast Page Mode Current * (RAS=VIL, CAS cycling : tPC=min) ICC5 : Standby Current (RAS=CAS=W=Vcc-0.2V) ICC6*: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min) I(IL) : Input Leakage Current (Any input 0VINVcc+0.5V, all other pins not under test=0 V) I(OL) : Output Leakage Current(Data Out is disabled, 0VVOUTVcc) VOH : Output High Voltage Level (IOH = -5mA) VOL : Output Low Voltage Level (IOL = 4.2mA) * NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one Fast page mode cycle time, tPC.
DRAM MODULE
CAPACITANCE (TA = 25C, f = 1MHz)
Item Input capacitance[A0, B0, A1 - A12] Input capacitance[W0, W2, OE0, OE2] Input capacitance[RAS0, RAS2] Input capacitance[CAS0, CAS4] Input/Output capacitance[DQ0 - 71] Symbol CIN1 CIN2 CIN3 CIN4 CDQ Min
-
KMM372C80(8)3CK/CS
Max 20 20 45 20 17 Unit pF pF pF pF pF
AC CHARACTERISTICS (0CTA70C, VCC=5.0V10%. See notes 1,2.)
Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V, output loading CL=100pF Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay Transition time(rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold referencde to CAS Read command hold referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data in set-up time Data in hold time Refresh period(4K & 8K) Write command set-up time CAS to W delay time Column address to W delay time CAS prechange to W delay time RAS ro W delay time Symbol -5 Min 90 133 50 18 30 5 5 1 30 50 18 45 13 18 13 10 5 8 0 10 30 0 0 -2 10 10 20 13 -2 15 64 0 36 48 53 73 0 40 55 60 85 10K 32 20 10K 18 50 5 5 1 40 60 20 55 15 18 13 10 5 8 0 10 35 0 0 -2 10 10 20 15 -2 15 64 10K 40 25 10K 20 50 Max Min 110 155 60 20 35 -6 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns 7 7 7 7 7,11 9,11 9,11 11 8 8,11 11 4,11 10,11 11 11 11 11 11 3,4 3,4,5,11 3,10,11 3,11 6,11 2 Note
tRC tRWC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS tDH tREF tWCS tCWD tAWD tCPWD tRWD
DRAM MODULE
AC CHARACTERISTICS (0CTA70C, VCC=5.0V10%. See notes 1,2.)
Parameter CAS setup time(CAS-before-RAS refresh) CAS hold time(CAS-before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Fast page mode cycle time Fast page mode read-modify-write cycle time CAS precharge time(Fast page cycle) RAS pulse width(Fast page cycle) RAS hold time from CAS precharge W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time Present Detect Read Cycle PDE to Valid PD bit PDE to PD bit Inactive Symbol -5 Min 10 8 3 35 35 76 10 50 35 15 8 18 18 5 13 18 200K Max
KMM372C80(8)3CK/CS
-6 Min 10 8 3 40 40 85 10 60 40 15 8 20 20 5 15 20 200K Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 11 11 11 11 11 11 Note 11 11 11 3,11
tCSR tCHR tRPC tCPA tPC tPRWC tCP tRASP tRHCP tWRP tWRH tOEA tOED tOEZ tOEH
tPD tPDOFF
10 2 7 2
10 7
ns ns
NOTES
1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCDtRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 7. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameter. They are included in the data sheet as electrical characteristics only. If tWCStWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. If tRWDtRWD(min), tCWDtCWD(min), tAWDtAWD(min) and tCPWDtCPWD(min). The cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of data out(at access time) is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to the CAS leading edge in early write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 11. The timing skew from the DRAM to the DIMM resulted from the addition of buffers.
DRAM MODULE
READ CYCLE
KMM372C80(8)3CK/CS
tRC tRAS
RAS VIH VIL -
tRP
tCSH tCRP
CAS VIH VIL -
tRCD
tRSH tCAS tRAL tCAH
COLUMN ADDRESS
tCRP
tRAD tASR
A VIH VIL -
tRAH
tASC
ROW ADDRESS
tRCS
W VIH VIL -
tRCH tRRH tOFF tAA tOEZ tOEA tCAC
OE
VIH VIL -
DQ
VOH VOL -
tRAC OPEN
tCLZ
DATA-OUT
Dont care Undefined
DRAM MODULE
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
KMM372C80(8)3CK/CS
tRAS
RAS VIH VIL -
tRC
tRP
tCSH tCRP
CAS VIH VIL -
tRCD
tRSH tCAS tRAL tCAH
COLUMN ADDRESS
tCRP
tRAD tASR
A VIH VIL -
tRAH
tASC
ROW ADDRESS
tCWL tRWL tWCS
W VIH VIL -
tWCH tWP
OE
VIH VIL -
tDS
DQ VIH VIL -
tDH
DATA-IN
Dont care Undefined
DRAM MODULE
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
KMM372C80(8)3CK/CS
tRC tRAS
RAS VIH VIL -
tRP
tCSH tCRP
CAS VIH VIL -
tRCD tRAD
tRSH tCAS tRAL tCAH
COLUMN ADDRESS
tCRP
tASR
A VIH VIL -
tRAH
tASC
ROW ADDRESS
tCWL tRWL
W VIH VIL -
tWP
OE
VIH VIL -
tOED tDS
tOEH tDH
DATA-IN
DQ
VIH VIL -
Dont care Undefined
DRAM MODULE
READ - MODIFY - WRTIE CYCLE
KMM372C80(8)3CK/CS
tRWC tRAS
RAS VIH VIL -
tRP
tCRP
CAS VIH VIL -
tRCD tRAD tRAH
tRSH tCAS tCAH tCSH
tASR
VIH VIL -
tASC
COLUMN ADDRESS
A
ROW ADDR
tAWD tCWD
W VIH VIL -
tRWL tCWL tWP
OE
VIH VIL -
tRWD tOEA tCLZ tCAC tAA tOED tOEZ
VALID DATA-OUT
tDS
tDH
DQ
VI/OH VI/OL -
tRAC
VALID DATA-IN
Dont care Undefined
DRAM MODULE
FAST PAGE READ CYCLE
NOTE : DOUT = OPEN
KMM372C80(8)3CK/CS
tRASP
RAS VIH VIL o
tRP tRHCP
tCRP
CAS VIH VIL -
tPC tRCD tCAS tRAD tASC tCSH tCAH
COLUMN ADDRESS
tCP tCAS
o
tCP
tRSH tCAS
tASR
A VIH VIL ROW ADDR
tRAH
tASC
tCAH
o o
tASC
tCAH
COLUMN ADDRESS
COLUMN ADDRESS
tRRH tRCS
W VIH VIL -
tRCH
tRCS
o
tRCS
tRCH
tCAC tOEA
OE VIH VIL -
tCAC tOEA
o o
tCAC tOEA
tAA tRAC tCLZ tOEZ
VALID DATA-OUT
tAA tOFF tCLZ
tOEZ
VALID DATA-OUT
tAA tOFF tCLZ
VALID DATA-OUT
tOFF tOEZ
DQ
VOH VOL -
Dont care Undefined
DRAM MODULE
FAST PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
KMM372C80(8)3CK/CS
tRASP
RAS VIH VIL o
tRP tRHCP
tCRP
CAS VIH VIL -
tPC tRCD tCAS tRAD tASC tCP
tPC tCP tCAS
o
tRSH tCAS
tASR
A VIH VIL -
tRAH
tCSH tCAH
COLUMN ADDRESS
tASC
tCAH
o o
tASC
tCAH
ROW ADDR
COLUMN ADDRESS
COLUMN ADDRESS
tWCS
W VIH VIL -
tWCH tWP tCWL
tWCS tWP
tWCH
o
tWCS
tWCH tWP tCWL tRWL
tCWL
o o
OE
VIH VIL -
tDS
DQ VIH VIL -
tDH
tDS
tDH
o
tDS
tDH
VALID DATA-IN
VALID DATA-IN
VALID DATA-IN
o
Dont care Undefined
DRAM MODULE
FAST PAGE READ - MODIFY - WRITE CYCLE
KMM372C80(8)3CK/CS
tRASP
RAS VIH VIL -
tRP
tCSH tRCD tRSH tCP tCAS tRAD tRAH tASR tASC
COL. ADDR
tCRP tCAS tPRWC
CAS
VIH VIL -
tCAH
tRAL tASC
COL. ADDR
tCAH
A
VIH VIL -
ROW ADDR
tRCS
W VIH VIL -
tRWL tCWL tWP tCWD tAWD tRWD tOEA tOED tCAC tAA tOEZ tDH tDS tCWD tAWD tCPWD tOEA tCAC tAA tOEZ tOED tDH tDS tCWL tWP
OE
VIH VIL -
tRAC
DQ VI/OH VI/OL -
tCLZ
VALID DATA-OUT
tCLZ
VALID DATA-IN VALID DATA-OUT VALID DATA-IN
Dont care Undefined
DRAM MODULE
RAS - ONLY REFRESH CYCLE
NOTE : W, OE, DIN = Dont care DOUT = OPEN tRC
KMM372C80(8)3CK/CS
tRAS
RAS VIH VIL -
tRP
tCRP
CAS VIH VIL -
tRPC
tCRP
tASR
A VIH VIL ROW ADDR
tRAH
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE, A = Dont care tRC tRP
RAS VIH VIL -
tRAS
tRP
tRPC tCP tRPC tCSR tWRP tWRH tCHR
CAS
VIH VIL -
W
VIH VIL -
tOFF
DQ VOH VOL -
OPEN
Dont care Undefined
DRAM MODULE
HIDDEN REFRESH CYCLE ( READ )
KMM372C80(8)3CK/CS
tRC tRAS
RAS VIH VIL -
tRC tRP tRAS tRP
tCRP
CAS VIH VIL -
tRCD
tRSH
tCHR
tRAD tASR
A VIH VIL -
tRAH
tASC
tCAH
COLUMN ADDRESS
ROW ADDRESS
tWRH tRCS
W VIH VIL -
tRRH
tWRP
tAA
OE VIH VIL -
tOEA tCAC tRAC tCLZ tOEZ
DATA-OUT
tOFF
DQ
VOH VOL -
OPEN
Dont care Undefined
DRAM MODULE
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
KMM372C80(8)3CK/CS
tRC
RAS VIH VIL -
tRC tRP tRAS tRP
tRAS
tCRP
CAS VIH VIL -
tRCD tRAD
tRSH
tCHR
tASR
A VIH VIL -
tRAH
tASC
tCAH
COLUMN ADDRESS
ROW ADDRESS
tWRH tWRP
W VIH VIL -
tWCS tWP
tWCH
OE
VIH VIL -
tDS
DQ VIH VIL -
tDH
DATA-IN
Dont care Undefined
DRAM MODULE
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
KMM372C80(8)3CK/CS
tRP
RAS
VIH VIL VIH VIL -
tRAS tCPT tCHR tRSH tCAS tRAL tASC tCAH
tCSR
CAS
A
VIH VIL -
COLUMN ADDRESS
READ CYCLE
W VIH VIL VIH VIL VOH VOL -
tWRP
tWRH
tAA tRCS tCAC
tRRH tRCH
OE
tCLZ
tOEA
tOEZ
DATA-OUT
tOFF
DQ
WRITE CYCLE
W VIH VIL VIH VIL -
tWRP
tWRH tWCS
tRWL tCWL tWCH tWP
OE
tDS
DQ VIH VIL -
tDH
DATA-IN
READ-MODIFY-WRITE
tWRP
W VIH VIL -
tWRH
tRCS
tAWD tCWD tCAC tWP
tCWL tRWL
tAA tOEA
OE VIH VIL -
tOED tCLZ tOEZ tDS
tDH
DQ
VI/OH VI/OL VALID DATA-OUT VALID DATA-IN
Dont care NOTE : This timing diagram is applied to all devices besides 16M DRAM 4th & 64M DRAM. Undefined
DRAM MODULE
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Dont care
KMM372C80(8)3CK/CS
tRP
RAS VIH VIL -
tRASS
tRPS tRPC tCHS
tRPC tCP
CAS
VIH VIL -
tCSR
tOFF
DQ VOH VOL -
OPEN tWRP tWRH
W
VIH VIL -
TEST MODE IN CYCLE
NOTE : OE, A = Dont care
tRC tRP
RAS VIH VIL -
tRAS
tRP
tRPC tCP tRPC tCSR tWTS tWTH tCHR
CAS
VIH VIL -
W
VIH VIL -
tOFF
DQ VOH VOL -
OPEN
Dont care Undefined
DRAM MODULE
PACKAGE DIMENSIONS
KMM372C80(8)3CK/CS
Units : Inches (millimeters)
5.250 (133.350) 0.118 (3.000) 5.014 (127.350)
0.054 (1.372)
R 0.079 (R 2.000) 0.1570.004 (4.0000.100)
(31.75)
1.250
0.118 (3.000)
.118DIA.004 (3.000DIA.100) 0.350 (8.890)
0.250 (6.350) .450 (11.430) 1.450 (36.830) 4.550 (115.57)
0.250 (6.350) 2.150 (54.61)
( Front view )
0.100Max (2.54Max) TSOPII 0.200Max (5.08Max) SOJ (4.19 Min) 0.165 Min
(2.540Min)
0.100Min
A
B
C
(17.780) 0.0500.0039 (1.2700.10) 0.01Max (0.25 Max)
( Back view )
0.250 (6.350)
0.250 (6.350)
(2.540 Min)
0.100 Min
0.1230.0050 (3.125.125)
0.1230.0050 (3.125.125)
0.079.0040 (2.000.100)
0.079.0040 (2.000.100)
0.050 (1.270)
Detail A
Detail B
Detail C
Tolerances : .005(.13) unless otherwise specified The used device is 8Mx8 DRAM with Fast Page mode, SOJ or TSOP II. DRAM Part No. : KMM372C803CK/CS - KM48C8100CK, KM48C8100CS KMM372C883CK/CS - KM48C8000CK, KM48C8000CS
0.700
0.039.002 (1.000.050)

▲Up To Search▲

Price & Availability of KMM372C803CK

	To Download KMM372C803CK Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .