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CH7203
CHRONTEL
MPEG to TV Encoder with 16-bit Input
Features
* * * * * * * * * * * * * * Outputs to NTSC, PAL (B, D, G, H, I) and PAL-60 16-bit YCrCb (4:2:2) input format Simultaneous composite/S-video outputs Triple 9-bit video DACs 27 MHz DAC operating frequency eliminates the need for 1/sinc(x) correction filter Low-jitter phase-locked loop circuitry operates using a low-cost 14.31818 MHz crystal 40.5 or 33.9 MHz video decoder clock output 16.934 or 11.289 MHz audio decoder clock output 13.5 MHz and 27 MHz video pixel clock outputs Optimized luminance and chrominance internal filters for NTSC and PAL HSYNC* and VSYNC* outputs for master mode operation Sleep mode CMOS technology in 44-pin PLCC 5V single-supply operation
Description
The CH7203 video encoder integrates a dual PLL clock generator and a digital NTSC/PAL video encoder. By generating all essential clock signals for MPEG playback, and converting digital video inputs to either NTSC or PAL video signals, the CH7203 is an essential component of any low-cost solution for video-CD playback machines. The CH7203 dual PLL clock synthesizer generates all clocks and timing signals from a 14.31818 MHz reference crystal (see application note 19 "Tuning Clock Outputs" for selection and tuning of the 14.31818 MHz crystal). The CH7203 generates a 40.5 or 33.9 MHz video decoder clock, 13.5 MHz and 27 MHz video pixel clocks, and a 16.934 or 11.289 MHz audio decoder clock. Timing signals from the PLLs are used to generate the horizontal and vertical sync signals which enable operating the CH7203 in master mode. The fully digital video encoder is pin-programmable to generate either a 525-line NTSC or a 625-line PAL compatible video signal. It also features a logic selectable sleep mode which turns the encoder off while leaving both PLL's running.
MOD 0
MOD 1
FS
C RSEN*
CR S
VDD
AVDD
R SET
IREF
BL AN KING H ,V SYNC GEN ERATO R
Y FILTER
M U X
9
DAC
Y
Y[7 :0], C[7:0 ]
16
I NTE RFACE L INE AR INTE RP OLATO R
U FILTER M U X
9
DAC
CVB S
H SYNC* VSYNC*
S TAT E M ACHI NE
X
9
DAC
C
PC LK 2XPC LK DC LK
1/ 2
PLL1
V FILTER
M U X
X
S IN + COSINE GENERATOR
B LA NKIN G
A CLK
PLL2
OSC
COL O R-B URST CO NT RO L
XI
XO/FIN
GN D
A GN D
Figure 1: Functional Block Diagram
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CHRONTEL
CH7203
2XPCLK
XO/FIN
AGND
ACLK
DCLK 41
AVDD
GND
6
5
4
3
2
1
44
43
42
CRSEN* FS MOD1 CRS C[7] C[6] C[5] C[4] C[3] C[2] C[1]
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
40 39 38 37 36
GND
VDD
VDD
XI
PCLK MOD0 VSYNC* VDD HSYNC* GND GND Y CVBS C AVDD
CHRONTEL CH7203
35 34 33 32 31 30 29
Figure 2: CH7203 Pinout Diagram
2
AGND
RSET
C[0]
Y[7]
Y[6]
Y[5]
Y[4]
Y[3]
Y[2]
Y[1]
Y[0]
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Table 1. Pin Descriptions
Pin 1 Type Out S ymbol ACLK Description
CH7203
Audio Decoder Clock Output 16.934 MHz or 11.289 MHz clock output (selectable by FS) for MPEG audio decoder operation. The output swing is 5V. Digital Supply Voltage These pins supply the 5V power to the digital section of the CH7203. Crystal Output or External F REF Input 1 A 14.31818 MHz ( 50 ppm) parallel resonance crystal may be attached between XO/FIN and XI. An external CMOS compatible clock can be connected to XO/FIN as an alternative. Crystal Input 1 A 14.31818 MHz ( 50 ppm) parallel resonance crystal should be attached between XI and XO/FIN. However, if an external CMOS clock is attached to XO/FIN, XI should be connected to ground. Analog ground These pins provide the ground reference for the analog section of the CH7203. These pins MUST be connected to the system ground to prevent latchup. Analog Supply Voltage These pins supply the 5V power to the analog section of the CH7203. Cr Select Enable. Internally pulled-up. CRSEN*=0, Cr, Cb data sequence is specified by the CRS pin. CRSEN*=1, Cr, Cb data sequence is specified by the CH7203's internal default condition: Horizontal count = even, data is Cb; data is Cr otherwise. State of CRS is ignored when CRSEN*=1. See Figure 6 on page 7. Frequency Select. Internally pulled-up FS = 1 (default), then DCLK = 40.5 MHz, ACLK = 16.934 MHz FS = 0, then DCLK = 33.9 MHz, ACLK = 11.289 MHz Mode bit 1 - Internally pulled-up This input works in conjunction with the MOD0 input to select NTSC, PAL, or Sleep mode functions. Refer to Table 3, "Video Encoder Modes," on page 6 for details. Cr Select. When CRSEN*=0, CRS specifies the CrCb data sequence. CRS is an alternating signal. CRS=1 indicates that C[7:0] carry the Cr data. C[7:0] carry the Cb data otherwise. See Figure 7 on page 8. Video Input These pins accept the "CrCb" data of the YCrCb (4:2:2) digital video format. The Cb & Cr data appear alternately. The sequence of the Cb, Cr data is either predefined by the internal horizontal counter (even = Cb, odd = Cr) or as specified by pin CRS (data is Cr for CRS=1 and Cb otherwise. For more details, please refer to the timing diagram shown in Figure 6 on page 7. Cb & Cr have a nominal range of 16-240, with 128 equal to zero.
2, 36, 42
Power
VDD
3
In
XO/FIN
4
In
XI
5, 27
Power
AGND
6,29
Power
AVDD
7
In
CRSEN*
8
In
FS
9
In
MOD1
10
In
CRS
11 - 18
In
C[7:0]
Note: 1. Please refer to crystal manufacturer specifications for proper load capacitances. The optional variable tuning capacitor is required only if the crystal oscillation frequency cannot be controlled to the required accuracy. The capacitance value for the tuning capacitor should be obtained from the crystal manufacturer. For further information, request a copy of Application Note AN-19, "Tuning Clock Outputs."
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Table 2. Pin Descriptions (continued)
Pin 19-26 Type In Symbol Y[7:0] Description
CH7203
Video Input These pins accept the "Y" data of the YCrCb (4:2:2) digital video format. For more details, please refer to the timing diagram shown in Figure 7 on page 8. Y has a nominal range of 16-235. Reference Resistor A 360 resistor with short and wide traces should be attached between RSET and ground. No other connections should be made to this pin. Chrominance Output A 75 termination resistor with short traces should be attached between C and ground for optimum performance. Composite Output A 75 termination resistor with short traces should be attached between CVBS and ground for optimum performance. Luminance Output A 75 termination resistor with short traces should be attached between Y and ground for optimum performance. Digital Ground These pins provide the ground reference for the digital section of the CH7203. These pins MUST be connected to the system ground through independent ground vias. Horizontal Sync Output The horizontal sync output is generated by the CH7203 for master mode operation. HSYNC* is an active low signal with a 5V output swing. For additional information, please refer to the timing diagrams shown in Figures 5 and 6 on page 7. Vertical Sync Output The vertical sync output is generated by the CH7203 for master mode operation. VSYNC* is an active low signal with a 5V output swing. For additional information, please refer to the timing diagrams shown in Figures 5 and 7 on page 7 and 8. Mode bit 0 - internally pulled-up This input works in conjunction with the MOD1 input to select NTSC, PAL, or Sleep Mode functions. Refer to Table 3, "Video Encoder Modes," on page 6 for details. Video Pixel Clock Output 13.5 MHz clock output. The output swing is 5V. MPEG Decoder Clock Output 40.5 MHz or 33.9 MHz clock output (selectable by FS). The output swing is 5V. Double Pixel Clock Output 27 MHz clock output. The output swing is 5V.
28
In
RSET
30
Out
C
31
Out
CVBS
32
Out
Y
33, 34, 40, 44
Power
GND
35
Out
HSYNC*
37
Out
VSYNC*
38
In
MOD0
39 41
Out Out
PCLK DCLK
43
Out
2XPCLK
4
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CH7203
8 8
19-26 11 - 18 1 41 43
Y[7:0] Y C[7:0] ACLK DCLK 2XPCLK PCLK VSYNC* HSYNC* CRSEN C 30 32
Ferrite Bead
1
MPEG Decoder and System Controller
39 37 35 7 10 9 38
Ferrite Bead
1
75
CRS MOD1 MOD0
CVBS
31
Ferrite Bead
1
75 28 RSET
27 pF2 3 14.318 MHz 27 pF2 XO/FIN 8
360
4
XI
FS
JUMPER
Figure 3: CH7203 Interface Diagram
Note: 1. 2. Please refer to the Optional Output Filter diagram below The proper value of these capacitors depends on the crystal manufacturer's specifications. Please refer to AN06 for the details of the calculation.
47 pF
1.2uH Y, C, CVBS 75 150 pF
1.2uH OUTPUT 270 pF
Figure 4: Optional Output Filter
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Composite Connector
CH7203
S-Video Connector
75
5
CHRONTEL
General Description
CH7203
The CH7203 is a fully integrated solution for converting 16-bit YCrCb (4:2:2) digital video inputs into highquality NTSC or PAL video signals while generating all essential clock signals for MPEG playback. All essential circuitry for this conversion and clock generation (Dual PLL's, linear interpolator, digital filters, NTSC/PAL encoder, DAC's) are contained in the CH7203 making it an essential component of any low-cost solution for video-CD playback machines. Refer to the Block Diagram on page 1 and the Interface Diagram on page 5.
Functional Description
The encoded luminance (Y) and color-difference (U,V) are interpolated, and filtered through digital filters to minimize aliasing problems. The filtered signals go to the digital encoder where they are transformed to composite and S-video outputs, and then they are converted by the three 9-bit DACs to analog outputs.
16-bit YCrCb (4:2:2) Input
Y data is input through the Y[7:0] inputs and CrCb data is multiplexed through the C[7:0] inputs. When CRSEN* = 1, the Cr Select input, CRS, is ignored, and all even horizontal pixels are Cb data and all odd horizontal pixels are Cr. Refer to Figure 6 on page 7 for the definition of "even" and "odd" pixels. When CRSEN* = 0, the alternating CRS signal specifies the CrCb sequence. CRS = 1 indicates C[7:0] carries Cr data, and CRS = 0 indicates C[7:0] carries Cb data.
Clock/Data/Synchronization Timing
The CH7203 not only works as an NTSC/PAL encoder, it also supplies the necessary clocks (1X pixel, 2X pixel, video system, and audio) and synchronization (HSYNC* and VSYNC*) signals to other building blocks in the video system. For this reason, the CH7203 works only in the Master mode. It is important to note the CH7203 does not have a "pixel clock" input pin. Therefore, the timing issues related to video pixel data being supplied from, for example, the MPEG decoder, to the CH7203 (pins Y[7:0] and C[7:0]) need to be clarified. Assume the pixel synchronization of a system is based on the 2X pixel clock (2XPLCK). In this type of design, 2XPCLK is distributed across the entire video system, and it is also used to latch the incoming data appearing at pins Y[7:0] and C[7:0]. Figure 7 on page 8 shows all timing referenced to the 2XPCLK output signal (loaded with 50pF).
Video Encoder Modes
Combinations of the two signals MOD1 and MOD0 select the various power saving modes as shown below. Table 3 * Video Encoder Modes
MOD1 1 1 0 0 MOD0 1 0 1 0 Video Encoder Mode NTSC PAL PAL-60 Sleep mode (Encoder off,both PLLs running)
Frequency Select Modes
The frequency select input FS affects the DCLK and ACLK outputs as shown below: FS = 1 (default) DCLK = 40.5 MHz, ACLK = 16.934 MHz FS = 0 DCLK = 33.9 MHz, ACLK = 11.289 MHz
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CH7203
Timing Diagrams
HSYNC*
t7
VSYNC*
O DD FI E LD MA S T ER MODE
t7
VSYNC*
E VE N F IE LD MAS T E R MODE
Figure 5: HSYNC* and VSYNC* Timing
2XPCLK (out) PCLK (out) First (Y,C) data latched in after HSYNC* goes low Y (in) C (in) HSYNC* (out) Pixel[0] Pixel[1] Pixel[2]
Cb
Cr
Cb
Cr
t10 64 2XPCLK cycles
Figure 6: Cb, Cr Sequence Diagram
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CH7203
Data is latched into the device on the falling edge of 2XPCLK, when PCLK is low.
t1 t2
2XPCLK PCLK
t6 t5 Latch Latch Latch
H/V Sync Pixel Data
t3 t4
Figure 7: Clock/Data/Synchronization Timing Diagram
Note: Refer to Table 8 on page 14 for timing values
STAR ST T ART OF OF VSYN VS C YNC AN LOG S tart ANA o f ALOG fi el d FIELD 1 1IELD 1 F
5 23 520 520
5 24 521 521
52 5 522 522
523 523 1
524 524 2
525 525 3
1 1 4
2 2 5
36 3
47 4
5 5 8
69 6
1 70 7
11 8 8
12 9 9
Pre -e qu al iz in g pu lse ve rtica l
Ver ti ca l syn c p ul se i nte rva l
P os t- eq ua li zin g p ul se i nte rva l
L in e ReAN n ce fere LOG A ve rtic al suANArie r ph a se b- carLOG Fr fi el d 2 IELD 2 coFIELD 1 lo t1 +V in terv al
2 61 258 258
26 2592 259
26 2603 260
26 4 261 261 S ta rt of fi el d 2
2 65 262 262
26 2636 263
2 67 264 264
2 68 265 265
2 69 266 266
27 0 267 267
2 71 268 268
27 2692 269
27 2703 270
2 74 271 271
275 272 272
ST T AR OF VS C YN
Re fere n ce AN LOG A suIELD 1 p ha se Fb -ca rrie r t2 +V co lo r fi el d 2
52 3 520
5 24 521
52 5 522
1 523 S ta rt of fi el d 3
2 524
3 525
4 1
5 2
6 3
7 4
8 5
9 6
10 7
11 8
12 9
Re fere n ce AN LOG A su b- ca rrie r ph a se F fie ld 3 co lo rIELD 2 t3 +V
2 61 258
26 2 259
263 260
26 4 261 Sta rt o f fie ld 4
2 65 262
26 6 263
26 7 264
26 8 265
2 69 266
27 0 267
27 1 268
272 269
27 2703
2 74 271
27 5 272
R efe re nce su b-c arr ie r ph as e c ol or fie ld 4
Figure 8: Interlaced NTSC Timing Diagram
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SR TA T O F VN SY C
CH7203
ALO A AL G N OG F LD 1 IE
620 0 62
62 1
62 2
62 3
62 4
62 5
1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
ALO A AL G N OG F LD 2 IE
30 8
30 9
31 0
31 1
31 2
31 3
31 4
315 31 5
316 31 6
317 31 7
318 31 8
319 31 9
320 32 0
321 32 1
322 32 2
323 32 3
ALO A AL G N OG F LD 3 IE
620 62 0
62 1
62 2
62 3
62 4
62 5
1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
ALO A AL G N OG F LD 4 IE
30 8
30 9
31 0
31 1
31 2
31 3
31 4
315 5 31
316 6 31
317 7 31
318 8 31
319 9 31
320 0 32
321 1 32
322 2 32
323 3 32
B RST BU ST UR B KIN BLAN ING LAN G K
IN TE R VA L S
4 3 B RST PH SE = E E EN E P A EF R NC H 5 ELA IVE T EL T IV BU ST P AS = R FE E CE PH SE = 13 R AT E TO U UR HA E O P SW C IT 0, C PO 2 T OM N PAL SW CH = 0 +V C M ON N AL IT H , OP E 2 5 ELA VE O B RST PH SE = E E EN E 1H EF R NC P A 25 E T E BU ST P AS = R FE E CE PH SE+ 90 = 22 R LA IV T U UR HA E TI P SW C IT 1, V C MP N N PAL SW CH = 1 - V CO PO E T AL IT H , OM O
Figure 9: Interlaced PAL Timing Diagram
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CH7203
Color / Level Wh ite Yellow Cyan Green Magenta Red Blue Black Blank
mA 24.60 26.59 22.85 24.59 19.85 21.30 18.11 19.30 15.23 16.15 13.49 14.15 10.49 11.00 8.74 9.00 7.49 7.58
V 0.922 0.997 0.857 0.922 0.745 0.799 0.679 0.724 0.571 0.606 0.506 0.531 0.393 0.413 0.327 0.338 0.281 0.284
COLOR BARS :
Sync
0.50 0.00
0.019 0.000
Note: 1 100% amplitude, 100% saturation color bars are shown Note: 2 Vref = 1.235V, RSET = 360 , 75 doubly terminated load
Figure 10: NTSC Y (Luminance) Output Waveform
Color / Level Wh ite Yellow Cyan Green Magenta Red Blue Black Blank Blank
mA 24.60 26.83 22.85 24.69 19.85 21.19 18.11 19.05 15.23 15.70 13.49 13.57 10.49 10.21 8.74 8.08 7.49
V 0.922 1.006 0.857 0.926 0.745 0.795 0.679 0.715 0.571 0.589 0.506 0.509 0.393 0.383 0.327 0.303 0.281
COLOR BARS :
Sync
0.50 0.00
0.019 0.000
Note: 1 100% amplitude, 100% saturation color bars are shown Note: 2 Vref = 1.235V, RSET = 360 , 75 doubly terminated load
Figure 11: PAL Y (Luminance) Video Output Waveform
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CH7203
Color / Level Cyan / Red Green / Magenta Yellow / Blue
mA 22.60 25.37 21.85 24.59 19.61 22.16
V 0.848 0.951 0.819 0.922 0.735 0.831 0.599 0.681 0.468 0.536 0.337 0.391
COLOR BARS :
Peak Burst Blank Peak Burst
15.98 18.15 12.49 14.294 8.99 10.44
3.579545 MHz Color Burst (9 cycles) Yellow / Blue Green / Magenta Cyan / Red 5.37 6.43 3.12 4.00 2.37 3.21 0.201 0.241 0.117 0.150 0.089 0.121
Note: 1 100% amplitude, 100% saturation color bars are shown Note: 2 Vref = 1.235V, RSET = 360, 75 doubly terminated load
Figure 12: NTSC C (Chrominance) Video Output Waveform
Color / Level Cyan / Red Green / Magenta Yellow / Blue
mA 22.60 27.06 21.85 26.22 19.61 23.63 16.23 19.21 12.49 15.24 8.74 11.28 5.37 6.85 3.12 4.27 2.37 3.43
V 0.848 1.015 0.819 0.983 0.735 0.886 0.609 0.720 0.468 0.572 0.328 0.423 0.201 0.257 0.117 0.160 0.089 0.129
COLOR BARS :
Peak Burst Blank Peak Burst
4.433619 MHz Color Burst (10 cycles)
Yellow / Blue Green / Magenta Cyan / Red
Note: 1 100% amplitude, 100% saturation color bars are shown Note: 2 Vref = 1.235V, RSET = 360, 75 doubly terminated load
Figure 13: PAL C (Chrominance) Video Output Waveform
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CHRONTEL
M EN A AG T YE LLOW
CH7203
BLA K C BLA K C
GR EN E
W IT HE
CN YA
Color / Level Pea C k hrom a W hite
mA 33.89 32.45 26.59 27.37
V 1.271 1.217 0.997 1.026
COLOR BARS :
3.5795 M z 45 H C rB olo urst (9 C les yc ) Pea Bu t k rs Black Blank Pea Bu t k rs 12.00 11.43 9.00 9.62 7.58 8.16 4.32 3.72 0.450 0.429 0.338 0.360 0.306 0.284 0.162 0.139
Sy nc
0.50 0.00
0.019 0.000
Figure 14: Composite NTSC Video Output Waveform
Note: Vref = 1.235V, RSET = 360 , 75 doubly terminated load
M EN A AG T
YE LLOW
GR EN E
W IT HE
CN YA
Color / Level Pea C k hrom a W hite
mA 33.89 33.08 27.37 26.83
V 1.271 1.240 1.026 1.006
COLOR BARS :
4.4336 M z 19 H C rB olo urst (10 C le yc s) Pea Bu t k rs Blank/ Blac k Pea Bu t k rs 12.00 12.04 8.64 8.08 4.58 4.12 0.450 0.452 0.324 0.303 0.171 0.154
Sy nc
0.50 0.00
0.019 0.000
Figure 15: Composite PAL Video Output Waveform
Note: Vref = 1.235V, RSET = 360 , 75 doubly terminated load
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BLU E
R ED
BLU E
R ED
CHRONTEL
Electrical Specifications
Table 4 * Absolute Maximum Ratings
CH7203
Description Min Typ Max Units VDD relative to GND - 0.5 7.0 V Input voltage of all digital pins 1 GND - 0.5 VDD + 0.5 V T SC Analog output short circuit duration Indefinite Sec Ambient operating temperature - 55 125 C TAMB TSTOR Storage temperature - 65 150 C TJ Junction temperature 150 C TVPS Vapor phase soldering (one minute) 220 C PMAX Maximum power dissipation TBD W Note: Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated under the normal operating conditions is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect reliability. The device is fabricated using high-performance CMOS technology. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5V can induce destructive latchup.
Symbol
Table 5 * Recommended Operating Conditions
Symbol AVDD DVDD TA RL Description Analog supply voltage Digital supply voltage Ambient operating temperature Output load to DAC outputs Min Typ 5.00 5.00 25 37.5 Max Units
0
70
C
Table 6 * Electrical Characteristics (Operating Conditions: TA = 0C - 70C, VDD = 5V 5%)
Symbol Description Min Typ Max Unit Video D/A resolution 9 9 9 Bits Full scale output current 33.08 mA Video level error using internal reference 10 % Total Current Consumption 135 mA As applied to Tables 4, 5, and 6, Recommended Operating Conditions are used as test conditions unless otherwise specified. RSET = 360 , and NTSC CCIR601 operation. Typical values are based on 25 C and +5V.
Note:
Table 7 * Digital Inputs / Outputs
Symbol VOH VOL VIH VIL I PU ILK CDIN CDOUT Description Output high voltage Output low voltage Input high voltage Input low voltage Input internal pull-up current Input leakage current Input capacitance Output capacitance Test Condition @ TA = 25C IOH = - 400 A IOL = 3.2 mA Min 2.4 2.0 GND - 0.5 5 -10 Typ Units V 0.4 V VDD + 0.5 V 0.8 V 25 A 10 A pF pF Max
f = 1 MHz, VIN = 2.4V
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Electrical Specifications (continued)
Table 8 * AC Characteristics
Symbol t1 t2 t3 t4 t5 t6 t7 t10 Description 2XPCLK 2XPCLK high time Pixel/Sync setup time Pixel/Sync hold time Sync active delay time Sync inactive delay time HSYNC* to VSYNC* delay HSYNC* pulse width VSYNC* delay time VSYNC* pulse width Test Conditions: 30 64 x t1 17 2.0 20 14.8 6 3 3 17 30 Min Typ 37 22.2 Max
CH7203
Units ns ns ns ns ns ns ns ns ns Hor. lines
Unless otherwise specified, the testing conditions are the same as in Table 5, "Recommended Operating Conditions," on page 13. TTL input values are 0 - 3V, with input rise / fall times < 3 ns, measured between the VIL and VIH. Timing reference points at 50% for non-TTL inputs and outputs. TTL reference points at 1.5V for inputs and outputs. Analog output load < 10 pF. Since the CH7203 does not have a pixel clock input, all input signal timing is chosen with respect to the output clock timing of 2XPCLK and PCLK. PCLK can be used at the "Qualifying" clock for certain MPEG decoders.
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CH7203
ORDERING INFORMATION
Part number CH7203-V Package type PLCC Number of pins 44 Voltage supply 5V
Chrontel
2210 O'Toole Avenue San Jose, CA 95131-1326 Tel: (408) 383-9328 Fax: (408) 383-9338
19 97 Ch rontel , Inc. All R igh ts Re served . C hron te l PRODU CTS ARE NOT AUTHORIZED FOR AN D SHOUL D NOT BE USED WITH IN LIFE SU PPOR T SYSTEMS OR NU CLEAR FACILITY APPLICATION S WITHOUT TH E SPEC IFIC WRITTEN CONSEN T OF Chro ntel. Life su ppo rt systems are th ose in te nde d to sup port or sustai n li fe and w hose fa ilu re to p erform w hen used a s dire cte d can re ason abl y e xpect to resu lt i n p erson al in jury or dea th . C hron te l reserve s the rig ht to make chan ges at any ti me witho ut no ti ce to imp rove an d su ppl y the be st po ssibl e prod uct an d is n ot re spon sibl e and d oes no t assu me any li abi lity fo r mi sapp lica ti on or use o utside the li mits sp ecifie d in this do cumen t. We pro vi e n o warra nty for the use of our pro ducts and a ssume no d l iab ili ty for errors con ta ine d in this do cumen t. Printed i n th e U.S.A.
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