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LUPA-1300 Datasheet
LUPA-1300
1.3 M Pixel High Speed CMOS Image Sensor
Datasheet
Cypress Semiconductor Corporation
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LUPA-1300 Datasheet
Document history record
Issue Date 2.1 April, 2003 3.0 March, 2004
3.1
December, 2004
Description of changes First draft. Updated timing diagrams Updated layout Updated package drawings Disclaimer Soldering and handling conditions Updated specifications Added equivalent Cypress part numbers, ordering information. Added Cypress Document # 38-05711 Rev ** in the document footer.
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LUPA-1300 Datasheet
Table 1
of contents
OVERVIEW .............................................................................................................................. 5 MAIN FEATURES ...................................................................................................................... 5 PART NUMBER ........................................................................................................................ 6
PREAMBLE ................................................................................................................................. 5 1.1 1.2 1.3
2
SPECIFICATIONS ...................................................................................................................... 7 2.1 GENERAL SPECIFICATIONS....................................................................................................... 7 2.2 ELECTRO-OPTICAL CHARACTERISTICS ..................................................................................... 7 2.2.1 Overview......................................................................................................................... 7 2.2.2 Features and general specifications.............................................................................. 8 2.2.3 Spectral response curve ................................................................................................. 9 2.2.4 Photo-voltaic response curve....................................................................................... 10 2.3 ELECTRICAL SPECIFICATIONS ................................................................................................ 11 2.3.1 Absolute maximum ratings.......................................................................................... 11 2.3.2 Recommended operating conditions ........................................................................... 11
3
SENSOR ARCHITECTURE .................................................................................................... 13 3.1 PIXEL ARCHITECTURE............................................................................................................ 14 3.2 COLUMN READOUT AMPLIFIERS............................................................................................. 15 3.3 OUTPUT AMPLIFIERS.............................................................................................................. 16 3.4 FRAME RATE AND WINDOWING.............................................................................................. 17 3.4.1 Frame rate calculation ................................................................................................ 17 3.4.2 X-Y addressing and windowing................................................................................... 17 3.5 TEMPERATURE REFERENCE CIRCUITS .................................................................................... 18 3.5.1 Temperature diode....................................................................................................... 18 3.5.2 Temperature module.................................................................................................... 18 3.6 SYNCHRONOUS SHUTTER....................................................................................................... 20 3.7 NON-DESTRUCTIVE READOUT (NDR).................................................................................... 21 3.8 OPERATION AND SIGNALING.................................................................................................. 21 3.8.1 Power supplies and grounds........................................................................................ 22 3.8.2 Biasing and analog signals ......................................................................................... 24 3.8.3 Pixel array signals ....................................................................................................... 24 3.8.4 Digital signals .............................................................................................................. 26 3.8.5 Test signals................................................................................................................... 27
4
TIMING ...................................................................................................................................... 28 4.1 TIMING OF THE PIXEL ARRAY................................................................................................. 28 4.2 READOUT OF THE PIXEL ARRAY ............................................................................................. 29 4.2.1 Reduced Row Overhead Time timing.......................................................................... 31 4.3 TIMING OF THE SERIAL PARALLEL INTERFACE (SPI)............................................................. 33
5 6
PIN CONFIGURATION ........................................................................................................... 34 PAD POSITIONING AND PACKAGING .............................................................................. 39 6.1 PACKAGE............................................................................................................................... 39 6.2 PACKAGE AND DIE................................................................................................................. 40 6.3 COLOR FILTER ....................................................................................................................... 41 6.4 GLASS TRANSMITTANCE........................................................................................................ 42 6.4.1 Monochrome................................................................................................................ 42 6.4.2 Color............................................................................................................................. 42 6.5 HANDLING AND STORAGE PRECAUTIONS............................................................................... 43
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LUPA-1300 Datasheet
6.6 6.7 7 8 HANDLING PRECAUTIONS ...................................................................................................... 43 STORAGE CONDITIONS........................................................................................................... 44
ORDERING INFORMATION ................................................................................................. 44 APPLICATION NOTES & FAQ.............................................................................................. 45
APPENDIX A: LUPA-1300 EVALUATION KIT........................................................................... 47
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LUPA-1300 Datasheet
1 Preamble
1.1 Overview
This document describes the interfacing and the driving of the image sensor LUPA1300, which is a 1280 by 1024 CMOS pixel array working at 450 frames/sec. The sensor is an active pixel sensor with synchronous shutter. The pixel size is 14 * 14 m and the sensor is designed to achieve a fame rate of 450 frames/sec at full resolution. This high frame rate can be achieved by 16 parallel output amplifiers each working at 40MHz pixel rate. The readout speed can be boosted by means of windowed Region Of Interest (ROI) readout. High dynamic range scenes can be captured using the double slope functionality. The sensor uses a 3-wire Serial-Parallel (SPI) interface. It is housed in a 145-pin ceramic PGA package. In the following sections the different modules of the image sensor are discussed more into detail. This datasheet allows the user to develop a camera-system based on the described timing and interfacing.
1.2 Main features
The main features of the image sensor are identified as: * * * * * * * * * * * * SXGA resolution: 1280 x 1024 active pixels. 14 m2 square pixels (based on the high-fill factor active pixel sensor technology of FillFactory (US patent No. 6,225,670 and others)). Pixel rate of 40 MHz using 16 parallel outputs. Random programmable windowing. Dual slope integration possible 145-pin PGA package Peak QE x FF of 15%. Optical format: 1,43" (17.9 mm x 14.3 mm) Optical dynamic range: 62 dB (1330:1) in single slope operation and 80...100 dB in double slope operation. 16 parallel analog output amplifiers. Synchronous pipelined shutter. Processing is done in a CMOS 0.50 m triple metal process.
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LUPA-1300 Datasheet
1.3 Part Number
Name LUPA-1300-M CYIL1SM1300AA-GBC (preliminary) LUPA-1300-C CYIL1SC1300AA-GAC (preliminary) Package 145-pins PGA package. 145-pins PGA package. Monochrome / color Monochrome. RGB Bayer pattern.
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LUPA-1300 Datasheet
2 Specifications
2.1 General specifications
Parameter Specification Remarks
Pixel architecture Pixel size Resolution Pixel rate Shutter type Full frame rate Package
6T-pixel 14 m x 14 m 1280 x1024 640 MHz Pipelined snapshot shutter 450 frames/second
Based on the high-fill factor active pixel sensor technology of FillFactory The resolution and pixel size results in a 17.9 mm x 14.3 mm optical active area. Using a 20 MHz system clock and 16 parallel outputs. Full snapshot shutter with variable integration time Frame rate increase possible with ROI read out and/or sub sampling.
Pin grid array 145 pins Table 1: general specifications of the LUPA sensor
2.2 Electro-optical characteristics
2.2.1 Overview
Parameter Specification Remarks
FPN PRNU Conversion gain Output signal amplitude Saturation charge Sensitivity Fill Factor Peak QE * FF Peak SR * FF MTF Temporal Noise
<2 % RMS 20 % RMS 16 uV/electron 1V 62.500 e1500 V.m2/W.s 8.33 V/lux.s 21.43 V/lux.s 50% 15% 0.08 A/W X: 67 % Y: 66% 45e-
<10 % p/p. Half saturation. Unity gain. Is more then 60.000 (=1V/16uV/e-) due to nonlinearity in saturated region. Average white light. Visible band only (180 lx = 1 W/m2). Visible + NIR (70 lx = 1 W/m2). 100%-metal and polycide coverage. See spectral response curve. @ Nyquist Dark environment, measured at T=21C.
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LUPA-1300 Datasheet 1330 1330 = 60000:45 = 62 dB. S/N ratio 400 - 1000 nm Spectral sensitivity range < 0.5 % I.e. sensitivity of the storage node compared to Parasitic light the sensitivity of photodiode sensitivity 900 mWatt Typical. Power dissipation 200-300 Ohms Typical Output impedance Table 2: electrical-optical specifications of the LUPA-1300 sensor 2.2.2 Features and general specifications Feature Electronic shutter type Windowing (ROI) Read out sequence Extended dynamic range X clock Number of outputs Supply voltage VDD Specification/Description Synchronous pipelined shutter with variable integration time. Programmable via SPI. Progressive scan. Double slope extended dynamic range. 20 MHz (pixel rate of 40 MHz) 16. Image core supply: Range from 3V to 6 V. Analog supply: Nominal 5 V. Digital: Nominal 5 V. 5V (digital supply) 0C to 60C, with degradation of dark current.
Logic levels Operational temperature range 145-pins Pin Grid Array (PGA). Package Table 3: Features and general specifications
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LUPA-1300 Datasheet 2.2.3 Spectral response curve
0.12
0.1
Response (A/W)
0.08
QE=10%
0.06
QE=15% QE= 20%
0.04
LUPA-1300
0.02
0 400 500 600 700 Wavelength (nm) 800 900 1000
Figure 1: Spectral response curve Figure 1 shows the spectral response characteristic. The curve is measured directly on the pixels. It includes effects of non-sensitive areas in the pixel, e.g. interconnection lines. The sensor is light sensitive between 400 and 1000 nm. The peak QE * FF is 15% approximately between 500 and 700 nm.
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LUPA-1300 Datasheet 2.2.4 Photo-voltaic response curve
Figure 2: Output voltage as a function of the number of electrons. As one can see from Figure 2, the output signal ranges between 1.1 V (dark) to 0 V (saturation) and is linear until around 800mV. Note that the upper part of the curve (near saturation) is actually a logarithmic response.
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LUPA-1300 Datasheet
2.3 Electrical specifications
2.3.1 Absolute maximum ratings Symbol Parameter Value Unit VDC DC supply voltage -0.5 to +7 V VIN DC input voltage 0.5 to VDC + 0.5 V VOUT DC output voltage -0.5 to VDC + 0.5 V DC current per pin; any single input I or output. (see table 7 for more 50 mA exceptions) TSTG Storage temperature range. -40 to 100 C Lead temperature (10 seconds TL 300 C soldering). Table 4: Absolute maximum ratings Note: Absolute Ratings are those values beyond which damage to the device may occur. 2.3.2 Recommended operating conditions Parameter Typ Power supply column read 5 out module. Power supply digital Vdd 5 modules Power supply logic for Vddr 5 drivers Power supply output stages 5 Voo Power supply reset drivers 6 Vres Power supply multiple slope Vres_ds 4.5 reset driver Power supply memory Vmem_h 6 element (high level) Power supply memory Vmem_l 4.5 element (low level) Power supply pixel array 4.5 Vpix Power supply output stages. Vstable Decouples noise on the Voo 5.5 supply from the output signal. Table 5: Recommended operation conditions Symbol Vdda Unit V V V V V V V V V V
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LUPA-1300 Datasheet Note: 1. All parameters are characterized for DC conditions after thermal equilibrium has been established. 2. Unused inputs must always be tied to an appropriate logic level, e.g. either VDD or GND. 3. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however it is recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high impedance circuit.
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LUPA-1300 Datasheet
3
Sensor architecture
The image sensor consists of the pixel array, the column readout electronics, X-and Y addressing, on chip drivers, the output amplifiers and some logic.
Sensor Imager core
Drivers for the pixel array signals
Control signals
Pixel System clock 40 MHz Y-addressing
16
Pixel core
15 14
Column amplifiers
Analog multiplexer
Output amplifiers
3 2
X-addressing
1
SPI interface
Figure 3: architecture of the LUPA sensor Figure 3 shows a schematic representation of the image sensor on which the different modules are displayed. The image core is a pixel array of 1280 * 1024 pixels each of 14 *14 m2 in size. The readout is from bottom left to top right. To obtain a frame rate of 450 frames/sec for this resolution, 16 output amplifiers each capable of driving an output capacitance of 10 pF at 40MHz are placed on the image sensor. The column readout amplifiers bring the pixel data to the output amplifiers. The logic and the x- and y addressing controls the image sensor so that progressive scan and windowing is possible. Extra pixel array drivers are foreseen at the top of the image sensor to control the global pixel array signals.
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LUPA-1300 Datasheet
3.1 Pixel architecture
The active pixels allow synchronous shutter "i.e. all pixels are illuminated during the same integration time, starting from the same moment in time. After a certain integration time, the pixels are readout sequentially. Readout and integration are in parallel, which means that when the image sensor is readout, the integration time for the next frame is ongoing. This feature requires a memory element inside the pixel, which affects the maximum fill factor. A schematic representation of the pixel is given in figure 4.
Vpix reset sample Row select
precharge
Mem
Figure 4: schematic representation of the synchronous pixel as used in the LUPA design The signals mentioned in figure 4 are the internal signals, generated by the internal drivers, required to have the synchronous shutter feature.
The photodiode is designed to obtain sensitivity as high as possible for a dynamic range of at least 60dB. Consequently the photodiode capacitance is 10fF @ the output, resulting in a S/N of more than 60dB as the rms noise level is within the expectation of 45 noise electrons. The pixel was specially designed to have a very low parasitic light sensitivity (<0.5%). The pixels are based on the high-fill factor active pixel sensor technology of FillFactory (US patent No. 6,225,670 and others)).
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LUPA-1300 Datasheet
3.2 Column readout amplifiers
The column readout amplifiers are the interface between the pixels and the output amplifiers. The pixels in the array are selected line by line and the pixels of the selected line are connected to the column readout amplifiers, which bring the pixel data in the correct format to the output amplifiers. To obtain a high frame rate, the complexity and the number of stages in the column readout amplifiers must be minimized, so that the power dissipation remains as low as possible, but also to minimize the row blanking time. Figure 5 is a schematic representation of the column readout structure. It consists of 2 parts. The first part is a module that reduces the row blanking time. The second part shifts the signal to the correct level for the output amplifiers and allows multiplexing in the x-direction. From the moment that a new row is selected, the pixel data of that row is placed onto the columns of the pixel array. These columns are long lines and have a large parasitic capacitance. As the pixel is small, it is not possible to match the transistor inside the pixel, which drives this column. Consequently, the first module in the column readout amplifiers must solve the mismatch between the pixel driver and the large column capacitance.
column Module 1 : track & hold or reference set method Sh kol Norow sel
Module 2 : signal conditioning and multiplexing
X-mux
Output stage
Figure 5: Schematic representation of the column readout structure.
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LUPA-1300 Datasheet
3.3 Output amplifiers
16 output amplifiers each capable of working at 40MHz pixel rate are placed equidistant on the bottom of the image sensor. These output amplifiers are required to obtain a frame rate of 450 frames/sec. A single output stage, not only to reduce power, but also to achieve the required pixel rate is designed. Figure 6 is a schematic representation of this module.
Stabilize power supply Vstable
In
Out Cload 10 pF Output stage load
Figure 6: schematic representation of a single output stage.
Each output stage is designed to drive a load of 10pF at a pixel rate of 40MHz. The load in the output stage determines this pixel rate. In case the load capacitance is less than 10pF, the load in the output stage can increase, resulting in less power dissipation of the output stages and consequently of the whole sensor. Additionally, decreasing the load of the output stage allows having more current available for the output stage to charge or discharge the load capacitance to obtain a higher pixel rate. To avoid variations on the supply voltage to be seen on the output signal, a special module to stabilize the power supply is required. This module that requires an additional supply voltage (Vstable) allows variation on the supply voltage Voo without being seen on the output signal. One can also choose to have a passive load of chip instead of the active output stage load. This deteriorates the linearity of the output stages, but decreases the power dissipation, as the dissipation in the load is external. Note: The LUPA-1300 is designed to drive a capacitive load, not a resistive. When one wants to transport the output signals over long distances (more than 1 inch), make sure to place buffers on the outputs with high input impedances (preferably >1Mohms). This is necessary because the output impedance of the LUPA-1300 is between 200-300 ohms typically.
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LUPA-1300 Datasheet
3.4 Frame rate and windowing
3.4.1 Frame rate calculation
The frame period of the LUPA-1300 sensor can be calculated as follows: Frame period = FOT + (Nr.Lns* (RBT + pixel period * Nr. Pxs / 16) with: FOT: Frame Overhead Time = 1 us. Nr. Lns : Number of Lines read out each frame (Y). Nr. Pxs: Number of pixels read out each line (X). RBT: Row blanking time = 200 ns (nominal; can be further reduced). Pixel period: clock_x period/2 (both rising and falling edge are active edges). - Example 1 read out of the full resolution at nominal speed (40 MHz pixel rate): Frame period = 5 us + (1024 * (200 ns + 25 ns * 1280 / 16) = 2.25 ms => 444 fps. - Example 2 read out of 800x600 at nominal speed (40 MHz pixel rate): Frame period = 5 us + (600 * (200 ns + 25 ns * 800 / 16) = 871 us => 1148 fps. - Example 3 read out of 640x480 at nominal speed (40 MHz pixel rate): Frame period = 5 us + (480 * (200 ns + 25 ns * 640 / 16) = 577 us => 1733 fps. - Example 4 read out of the full resolution at nominal speed (40 MHz pixel rate) with reduced overhead time: Frame period = 5 us + (1024 * (100 ns + 25 ns * 1280 / 16) = 2.15 ms => 465 fps.
3.4.2 X-Y addressing and windowing
The pixel array is readout by means of programmable X and Y shift registers. The pixel array is scanned line-by-line and column-by-column. The starting point in X and Y is defined individually for each register and is determined by the address downloaded by the Serial - Parallel Interface (SPI). Both registers work in the same way. A sync pulse that sets the address pointer to the starting address of each register, initializes them. A clock pulse for the x- and y-shift register shifts the pointer individually and makes sure that the sequential selection of the lines and columns is correct.
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LUPA-1300 Datasheet
3.5 Temperature reference circuits
3.5.1 Temperature diode The most commonly used temperature measurement is monitoring of the junction voltage of a diode, therefore we also added a temperature diode to measure the temperature of the silicon die. This diode junction voltage is generated by a "small", forward biased, constant current flow (in between 10 and 100 A).
This junction voltage has a nearly linear relationship with the temperature of the die with a typical sensitivity of about 430C per volt (2.3 mV per C) for silicon junctions.
3.5.2 Temperature module
On the same image sensor we have foreseen a module to verify the temperature on chip and the variation of the output voltage (dark level of the pixel array) due to a temperature variation. This module contains a copy of the complete signal path, including a blind pixel, the column amplifiers and an output stage. It DC response may serve a temperature calibration for the real signal. The temperature functionality is given in figure 7. Between room temperature and 60 C we see a voltage variation of about 0.5 mV. Due to different applied supply voltages, as there are: Vreset, Vmem, Vpix... an offset between the output voltage of the temperature sensor and the output of a black signal of the pixel array can occur. Depending on the working conditions of the image sensor one can fine-tune the temperature module with its voltage supply. In case one has a 6V signal for reset and a 4-6V signal for Vmem, a supply voltage of 5.5V for the temperature sensor will result in a closer match between this temperature sensor and the black level of the image sensor. Changing the supply voltage of the temperature sensor results only in a shift of the output voltage therefore the supply voltage of the temperature module can be tuned to make the output of the module equal to the dark signal of the pixel array at a certain working temperature. Vsupply (V) Vout @ 21C 5 0.58 5.5 0.8 6 1.03 6.1 1.07 6.2 1.12 6.3 1.17 6.4 1.22 6.5 1.27
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LUPA-1300 Datasheet
1.13 1.11 1.09 6 Vout (V) 1.07 1.05 1.03 1.01 0.99 25 35 45 55 65 75 6.1 6.2
Temperature (C)
Figure 7: Output voltage of the temperature module versus temperature
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LUPA-1300 Datasheet
3.6 Synchronous shutter
In a synchronous (snapshot) shutter light integration takes place on all pixels in parallel, although subsequent readout is sequential.
Line number COMMON SAMPLE&HOLD
Flash could occur here
COMMON RESET
Time axis Integration time Burst Readout time
Figure 8: Synchronous shutter operation
Figure 8 shows the integration and read out sequence for the synchronous shutter. All pixels are light sensitive at the same period of time. The whole pixel core is reset simultaneously and after the integration time all pixel values are sampled together on the storage node inside each pixel. The pixel core is read out line by line after integration. Note that the integration and read out cycle can occur in parallel.
Read frame I Read frame I + 1
Integration I + 1
Integration I + 2
Figure 9:Integration and read out in parallel The control of the readout of the frame and of the integration time are independent of each other with the only exception that the end of the integration time from frame I+1 is the beginning of the readout of frame I+1.
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LUPA-1300 Datasheet
3.7 Non-destructive readout (NDR)
The sensor can also be read out in a non-destructive way. After a pixel is initially reset, it can be read multiple times, without resetting. The initial reset level and all intermediate signals can be recorded. High light levels will saturate the pixels quickly, but a useful signal is obtained from the early samples. For low light levels, one has to use the later or latest samples.
time
Figure 10. Principle of non-destructive readout.
Essentially an active pixel array is read multiple times, and reset only once. The external system intelligence takes care of the interpretation of the data. Table 6 summarizes the advantages and disadvantages of non-destructive readout. Table 6: Advantages and disadvantages of non-destructive readout.
Advantages Low noise - as it is true CDS.
Disadvantages System memory required to record the reset level and the intermediate samples. High sensitivity - as the conversion Requires multiples readings of each pixel, capacitance is kept rather low. thus higher data throughput. High dynamic range - as the results Requires system level digital calculations. includes signal for short and long integrations times.
3.8 Operation and signaling
One can distinguish the different signals into different groups: * Power supplies and grounds * Biasing and analog signals * Pixel array signals * Digital signals * Test signals
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LUPA-1300 Datasheet 3.8.1 Power supplies and grounds
Every module on chip, as there are: column readout, output stages, digital modules, drivers, ... has its own power supply and ground. Off chip the grounds can be combined, but not all power supplies may be combined. This results in several power supplies, but is required to reduce electrical crosstalk and to improve shielding. On chip we have the ground lines also separately for every module to improve shielding and electrical crosstalk between them. The only special ground is "Gnd_res", which can be used to remove the blooming if any and which can improve optical crosstalk. An overview of the supplies is given in table 7. The power supplies related to the pixel array signals are described in the paragraph concerning the pixel array signals. Note: Normal application doesn't require this Gnd_res and it can be connected to ground.
Name Vdda Vdd Voo Vstable Vpix Vddr Vres VmemH VmemL
Max curren t 50mA 20mA 85mA 6mA
Typ. Max 5V 5V 5V 5.5V
Description
Power supply column readout module Power supply digital modules Power supply output stages 6V Power supply output stages. Decouples noise on the Voo supply from the output signal. 200mA 5V 6V Power supply pixel array. 20mA 5V Power supply logic for drivers 50mA 6V Power supply to reset the pixels 50mA 6V Power supply for high DC level Vmem 50mA 4.5V Power supply for low DC level Vmem Table 7: power supplies used in the LUPA design
The maximum currents mentioned in table 7 are peak currents. The power supplies need to be able to deliver these currents especially the maximum supply current for Vpix. It is important to notice that we don't do any power supply filtering on chip and that noise on these power supplies can contribute immediately to the noise on the signal. Especially the voltage supplies Vpix and Vdda are important to be well noise free. With respect to the power supply Voo, a special decoupling is used, for which an additional power supply Vstable is required.
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LUPA-1300 Datasheet
Important notes: 1.At start up the Vpix supply draws a very high current (> 300 mA) which has to be limited (max. 200 mA) otherwise the bond wires of the particular supply will be destroyed. One should make sure that the Vpix power supply limits the current draw to the Vpix sensor supply pins to max. 200mA. When the bond wires of Vpix are destroyed the sensor isn't operating normally and will not meet the described specifications. 2. VmemL must sink a current, not source it. All power supplies should be decoupled very close to the sensor pin (typical 100nF to filter high frequency dips and 10 microF to filter slow dips). A typical decoupling circuit is shown in the figure below. Vres_ds must be able to sink and source current.
Figure 11a: Schematic of typical decoupling of power supply (source current)
Figure 11b: Schematic of typical decoupling of power supply (sink current)
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LUPA-1300 Datasheet 3.8.2 Biasing and analog signals
Besides the biasing signals, the only analog signals are the output signals Out1 - Out16. Each output signal is analog with respect to the voltage level, but is discrete in time. This means that on the speed of Clock_x, the outputs change to a different level, depending on the illumination of the corresponding pixels. The biasing signals determine the speed and power dissipation of the different modules on chip. These biasing signals have to be connected trough a resistor to ground or power supply and should be decoupled with a capacitor. If the sensor is working properly, each of the biasing signals will have a dc-voltage depending on the resistor value and on the internal circuitry. These dc-voltages can be used to check the operation of the image sensor. Table 8 gives the different biasing signals, the way they should be connected, and the expected dc-voltage. Due to small process variations, these dc-voltages change from chip to chip and 10% variation is possible.
Signal Pre_load
Comment
Connect with 10K to Vdda and capacitor of 100nF to Gnd Col_load Connect with 2M to Vdda and capacitor of 100nF to Gnd Psf_load Connect with 240K to Gnd and capacitor of 100nF to Vdda Nsf_load Connect with 100K to Vdda and capacitor of 100nF to Gnd Load_out Connect with 27K to Voo and capacitor of 100nF to Gnd Decx_load Connect with 27K to Gnd and capacitor of 100nF to Vdd Decy_load Connect with 27K to Gnd and capacitor of 100nF to Vdd Table 8 : overview of biasing signals
Expected dclevel 2.0V 0.9V 3.7V 1.3V 1.6V 2.8V 2.8V
Each resistor controls the speed and power dissipation of the corresponding module, as this resistor determines the current required to charge and/or discharge internal nodes inside the module. A decoupling with a small capacitor is advisable to reduce the HF noise onto the analog signals. Only the capacitor on the Pre_load signal can be omitted.
3.8.3 Pixel array signals
Figure 4 in paragraph 2.2 is a schematic representation of the pixel as used in the LUPA design. The applied signals to this pixel are: reset, sample, Precharge,
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Vmemory, row select and Vpix. These are internal generated signals derived by on chip drivers from external applied signals. Consequently it is important to understand the relation between both internal and external signals and to understand the operation of the pixel. The timing of the pixel is given in figure 12 in which only the internal signals are given.
Figure 12: Internal timing of the pixel.
At the end of the integration time, the information on the photodiode node needs to be sampled and stored onto the pixel memory, required to allow synchronous shutter. To do this, we need the signals "Precharge" and "Sample". "Precharge" resets the pixel memory and "Sample" places the pixel information onto the pixel memory. Once this information stored, the readout of the pixel memories can start in parallel with a new integration time. An additional signal "Vmem" is needed to obtain a larger output swing. Except from Vpix power supply, drivers generate the other pixel signals on chip. The external signals to obtain the required pulses consist of 2 groups. One is the group of digital signals to indicate when the pulse must occur and the other group is dc-supply lines indicating the levels of the pulses. Table 9 summarizes the relation between the internal and external pixel array signals
External Low dc High dc control level level signal 0 5V Precharge Gnd Vddr Precharge 0 5V Sample Gnd Vddr Sample 0V 4 - 6V Reset & Gnd_res Vres & Reset Reset_ds Vres_ds 4.5V 6V Mem_hl Vmem_l Vmem_h Vmemory Table 9: overview of the internal and external pixel array signals.
The Precharge and Sample signals are the most straightforward signals. The internal
Internal signal
Vlow
Vhigh
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signal Vmemory is a signal that switches between a low voltage (3.5 - 5.5V) and a high voltage (5-6V). The signal Mem_hl controls the applied level and the power supply lines Vmem_l and Vmem_h determine the low and high dc-levels. The Reset signal is due to the dual slope technique a little more complex. In case the dual slope is not used, the reset signal is straightforward generated from the external reset pulse. In this case the supply voltage Vres determines the level to which the pixel is resetted. In case the dual slope operation is desired, one needs to give a second pulse to a lower reset level during integration. This can be done by the control signal Reset_ds and by the power supply Vres_ds that defines the level to which the pixel has to be resetted. If a pulse is given on the Reset_ds signal, a second pulse on the internal reset line is generated to a lower level, determined by the supply Vres_ds. If no Reset_ds pulse is given, the dual slope technique is not implemented. Note that Reset is dominant over Reset_ds, which means that the high voltage level will be applied for reset, if both pulses occur at the same time. The external control signals should be capable of driving input capacitance of about 20pF.
3.8.4 Digital signals
The digital signals control the readout of the image sensor. These signals are: * Sync_y: Starts the readout of the frame or window at the address defined by the y-address register. This pulse synchronizes the y-address register: active high. This signal is at the same time the end of the frame or window and determines the window width. * Clock_y: Clock of the y-register. On the rising edge of this clock, the next line is selected. * Sync_x: Starts the readout of the selected line at the address defined by the xaddress register. This pulse synchronizes the x-address register: active high. This signal is at the same time the end of the line and determines the window length. * Address: the x- and y-address is downloaded serial through this signal. * Clock_spi: clock of the serial parallel interface. This clock downloads the address into the SPI register. * Load_addr: when the SPI register is downloaded with the desired address, the signal Load_addr signal loads the x-and y-address into their address register as starting point of the window of interest. * Sh_col: control signal of the column readout. Is only used in sample & hold mode (See timing) * Norow_sel: Control signal of the column readout. Is only used in Norow_sel mode ( See timing) * Pre_col: Control signal of the column readout to reduce row blanking time * Sel_active: activates the active load on chip for the output amplifiers. If not used, a passive load can be used or one can use this signal to put the output
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stages in standby mode. Eos_x: end of scan signal: is an output signal, indicating when the end of the line is reached. Is not generated when doing windowing Eos_y: end of scan signal: is an output signal, indicating when the end of the frame is reached. Is not generated when doing windowing.
* *
All digital signals are buffered and filtered on chip to remove spikes and to achieve the required on chip driving speed. The applied digital signals should be capable of driving 20pF input capacitance.
3.8.5 Test signals
Some test signals are required to evaluate the optical performance of the image sensor. Other test signals allow us to test internal modules in the image sensor and some test signals will give us information concerning temperature and influence of the temperature on the black level. Evaluation on the optical performance (Spectral response, fill factor) * Array_diode * Full_diode Evaluation of the output stages: * Black * Dc_black Evaluation of the x and y -shift registers: * Eos_x * Eos_y Indication of the temperature and influence on the black level: * Temp_diode_n * Temp_diode_p
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4 Timing
4.1 Timing of the pixel array
The timing of the image sensor can be divided in two major parts. The first part of the timing is related with the timing of the pixel array. This implies the control of the integration time, the synchronous shutter operation, and the sampling of the pixel information onto the memory element inside each pixel. The signals needed for this control are described in previous paragraph 3.7.3 and figure 12 shows the timing of the internal signals. Figure 13 should make the timing of the external signals clear.
Figure 13: timing of the pixel array. All external signals are digital signals between 0 and 5V. The Reset_ds is only required in case dual slope is desired.
Symbol a b c d e f
> 5 sec > 200 nsec > 500 nsec > 3.9 sec > 400 nsec > 2 sec Table 10: Typical timings of the pixel array
Name Mem_HL MEM_HL -Precharge Precharge Sample Precharge-Sample Integration time
Value
The timing of the pixel array is straightforward. Before the frame is read, the information on the photodiode needs to be stored onto the memory element inside the pixels. This is done by means of the signals Vmemory, Precharge and Sample. Precharge sets the memory element to a reference level and Sample stores the photodiode information onto the memory element. Vmemory pumps up this value to
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reduce the loss of signal in the pixel and this signal must be the envelop of Precharge and Sample. After Vmemory is high again, the readout of the pixel array can start. The frame blanking time or frame overhead time is thus the time that Vmemory is low, which is about 5sec. Once the readout starts, the photodiodes can all be initialised by reset for the next integration time. The duration of the reset pulse indicates the integration time for the next frame. The longer this duration, the shorter the integration time becomes. Maximum integration time is thus the time it takes to readout the frame, minus the minimum pulse for reset, which is preferred not to be less than 10sec. The minimal integration time is the minimal time between the falling edge of reset and the rising edge of sample. Keeping the slow fall times of the corresponding internal generated signals, a minimal integration time is about 2sec. An additional reset pulse can be given during integration by Reset_ds to implement the double slope integration mode. (See paragraph 6.1)
4.2 Readout of the pixel array
Once the photodiode information is stored into the memory element in each pixel, the total pixel array of 1280 * 1024 needs to be readout in less than 2 msec (2msec - frame overhead time = 1995sec). Additionally, it is possible that only a part of the whole frame is read out. This is controlled by the starting address that has to be downloaded and from the end address, which is controlled by the synchronisation pulses in x- and y direction. The readout itself is straightforward. Line by line is selected by means of a sync-pulse and by means of a Clock_y signal. Once a new line selected, it takes a while (row blanking time) before the information of that line is stable. After this row blanking time the data is multiplexed in blocks of 16 to the output amplifiers. A sync-pulse and a clock pulse in the x-direction do this multiplexing. Figure 14 shows the y-address timing. The top curves are the selection signals of the pixels, which are sequentially active, starting by the sync pulse. The next line is selected on the rising edge of Clock_y. It is important that the Sync_y pulse covers 1 rising edge of the Clock_y signal. Otherwise the synchronization will not work properly.
Figure 14 : timing of the y shift register.
The first selected line after a Sync_y pulse is the line defined by the y-address in the y-address register. Every select line is in principle 1 clock period long, except for the
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first select line. The first select line goes high as soon as a Sync_y pulse occurs together with a rising edge of Clock_y. On the next rising edge of Clock_y, the next row is selected, unless Sync_y is still active. In figure 15, a short Sync_y pulse makes sure that the first row is selected during 1 period of Clock_y. Once a line is selected, it needs to stabilize first of all, which is called the row blanking time, and secondly the pixels need to be read out. Figure 15 shows the principle.
Figure 15: Readout time of a line is the sum of the row blanking time and on the line readout time.
Symbol a b c d Name Sync_Y Sync_Y-Clock_Y Clock_Y-Sync_Y Sync_X -Clock_X Value
> 100 nsec > 50 nsec > 50 nsec > 50ns
Once the information of the selected line is stable the addressing of the pixels can start. This is done by means of a Sync_x and a Clock_x pulse in the same way as the Y-addressing. The Sync_x pulse downloads the address in the address register into the shift register and connects the first block of 16 columns to the 16 outputs. In fact on chip is a 32-output bus instead of 16, but on the rising edge of Clock_x the first 16 columns of the bus are connected to the output stages. On the falling edge of Clock_x, the last 16 columns of the selected bus are connected to the output stages.
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Figure 16: Timing of the x-shift register. The curves from bottom to top : Clock_x, Sync_x, Internal generated Clock, Sel_block1, sel_block2,...
The timing in figure 16 is comparable with the timing of the y-shift register, only that the timing is much faster. Again the synchronization pulse must be high on the rising edge of Clock_x. IMPORTANT note : The applied Clock_x, is filtered on chip to remove spikes. This is especially required at these high speeds. This filtering results in an on chip Clock_x that is delayed in time with about 10nsec. In other words, the data at the output has, with respect to the external Clock_x, a propagation delay of 20nsec. This 20nsec come from 10nsec of the generation of the internal Clock_x and 10nsec due to other on chip generated signals.
4.2.1 Reduced Row Overhead Time timing
The row overhead time is the time between the selection of lines that one has to wait to get the data stable at the column amplifiers. This row overhead time is a loss in time, which should be reduced as much as possible.
4.2.1.1 Reduced timing
A straightforward way of reducing the R.O.T is by using a sample and hold function. By means of Sh_col the analog data is tracked during the first 200nsec during the selection of a new set of lines. After 200nsec, the analog data is stored. The ROT is in this case reduced to 200nsec, but as the internal data was not stable yet dynamic range is lost because not the complete analog levels are reached yet after 200ns. Figure 17 shows this principle. Sh_col is now a pulse of 100ns-200ns starting 25 ns after Norowsel. The duration of Sh_col is equal to the ROT. The shorter this time the shorter the ROT will be however this lowers also the dynamic range.
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Figure 17: Reduced standard ROT by means of Sh_col signal. pre_col (short pulse) , Norowsel (short pulse) and Sh_col (large pulse). 4.2.1.2 Standard timing (ROT = 200 ns)
Figure 18: Only pre_col and Norowsel control signals are required. SH_col is made active low.
In this case the control signals Norowsel and pre_col are made active for about 50 nsec from the moment the next line is selected. The time these pulses have to be active is related with the biasing resistance Pre_load. The lower this resistance, the shorter the pulse duration of Norowsel and pre_col may be. After these pulses are given, one has to wait for 180nsec before the first pixels can be sampled. For this mode Sh_col must be made active low.
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4.3
Timing of the Serial Parallel Interface (SPI)
The serial parallel interface is used to upload the x- and y-address into the x- and yaddress registers. This address is the starting point of the window of interest and is uploaded in the shift register by means of the corresponding synchronization pulse. The elementary unit cell of the serial to parallel interface is shown in Figure 19. 16 of these cells are connected in parallel, having a common Load_addr and Clock_spi form the entire uploadable address block. The uploaded addresses are applied to the sensor on the rising edge of signal Load_addr.
To address registers 16 outputs to sensor : 6 x-address bits and 10 y-address bits
D Load_address C
Address Q Clock_spi
Load_addr Address_in D C Q Address_out Clock_spi
Entire uploadable address block
Clock_spi
Unity Cell
address Load_addr
A1
A2
A3
A16
command applied to sensor
Figure 19: Schematic of the SPI interface
The Y-address has to be applied first and the X-address last. With respect to the timing in figure 19, A1 corresponds with the least significant bit of the Y-address (Y0) and A16 corresponds with the most significant bit of the X-address (X5). The Y-address is a 10 bit and the X-address is a 6-bit address register.
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5 Pin configuration
The LUPA-1300 sensor will be packed in a PGA package with 145 pins. Each bond pad consists of 2 pad openings, one for wafer probing and one for bonding. Table 11 gives an overview of the pin names and their functionality.
Pin B3 C3 D3 A2 B2 E3 C2 D2 E2 A1 F3 F2 B1 C1 D1 G3 E1 G2 F1 G1 H3 H2 H1 J1 J2 J3 K1 K2 L1 K3 L2 M1 N1 L3 M2
fp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
Name n.c. n.c. Voo Gnd Out1 Voo Out2 Gnd Out3 Voo Out4 Gnd Out5 Voo Out6 Gnd Out7 Voo Out8 Gnd Out9 Voo Out10 Gnd Out11 Voo Out12 Gnd Out13 Voo Out14 Gnd Out15 Voo Out16
Function
Not connected Supply 5V Ground Analog out Supply 5V Analog out Ground Analog out Supply 5V Analog out Ground Analog out Supply 5V Analog out Ground Analog out Supply 5V Analog out Ground Analog out Supply 5V Analog out Ground Analog out Supply 5V Analog out Ground Analog out Supply 5V Analog out Ground Analog out Supply 5V Analog out
description
Supply voltage output stages : 5V Ground of the sensor Output 1 Supply voltage output stages : 5V Output 2 Ground of the sensor Output 3 Supply voltage output stages : 5V Output 4 Ground of the sensor Output 5 Supply voltage output stages : 5V Output 6 Ground of the sensor Output 7 Supply voltage output stages : 5V Output 8 Ground of the sensor Output 9 Supply voltage output stages : 5V Output 10 Ground of the sensor Output 11 Supply voltage output stages : 5V Output 12 Ground of the sensor Output 13 Supply voltage output stages : 5V Output 14 Ground of the sensor Output 15 Supply voltage output stages : 5V Output 16
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LUPA-1300 Datasheet P1 N2 M3 P2 N3 N4 N5 P3 P5 P4 Q1 N6 P6 Q2 Q3 Q4 N7 P7 Q5 Q6 Q7 N8 P8 Q8 Q9 P9 N9 Q10 Q11 Q12 P10 N10 Q13 P11
36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 Gnd Voo n.c. n.c. Gnd Voo Vstable Load_out Dc_black Vdd Gnd Vdda Gnd Vpix Eos_x Nsf_load Psf_load Col_load Pre_load n.c. Array_diode Full_diode Temp_diode_p Temp_diode_n n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. Vpix Ground Ground of the sensor Supply 5V Supply voltage output stages : 5V
Ground Ground of the sensor Supply 5V Supply voltage output stages : 5V Supply 5V Supply voltage to stabilize output stages : 5.5V Biasing Analog bias for output amplifiers 27K to Voo and capacitor of 100nF to ground Testpin 6 dc-black signal required to characterise the output stages Supply 5V Supply voltage digital modules : 5V Ground Ground of the sensor Supply 5V Supply voltage analog modules : 5V Ground Ground of the sensor Supply 5V Supply voltage pixel array : 5V Digital I/O End of scan signal of the x-register : active high pulse indicates the end of the shift register is reached Biasing Analog bias for column stages : 100K to Vdda and capacitor of 100nF to ground Biasing Analog bias for column stages : 240K to gnd and capacitor of 100nF to Vdda Biasing Analog bias for column stages : 2M to Vdda and capacitor of 100nF to ground Biasing Analog bias for column stages : 10K to Vdda and capacitor of 100nF to ground Testpin 3 Testpin 4 Testpin 1 Testpin 2 Array of pixels as designed in pixel array Full diode with same array as array diode : 140 * 70 m2 Temperature diode p side Temperature diode n side
Supply 5V Supply voltage pixel array : 5V
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LUPA-1300 Datasheet P12 N11 N12 P13 N13 M13 Q14 P14 L13 N14 M14 L14 Q15 K13 K14 P15 N15 M15 J13 L15 J14 K15 J15 H13 H14 H15 G15 G14 G13 F15 F14 E15 F13 E14
70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 Gnd Vddr n.c. Vmem_l Vmem_h Vres_ds Vres Gnd_res n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. Gnd Temp Vdd n.c. n.c. n.c. n.c. Reset_ds Reset Mem_hl Ground Ground of the sensor Supply 5V Supply voltage of the logic for the drivers : 5V Voltage supply for Vmemory drivers : 3V- 5V (typ: 4.5V) Supply Voltage supply for Vmemory drivers : 4V- 6V (typ. 6V) Supply Voltage supply for reset double sloped drivers : 4V - 5V Supply Voltage supply for reset drivers : 5V - 6V (typ 6V) Ground_ab Ground anti-blooming : 0 - 1V Supply
Ground Testpin 5 Supply
Ground for temperature module Dark level signal as function of temperature (figure 7) Supply voltage temperature module : 5V (has to be tunable to adjust output of temperature module to analog output)
Digital I/O Double slope reset of the pixels: active high pulse Digital I/O Reset signal of the pixels : active high pulse Digital I/O Control of Vmemory signal : 5V: Vmem_h, 0V : Vmem_l
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LUPA-1300 Datasheet D15 C15 E13 D14 B15 C14 D13 B14 C13 C12 C11 B13 B11 B12 A15 C10 B10 A14 A13 A12 C9 B9 A11 A10 A9 C8 B8 A8 A7
104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Sample Precharge Eos_y Gnd_Res Vres Vres_ds Vmem_h Vmem_l Vddr Vpix Vdd Gnd n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. Load_addr Address Clock_spi Decy_load Sync_y Clock_y Norow_sel Digital I/O Samples the photodiode voltage onto the memory cell inside each pixel : active high pulse Digital I/O Precharge the memory cell inside the pixel : active high pulse Digital I/O End of scan signal of the y-register : active high pulse indicates the end of the shift register is reached Ground_ab Ground for the reset drivers. Can be used as anti-blooming by applying 1V instead of 0V Supply Voltage supply for reset drivers : 5V - 6V (typ: 6V) Supply Voltage supply for reset double sloped drivers : 4V - 5V Supply Voltage supply for Vmemory drivers : 5V- 6V (typ: 6V) Supply Voltage supply for Vmemory drivers : 3V- 5V (typ: 4.5V) Supply 5V Supply voltage of the logic for the drivers : 5V Supply 5V Supply voltage pixel array : 5V Supply 5V Supply voltage digital modules : 5V Ground Ground of the sensor
Digital I/O Loads the address into the serial parallel interface (SPI) Digital I/O Serial address to be downloaded into the SPI Digital I/O Clock for the SPI Digital I/O Bias for y address register : 27K to ground and capacitor of 100nF to Vdd Digital I/O Synchronisation of y-address register : active high Digital I/O Clock of y-address register Digital I/O Control signal for Norow_sel mode to reduce row blanking time : active low
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Digital I/O Control signal for Sh_col mode to reduce row blanking time : active low (baseline method) : active low Pre_col Digital I/O Additional control signal for reducing the row C7 134 blanking time Sync_x Digital I/O Synchronisation of the x-address register : A6 135 active high Clock_x Digital I/O Clock of the x-address register A5 136 Decx_load Biasing A4 137 Bias for x address register : 27K to ground and capacitor of 100nF to Vdd Black Digital I/O Controls black test function of the output B6 138 stages : active high Sel_active Digital I/O set the output stages active or in standby mode C6 139 : active low Vdd Supply 5V Supply voltage digital modules : 5V A3 140 Gnd Ground Ground of the sensor B5 141 Vdda Supply 5V Supply voltage analog modules : 5V B4 142 Gnd Ground Ground of the sensor C5 143 Voo Supply 5V Supply voltage output stages : 5V C4 144 Table 11 : pin description of the assembled LUPA-1300 sensor in the PGA 144 package.
B7
133
Sh_col
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6 Pad positioning and packaging
6.1 Package
2,54
,78 O1
D B scale 4/1 etail
15 14 13 12 11 10 9
note: 1 die attach area should be m . etallized an d con nected to pad n ber D um 4
3 5,56
8
7
6
5
4
0,90
0,90
,2 R1 7
S C IO A ' E T N -A
4 x 0,5
note 1
C
40,01
R1 ,27
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A'
D 1etail C scale 4/1 ,02 0,51
40,01 23 ,5 1 9,5 1 7,5
0,20
29,62 23,62 25,62
1 ,27 B
0,25
2,80
Figure 20: Package drawing of the LUPA-1300 sensor
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A
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all dim sion in m en s m
4,57
M
G
Q 3 2 1
C
D
H
N
A
B
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P
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6.2 Package and die
Figure 21: Package drawing with die of the LUPA-1300 sensor
The center of the pixel array is located 200 m to the right and 51 m above the center of the package. The first pixel is located at 9160 m to the left and 7219 to the bottom from this center. All distances are with a deviation of 50 m.
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6.3 Color filter
An optional color filter can be processed as well. The LUPA-1300 can also be processed with a Bayer RGB color pattern. Pixel (0,0) has a red filter.
Figure 22: Color filter arrangement on the pixels.
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6.4 Glass transmittance
6.4.1 Monochrome
A D263 glass will be used as protection glass lid on top of the LUPA-1300 monochrome sensors. Figure 23 shows the transmission characteristics of the D263 glass.
100 90
Transmission [%]
80 70 60 50 40 30 20 10 0 400 500 600 700 800 900
Wavelength [nm ]
Figure 23: Transmission characteristics of the D263 glass used as protective cover for the IBIS5A-1300 sensors.
6.4.2 Color
For color devices a near infrared attenuating color filter glass is used. The dominant wavelength is around 490 nm. Figure 24 shows the transmittance curve for the glass. A S8612 glass will be used as NIR cut-off filter on top of the LUPA-1300-C color image sensor. Figure 24 shows the transmission characteristics of the S8612 glass.
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Figure 24: Transmission characteristics of the S8612 glass used as NIR cut-off filter.
6.5 Handling and Storage precautions 6.6 Handling precautions
Special care should be given when soldering image sensors with color filter arrays (RGB color filters), onto a circuit board, since color filters are sensitive to high temperatures. Prolonged heating at elevated temperatures may result in deterioration of the performance of the sensor. The following recommendations are made to ensure that sensor performance is not compromised during end-users' assembly processes. Board Assembly: Device placement onto boards should be done in accordance with strict ESD controls for Class 0, JESD22 Human Body Model, and Class A, JESD22 Machine Model devices. Assembly operators should always wear all designated and approved grounding equipment; grounded wrist straps at ESD protected workstations are recommended including the use of ionized blowers. All tools should be ESD protected. Manual Soldering: When a soldering iron is used the following conditions should be observed: Use a soldering iron with temperature control at the tip.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact info@Fillfactory.com
Document # : 38-05711 Rev.**( Revision 3.1)
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LUPA-1300 Datasheet
The soldering iron tip temperature should not exceed 350C. The soldering period for each pin should be less than 5 seconds.
Precautions and cleaning: Avoid spilling solder flux on the cover glass; bare glass and particularly glass with antireflection filters may be adversely affected by the flux. Avoid mechanical or particulate damage to the cover glass. It is recommended that isopropyl alcohol (IPA) be used as a solvent for cleaning the image sensor glass lid. When using other solvents, it should be confirmed beforehand whether the solvent will dissolve the package and/or the glass lid or not.
6.7 Storage conditions
Description Minimum Temperature -10 Temperature -10 Note: RH = Relative Humidity Maximum 66 38 Units C C Conditions @ 15% RH @ 86% RH
7 Ordering Information
FillFactory Part Number Cypress Semiconductor Part Number
LUPA-1300-C LUPA-1300-M
CYIL1SC1300AA-GAC CYIL1SM1300AA-GBC
Disclaimer
FillFactory image sensors are only warranted to meet the specifications as described in the data sheet. Specifications are subject to change without notice.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact info@Fillfactory.com
Document # : 38-05711 Rev.**( Revision 3.1)
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LUPA-1300 Datasheet
8 Application notes & FAQ
Q: Can the LUPA-1300 directly drive an ADC? A: Yes, coupling the LUPA-1300 to a set of 16 ADC's close to the chip is the preferred way of operation. A suitable ADC must have thus * Input range equal or larger than the 1.2 V- 0 V sensor signal swing * In view of the LUPA-1300's S/N 10 bits are suitable. 11 or 12 bits may be considered too. * Input capacitance 20 pF or lower (high output loads will limit the speed). And no significant resistive loading. * Sampling frequency 40 MHz (or the application specific sample rate) * The ADC's input bandwidth must be sufficiently higher than the sampling frequency, in order to avoid RC contamination between successive pixels. Q: How does the dual slope extended dynamic range mode works? A:
Reset pulse Double slope reset pulse Read out
Reset level 1 p1 Reset level 2 p2 p3 p4 Saturation level
Double slope reset time (usually 5-10% of the total integration time)
Total integration time
Figure 25: Dual slope diagram
The green lines are the analog signal on the photodiode, which decrease as a result of exposure. The slope is determined by the amount of light at each pixel (the more light the steeper the slope). When the pixels reach the saturation level the analog signal will not change despite further exposure. As you can see without any double slope pulse pixels p3 and p4 will reach saturation before the sample moment of the analog
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact info@Fillfactory.com
Document # : 38-05711 Rev.**( Revision 3.1)
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LUPA-1300 Datasheet
values, no signal will be acquired without double slope. When double slope is enabled a second reset pulse will be given (blue line) at a certain time before the end of the integration time. This double slope reset pulse resets the analog signal of the pixels BELOW this level to the reset level. After the reset the analog signal starts to decrease with the same slope as before the double slope reset pulse. If the double slope reset pulse is placed at the end of the integration time (90% for instance) the analog signal that would have reach the saturation levels aren't saturated anymore (this increases the optical dynamic range) at read out. It's important to notice that pixel signals above the double slope reset level will not be influenced by this double slope reset pulse (p1 and p2). Please look at our website to find some pictures taken with the double slope mode on: http://www.fillfactory.be/htm/technology/htm/dual-slope.htm
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact info@Fillfactory.com
Document # : 38-05711 Rev.**( Revision 3.1)
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LUPA-1300 Datasheet
APPENDIX A: LUPA-1300 Evaluation kit
For evaluating purposes a LUPA-1300 evaluation kit is available. The LUPA-1300 evaluation kit consists of a multifunctional digital board (memory, sequencer and IEEE 1394 Fire Wire interface), an ADC-board and an analog image sensor board. Visual Basic software (under Win 2000 or XP) allows the grabbing and display of images and movies from the sensor. All acquired images and movies can be stored in different file formats (8 or 16-bit). All setting can be adjusted on the fly to evaluate the sensors specs. Default register values can be loaded to start the software in a desired state.
Please contact Fillfactory (info@Fillfactory.com) if you want any more information on the evaluation kit.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact info@Fillfactory.com
Document # : 38-05711 Rev.**( Revision 3.1)
Page 47 of 48
LUPA-1300 Datasheet
Document History Page
Document Title: Document Number: LUPA-1300 1.3M High Speed CMOS Image Sensor 38-05711
Rev. **
ECN No. 310396
Issue Date See ECN
Orig. of Change SIL
Description of Change Initial Cypress release
(EOD)
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact info@Fillfactory.com
Document # : 38-05711 Rev.**( Revision 3.1)
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