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| Picture Processor SDA 9290-5 Preliminary Data Features q Noise and cross color reduction by field - or frame q q q q q q q q q NMOS IC recursive filtering 3 adjustments: 4-dB-, 7-dB- or 12-dB reduction Automatic adaption to signal quality during vertical blanking Pixel adaptive movement detection Split screen modes for demonstration purposes Multi-picture facilities Picture decimation using vertical filtering 8 programmable grey levels for framing 4:1:1 and 4:2:2 (Y:U:V) compatibility 8-bit word size for all components P-LCC-68-1 Type SDA 9290-5 Ordering Code Q67100-H5088 Package P-LCC-68-1 (SMD) Functional Description The NMOS device SDA 9290-5 is a picture processor and belongs to a family of devices forming an extended third-generation digital TV signal-processing system for enhanced picture quality with special functions (Featurebox). Besides the Picture Processor (PP) that is described here, the system consists of a field memory (at least three triple-port, 1-Mbit generation TV SequentialAccess Memory devices (SDA 9251 X), a Memory Sync Controller (MSC SDA 9220-5) and a Video D/A converter (SDA 9094-5). A block diagram of the Featurebox is shown in figure 1. The Picture Processor SDA 9290-5 is a follow-on development of the Picture Processor SDA 9090 from the second-generation Featurebox and permits further picture improvement by reducing the video noise and cross-color interference. The SDA 9290-5 can be set independently at the picturesignal input and output via the two pins FSBQ/FSI to the 4:1:1 and 4:2:2 formats. A 4:1:1 Featurebox (3 TV-SAMs) can therefore be operated with 4:2:2 input signals as well. Semiconductor Group 259 01.94 SDA 9290-5 The necessary decimation and interpolation operations are activated automatically when the format is set. Together with a corresponding Memory Sync Controller (SDA 9220) it enables functions like multi-picture, tuner scanning, picture-in-still and still-in-picture. The different modes can be activated by a microcontroller on the I2C Bus interface (slave receiver). The I2C Bus address for accessing the device is 0 0 1 0 1 0 1 0 Circuit Description The core of the picture processor (see block diagram) is formed of the Image-lmproving Processor (IIP) and the Multi-Picture Processor (MPP). The IIP is responsible for noise and cross-color reduction, while the MPP together with the new Memory Sync Controller implements the functions multi-picture, tuner scanning, picture-in-still and still-in-picture. Image-lmproving Processor The signal inputs Yl0-YI7 and UVI0-UVI7 and the back-channel signal inputs YB0-YB7 and UVB0UVB7 picture data with 12 bits in quasi-parallel format (4:1:1) and with 16 bits in parallel format (4:2:2). The clock rate for both signals is 13.5 MHz. For signal processing in the IIP and MPP the chrominance bit levels have to be separated in the case of the quasi parallel format by demultiplexers DEMUXS and DEMUXR, these being largely identical in design. A reduction in video noise is achieved by correlating the picture contents of two successive fields, the non-correlated components (noise) being attenuated by the digital filter. To achieve this, the instantaneous digital picture signal on the outputs of the demultiplexer DEMUXS and the picture signal delayed by a field interval on the outputs of the back-channel demultiplexer DEMUXR are fed to the IIP and combined. The signal-to-noise ratio (S/N) unit detects the noise components of the input signals and the movement detector uses this information to select an appropriate set of parameters with filter coefficients and thresholds for the comparators. For this purpose the luminance signal is assigned to one of three classes according to its S/N ratio, with each class defining a different degree of maximum noise reduction. The limits between the middle class and the upper and lower classes can be programmed by the I2C Bus registers R1 and R2 with the values for the thresholds SU and SL. When the picture signals come from a video cassette recorder, the adaptation on the S/N ratio of the input signal should be disabled by I2L Bus register R0, VCR bit D2. Measurement of the signal-to-noise ratio in the automatic mode has been advanced from line 7 to line 6 in order to avoid conflicts with future text and data services. The degree of noise reduction for the luminance and chrominance signals can be varied between 0 dB and 12 dB by selecting the appropriate filter coefficients. A picture signal with reduced noise and cross-color appears on the output of the IIP for further processing. The signal will be forwarded via blocks MUXI and MUXO to the picture memories through the outputs (YQ0-YQ7 and UVQO-UVQ7 respectively). The coefficients of the selected class are controlled by the movement detector as a function of pixels to prevent artifacts (loss of focus) in moving parts of the picture. Semiconductor Group 260 SDA 9290-5 Multi-Picture Processor Signals are processed in the 4:1:1 format. The vertical-decimation line memory now operates with 208 (formerly 216) pixels per line to adapt the 1/9th picture format to the new picture memory with TV-SAMs. Gray frame generation is similarly affected by this change in pixel value. The signal processing in the decimation filter of the MPP reduces the picture to approximately 1/9th of its original size. This produces a basis for new features, the full implementation of which calls for a matching MSC (SDA 9220). Figure 5 shows how the screen is divided up. The following modes can be implemented with the MPP: 1. Multi-Picture (automatic) Fields are extracted from a sequence of movements at fixed intervals, reduced and reproduced on the screen as a sequence of stills. At one position it is possible to show a moving picture. 2. Multi-Picture (manual) This differs from the above in that the viewer can determine at the push of a button what phases of movement are to be stored. 3. Multi-Picture (tuner scanning) The pictures of the sequence of stills are derived from the different TV channels and give an overview of the programs on offer. In this mode the picture memory is operated with a crystalcontrolled clock to ensure that the picture remains stable when switching from one channel to another. 4. Still-in-Picture A field is extracted from the on-going program, reduced and inserted as a still in the master channel. 5. Picture-in-Still The on-going program is inserted as a reduced-size moving picture in a still. The framing block that follows the decimation filter in the MPP permits frames to be inserted in order to border the reduced-size pictures on the screen. The brightness of the framing can be varied in eight steps by the I2C Bus. The format conversion produced in the demultiplexers for signal processing in the IIP and MPP is reversed again in the multiplexer MUXO. The picture signal appears again in quasi-parallel format or parallel format on the output of the MUXO block. The inputs of the TV-SAMs are directly driven by the sixteen outputs YQ0-YQ7 and UVQ0-UVQ7. Semiconductor Group 261 SDA 9290-5 I2C Bus Interface An I2C Bus interface configured as a "slave receiver" is used for programming the different functions and modes of the picture processor. Via this interface up to four registers can be written according to the following transfer protocol for controlling the operation mode: S Slave Address 0A Sub Address A Data Byte A AP S: Start condition A: Acknowledge P: Stop condition Slave address: 0 0 1 0 1 0 1 (Note: There is a general description of the I2C Bus in the Siemens publication "I2C Bus Technical Description".) After every data byte that is transmitted the internal register address (subaddress) is automatically incremented to the next register so that, if necessary, several registers can be loaded with one I2C Bus telegram. In the multi-picture mode the operating mode transmitted on the I2C Bus is switched within the vertical blanking interval, i.e. during the high phase of signal VS1, if the Memory Sync Controller (MSC) activates the DREQ line during this period. It should be noted that the new operating mode has always to be transmitted to the picture processor first and immediately afterwards to the MSC on the I2C Bus at an interval not longer than 30 ms. This is the only way to ensure interference-free synchronization of the picture processor and the MSC. The four I2C Bus registers are described below in more detail. The values marked "*D" in the right-hand margin are set by an internally generated reset signal (default values) when the operating voltage is applied. Register Subaddress1) D7 R0 R1 R2 R3 00 01 02 03 B1 YF5 0 Data Byte D6 B0 YF4 0 D5 FR YF3 0 SNT0 D4 0 SL4 SU4 KTEN D3 SS SL3 SU3 KT3 D2 VCR SL2 SU2 KT2 D1 NR SL1 SU1 KT1 D0 SUV8 SL0 SU0 KT0 SNTEN SNT1 Semiconductor Group 262 SDA 9290-5 Register R0: This control register sets the operating mode of the picture processor. Bits D7, D6: Mode Normal Multi-picture (MP) Still-in-picture (SIP) Picture-in still (PIS) Bit D5: MPP: Narrow Frame Without narrow frame With narrow frame Bit D4: Bit D3: No function; default 0 Display Mode Full screen Split screen Specialities: Split Screen Display For demonstration purposes the noise reduction can be disabled for half of the picture by means of I2C Bus register R0, bit D3. In this way a direct comparison is possible between a noise-reduced (filtered) and an unfiltered picture. SS 0 1 *D B1 0 0 1 1 FR 0 1 B0 0 1 0 1 *D Bit D2: Control of SNR adaptation TV mode VCR mode VCR 0 1 NR 0 1 SUV8 0 1 *D *D Bit D1: Noise reduction ON/OFF Noise reduction OFF Noise reduction ON Bit D0: Word width input 7 bits 8 bits Semiconductor Group 263 SDA 9290-5 Register R1: This control register sets the frame luminance for multi-picture and the threshold SL for S/N adaptation. Bits D7-D5: Frame Luminance YF 0 : : : 7 Bits D4-D0: black : : : white SL4 0 : : 0 : : 1 YF5 0 : : : 1 SL3 0 : : 0 : : 1 YF4 0 : : : 1 SL2 0 : : 1 : : 1 SL1 0 : : 0 : : YF3 0 : : : 1 SL0 0 : : 0 : : 1 *D *D Threshold SL (S/N adaptation) 0 : : 4 : : 31 Register R2: This control register sets the threshold SU for S/N adaptation. Bits D7-D5: Bits D4-D0: No function; default 0 Threshold SL (S/N adaptation) 0 : : 16 : : 31 SU4 0 : : 1 : : 1 SU3 0 : : 0 : : 1 SU2 0 : : 0 : : 1 SU1 0 : : 0 : : 1 SU0 0 : : 0 : : 1 *D Semiconductor Group 264 SDA 9290-5 Register R3: This register is for testing. certain S/N classes and filter coefficients for the motion detector can be firmly set. Bits D7-D5: S/N Class Automatic adaptation Class 0 Class 1 Class 2 Bits D4-D0: Filter Coefficient Motion detector ON K=1 K = 3/4 K = 5/8 K = 9/16 K = 3/4 K = 1/2 K = 3/8 K = 5/16 K = 5/8 K = 3/8 K = 1/4 K = 3/16 K = 9/16 K = 5/16 K = 3/16 K = 1/8 Note: X is ignored. *D = Default values after reset. SNTEN 0 1 1 1 KTEN 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 KT3 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SNT1 X 0 0 1 KT2 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 KT1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SNT0 X 0 1 0 KT0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 *D *D Semiconductor Group 265 SDA 9290-5 Block Diagram Semiconductor Group 266 SDA 9290-5 Pin Configuration (top view) Semiconductor Group 267 SDA 9290-5 Pin Definitions and Functions Pin No. 1 2-9 Symbol Function Positive supply voltage (+ 5 V) Data outputs Description Positive supply voltage (+ 5 V) Push-pull outputs for directly driving the TV-SAM chrominance inputs: 8 bits for 4:2:2 format; 4 bits for 4:1:1 format; [UVQ0 ... UVQ3 only valid for 4:2:2 format] Ground (0 V) VDD UVQ7 ... UVQ0 10 11-18 19-26 27-34 35-42 43 VSS UVB0 ... UVB7 YB0 ... YB7 UVI0 ... UVI7 YI0 ... YI7 DREQ Ground Back-channel data Back-channel inputs for chrominance data from TV-SAM outputs Back- channel data inputs Data inputs Data inputs Data request signal for multipicture mode Ground Blanking signal (15.625 kHz) First system clock (13.5 or 27 MHz) Selection of system clock frequency (LLIN) Back-channel inputs for luminance data from TV-SAM Data inputs for chrominance data accept the dig. YUV signal Data inputs for luminance data accept the dig. YUV signal Data-request input; initiates data transfer in multi-picture mode and switches mode together with signal VS1 Ground (0 V) Input for line-synchronous blanking signal that determines line blanking interval (active low) and synchronizes clock and sequence control Input for line-locked system clock, optionally 13.5 MHz or 27 MHz, from which internal timing is derived. Positive edge indicates validity of input data Selection of input clock frequency at pin LLIN for adapting the IC to the system clock. Low level for 27-MHz clock frequency; high level for 13.5-MHz clock frequency; no switching inactive mode without picture interference Input for line-locked 13.5-MHz clock that ensured picture stability in multi-picture mode and is used as output clock in every mode I2C Bus shift-clock input 44 45 VSS BLN 46 LLIN 47 LLSEL 48 LL3X Second system clock (13.5 MHz) I2C Bus shift clock input 49 SCL Semiconductor Group 268 SDA 9290-5 Pin Definitions and Functions (cont'd) Pin No. 50 51 52 53 54 55 56 57-59 60 61-68 Symbol SDA VS1 Function I2C Bus data input/output Description I2C Bus data input/output Vertical sync input Vertical sync input; determines vertical position of TV (50 Hz) picture for 50-Hz or 60-Hz field frequency Positive supply voltage (+ 5 V) Positive supply voltage (+ 5 V) VDD FSBQ FSI CLKEN SPEN N.C. Selection of output Switching of data output format: format Low level for 4:1:1 format; high level for 4:2:2 format Selection of input format Switching of data input format: Low level for 4:1:1 format; high level for 4:2:2 format Connect test pin 2 Has to be grounded (0 V) in normal mode Connect test pin 2 Has to be grounded (0 V) in normal mode Reserved Ground Data outputs No connections possible or meaningful Ground (0 V) Push-pull outputs for directly driving TV-SAM inputs for 4:1:1 and 4:2:2 modes; (8-bit luminance) VSS YQ7 ... YQ0 Absolute Maximum Ratings (all voltages are referred to VSS) Parameter Ambient temperature Storage temperature Total power dissipation Supply voltage Input/output voltage Thermal resistance system-air Operating Range Supply voltage Supply current Ambient temperature Symbol Limit Values min. max. 70 125 2.5 - 0.3 - 0.3 6 6 25 C C W V V K/W with heat sink 0 - 40 Unit Remarks TA Tstg Ptot VDD VI/Q Rth SA VDD IDD TA 4.5 0 5.5 450 70 V mA C Semiconductor Group 269 SDA 9290-5 Characteristics (all voltages are referred to VSS) Parameter H-input voltage 1) L-input voltage Input current 1) Input capacitance 1) (except BLN, LLIN) Input capacitance 1) (only BLN, LLIN) H-input voltage 2) L-input voltage 2) Input capacitance Input current 2) H-output voltage 3) L-output voltage 3) L-output voltage 4) Permissible output voltage 4) 1) Symbol Limit Values min. typ. max. 5.5 0.8 10 10 5 3.0 0 5.5 0.8 10 10 2.4 0.4 0.4 5.5 2.0 0 Unit V V A pF pF V V pF A V V V V Test Condition VIH VIL IIR CI CI VIH VIL 2) 1) CI IIM VQH VQL VQL VQM IQH = - 2.0 mA IQH = 3.0 mA IQH = 3.0 mA Input signals UVI0 ... UVI7, YI0 ... YI7, UVB0 ... UVB7, YB0 ... YB7, BLN, LLSEL, FSI, FSBQ, LLIN, LL3X, DREQ, VS1 Input signals SDA, SCL (refer to figure 3) Output signals YQ0-YQ7, UVQ0-UVQ7 Output signal SDA (open drain) 2) 3) 4) Semiconductor Group 270 SDA 9290-5 Characteristics (cont'd) (all voltages are referred to VSS) Parameter Symbol Limit Values min. Input Clock LL3X = 13.5 MHz (refer to figure 3) Cycle Fall time Rise time H-pulse width L-pulse width Change in rel to LLIN TLLL3X 68 74 80 5 5 25 25 0 15 ns ns ns ns ns ns typ. max. Unit Test Condition tTHL tTHL tWH tWL tSK Input Clock LLIN (refer to figure 3) Cycle H-pulse width L-pulse width Cycle H-pulse width L-pulse width Fall time Rise time TLLIN 68 25 25 35 10 10 5 2 5 37 40 74 80 ns ns ns ns ns ns ns ns LLSEL = high LLSEL = high LLSEL = high LLSEL = low LLSEL = low LLSEL = low tWH tWL TLLIN tWH tWL tTHL tTHL Input Clock BLN (refer to figure 2) Setup time Hold time Setup time Hold time H-pulse width Cycle, 625 lines Cycle, 525 lines tSU tIH tSU tIH tWH TBLN TBLN 7 6 15 5 720 864 858 ns ns ns ns TLL3X TLL3X TLL3X LLSEL = low LLSEL = low LLSEL = high LLSEL = high Semiconductor Group 271 SDA 9290-5 Characteristics (cont'd) (all voltages are referred to VSS) Parameter Symbol Limit Values min. Input Signal VS1 Setup time Hold time Cycle, 625 lines Cycle, 525 lines H-pulse width, 625 lines L-pulse width, 525 lines Input Signal DREQ Setup time Hold time H-pulse width typ. max. Unit Test Condition tSU tIH TVS1 TVS1 15 5 312.5 262.5 26.5 16.5 ns ns TBLN TBLN TBLN TBLN Reference LL3X Reference LL3X tWH tWL tSU tIH tWH 15 5 1 16 ns ns TLL3X Reference LL3X Reference LL3X Input Signal (Data) YI0 ... YI7, UVI0 ... UVI7, YB0 ... YB7, UVB0 ... UVB7 (refer to figure 2) Setup time Hold time Setup time Hold time tSU tIH tSU tIH 15 5 15 5 ns ns ns ns Reference LL3X Reference LL3X Reference LLIN Reference LLIN Output Signal (Data) YQ0 ... YQ7, UVQ0 ... UVQ7 (refer to figure 2) Hold time Delay time tQH tQD 6 50 ns ns Reference LL3X Reference LL3X CL = 30 pF Semiconductor Group 272 SDA 9290-5 Figure 1 Application Circuit (simplified) Semiconductor Group 273 SDA 9290-5 Figure 2 Timing Diagram Semiconductor Group 274 SDA 9290-5 Figure 3 Timing Diagram Semiconductor Group 275 SDA 9290-5 Figure 4 Timing for I2C Bus All values are referred to specified input levels VIH and VIL. Parameter Clock frequency Inactive time before start of new transmission Hold time for start condition (after this time first clock pulse is generated) Low clock phase High clock phase Setup time for data Rise time for SDA and SCL signals Fall time for SDA and SCL signals Setup time for SCL clock in stop condition Symbol Limit Values min. max. 100 kHz s s s s ns 1 300 4.7 s ns s 0 4.7 4.0 4.7 4.0 250 Unit fSCL tBUF tHD; STA tLOW tHIGH tSU; tTLH tTHL tSU; STO DAT Semiconductor Group 276 SDA 9290-5 Figure 5 Picture Formats for 9-Image Display Semiconductor Group 277 SDA 9290-5 Y:7-Bit Signal Y:8-Bit Signal Input Picture Processor Back Channel Input YB7 YB6 YB5 YB4 YB3 YB2 YB1 YB0 UVB7 UVB6 UVB5 UVB4 Output YQ7 YQ6 YQ5 YQ4 YQ3 YQ2 YQ1 YQ0 UVQ7 UVQ6 UVQ5 UVQ4 Y6 Y5 Y4 Y3 Y2 Y1 Y0 - U6 U4 U2 U0 U5 U3 U1 V6 V4 V2 V0 V5 V3 V1 Y: Luminance Signal U: Chrominance Signal V: Chrominance Signal Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 U7 U5 U3 U1 U6 U4 U2 U0 V7 V5 V3 V1 V6 V4 V2 V0 YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 UVI7 UVI6 UVI5 UVI4 Figure 6 Assignment of Signal and Pin Names Format 4:1:1 Semiconductor Group 278 SDA 9290-5 Signal Input Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 UVI7 UVI6 UVI5 UVI4 UVI3 UVI2 UVI1 UVI0 Picture Processor Back Channel Input YB7 YB6 YB5 YB4 YB3 YB2 YB1 YB0 UVB7 UVB6 UVB5 UVB4 UVB3 UVB2 UVB1 UVB0 Output YQ7 YQ6 YQ5 YQ4 YQ3 YQ2 YQ1 YQ0 UVQ7 UVQ6 UVQ5 UVQ4 UVQ3 UVQ2 UVQ1 UVQ0 Figure 7 Assignment of Signal and Pin Names Format 4:2:2 Semiconductor Group 279 SDA 9290-5 Figure 8 Output Data Delay Times Semiconductor Group 280 |
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