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Picture Processor
SDA 9290-6
Preliminary Data Features * Noise and cross color reduction by field - or frame recursive filtering * Adjustment of degree of noise reduction * Automatic adaption to signal quality during vertical blanking * Pixel adaptive movement detection * Split screen modes for demonstration purposes * Multi-picture facilities * Picture decimation using vertical filtering * 8 programmable grey levels for framing * 4:1:1 and 4:2:2 (Y:U:V) compatibility * 8-bit word size for all components * IIC-Bus programming of the video line for S/N measurement in automatic adaption mode * Optimized characteristics of the recursive filters
CMOS IC
P-LCC-68-1
Type SDA 9290-6 Functional Description
Ordering Code Q67101-H5193
Package P-LCC-68-1 (SMD)
The CMOS device SDA 9290-6 is a picture processor and belongs to a family of devices forming an extended third-generation digital TV signal-processing system for enhanced picture quality with special functions (Featurebox). Besides the Picture Processor (PP) that is described here, the system consists of a field memory (at least three triple-port, 1-Mbit generation TV Sequential-Access Memory devices (SDA 9251 X), a Memory Sync Controller (MSC SDA 9220-5) and a Display Prozessor (SDA 9280). A block diagram of the Featurebox is shown in figure 4. The Picture Processor SDA 9290-6 is a follow-on development of the Picture Processor SDA 9290-5. Modifications of the movement detector and the recursive filters permits further picture improvement by reducing the video noise and cross-color interference. The SDA 9290-6 can be set independently at the picture-signal input and output via the two pins FSBQ/FSI to the 4:1:1 and 4:2:2 formats. A 4:1:1 Featurebox (3 TV-SAMs) can therefore be operated with 4:2:2 input signals as well.
Semiconductor Group
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SDA 9290-6
The necessary decimation and interpolation operations are activated automatically when the format is set. Together with a corresponding Memory Sync Controller (SDA 9220) it enables functions like multi-picture, tuner scanning, picture-in-still and still-in-picture. The different modes can be activated by a microcontroller on the I2C-Bus interface (slave receiver). The I2C-Bus address for accessing the device is 0 0 1 0 1 0 1 0
Circuit Description The core of the picture processor (see block diagram) is formed of the Image-lmproving Processor (IIP) and the Multi-Picture Processor (MPP). The IIP is responsible for noise and cross-color reduction, while the MPP together with the new Memory Sync Controller implements the functions multi-picture, tuner scanning, picture-in-still and still-in-picture. Image-lmproving Processor The signal inputs Yl0-YI7 and UVI0-UVI7 and the back-channel signal inputs YB0-YB7 and UVB0-UVB7 picture data with 12 bits in quasi-parallel format (4:1:1) and with 16 bits in parallel format (4:2:2). The clock rate for both signals is 13.5 MHz. For signal processing in the IIP and MPP the chrominance bit levels have to be separated in the case of the quasi parallel format by demultiplexers DEMUXS and DEMUXR, these being largely identical in design. A reduction in video noise is achieved by correlating the picture contents of two successive fields, the non-correlated components (noise) being attenuated by the digital filter. To achieve this, the instantaneous digital picture signal on the outputs of the demultiplexer DEMUXS and the picture signal delayed by a field interval on the outputs of the back-channel demultiplexer DEMUXR are fed to the IIP and combined. The signal-to-noise ratio (S/N) unit detects the noise components of the input signals and the movement detector uses this information to select an appropriate set of parameters with filter coefficients and thresholds for the comparators. For this purpose the luminance signal is assigned to one of three classes according to its S/N ratio, with each class defining a different degree of maximum noise reduction. The limits between the middle class and the upper and lower classes can be programmed by the I2C-Bus registers R1 and R2 with the values for the thresholds SU and SL. When the picture signals come from a video cassette recorder, the adaptation on the S/N ratio of the input signal should be disabled by I2L-Bus register R0, VCR bit D2. Measurement of the signal-to-noise ratio in the automatic mode has been advanced from line 6 to line 4 in order to avoid conflicts with future text and data services. The degree of noise reduction for the luminance and chrominance signals can be varied between 0 dB and 12 dB by selecting the appropriate filter coefficients.
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SDA 9290-6
A picture signal with reduced noise and cross-color appears on the output of the IIP for further processing. The signal will be forwarded via blocks MUXI and MUXO to the picture memories through the outputs (YQ0-YQ7 and UVQO-UVQ7 respectively). The coefficients of the selected class are controlled by the movement detector as a function of pixels to prevent artifacts (loss of focus) in moving parts of the picture. The video line for S/N measurement can be programmed by the I2C-Bus register R2 (D7-D5). Multi-Picture Processor Signals are processed in the 4:1:1 format. The vertical-decimation line memory again operates with 208 pixels per line to adapt the 1/9th picture format to the new picture memory with TV-SAMs. Gray frame generation is similarly affected by this change in pixel value. The signal processing in the decimation filter of the MPP reduces the picture to approximately 1/9th of its original size. This produces a basis for new features, the full implementation of which calls for a matching MSC (SDA 9220). Figure 8 shows how the screen is divided up. The following modes can be implemented with the MPP: 1. Multi-Picture (automatic) Fields are extracted from a sequence of movements at fixed intervals, reduced and reproduced on the screen as a sequence of stills. At one position it is possible to show a moving picture. 2. Multi-Picture (manual) This differs from the above in that the viewer can determine at the push of a button what phases of movement are to be stored. 3. Multi-Picture (tuner scanning) The pictures of the sequence of stills are derived from the different TV channels and give an overview of the programs on offer. In this mode the picture memory is operated with a crystal-controlled clock to ensure that the picture remains stable when switching from one channel to another. 4. Still-in-Picture A field is extracted from the on-going program, reduced and inserted as a still in the master channel. 5. Picture-in-Still The on-going program is inserted as a reduced-size moving picture in a still. The framing block that follows the decimation filter in the MPP permits frames to be inserted in order to border the reduced-size pictures on the screen. The brightness of the framing can be varied in eight steps by the I2C Bus. The format conversion produced in the demultiplexers for signal processing in the IIP and MPP is reversed again in the multiplexer MUXO. The picture signal appears again in quasi-parallel format or parallel format on the output of the MUXO block. The inputs of the TV-SAMs are directly driven by the sixteen outputs YQ0-YQ7 and UVQ0-UVQ7.
Semiconductor Group 3 1997-07-22
SDA 9290-6
1. Field 624 CVBS 625 1 2 3 4 5 6 7 8
BLN
VS SDA 9290-6 000 LINE 001 010 011 100 101 110 111
(4) (Default) (0) (1) (2) (3) (5) (6) (7)
SDA 9290-5
2. Field 312 313 314 315 316 317 318 319 320
BLN
VS SDA 9290-6 000 LINE 001 010 011 100 101 110 111
(4) (Default) (0) (1) (2) (3) (5) (6) (7)
UED09849
SDA 9290-5
Figure 1 Programmable Video Lines
Semiconductor Group 4 1997-07-22
SDA 9290-6
I2C Bus Interface An I2C Bus interface configured as a "slave receiver" is used for programming the different functions and modes of the picture processor. Via this interface up to four registers can be written according to the following transfer protocol for controlling the operation mode:
S
Slave Address
0A
Sub Address
A
Data Byte
A
AP
S: Start condition A: Acknowledge P: Stop condition Slave address: 0 0 1 0 1 0 1 (Note: There is a general description of the I2C Bus in the Siemens publication "I2C Bus Technical Description".) After every data byte that is transmitted the internal register address (subaddress) is automatically incremented to the next register so that, if necessary, several registers can be loaded with one I2C Bus telegram. In the multi-picture mode the operating mode transmitted on the I2C Bus is switched within the vertical blanking interval, i.e. during the high phase of signal VS1, if the Memory Sync Controller (MSC) activates the DREQ line during this period. It should be noted that the new operating mode has always to be transmitted to the picture processor first and immediately afterwards to the MSC on the I2C Bus at an interval not longer than 30 ms. This is the only way to ensure interference-free synchronization of the picture processor and the MSC. The four I2C Bus registers are described below in more detail. The values marked "*D" in the right-hand margin are set by an internally generated reset signal (default values) when the operating voltage is applied.
Register Subaddress1) D7 R0 R1 R2 R3 00 01 02 03 B1 YF5 LINE2
Data Byte D6 B0 YF4 LINE1 D5 FR YF3 LINE0 SNT0 D4 0 SL4 SU4 KTEN D3 SS SL3 SU3 KT3 D2 VCR SL2 SU2 KT2 D1 NR SL1 SU1 KT1 D0 SUV8 SL0 SU0 KT0
SNTEN SNT1
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SDA 9290-6
Register R0:
This control register sets the operating mode of the picture processor. B1 0 0 1 1 FR 0 1 *D B0 0 1 0 1 *D
Bits D7, D6: Mode Normal Multi-picture (MP) Still-in-picture (SIP) Picture-in still (PIS) Bit D5: MPP: Narrow Frame Without narrow frame With narrow frame Bit D4: Bit D3: No function; default 0 Display Mode Full screen Split screen
SS 0 1 *D
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Specialities Split Screen Display For demonstration purposes the noise reduction can be disabled for half of the picture by means of I2C-Bus register R0, bit D3. In this way a direct comparison is possible between a noise-reduced (filtered) and an unfiltered picture.
Bit D2:
Control of SNR adaptation TV mode VCR mode
VCR 0 1 NR 0 1 SUV8 0 1 *D *D *D
Bit D1:
Noise reduction ON/OFF Noise reduction OFF Noise reduction ON
Bit D0:
Word width input 7 bits 8 bits
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Register R1:
This control register sets the frame luminance for multi-picture and the threshold SL for S/N adaptation. YF5 0 : : : 1 SL4 0 : : 0 : : 1 SL3 0 : : 0 : : 1 YF4 0 : : : 1 SL2 0 : : 1 : : 1 SL1 0 : : 0 : : YF3 0 : : : 1 SL0 0 : : 0 : : 1 *D *D
Bits D7-D5: Frame Luminance YF 0 : : : 7 black : : : white
Bits D4-D0: Threshold SL (S/N adaptation) 0 : : 4 : : 31
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Register R2:
This control register sets the threshold SU for S/N adaptation, and the values for the line counter. Noise Measurement: Decoded Values of the Line Counter
Bits D7-D5: LINE2 0 0 0 0 1 1 1
LINE1 0 0 1 1 0 0 1
LINE0 0 1 0 1 0 1 0
Decoded Value 4 0 1 2 3 5 7 *D
Bits D4-D0: Threshold SU (S/N adaptation) 0 : : 16 : : 31
SU4 0 : : 1 : : 1
SU3 0 : : 0 : : 1
SU2 0 : : 0 : : 1
SU1 0 : : 0 : : 1
SU0 0 : : 0 : : 1 *D
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Register R3:
This register is for testing. certain S/N classes and filter coefficients for the motion detector can be firmly set. SNTEN 0 1 1 1 KTEN 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 KT3 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SNT1 X 0 0 1 KT2 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 KT1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SNT0 X 0 1 0 KT0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 *D
*D
Bits D7-D5: S/N Class Automatic adaptation Class 0 Class 1 Class 2 Bits D4-D0: Filter Coefficient Motion detector ON K=1 K = 3/4 K = 5/8 K = 9/16 K = 3/4 K = 1/2 K = 3/8 K = 5/16 K = 5/8 K = 3/8 K = 1/4 K = 3/16 K = 9/16 K = 5/16 K = 3/16 K = 1/8
Note: X is ignored. *D = Default values after reset.
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Semiconductor Group 11 1997-07-22
Figure 2 Block Diagram
YI UVI DREQ LL3X BLN VS1 LLIN LLSEL FSI FSBQ SDA SCL YB UVB 8 8 8 8
2
GND MPP DEMUXS 16 12 Decimation- 12 4:1:1 Filters Decimation Line Memory 12 4:2:2 Interpolator Framing 16
V DD
Clock Generation ControlSignals
YS, USVS 16 YS 8 "S / N" Measure ment 12 SN S1,S2 10 8 8 16 YR , URVR YS YR ROM K0,K1 10 KY 5 Movement 5 Detector KUV IIP
YIM, UIMVIM
YI, MUXI MUXO 8 UIVI "1" 16 8 "0" 16 Recursive Filters 16 16 SI YII, UIIVII
YO UVO
C Bus Receiver
DEMUXR
SDA 9290-6
UEB09850
SDA 9290-6
UVQ0 UVQ1 UVQ2 UVQ3 UVQ4 UVQ5 UVQ6 UVQ7 V DD YQ0 YQ1 YQ2 YQ3 YQ4 YQ5 YQ6 YQ7
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 GND UVB0 UVB1 UVB2 UVB3 UVB4 UVB5 UVB6 UVB7 YB0 YB1 YB2 YB3 YB4 YB5 YB6 YB7 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 GND N.C. N.C. N.C. SPEN CLKEN FSI FSBQ V DD VS1 SDA SCL LL3X LLSEL LLIN BLN GND
SDA 9290-6
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
UVI0 UVI1 UVI2 UVI3 UVI4 UVI5 UVI6 UVI7 YI0 YI1 YI2 YI3 YI4 YI5 YI6 YI7 DREQ
UEP09851
Figure 3 Pin Configuration (top view)
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Pin Definitions and Functions
Pin No. Symbol 1 2-9 Function Positive supply voltage (+ 5 V) Description Positive supply voltage (+ 5 V) Push-pull outputs for directly driving the TV-SAM chrominance inputs: 8 bits for 4:2:2 format; 4 bits for 4:1:1 format; [UVQ0 ... UVQ3 only valid for 4:2:2 format] Ground (0 V) Back-channel inputs for chrominance data from TV-SAM Back-channel inputs for luminance data from TV-SAM Data inputs for chrominance data accept the dig. YUV signal Data inputs for luminance data accept the dig. YUV signal Data-request input; initiates data transfer in multi-picture mode and switches mode together with signal VS1 Ground (0 V) Input for line-synchronous blanking signal that determines line blanking interval (active low) and synchronizes clock and sequence control Input for line-locked system clock, 13.5 MHz, from which internal timing is derived. Positive edge indicates validity of input data Must be connected to VDD (high-level) Input for line-locked 13.5-MHz clock that ensured picture stability in multi-picture mode and is used as output clock in every mode
VDD
UVQ7 ... Data outputs UVQ0
10 11-18 19-26 27-34 35-42 43
GND UVB0 ... UVB7 YB0 ... YB7 UVI0 ... UVI7 YI0 ... YI7 DREQ
Ground Back-channel data outputs Back- channel data inputs Data inputs Data inputs Data request signal for multipicture mode Ground Blanking signal (15.625 kHz) First system clock (13.5 MHz) none Second system clock (13.5 MHz)
44 45
GND BLN
46
LLIN
47 48
LLSEL LL3X
49 50 51 52
SCL SDA VS1
I2C Bus shift clock I2C-Bus shift-clock input input I2C Bus data input/output I2C-Bus data input/output
Vertical sync input Vertical sync input; determines vertical position of TV (50 Hz) picture for 50-Hz or 60-Hz field frequency Positive supply voltage (+ 5 V) Positive supply voltage (+ 5 V)
VDD
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SDA 9290-6
Pin Definitions and Functions (cont'd)
Pin No. Symbol 53 54 55 56 57-59 60 61-68 FSBQ FSI CLKEN SPEN N.C. GND YQ7 ... YQ0 Function Description Selection of output Switching of data output format: format Low level for 4:1:1 format; high level for 4:2:2 format Selection of input format Switching of data input format: Low level for 4:1:1 format; high level for 4:2:2 format
Connect test pin 2 Has to be grounded (0 V) in normal mode Connect test pin 2 Has to be grounded (0 V) in normal mode Reserved Ground Data outputs No connections possible or meaningful Ground (0 V) Push-pull outputs for directly driving TV-SAM inputs for 4:1:1 and 4:2:2 modes; (8-bit luminance)
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Electrical Characteristics Absolute Maximum Ratings (all voltages are referred to GND) Parameter Ambient temperature Storage temperature Total power dissipation Supply voltage Input/output voltage Thermal resistance system-air Symbol Limit Values min. max. 70 125 1 - 0.3 - 0.3 6 6 38 C C W V V K/W with heat sink 0 - 40 Unit Remarks
TA Tstg Ptot VDD VI/Q Rth SA
Operating Range Supply voltage Supply current Ambient temperature
VDD IDD TA
4.5 0
5.5 180 70
V mA C
Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Note: In the operating range the functions given in the circuit description are fulfilled.
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SDA 9290-6
Characteristics (all voltages are referred to GND) Parameter H-input voltage 1) L-input voltage 1) Input current 1) Input capacitance 1) (except BLN, LLIN) Input capacitance 1) (only BLN, LLIN) H-input voltage 2) L-input voltage 2) Input capacitance 2) Input current 2) H-output voltage 3) L-output voltage 3) L-output voltage 4) Permissible output voltage 4)
1)
Symbol
Limit Values min. typ. max. 5.5 0.8 10 10 5 3.0 0 5.5 0.8 10 10 2.4 0.4 0.4 5.5 2.0 0
Unit V V A pF pF V V pF A V V V V
Test Condition
VIH VIL IIR CI CI VIH VIL CI IIM VQH VQL VQL VQM
IQH = - 2.0 mA IQH = 3.0 mA IQH = 3.0 mA
Input signals UVI0 ... UVI7, YI0 ... YI7, UVB0 ... UVB7, YB0 ... YB7, BLN, LLSEL, FSI, FSBQ, LLIN, LL3X, DREQ, VS1 Input signals SDA, SCL (refer to figure 6) Output signals YQ0-YQ7, UVQ0-UVQ7 Output signal SDA (open drain)
2) 3) 4)
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SDA 9290-6
Characteristics (cont'd) (all voltages are referred to GND) Parameter Symbol Limit Values min. typ. max. Unit Test Condition
Input Clock LL3X = 13.5 MHz (refer to figure 6) Cycle Fall time Rise time H-pulse width L-pulse width Change in rel to LLIN TLLL3X 68 74 80 5 5 25 25 0 15 ns ns ns ns ns ns
tTHL tTHL tWH tWL tSK
Input Clock LLIN (refer to figure 6) Cycle H-pulse width L-pulse width Fall time Rise time TLLIN 68 25 25 5 2 5 74 80 ns ns ns ns ns LLSEL = high LLSEL = high LLSEL = high
tWH tWL tTHL tTHL
Input Clock BLN (refer to figure 5) Setup time Hold time H-pulse width Cycle, 625 lines Cycle, 525 lines
tSU tIH tWH
TBLN TBLN
15 5 720 864 858
ns ns TLL3X TLL3X TLL3X
LLSEL = high LLSEL = high
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Characteristics (cont'd) (all voltages are referred to GND) Parameter Symbol Limit Values min. Input Signal VS1 Setup time Hold time Cycle, 625 lines Cycle, 525 lines H-pulse width, 625 lines H-pulse width, 525 lines Input Signal DREQ Setup time Hold time H-pulse width typ. max. Unit Test Condition
tSU tIH
TVS1 TVS1
15 5 312.5 262.5 26.5 16.5
ns ns TBLN TBLN TBLN TBLN
Reference LL3X Reference LL3X
tWH tWH
tSU tIH tWH
15 5 1 16
ns ns TLL3X
Reference LL3X Reference LL3X
Input Signal (Data) YI0 ... YI7, UVI0 ... UVI7, YB0 ... YB7, UVB0 ... UVB7 (refer to figure 5) Setup time Hold time Setup time Hold time
tSU tIH tSU tIH
15 5 15 5
ns ns ns ns
Reference LL3X Reference LL3X Reference LLIN Reference LLIN
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Characteristics (cont'd) (all voltages are referred to GND) Parameter Symbol Limit Values min. typ. max. Unit Test Condition
Output Signal (Data) YQ0 ... YQ7, UVQ0 ... UVQ7 (refer to figure 5) Hold time Delay time
tQH tQD
6 50
ns ns
Reference LL3X Reference LL3X CL = 30 pF
Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage.
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Figure 4 Application Circuit (simplified)
Y8
13.5 MHz
YI
V DD GND SDA SCL
12 SQB YB UVB 13.5 MHz 12 SDC YQ UVQ 13.5 MHz
V DD GND
12
V DD
GND
Y -( B-Y ) -( R-Y )
UV 4
13.5 MHz
UVI FSI
PP II SDA 9290-6
3 x TV-SAM SDA 9251-2X
YI SQA 27 MHz UVI OEA
SCA CLL
DP SDA 9280
FSBQ
OEB
BLN LLIN LLSEL VS1 DREQ LL3X
SCB WT RB SAC SAR SCAD RE RA SCA
BLN
SDA
SCL
V DD
LL3X WT RB SAC SAR SCAD RE RA SCA MUX
LL1.5X
DREQ VS1 VS BLN LL3 VS BLN LLIN LLSEL CFH CFH
LL1.5X BLN2 FRM FRM
MSC III SDA 9220-5
VS2 VS2 HS2 CSY HS2 CSY
WEI ADR V DD GND V DDA GND OSCI OSCO RST NW RESI RESO SDA SCL
SDA 9290-6
C 2 C F2 C1
RF C F1
UES09852
SDA 9290-6
T LLIN ,TLL3X
t WH
Input Clocks LL3X, LLIN
t THL
t WL
t TLH
2.0V 0.8V
t SU
Input Signals
t IH
2.0V 0.8V
t QH
2.4V Output Signals 0.4V
t QD
UET02221
Figure 5 Timing Diagram
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T LLIN
t WH
Input Clock
t WL VH VL
t SK
t THL
t TLH
VQH
Reference Clock LL3X
VQL t WH t THL
T
t WL
t TLH
T LL3X Output Reference Clock 2.4V 0.4V
t WH t QH
t THL
t WL
t TLH
2.4V Output Signal 0.4V
t QD
T LLIN
t WH
Input Reference Clock
t THL
t WL
t TLH
2.0V= VIH 0.8V= VIL
t SU
Input Signal
t IH
2.0V 0.8V
UET02222
Figure 6 Timing Diagram
Semiconductor Group 22 1997-07-22
SDA 9290-6
t HD, STA
SDA
t BUF
SCL Stop Start
t TLH
t THL
t LOW t HD, DAT
t HIGH t SU, DAT
Stop
t SU, STO
UET00130
Figure 7 Timing for I2C Bus
Table 1 All values are referred to specified input levels VIH and VIL. Parameter Clock frequency Inactive time before start of new transmission Hold time for start condition (after this time first clock pulse is generated) Low clock phase High clock phase Setup time for data Rise time for SDA and SCL signals Fall time for SDA and SCL signals Setup time for SCL clock in stop condition Symbol Limit Values min. max. 100 kHz s s s s ns 1 300 4.7 s ns s 0 4.7 4.0 4.7 4.0 250 Unit
fSCL tBUF tHD; STA tLOW tHIGH tSU; DAT tTLH tTHL tSU; STO
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SDA 9290-6
720 Pixels 48 Pixels 208 Pixels 48 Pixels
18(15) Lines
84(71) Lines
1
2
3
288(243) Lines
4
5
6
18(15) Lines
7
8
9
Without Frame Stored Picture 48 Pixels 204 Pixels 4 Pixels
52 Pixels
18(15) Lines
82(69) Lines
1
2
3
2(2) Lines
4
5
6
20(17) Lines
7
8
9
With Frame
50(60)-Hz Standard
UES02223
Figure 8 Picture Formats for 9-Image Display
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SDA 9290-6
Table 2 Assignment of Signal and Pin Names Format 4:1:1 Y:7-Bit Signal Y:8-Bit Signal Input Picture Processor Back Channel Input YB7 YB6 YB5 YB4 YB3 YB2 YB1 YB0 UVB7 UVB6 UVB5 UVB4 Output
Y6 Y5 Y4 Y3 Y2 Y1 Y0 - U6 U4 U2 U0 U5 U3 U1 V6 V4 V2 V0 V5 V3 V1
Y: Luminance Signal U: Chrominance Signal V: Chrominance Signal
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 U7 U5 U3 U1 U6 U4 U2 U0 V7 V5 V3 V1 V6 V4 V2 V0
YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 UVI7 UVI6 UVI5 UVI4
YQ7 YQ6 YQ5 YQ4 YQ3 YQ2 YQ1 YQ0 UVQ7 UVQ6 UVQ5 UVQ4
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Table 3 Assignment of Signal and Pin Names Format 4:2:2 Signal Input Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 UVI7 UVI6 UVI5 UVI4 UVI3 UVI2 UVI1 UVI0 Picture Processor Back Channel Input YB7 YB6 YB5 YB4 YB3 YB2 YB1 YB0 UVB7 UVB6 UVB5 UVB4 UVB3 UVB2 UVB1 UVB0 Output YQ7 YQ6 YQ5 YQ4 YQ3 YQ2 YQ1 YQ0 UVQ7 UVQ6 UVQ5 UVQ4 UVQ3 UVQ2 UVQ1 UVQ0
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SDA 9290-6
Figure 9 Output Data Delay Times
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SDA 9290-6
Package Outlines P-LCC-68-1 (SMD) (Plastic Leaded Chip Carrier)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 28
Dimensions in mm 1997-07-22
GPL05099

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