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FEATURES 11 LDOs Optimized for Specific CDMA Subsystems 4 Backup LDOs for Standby Mode Operation Ultra Low Standby Supply Current High Accuracy Battery Charger (0.7%) 3 Li-Ion Battery Charge Modes 5 mA Precharge Low Current Charge Full Current Charge Integrated RTC Ambient Temperature: -30 C to +85 C 64-Lead 7 mm 7 mm 1 mm TQFP Package APPLICATIONS CDMA/CDMA2000/PCS Handsets
CDMA Power Management System ADP3502
FUNCTIONAL BLOCK DIAGRAM
LOGIC BLOCK POWER ON DELAY 10ms ANALOG BLOCK BATTERY CHARGER
KEYPAD I/F
INTERRUPT CONTROL LDO CONTROL
REFERENCE
GPIO
LDO1 TO LDO11
SERIAL I/F
RESET
VOLTAGE DETECTOR
32kHz OUTPUT CONTROL
RTC COUNTER
GENERAL DESCRIPTION
RESET OUTPUT
ADP3502
STAY-ALIVE TIMER
The ADP3502 is a multifunction chip optimized for CDMA-1x cell phone power management. It offers a total power solution for the handset baseband and RF section, including LDOs to power 11 subsystems. Also integrated are a real-time clock (RTC), serial bus interface, and charging control for Li-Ion/ Li-Polymer batteries. Sophisticated controls are available for power-up during battery charging, keypad interface, GPIO/INT function, and RTC function. The ADP3502 is optimized for CDMA handsets powered by single-cell Li-Ion batteries. Its high level of integration significantly reduces the design effort, number of discrete components, and solution size/cost. The main-sub LDO structure reduces the standby current consumption, and as a result, greatly extends the standby time of the phone. System operation has been proven to be fully compatible with MSM51xx-based designs. The ADP3502 comes in a 64-lead 7 mm x 7 mm x 1 mm TQFP package and is specified over a wide temperature range of -30C to +85C.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
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ADP3502-SPECIFICATIONS
MAIN FUNCTIONS
Parameter SHUTDOWN GND CURRENT Power OFF
(TA = -30 C to +85 C, CVBAT = 1 F MLCC, VBAT = 3.6 V, unless otherwise noted. See Table II for COUT.)
Symbol Conditions IGND TA = -20C to +60C LDO3b: ON, Connect to RTCV through Schottky Diode RTC/32K OSC: Active All Other LDOs: OFF All Logic Inputs: VBAT or GND MVBAT: OFF IGND LDO1b, LDO2b, LDO3b, LDO6b: ON IO = 1 mA for LDO3b and LDO6b IO = 3 mA for LDO1b IO = 300 A for LDO2b All Other LDOs: OFF RTC/32K OSC: Active MVBAT: OFF All Logic Output: No Load LDO1, LDO2, LDO3, LDO6, All Sub-LDOs: ON, IO = 70% Load All Other LDOs: OFF RTC/32K OSC: Active MVBAT: ON All Logic Outputs: No Load LDO5: OFF All Other LDOs: ON, 70% Load RTC/32K OSC: Active All Logic Outputs: No Load MVBAT: ON 60 125 A 25 45 A Min Typ Max Unit
OPERATING GND CURRENT Standby Mode Operation (Light Load)
Standby Mode Operation (Midload)
300
A
Active Operation
700
A
THERMAL SHUTDOWN THRESHOLD THERMAL SHUTDOWN HYSTERESIS ADAPTER/ADPSUPPLY VOLTAGE RANGE VADP VBAT VOLTAGE RANGE VBAT 5 3.3
160 35 12 5.5
C C V V
LDO SPECIFICATIONS
Parameter
(TA = 25 C, CVBAT = 1 F MLCC, VBAT = VOUT + 1 V, NRCAP = 0.1 F. See Table II for COUT.)
Symbol Conditions VLDO1a CLDO1a VDO IO = 1 mA to 150 mA TA = -30C to +85C IO = 150 mA Min 2.81 2.2 200 250 2.8 2.87 3.0 Typ 2.90 Max 2.99 Unit V F mV s V
BASEBAND VDD MAIN-LDO (LDO1a) Output Voltage Output Capacitor Required for Stability Dropout Voltage Start-Up Time from Shutdown BASEBAND VDD SUB-LDO (LDO1b) Output Voltage
VLDO1b
IO = 3 mA TA = -30C to +85C
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ADP3502
Parameter BASEBAND AVDD MAIN-LDO (LDO2a) Output Voltage Symbol VLDO2a Conditions 16 Steps, 20 mV/Step, IO = 50 mA Code: 1000 Code: 0111 TA = 25C IO = 50 mA, TA = 25C 16 Steps, 20 mV/Step, IO = 50 mA Code: 1000 Code: 0111 TA = -30C to +85C IO = 50 mA, TA = -30C to +85C IO = 50 mA f = 1 kHz f = 100 Hz to 100 kHz Min Typ Max Unit
2.30 2.60 2.46 2.29 2.57 2.42 1
2.36 2.66 2.52 2.36 2.66 2.52 210 60 120 250
2.43 2.74 2.6 2.47 2.81 2.66
V V V V V V F mV dB V rms s V
Output Default Voltage Output Voltage
VLDO2a VLDO2a
Output Default Voltage Output Capacitor Required for Stability Dropout Voltage Ripple Rejection Output Noise Voltage Start-Up Time from Shutdown BASEBAND AVDD SUB-LDO (LDO2b) Output Voltage REFO SWITCH On Resistance Off Leak COIN CELL MAIN-LDO (LDO3a) Output Voltage Dropout Voltage Output Capacitor Required for Stability Start-Up Time from Shutdown COIN CELL SUB-LDO (LDO3b) Output Voltage AUDIO LDO (LDO4) Output Voltage Output Capacitor Required for Stability Dropout Voltage Ripple Rejection Output Noise Voltage Start-Up Time from Shutdown VIBRATOR LDO (LDO5) Output Voltage Dropout Voltage Output Capacitor Required for Stability BASEBAND CORE MAIN-LDO (LDO6a) Output Voltage Output Capacitor Required for Stability Dropout Voltage Start-Up Time from Shutdown
VLDO2a CLDO2a VDO VNOISE
VLDO2b
IO = 300 A, VLDO2MAIN = 2.6 V TA = -30C to +85C TA = -30C to +85C, IO = 500 A LDO2: ON, Switch: OFF IO = 1 mA to 50 mA TA = -30C to +85C IO = 50 mA
2.50
2.57
2.70
RON ILEAK VLDO3a VDO CLDO3a
50 0.01 2.90 3.0 140 1 250
130 1 3.09
A V mV F s
VLDO3b
IO = 1 mA TA = -30C to +85C IO = 1 mA to 180 mA TA = -30C to +85C IO = 180 mA f = 1 kHz f = 100 Hz to 10 kHz
2.85
2.97
3.15
V
VLDO4 CLDO4 VDO VNOISE
2.81 2.2
2.9
2.99
V F mV dB V rms s
200 60 50 250 2.75 2.9 200 2.2 3.05
VLDO5 VDO CLDO5 VLDO6a CLDO6a VDO
IO = 1 mA to 150 mA TA = -30C to +85C IO = 150 mA
V mV F
IO = 1 mA to 150 mA TA = -30C to +85C IO = 150 mA
2.75 2.2
2.85
2.95
V F mV s
200 250
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ADP3502 LDO SPECIFICATIONS (continued)
Parameter BASEBAND CORE SUB-LDO (LDO6b) Output Voltage RF RX1 LDO (LDO7) Output Voltage Output Capacitor Required for Stability Dropout Voltage Ripple Rejection Output Noise Voltage Start-Up Time from Shutdown RF TX LDO (LDO8) Output Voltage Output Capacitor Required for Stability Dropout Voltage Ripple Rejection Output Noise Voltage Start-Up Time from Shutdown RF RX2 LDO (LDO9) Output Voltage Output Capacitor Required for Stability Dropout Voltage Ripple Rejection Output Noise Voltage Start-Up Time from Shutdown RF OPTIONAL LDO (LDO10) Output Voltage Output Capacitor Required for Stability Dropout Voltage Ripple Rejection Output Noise Voltage Start-Up Time from Shutdown OPTIONAL LDO (LDO11) Output Voltage Output Capacitor Required for Stability Ripple Rejection Output Noise Voltage Start-Up Time from Shutdown VOLTAGE DETECTOR FOR LDO1 AND LDO6 LDO1 Detect Voltage LDO1 Release Voltage LDO1 Hysteresis LDO6 Detect Voltage LDO6 Release Voltage LDO6 Hysteresis Symbol VLDO6b Conditions IO = 1 mA TA = -30C to +85C IO = 1 mA to 100 mA TA = -30C to +85C IO = 100 mA f = 1 kHz f = 100 Hz to 100 kHz Min 2.70 Typ 2.80 Max 2.90 Unit V
VLDO7 CLDO7 VDO VNOISE
2.81 1.5
2.9
2.99
V F mV dB V rms s
200 60 40 250 2.81 2.2 2.9 2.99
VLDO8 CLDO8 VDO VNOISE
IO = 1 mA to 150 mA TA = -30C to +85C IO = 150 mA f = 1 kHz f = 100 Hz to 100 kHz
V F mV dB V rms s
200 60 40 250 2.81 1 2.9 2.99
VLDO9 CLDO9 VDO VNOISE
IO = 1 mA to 50 mA TA = -30C to +85C IO = 50 mA f = 1 kHz f = 100 Hz to 100 kHz
V F mV dB V rms s
150 60 40 250 2.81 1 2.9 2.99
VLDO10 CLDO10 VDO VNOISE
IO = 1 mA to 50 mA TA = -30C to +85C IO = 50 mA f = 1 kHz f = 100 Hz to 100 kHz
V F mV dB V rms s
150 60 40 250 1.42 2.2 1.5 1.58
VLDO11 CLDO11 VNOISE
IO = 1 mA to 100 mA TA = -30C to +85C f = 1 kHz f = 100 Hz to 100 kHz
V F dB V rms s
60 50 250
VDET1 VDET1 VHYS1 VDET6 VDET6 VHYS6
TA = -30C to +85C TA = -30C to +85C TA = -30C to +85C TA = -30C to +85C TA = -30C to +85C TA = -30C to +85C
2.7 35 2.50 45
2.72 2.77 52 2.58 2.67 90
V VLDO1-NOM V mV V VLDO6-NOM V mV
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ADP3502 BATTERY VOLTAGE DIVIDER: MVBAT
Parameter MVBAT OUTPUT VOLTAGE 5-Bit Programmable Symbol VMVBAT
(TA = -30 C to +85 C, CVBAT = 10 F MLCC, CADAPTER = 1 F MLCC, unless otherwise noted.)
Conditions VBAT = 4.35 V, MVEN = 1 TA = 25C Code: 10000 Code: 01111 VBAT = 4.35 V, MVEN = 1 1 0 < IOUT < 100 A VBAT = 4.35 V, MVEN = 1 VBAT = 4.35 V, MVEN = 0 Min Typ Max Unit
2.459 2.648
2.508 2.538 2.697 2.732 6 2 3 78 5 97 1
V V mV/LSB mA mV A A
MVBAT OUTPUT VOLTAGE STEP OUTPUT DRIVE CURRENT CAPABILITY MVBAT LOAD REGULATION OPERATING BATTERY CURRENT SHUTDOWN CURRENT
VSTEP IOUT MVBAT
BATTERY CHARGER
Parameter
(TA = -30 C to +85 C, CVBAT = 10 F MLCC, CADAPTER = 1 F MLCC, 4.0 V otherwise noted.)
Symbol VBAT SENSE Conditions TA = 25C VR_SENSE = 30 mV, CHI = 1 4.8 V ADAPTER 12 V Code: 00 (Default) Code: 01 Code: 10 Code: 11 TA = -20C to +55C VR_SENSE = 160 mV, CHI = 1 4.8 V ADAPTER 12 V (Note 1) Code: 00 (Default) Code: 01 Code: 10 Code: 11 +25C to +55C or +25C to -20C VR_SENSE = 30 mV, Constant Adapter Voltage between 4.8 V and 12 V ADAPTER-VBAT ADAPTER-VBAT IADAPTER ADAPTER-VISNS ADAPTER = 5 V, VBAT = 4.3 V ADAPTER = 5 V VBAT = 3.6 V VBAT = 3.0 V VBAT DDLO DDLO VBAT< DDLO, TA = 25C, (5 mA Precharge), VBAT Ramping Up
ADAPTER
Min
12 V, unless
Typ Max Unit
CHARGER CONTROL VOLTAGE RANGE 2-Bit Programmable
3.440 4.175 4.195 4.215
3.500 4.205 4.225 4.245
3.560 4.235 4.255 4.275
V V V V
CHARGER CONTROL VOLTAGE RANGE1 2-Bit Programmable
VBAT SENSE
3.440 4.155 4.175 4.195 -20
3.500 4.205 4.225 4.245
3.560 4.255 4.275 4.295 +20
V V V V mV
CHARGER VOLTAGE TEMPERATURE DRIFT1 CHARGER DETECT ON THRESHOLD CHARGER DETECT OFF THRESHOLD CHARGER SUPPLY CURRENT CURRENT LIMIT THRESHOLD High Current Limit (Full Charge Current Enabled) Low Current Limit (Full Charge Current Disabled) PRECHARGE CURRENT SOURCE BASE PIN DRIVE CURRENT DEEP DISCHARGE LOCK-OUT (Releasing Voltage) DEEP DISCHARGE LOCK-OUT HYSTERESIS2 ISENSE BIAS CURRENT IISNS
110 0
165 25
225 60 2
mV mV mA mV mV mA mA V
170 40 3 20
210 60 5 35
255 75 7
2.650 2.80
100 VISNS = 5 V
200 1
mV A
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ADP3502 BATTERY CHARGER (continued)
Parameter Symbol Conditions No Adapter Present CBAT = 10 F MLCC, No Battery Min Typ Max 1 10 Unit A mA CHARGE TRANSISTOR REVERSE ICHG - ILKG LEAKAGE CURRENT 3 MINIMUM LOAD FOR STABILITY1 IL
NOTES 1 Guaranteed but not tested. 2 DDLO hysteresis is dependent on DDLO threshold value. If DDLO threshold is at maximum, DDLO hysteresis is at maximum at the same time. 3 This includes the total reverse current from battery to BVS, BASE, ISENSE, and ADAPTER pins with no adapter present. No signal path between ADAPTER pin and ADPSUPPLY pin. Specifications subject to change without notice.
LOGIC DC SPECIFICATIONS
Parameter CS, CLKIN, RESETIN-, TCXOON, SLEEP- Input Current H/L Input High Voltage Input Low Voltage Hysteresis KEYPADROW (Internal 20 k Pull-Up) Input High Voltage Input Low Voltage Hysteresis GPIO, DATA Input Current H/L Input High Voltage Input Low Voltage Hysteresis Output High Voltage Output Low Voltage INT- Output High Voltage Output Low Voltage BLIGHT (Open-Drain Output) Output Low Voltage KEYPADCOL (Open-Drain Output) Output Low Voltage PWRONKEY-, OPT1 (Internal 140 k Pull-Up) Input High Voltage Input Low Voltage Hysteresis
(TA = 25 C, CVBAT = 1 F MLCC, VBAT = 3.6 V, unless otherwise noted.)
Symbol Conditions Min Typ Max Unit
IIL/IIH VIH VIL
VIN = VLDO1 or 0 V
-1 2.25 520
+1 0.5
A V V mV
VIH VIL
2.25 0.5 470
V V mV A V V mV V V V V V
IIL/IIH VIH VIL VOH VOL VOH VOL VOL
VIN = VLDO1 or 0 V
-1 2.25 260
+1 0.5
IOH = 400 A IOL = -1.8 mA IOH = 400 A IOL = -1.8 mA IOL = -100 mA
2.69 0.28 2.69 0.28 0.4
VOL
IOL = -1.8 mA
0.15
V
VIH VIL VHYS IIH VIH VIL VHYS VOL VIN = VBAT
0.8
VBAT 0.2 950 1 VBAT
V V mV A V V mV V
OPT2- (Input/Open-Drain Output) Input Current H Input High Voltage Input Low Voltage Hysteresis Output Low Voltage
0.8 IOL = -1.8 mA
VBAT 0.2 950 0.1 VBAT VBAT
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ADP3502 LOGIC (continued)
Parameter OPT3 Input Current H/L Input High Voltage Input Low Voltage Hysteresis 32K OUT Output High Voltage Output Low Voltage RESET+ (Open-Drain Output) Output Low Voltage OFF Leak RSTDELAY-, RESETOUT- (Open-Drain Output) Output Low Voltage SUPPLY CURRENT OR RTCV Symbol IIL/IIH VIH VIL VHYS VOH VOL VOL OFFLEAK Conditions VIN = VBAT or 0 V Min -1 0.7 Typ Max +1 VBAT 0.2 300 IOH = 400 mA IOL = -1.8 mA IOL = -1.8 mA 0.005 0.9 RTCV 0.1 0.28 1 RTCV VBAT Unit A V V mV V V V A
VOL IOSC
IOL = -1.8 mA RTCV = 3 V, VBAT = 2 V All Logic: No Load 1
0.28
V A
AC SPECIFICATIONS
Parameter OSCILLATOR FREQUENCY START-UP TIME FREQUENCY JITTER Cycle to Cycle >100 Cycles FREQUENCY DEVIATION
(All specifications include temperature, unless otherwise noted.)
Symbol RTCV FCLK tSTART fJITTER/SEC RTCV = 0 V to 3 V RTCV = 3 V, TA = 25C 40 50 RTCV = 3 V, 3 Minutes 1000 ns ns ppm Conditions Min 2 32.768 100 200 Typ Max 3.1 Unit V kHz ms
OPERATIONAL SUPPLY RANGE
SERIAL INTERFACE
Parameter tCKS tCSS tCKH tCKL tCSH tCSR tDS tDH tRD tRZ tCSZ Min 50 50 100 100 100 62 50 40 50 50 50 Typ Max Unit ns ns ns ns ns s ns ns ns ns ns Test Condition/Comments CLK Setup Time CS Setup Time CLK High Duration CLK Low Duration CS Hold Time CS Recovery Time Input Data Setup Time Input Data Hold Time Data Output Delay Time Data Output Floating Time Data Output Floating Time after CS Goes Low
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ADP3502
ABSOLUTE MAXIMUM RATINGS*
Voltage on ADAPTER, ADPSUPPLY Pin to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, 15 V Voltage on VBAT Pin to GND . . . . . . . . . . . . -0.3 V, +6.5 V Voltage on Pins 6-13, 21-28 to GND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, VLDO1 + 0.3 V Voltage on Pins 1, 62-64 . . . . . . . . . . . -0.3 V, VBAT + 0.3 V Voltage on Pins 20, 32 . . . . . . . . . . . . . -0.3 V, VRTCV + 0.3 V Voltage on Pin 60 . . . . . . . . . . . . . . -0.3 V, VADAPTER + 0.3 V Voltage on Pins 2-5, 14, 30, 31, 33 . . . . . . . . . -0.3 V, +6.5 V Storage Temperature Range . . . . . . . . . . . . -65C to +150C Operating Temperature Range . . . . . . . . . . . -30C to +85C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125C JA Thermal Impedance (TQFP-64) (2-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . . . . .87.4C/W JA Thermal Impedance (TQFP-64) (4-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . . . . 56.2C/W Lead Temperature Range (Soldering, 60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified all other voltages are referenced to GND.
ORDERING GUIDE
Model ADP3502ASU
Temperature Range -30C to +85C
Package 64-Lead TQFP
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3502 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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ADP3502
PIN CONFIGURATION
OPT2- OPT1- POWERONKEY- ISENSE ADPSUPPLY ADAPTER BASE MVBAT AGND NRCAP BVS LDO10 (RF OPTION) VBAT LDO9 (RF Rx2) AGND LDO8 (RF Tx)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
OPT3 KEYPADCOL0 KEYPADCOL1 KEYPADCOL2 KEYPADCOL3 KEYPADROW0 KEYPADROW1 KEYPADROW2 KEYPADROW3 KEYPADROW4 KEYPADROW5 TCXOON SLEEP- BLIGHT DGND INT-
49
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
48
47
46
45
44
43
ADP3502
TOP VIEW (Not to Scale)
42
41
40
39
38
37
36
35
34
33
VBAT LDO7 (REF Rx1) LDO6 (BASEBAND CORE) VBAT LDO5 (VIBRATOR) LDO4 (AUDIO) VBAT LDO2 (BASEBAND AVDD ) REFO AGND LDO3 (RTC/COIN-CELL) VBAT LDO1 (BASEBAND VDD) LDO11 (OPTION) VBAT RSTDELAY-
Pin No. Mnemonic 1 2 3 4 5 6 7 8 9 10 11 12 13 OPT3 KEYPADCOL0 KEYPADCOL1 KEYPADCOL2 KEYPADCOL3 KEYPADROW0 KEYPADROW1 KEYPADROW2 KEYPADROW3 KEYPADROW4 KEYPADROW5 TCXOON SLEEP-
I/O I O O O O I I I I I I I I
Supply VBAT LDO1 LDO1 LDO1 LDO1 LDO1 LDO1 LDO1 LDO1 LDO1 LDO1 LDO1 LDO1
Function Optional Power ON Input. ADP3502 will keep power ON when this pin goes high. Keypad Column Strobe 0 (Open-Drain, Pull Low) Keypad Column Strobe 1 (Open-Drain, Pull Low) Keypad Column Strobe 2 (Open-Drain, Pull Low) Keypad Column Strobe 3 (Open-Drain, Pull Low) Keypad Row Input 0. Pulled up internally, 20 k. Keypad Row Input 1. Pulled up internally, 20 k. Keypad Row Input 2. Pulled up internally, 20 k. Keypad Row Input 3. Pulled up internally, 20 k. Keypad Row Input 4. Pulled up internally, 20 k. Keypad Row Input 5. Pulled up internally, 20 k. Logic Input Pin for Main LDOs (LDO1, LDO2, LDO3, LDO6) Turning On Control. L: OFF, H: ON. Logic Input Pin for LDO7 and LDO9. This input gates register data for these LDOs. LDO7 and LDO9 are turned OFF when SLEEP goes low even if the registers are set to ON. If register of SLEEP7 and SLEEP9 are set to "1," the SLEEP signal is ignored. LED Drive. Open-drain output. Digital Ground Interrupt Signal Output
14 15 16
BLIGHT DGND INT-
O O
VBAT LDO1
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RTCV OSC IN AGND OSC OUT GPIO0 GPIO1 GPIO2 GPIO3 DATA CS CLKIN RESETIN- 32K OUT RESET+ RESETOUT- TEST
PIN FUNCTION DESCRIPTION
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ADP3502
PIN FUNCTION DESCRIPTION (continued)
Pin No. Mnemonic 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 RTCV OSC IN AGND OSC OUT GPIO0 GPIO1 GPIO2 GPIO3 DATA CS CLKIN RESETIN- 32K OUT RESET+ RESETOUT- TEST RSTDELAY- VBAT LDO11 LDO1 VBAT LDO3 AGND REFO LDO2 VBAT LDO4 LDO5 VBAT LDO6 LDO7 VBAT LDO8 AGND LDO9 VBAT LDO10
I/O
Supply
Function Supply input for RTC, 32 kHz OSC, and other logic. Connects to coin cell battery in typical operation.
RTCV RTCV I/O I/O I/O I/O I/O I I I O O O I O LDO1 LDO1 LDO1 LDO1 LDO1 LDO1 LDO1 LDO1 RTCV RTCV RTCV RTCV RTCV
Connect to 32.768 kHz crystal Analog Ground Connect to 32.768 kHz crystal General-purpose input and output port. Integrated interrupt function. Interrupt occurs on both the falling and rising edges. General-purpose input and output port. Integrated interrupt function. Interrupt occurs on both the falling and rising edges. General-purpose input and output port. Integrated interrupt function. Interrupt occurs on both the falling and rising edges. General-purpose input and output port. Integrated interrupt function. Interrupt occurs on both the falling and rising edges. Serial interface data input and output Serial interface chip select input. Active high input. Serial interface clock input Reset input signal for internal reset signal; Starts stay-alive timer. 32.768 kHz output. Output after 30 ms when reset is released. Reset output. Invert signal of RESETOUT-. Open-drain and low leakage. Reset output. Follows voltage detector operation. Open-drain output. Test pin. Reserved for ADI use. Connect to GND for normal operation. Reset output. 50 ms delayed. Connect to baseband's reset input in typical application. Open-drain output. Supply input. Connect to battery. Regulator No. 11 output. General-purpose supply. Regulator No. 1 output. Use for baseband I/O supply. Supply input. Connect to battery. Regulator No. 3 output. If VBAT > 2.7 V, the output is always active. Use for coin cell supply. Analog ground Output of LDO2 through FET switch Regulator No. 2 output. Use for baseband analog supply. Supply input. Connect to battery. Regulator No. 4 output. Use for general analog supplies, for example, speaker amp. Regulator No. 5 output. Use for vibrator. Supply input. Connect to battery. Regulator No. 6 output. Use for baseband core supply. Regulator No. 7 output. Use for RF Rx IC supply. Gated with SLEEP- signal input. Supply input. Connect to battery. Regulator No. 8 output. Use for RF Tx IC supply. Analog Ground Regulator No. 9 output. Use for RF Rx IC supply. Gated with SLEEP- input signal. Supply input. Connect to battery. Regulator No. 10 output. General-purpose supply.
O O O O O O O O O O O O
VBAT VBAT VBAT VBAT VBAT VBAT VBAT VBAT VBAT VBAT VBAT VBAT
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ADP3502
PIN FUNCTION DESCRIPTION (continued)
Pin No. Mnemonic 54 55 56 57 58 59 60 61 62 63 64 BVS NRCAP AGND MVBAT BASE ADAPTER ADPSUPPLY ISENSE PWRONKEY- OPT1- OPT2-
I/O
Supply
Function Battery voltage sense input for charger. Connect to battery with a separate low current trace
O O O I I I I I/O
VBAT VBAT ADAPTER ADAPTER ADAPTER VBAT VBAT VBAT
Noise reduction capacitor, 0.1 F MLCC Analog Ground Battery voltage divider output. Buffered internally. Connect to baseband ADC. Base drive output for PNP pass transistor AC Adapter Input Supply bias current to charging related blocks Charge current sense input Power ON/OFF key input. Pulled up internally with 140 k. Optional power ON input. ADP3502 will keep power on when this pin goes low. Optional power ON input. ADP3502 will keep power on when this pin goes low. While the part is powered up, the input is pulled low (GND) internally. Do not connect to any supply or signal source.
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ADP3502
AGND
56 50 39 19 52 48
VBAT ADAPTER ISENSE BASE BVS
45 42 37 34 59 61 58 54
VBAT 140k PWRONKEY- 62 OPT1- 63 OPT2- 64 OPT3
1
CHARGER_DETECT BATOV CHARGER CONTROL POWER ON BATID BATTERY CHARGER
60 ADPSUPPLY
POWERON N OPT1_N OPT2_N OPT3 RTC ALARM VOLTAGE_DETECT DELAY 10ms PWROFF CLK DATA IN INT_IN 5
MAIN
57 MVBAT (VBAT MEASURE)
DDLO LDO_EN DDLO CONTROL SIGNALS REF REF
40 REFO
LPF ON/OFF LOGIC ON/OFF LOGIC
LDO1
55 NRCAP 36 LDO1 (BASEBAND VDD)
SUB MAIN SUB
LDO1
41 LDO2 (BASEBAND AVDD )
CLK
SYNC 5
LDO2 LDO3 LDO6 LDO4 LDO5
38 LDO2 (RTC/COIN-CELL) 46 LDO6 (BASEBAND CORE)
BATOV INT- 16 LEVEL TRANS LDO1 LEVEL TRANS 4 KEYPAD I/F
ON/OFF MAIN LOGIC ON/OFF LOGIC
MAIN SUB
43 LDO4 (AUDIO)
KEYPADCOL0 KEYPADCOL1 KEYPADCOL2 KEYPADCOL3 KEYPADROW0 KEYPADROW1 KEYPADROW2 KEYPADROW3
2 3 4 5 6 7 8 9
44 LDO5 (VIBRATOR)
INT LDO7 SLEEP7
47 LDO7 (RF Rx1)
LDO7 LDO8
49 LDO8 (RF Tx)
6 LEVEL TRANS -LDO1
LDO9 SLEEP9 GPIO INT/GPI INTRST
51 LDO9 (RF Rx2)
LDO9
53 LDO10 (RF OPTION) LDO10 35 LDO11 (OPTION) LDO11
KEYPADROW4 10 KEYPADROW5 11 BLIGHT 14 DGND 15 CS 26 CLKIN 27 DATA 25 GPIO0 21 GPIO1 22 GPIO2 23 GPIO3 24
VOLTAGE DETECTOR SERIAL I/F LEVEL TRANS DATA LEVEL TRANS GPIO + INT DATA CLKs DGND LEVEL TRANSLATOR LEVEL TRANSLATOR VBAT AND RTCV DGND LDO1 LDO1
13 SLEEP- 12 TCXOON
28 RESETIN-
OSC IN 18 OSC OUT 20 32K OUT 29 32kHz
RTCV
RTCV
17 RTCV
DELAY 30ms
32 TEST
RTC /CLOCK
OPEN DRAIN CLKs DATA DELAY 50ms
33 RSTDELAY-
STAY/ALIVE TIMER 0.25SEC-8SEC
31 RESETOUT-
DATA RESETIN N
30 RESET+
Figure 1. Overall Block Diagram
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Typical Performance Characteristics- ADP3502
2.928 VBAT = 4V 2.926
LDOs OUTPUT VOLTAGE - V
LDOs OUTPUT VOLTAGE - V
2.914 VBAT = 4V 2.912 LDOs OUTPUT VOLTAGE - V 2.910 2.908 2.906 2.904 2.902 2.900 2.898 2.896 2.894
2.872 VBAT = 4V 2.870 2.868 2.866 2.864 2.862 2.860 2.858 2.856 2.854
2.924 2.922 2.920 2.918 2.916 2.914
10 20 40 60 80 100 120 140 160 180 OUTPUT CURRENT - mA
2.892
10 20 40 60 80 100 120 140 160 180 OUTPUT CURRENT - mA
10 20 40 60 80 100 120 140 160 180 OUTPUT CURRENT - mA
TPC 1. LDO1 Load Regulation
TPC 2. LDO4 Load Regulation
TPC 3. LDO6 Load Regulation
2.908 VBAT = 4V 2.906
LDOs OUTPUT VOLTAGE - V
2.928 ILOAD = 1mA 2.926 2.924 2.922 2.920 2.918 2.916 2.914 2.912 10 20 40 60 80 100 120 140 160 180 OUTPUT CURRENT - mA
LDOs OUTPUT VOLTAGE - V
2.916 ILOAD = 1mA 2.914
LDOs OUTPUT VOLTAGE - V
2.904 2.902 2.900 2.898 2.896 2.894 2.892
2.912
2.910
2.908
2.906
4.0
4.5 5.0 5.5 6.0 6.5 SUPPLY INPUT FOR LDOs - V
7.0
2.904
4.0
4.5 5.0 5.5 6.0 6.5 SUPPLY INPUT FOR LDOs - V
7.0
TPC 4. LDO8 Load Regulation
TPC 5. LDO1 Line Regulation
TPC 6. LDO4 Line Regulation
2.876 ILOAD = 1mA 2.874
2.908 ILOAD = 1mA
200 180
LDOs DROPOUT VOLTAGE - mV
4.0 4.5 5.0 5.5 6.0 6.5 SUPPLY INPUT FOR LDOs - V 7.0
2.906
LDOs OUTPUT VOLTAGE - V
LDOs OUTPUT VOLTAGE - V
160 140 120 100 80 60 40 20
2.872 2.870 2.868 2.866 2.864 2.862
2.904 2.902 2.900 2.898 2.896 2.894
0
4.0
4.5 5.0 5.5 6.0 6.5 SUPPLY INPUT FOR LDOs - V
7.0
0
25
50 75 100 125 OUTPUT CURRENT - mA
150
TPC 7. LDO6 Line Regulation
TPC 8. LDO8 Line Regulation
TPC 9. LDO1 Dropout Voltage
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ADP3502
200 180
LDOs DROPOUT VOLTAGE - mV LDOs DROPOUT VOLTAGE - mV
200 180 160 140 120 100 80 60 40 20 0 30 60 90 120 150 OUTPUT CURRENT - mA 180 0 0 25 50 75 100 125 OUTPUT CURRENT - mA 150
LDOs DROPOUT VOLTAGE - mV
200 180 160 140 120 100 80 60 40 20 0 0 25 50 75 100 125 OUTPUT CURRENT - mA 150
160 140 120 100 80 60 40 20 0
TPC 10. LDO4 Dropout Voltage
TPC 11. LDO6 Dropout Voltage
TPC 12. LDO8 Dropout Voltage
4.24
4.211
4.22
CODE 01 RSENSE = 0.2
CHARGER OUTPUT - V
CHARGER OUTPUT - V
4.20 4.18 4.16 4.14 4.12 4.10 VADAPTER = 5.5V RSENSE = 0.2
4.210
2.91V 2.9V
4.209
2.89V
ILOAD = 180mA COUT = 2.2 F
4.208
5V
4.207
4V LINE TRANSIENT RESPONSE TIME BASE: 100 s/DIV
8.5
10.5
5.5
6.5
11.5
7.5
8.0
9.5
10.0
0
100 200 300 400 500 600 700 800 900 CHARGING CURRENT - mA
ADAPTER VOLTAGE - V
TPC 13. Charger Load Regulation
TPC 14. Charger Line Regulation
11.0
12.0
6.0
7.0
9.0
4.206
TPC 15. LDO4 Line Transient
VBAT = 4V COUT = 2.2 F 2.9V 2.885V
ILOAD = 150mA COUT = 2.2 F 2.86V 2.85V
2.836V 2.85V
VBAT = 4V COUT = 2.2 F
2.84V
180mA 150mA
5V
20mA
4V
LOAD TRANSIENT RESPONSE TIME BASE: 100 s/DIV
20mA
LINE TRANSIENT RESPONSE TIME BASE: 100 s/DIV
LOAD TRANSIENT RESPONSE TIME BASE: 100 s/DIV
TPC 16. LDO4 Load Transient
TPC 17. LDO6 Line Transient
TPC 18. LDO6 Load Transient
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40
ILOAD = 150mA COUT = 2.2 F 2.91V 2.9V
2.886V 2.9V
VBAT = 4V COUT = 2.2 F
35 30
LDO 1 LDO 4 LDO 8
RMS NOISE - V
25 20 15 10 5
2.89V
150mA
5V 4V LINE TRANSIENT RESPONSE TIME BASE: 100 s/DIV
20mA
LOAD TRANSIENT RESPONSE TIME BASE: 100 s/DIV
0
0
10 20 30 40 OUTPUT CAPACITOR - F
50
TPC 19. LDO8 Line Transient
TPC 20. LDO8 Load Transient
TPC 21. RMS Noise vs. COUT
0 -10 -20 -30 COUT = 2.2 F ILOAD = 150mA VBAT = 4V
0 -10 -20 -30
PSRR - dB
PSRR - dB
0
COUT = 2.2 F ILOAD = 180mA VBAT = 4V
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100
COUT = 2.2 F ILOAD = 150mA VBAT = 4V
PSRR - dB
-40 -50 -60 -70 -80 -90 -100 50 100 1k 10k 100k FREQUENCY - Hz 1M 10M
-40 -50 -60 -70 -80 -90 -100 50 100 1k 10k 100k FREQUENCY - Hz 1M 10M
50 100
1k
10k 100k FREQUENCY - Hz
1M
10M
TPC 22. LDO1 PSRR
TPC 23. LDO4 PSRR
TPC 24. LDO8 PSRR
66
800 ACTIVE MODE
64 LIGHT LOAD STANDBY MODE 62
700
600
IGND - A
IGND - A
60
500
58
400
56
300
MIDLOAD STANDBY MODE
54 -30 -20 -10 0 10 20 30 40 50 60 70 80 TEMPERATURE - C
200 -30 -20 -10 0 10 20 30 40 50 60 70 80 TEMPERATURE - C
TPC 25. IGND vs. Temperature
TPC 26. IGND vs. Temperature
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ADP3502
THEORY OF OPERATION
As illustrated in the Functional Block Diagram, the ADP3502 can be divided into two high level blocks--analog and logic. The analog block consists mainly of LDO regulators, a battery charger, reference voltage, and voltage detector subblocks, all of which are powered by the main battery or the charging adapter. On the other hand, VBAT powers all the logic subblocks except the RTC counter, 32 kHz output control, RESET output, and stay-alive timer. The RTCV pin powers these subblocks (see the shaded area of Figure 2).
ANALOG BLOCKS Low Drop-Out (LDO) Regulators
There are four sub-LDOs for LDO1, LDO2, LDO3, and LDO6, in order to meet low power consumption at light load (standby operation). They are used at low load condition, but they are continuously on even if each of the main LDOs are on. LDO3 and LDO3b are used for the coin cell, and LDO3b is always on until the main battery (VBAT) is decreased to 2.5 V, the DDLO threshold. LDO7 and LDO9 are gated by a control signal from SLEEP or register setting of SLEEP7/SLEEP9. LDO4 and LDO11 are initially on. For details of LDO on/off control, refer to the LDO Control section.
[VBAT] 5 POWER ON 6 DELAY 10ms
4
KEYPAD I/F 7 INTERRUPT CONTROL
3
GPIO
2
SERIAL I/F 8 LDO CONTROL
ANALOG BLOCK
1
RESET
[RTCV]-RTC BLOCK 32K OUTPUT CONTROL 10 RESET OUTPUT 11 STAY-ALIVE TIMER 9 RTC COUNTER
Figure 2. Power Partitioning of Subblocks
Table I. Ground Currents of LDOs with Each Handset Operation
Baseband Baseband Coin VDD Core Cell 1 OFF Light Load Midload 10 A 60 A 6 OFF 5 A 55 A 55 A 55 A 55 A 3 10 A 10 A 60 A 60 A 60 A 60 A Baseband RF AVDD Rx1 2 OFF 5 A 55 A 55 A 55 A 55 A 7 OFF OFF OFF 80 A 80 A 80 A RF Tx 8 OFF OFF OFF 80 A 80 A 80 A RF Rx2 9 OFF OFF OFF 80 A 80 A 80 A RF Main Option Option REF 10 OFF OFF OFF 80 A 80 A 80 A 11 OFF OFF OFF OFF 80 A 80 A 20 A 20 A 20 A 20 A 20 A 20 A 30 A 50 A 250 A 570 A 675 A 744 A Total LDO IGND
LDO Names LDO Number Power OFF Standby Mode
Audio Vibrator 4 OFF OFF OFF OFF 55 A 55 A 5 OFF OFF OFF OFF OFF 69 mA
Active Load 60 A Talk Ring 60 A 60 A
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Table II. LDO Operation Overview
Regulator LDO1a LDO1b LDO2a LDO2b LDO3a LDO3b LDO4 LDO5 LDO6a LDO6b LDO7 LDO8 LDO9 LDO10 LDO11
Names Baseband VDD Baseband VDD Sub Baseband AVDD Baseband AVDD Sub RTC/Coin Cell RTC/Coin Cell Sub Audio Vibrator Baseband Core Baseband Core Sub RF Rx1 RF Tx RF Rx2 RF Option Option
Current Rating (mA) 150 3 50 0.3 50 1 180 150 150 1 100 150 50 50 100
Voltage (Typ) or Range (V) 2.90 2.87 2.36 ~ 2.66 2.33 ~ 2.63 3.0 2.97 2.9 2.9 2.85 2.80 2.9 2.9 2.9 2.9 1.5
Program Steps N/A N/A 16 16 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
Step Size (mV) N/A N/A 20 20 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
Default
COUT ( F) 2.2 2.2 1 1 1 1 2.2 2.2 2.2 2.2 1.5 2.2 1 1 2.2
2.52 V 2.49 V
CVBAT AC ADAPTER CADAPTER ADAPTER ISENSE BASE BVS Li-ION BATTERY RSENSE
1k
+ V(ISENSE) -
5mA
PRECHARGE
gm EN EN
gm MVBAT MVBAT
ADPSUPPLY DDLO
EN REF
EN
BVS
VBIAS
CHARGER DETECT
CHI LDO EN
CHEN
CHV MVEN 0/1
MV4:0
Figure 3. Battery Charger Block Diagram
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ADP3502
BATTERY CHARGER START
VADAPTER > VBAT ?
N
Y
SET CHARGER DETECT FLAG
PRECHARGE 5mA VBAT > DDLO ? N
Y
LDO3b: ON
DETERMINED BY EXTERNAL SENSE RESISTOR.
SET LOW CURRENT CHARGE IADAPTER = 275mA (55mV ON RSENSE) PRECHARGE: OFF
LDO1, LDO1b, LDO2, LDO2b, LDO3, LDO6, LDO6b VOLTAGE DETECTOR ALL ENABLED
VOLTAGE DETECTOR VLDO6 > 2.67V AND VLDO1 > 2.77V ? Y
N
A
Figure 4. Charger Flow Chart A
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ADP3502
A
RESET SEQUENCE RUNS
BASEBAND SETS CHARGE VOLTAGE BASEBAND SETS MVBAT GAIN
CHI = 0: FULL CURRENT CHARGE OFF CHI = 1: FULL CURRENT CHARGE ON
BASEBAND ENABLES FULL CHARGE CURRENT? (CHI = 1?)
N
Y
LOW CURRENT CHARGE: OFF SET FULL CURRENT CHARGE IADAPTER = 850mA MIN. (170mV MIN. ON RSENSE)
N
BASEBAND CHEN = 0?
Y
CHARGING TERMINATED
Figure 5. Charger Flow Chart B
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ADP3502
Adapter Connection Reference
There are two adapter connections on the ADP3502, Pins ADAPTER and ADPSUPPLY. The ADPSUPPLY pin only provides bias current to the charger detect comparator and precharge block. With a diode placed on the adapter side of the PNP transistor, as shown in Figure 3, the reverse battery current will be blocked.
Charger Detect Function
The ADP3502 will detect that a charging adapter has been applied when the voltage at the ADAPTER pin exceeds the voltage at BVS. The ADAPTER pin voltage must exceed the BVS voltage by a small positive offset. This offset has hysteresis to prevent jitter at the detection threshold. The charger detection comparator will set the charger detect flag in the 20h register and generate an interrupt to the system. If the ADAPTER input voltage drops below the detection threshold, charging will stop automatically, and the charger detect flag will be cleared and generate an interrupt also.
DDLO Function and Operation
The ADP3502 has an internal temperature compensated and trimmed band gap reference. The battery charger and LDOs all use this system reference. This reference is not available for use externally. However, to reduce thermal noise in the LDOs, the reference voltage is brought out to the NRCAP pin through a 50 k internal resistor. A cap on the NRCAP pin will complete a low-pass filter that will reduce the noise on the reference voltage. All the LDOs, with the exception of LDO3, use the filtered reference. Since the reference voltage appears at NRCAP through a 50 k series internal impedance, it is very important to never place any load current on this pin. Even a voltmeter with 10 M input impedance will affect the resulting reference voltage by about 6 mV or 7 mV, affecting the accuracy of the LDOs and charger. If for some reason the reference must be measured, be certain to use a high impedance range on the voltmeter or a discrete high impedance buffer prior to the measurement system.
LOGIC BLOCKS
The ADP3502 contains a comparator that will lock out system operation if the battery voltage drops to the point of deep discharge. When the battery voltage exceeds 2.675 V, the reference will start as will the sub-LDO3b. If the battery voltage drops below the hysteresis level, the reference and LDOs will be shut down if for some reason they are still active. Since LDO1 will be in deep drop-out and well below the voltage detector threshold at this point, the reset generator will have already shut down the rest of the system via RESET+, RESETOUT-, and RSTDELAY-. If a charging adapter has been applied to the system, the DDLO comparator will force the charging current to trickle charge if the battery is below the DDLO threshold. During this time, the charging current is limited to 5 mA. When the battery voltage exceeds the upper threshold, the low current charging is enabled, which allows 55 mV (typical) across the external charge current sense resistor (see Figure 4).
MVBAT
ADP3502 includes the following functions: * 3-wire serial interface (CS, CLK, DATA) * RTC counter section has year, month, day, week, hour, minute, and second and controls leap year and days in month automatically. * Detect alarms based on RTC counter * Periodically constant interrupt feature (2 Hz, 1 Hz, 1/60 Hz, 1/3600 Hz, once a month) * GPIO and INT ports control * Keypad interface * LED light control * LDO functions * Clock and reset output control * Stay-alive timer Figure 6 is a block diagram based on the logic circuit.
The ADP3502 provides a scaled buffered output voltage for use in reading the battery voltage with an A/D converter. The battery voltage is divided down to be nominally 2.600 V at the full-scale battery of 4.35 V. To assist with calibrating out system errors in the ADP3502 and the external A/D converter, this fullscale voltage may be trimmed digitally with five bits stored in register 12h. At full-scale input voltage, the output voltage of MVBAT can be scaled in 6 mV steps, allowing a very fine calibration of the battery voltage measurement. The MVBAT buffer is enabled by the MVEN bit of register 11h and will consume less than 1 A of leakage current when disabled.
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ADP3502
[VBAT] VOLTAGE DETECT DELAY DELAY 10ms VOLTAGE DETECT
CHARGER DETECT SYNC POWER ON PWRONKEY N OPT1 N OPT2 N OPT3 PWRONKEY N SYNC OPT1 N SYNC OPT3 SYNC SYNC DATA IN ANALOG BLOCK BLIGHT DGND KEYPADCOL[3:0] KEYPADROW[5:0] KEYPAD I/F KEYPAD INT LED CONTROL BL KEYPAD I/F INT CONTROL REGISTER (RESET AND MASK) GPIO CONTROL
INTERRUPT REGISTER BLOCK
POWER OFF BATOV
GPIO [3:0]
GPIO
INT N TCXOON SLEEP N
LDO CONTROL REGISTER CS CLKIN DATA SERIAL I/F WRITE ENABLE WRITE DATA [7:0] SP ADDR [4:0] ANALOG CONTROL REGISTERS
ANALOG BLOCKS
DATA SELECT
RTC WRITE DATA [7:0] RTC READ DATA [7:0] RTC WRITE ENABLE ALARM INT RTC SP ADDR [5:0]
RTC RESETIN N OSC OUT OSC IN 32K OSC RTC CLK32K
RTC CS
RESETIN N
RESETIN N (RESET FOR REGISTERS)
PIC INT
LDO CONTROL CLK32K
TEST VDEL SIGNAL
32K OUT
32K CLK OUTPUT CONTROL
CLK512 RTC TEST MODE REGISTER BLOCK
OUTPUT DATA SELECT
TEST MODE CONTROL SIGNAL
ADDRESS DECODE CLK1K
STAY-ALIVE TIMER
TIMING SIGNALS
RTC REGISTER BLOCK
RTC TEST
TEST IDOENABLE
TEST RTC VOLTAGE DETECT RESETOUT N RSTDELAY N RESET [RTCV] RESET OUTPUT CONTROL
TEST MODE RTC VOLTAGE DETECT
Figure 6. LOGIC Block Diagram
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ADP3502
RESET RESETIN- Signal
The internal reset function is activated by the external reset input, RESETIN-, and is an asynchronous signal. The internal reset signal is used in the following blocks: * * * * Serial I/F Interrupt control Stay-alive timer Registers (refer to the Register section for additional information).
cause the system to have an unexpected result. Take care to avoid this situation. RESETIN- is level translated from LDO1 to both VBAT and RTCV supplies.
RESET Output Control and 32 kHz Output Control
LDOs, controlled by Serial I/F, are applied "RESET" by RESETIN-. LDO5, LDO7, LDO8, LDO9, LDO10, and REFO are set to "0," and LDO4 and LDO11 are set to "1." In case RESETIN- has noise, the internal circuit may be in reset and
Using a voltage detect signal, the device generates 32K OUT, RSTDELAY-, RESETOUT-, and RESET signals. About 32 ms after the RTC Voltage Detect (voltage detect signal in RTCV supply) signal goes from "0" to "1," the 32K OUT signal is generated from the internal RTC_CLK32K signal. RSTDELAY N (RSTDELAY-) goes to "0" when the RTC Voltage Detect is "0," and it goes to "1" at 50 ms after the "0" to "1" transition of the RTC Voltage Detect. RESETOUT N (RESETOUT-) and RESET toggle their states. Signal CLK512 is a 512 Hz, which is generated in USEC counter block.
SERIAL INTERFACE
tCSR
CS
tCKL tCKS tCKH tCSH
CLKIN
tCSS tDS
SERIAL DATA
tDH
ADDR4 0 CTRL1 (W) CTRL2 (W) DATA7 1 DATA0
ADDR5
SERIAL I/F WRITE TIMING
tCSR
CS
tCKL tCKS tCKH
CLKIN
tCSS tDS
SERIAL DATA
tDH
ADDR4 0 CTRL1 (R) CTRL2 (R) DATA7 1 DATA0
ADDR5
tRD
SERIAL I/F READ TIMING SINGLE MODE
tCSZ
CS
tCKL tCKS tCKH
CLKIN
tCSS tDS
SERIAL DATA
tDH
ADDR4 0 CTRL1 (R) CTRL2 (R) DATA7 1 DATA0 ADDR5 ADDR4
ADDR5
tRD
SERIAL I/F READ TIMING CONTINUOUS MODE
tRZ
Figure 7. Serial Interface Signal
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Table III. Setup and Hold Specifications
Parameter* tCKS tCSS tCKH tCKL tCSH tCSR tDS tDH tRD tRZ tCSZ
Min 50 50 100 100 100 62 50 40
Typ
Max
Unit ns ns ns ns ns s ns ns ns ns ns
Test Condition/Comments CLK Setup Time CS Setup Time CLK High Duration CLK Low Duration CS Hold Time CS Recovery Time Input Data Setup Time Input Data Hold Time Data Output Delay Time Data Output Floating Time Data Output Floating Time after CS Goes Low
50 50 50
*These parameters are not tested.
Function Block
The ADP3502 integrates the serial bus interface for easy communication with the system. The data bus consists of three wires (CLK, CS, and DATA) and is capable of serial-toparallel/parallel-to-serial conversion of data, as well as clock transfer. Serial interface block works during the time period at CS signal enable. After the falling edge of CLKIN, signals right after the rising edge of the CS signal, address, transfer control signal, and write data are held in sequentially. In case of DATA READ, data will be prepared by the rising edge of CLKIN, and the baseband chip may want to read or latch the data at the falling edge of CLKIN. While CS is not asserted, CLKIN is ignored. If CS goes "L" while CLKIN is continuously applied or input
DATA, all data is canceled, and the DATA line would be high impedance. In this case, users need to input the data again. Note that CLKIN should stay "L" when CS goes "H." RTC counter registers should be accessed at a certain time (>62 s) after CS assertion. Asserting RESETIN N (RESETIN-), signal resets the block. Notes: * CLKIN should be "L" when CS goes "H." * In case of RTC counter access, the access should be approximately 62 s (two clock cycles of CLK32K) after the CS signal is asserted to hold the RTC value. * The CS should not be asserted for 62 s (2 clock cycles of CLK32K) after the CS is released. * CS signal should never be asserted for 1 sec or longer; otherwise the RTC counter makes an error. * CLKIN should be chosen as a multiple of 16 if CS < 31 s.
RESETIN N CS CLKIN DATAIN RW SEL SERIAL-TO-PARALLEL CONVERSION
SP ADDR [5:0] WRITE ENABLE
CREATION OF WRITE DATA SP DATA [7:0]
DATA
PARALLEL-TO-SERIAL CONVERSION
PS DATA [7:0]
SYNCHRONIZATION AND DATA SELECTION
Figure 8. Serial Interface Block Diagram
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ADP3502
DATA INPUT/OUTPUT TIMING
5
4
3
2
1
0
1
0
7
6
5
4
3
2
1
0
ADDRESS (6-BIT)
R/W (2-BIT)
READ DATA (8-BIT)
Figure 9. Serial I/F Data Read/Write Timing
In Figure 9: * SP ADDR[5:0]: 6-Bit Address * SP CTRL[1:0]: 2-Bit Read/Write Control (01: Write, 10: Read) * SP DATA[7:0]: 8-Bit Input/Output Data All transfers will be done MSB first.
GPIO + INT
Keypad Control and LED Drive
The GPIO block has 4-channel I/O function and interrupt. With the GPIO CONTROL register (1Ah), it is possible to control the input or output setting of each channel individually. The output data is set in the GPIO register (1Ch). When the port is set in input mode, the input signal transitions from "1" to "0" and from "0" to "1" and then generates an interrupt signal with edge detection. The held interrupt signals are reset by the GPIO INT RESET register (1Dh). Setting the GPIO MASK register (1Bh) to "1" enables the interrupt of GPIO. (Not MASKED, "1" at default in reset.)
INT Register
KEYPADCOL[3:0] are open-drain outputs. The KEYPADROW[5:0] are falling edge trigger inputs (input state transition from "1" to "0") and generate interrupt signal and are pulled up to LDO1. By providing four keypad-column outputs and six keypad-row inputs, the ADP3502 can monitor up to 24 keys with the baseband chip. Writing column outputs and reading row inputs are controlled through a serial interface. The address of the KEYPADROW is 19h, and KEYPADCOL is 18h. The initial register value is "1," which means the output of KEYPADCOL is low. Three-stage flip-flop synchronizes signals into interrupt circuit to 1 kHz clock. The back-light drive is an open-drain output. The maximum current of the internal FET is 100 mA. The initial register value is "0," which means the output of BLIGHT is high impedance.
Power ON Input
If the interrupt event occurs, "1," the signal is held in this register. INT detect and reset are synchronized at the rising edge of CLK32K. If the interrupt event and reset signal occur at the same time, the interrupt event has priority. The RESETIN N signal resets the INT register (1Eh) to "0" (no INT detected), except alarm int and pic int. The INT MASK register (1Fh) goes to "1" (not masked). This block masks alarm int and pic int, which generated in RTCV block, but these signals are reset with the ALARM CONTROL register (0Dh) and PIC CONTROL register (0Eh). The interrupt signal, INT N, is an inverted OR signal of the value in the INT register and GPIO register. The DATA-IN register is a port to read an interrupt status. The input data are through the SYNC block, except the alarm signal. Since this is for just readback purposes, the user cannot write any data.
SYNC BLOCK
PWRONKEY and OPT1 have pull-up resistors, and others do not. In addition to these inputs, other internal input signals, such as charger detect and alarm signal (alarm int) from RTC, enable the main and sub-LDOs of LDO1, LDO2, LDO3, LDO4, LDO6, and LDO11. The Power ON status is held by latch data in the delay circuit, called voltage detect delay (see 10 ms Delay section for more information). OPT3 has a lower voltage threshold. OPT2 has a different structure than the other inputs and is pulled down to zero by the internal signal when the phone is in Power ON status, in order to ensure Power ON status, even if short-term disconnection happens. Figure 11 is a block diagram of the Power ON sequence.
VBAT 140k VOLTAGE DETECT DELAY CHARGER DETECT ALARM INT PWRONKEY- OPT1- POWER ON 140k
BATOV RTC ALARM
CHARGER DETECT
OPT3
OPT1-
PWRONKEY-
REGISTER
OPT2- OPT3 INT BLOCK
DATA-IN REGISTER (ADDR: 20h)
Figure 11. Power ON Input Block Diagram
Figure 10. DATA-IN Block
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In Figure 11: * Voltage Detect Delay: Voltage Detect Signal (10 ms Delay) (1: Assert) * Charger detect: Charger Detect Signal (1: Assert) * Alarm INT: Alarm Detect Signal (Alarm 1 or Alarm 2) (1: Assert) * PWRONKEY-: Power On Key Input (0: Assert) * OPT1-: Power On Signal (0: Assert) * OPT2-: Power On Signal (0: Assert) * OPT3: Power On Signal (1: Assert)
10 ms Delay
the voltage detect signal is asserted, the voltage detect delay signal is asserted. If the duration of the voltage detect signal is less than 10 ms, the voltage detect delay signal will not be asserted. When the voltage detect signal is released, the voltage detect delay signal is released simultaneously. The voltage detect delay signal can be reset by writing "1" in the POWER OFF register (21h). If users want to go back to a Power ON state, users should set "1" to address 22h within a time constant of the external R/C network, which is suppose to be connected to OPT2. Note that users just need to write a "1" in the Power OFF register to reset the voltage detect delay and do not need to overwrite it with a "0."
This block generates a 10 ms delayed signal after the reset of the voltage detect signal is released. 10 ms (11 clocks of 1024 Hz) after
POWERONKEY POWER ON LDO1, LDO2, LDO3, LDO4, LDO6, LDO11 LDO1b, LDO2b, LDO6b
POWER ON
POWER OFF
VOLTAGE DETECTOR 10ms VOLTAGE DETECT DELAY 50ms RSTDELAY-
OPT2 INT- CLEAR INT SERIAL I/F CLEAR INT- AND SET PWROFF (21h) = 1
Figure 12. Power ON Sequence
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ADP3502
LDO Control
The LDO control block controls Power ON/OFF of the LDO block. The function in this block has: * Hardware control using external signals * Software control using serial interface * A mixture of the hardware and software above LDO1, LDO2, LDO3, and LDO6 are structured with main and sub-LDOs. LDO4, LDO5, LDO7, LDO8, LDO9, LDO10, and LDO11 are set through the serial interface, but LDO7 and LDO9 are gated (AND gate) with SLEEP- signal in order to get into the SLEEP mode. If the SLEEP- signal is enabled (goes low), the outputs of LDO7 and LDO9 are turned OFF. The Power ON
Logic controls the remainder of the LDOs, including LDO1, LDO2, and LDO6. A sub-LDO called LDO3b is independently controlled, and this LDO control block doesn't control LDO3b. Also, the main LDO3, called LDO3a, is turned on by the Power ON signal, but the sub-LDO3, called LDO3b, is always ON while the battery supplies, and only the DDLO controls LDO3b. A DDLO is the control signal from the battery charger block and is monitoring the battery voltage. When VBAT is under 2.5 V (200 mV hysteresis from VBAT = 2.7 V), DDLO minimizes (DDLO enable) the current flow from the Li-Ion battery. Main LDOs: LDO1a, LDO2a, LDO3a, LDO6a Sub-LDOs: LDO1b, LDO2b, LDO3b, LDO6b
Table IVa. DDLO Status Table
Status LDO1a LDO1b LDO2a LDO2b LDO3a Coin Cell OFF X OFF ON LDO3b LDO4 Audio OFF X REFO REFO OFF X LDO5 Vibrator OFF X LDO6a LDO6b LDO7 Rx1 OFF X LDO8 Tx OFF X LDO9 Rx2 OFF X LDO10 RF Option OFF X LDO11 Option OFF X
Baseband VDD DDLO Enable OFF OFF X
Baseband AVDD OFF X OFF X
Baseband Core OFF X OFF X
DDLO X Disable
X means a status of LDO depends on other conditions.
Table IVb. LDO Control Event Table1
Event LDO1a LDO1b LDO2a Baseband VDD Power ON2 TCXOON
3
LDO2b LDO3a
LDO3b
LDO4 Audio ON
REFO LDO5 REFO Vibrator
LDO6a LDO6b Baseband Core ON ON/ OFF ON
LDO7 Rx1
LDO8 Tx
LDO9 LDO10 Rx2 RF Option
LDO11 Option ON
Baseband AVDD Coin Cell ON ON/ OFF ON ON ON/ OFF
ON ON/ OFF
ON
SLEEP-4
ON/ OFF
ON/ OFF OFF OFF OFF OFF OFF OFF OFF OFF
RESETIN- ALLOFF Bit Goes "H" PWROFF Bit Goes "H"
OFF OFF
OFF OFF
OFF OFF
OFF OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
NOTES 1 This table indicates only the status change caused by an event. Blank cells mean no change and keep previous status. 2 Power-ON Event: Indicating a status just after the power-ON event. After the event, a status of LDO1a, LDO2a, LDO3a, and LDO6a are changed by the TCXOON signal.
3 4
TCXOON: Hardware control, change all main LDOs' ON/OFF status. SLEEP-: The LDO7 and LDO9 can be controlled by software if SLEEP = "H" level. If SLEEP- goes "L," these LDOs are turned OFF immediately.
Table IVc. Software Controllability of LDOs
LDO LDO1a LDO1b LDO2a LDO2b LDO3a LDO3b LDO4 Audio REFO REFO LDO5 Vibrator LDO6a LDO6b Baseband Core LDO7 Rx1 * LDO8 Tx LDO9 Rx2 * LDO10 LDO11
Description Baseband VDD Software Turn ON Software Turn OFF
Baseband AVDD Coin Cell
RF Option Option
*LDO7 and LDO9 have a gate with SLEEP-. If SLEEP- is in "L" (active) status, users cannot control it and both LDOs are kept in an OFF status. Users may want to use this function as an immediate control to get OFF status by using SLEEP- hardware control when setting Register "1" to the LDO control register.
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ADP3502
RTC Block
The calendar registers are set through the serial interface.
Function
counter until the CS signal is released. In case the CPU writes data into the SEC counter, the USEC counter is reset to zero. Note the following: * In case of RTC counter access, the access should wait approximately 62 s, (two clock cycles of CLK32K) after the CS signal is asserted, to hold the RTC value. * The CS signal should never be asserted 1 sec or longer since this effects counter operation.
USEC Counter Operation
* RTC counter using binary * Reading out and writing settings of year, month, day, week, hour, minute, and second data * Leap year controls, number of days in a month control * Alarm function (week, hour, minute) * Periodic interrupt function--2 Hz, 1 Hz, 1/60 Hz, 1/3600 Hz, each month (first day of each month) * Protection of wrong data readout during RTC data update
Operation
Synchronizing with the RTC CLK32K clock, the USEC counter generates a 1 sec timing clock, which hits the RTC counter. Through the serial interface, the CPU can write the setting value and read the RTC counter value. In case the RTC counter toggles during the serial interface access to the RTC counter, the wrong data can be read/written between the RTC counter and the interface. The CS signal stops the clocking to the RTC
The USEC counter counts up synchronizing with the RTC CLK32K clock. It generates a 1 sec timing signal and is used as an increment clocking of the RTC counter. In case the 1 sec signal is generated during the CS signal asserted, the increment clock is delayed until the CS signal is released.
RTC Counter Operation
The RTC counter uses the increment signal from the USEC counter to control the counting operation, including the leap year control and numbers of days in a month control.
RTC CLK32K RTC SP ADDR [5:0] RTC WRITE ENABLE RTC WRITE DATA [7:0] (FROM SERIAL I/F) RTC REGISTER BLOCK
LOADING ALARM TIMES ALARM COMPARATOR PERIODIC INTERRUPT RTC ALARM INT
RTC COUNTER RESET WILL BE ASSERTED WHEN RTC COUNTER IS WRITTEN.
LEAP YEAR AND DATE CONTROL
RTC CTFG INT
DATA SELECT
RTC DATA [7:0]
RTC CS USEC COUNTER
REGISTERS FOR TEST MODE
SEC COUNTER INCREMENT CONTROL
RESET TO RTC AND USEC COUNTERS WRITE INITIAL DATA OF USEC COUNTER
Figure 13. RTC Counter Block
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ADP3502
ENABLED SIGNALS CREATED BY DECODING OF RTC SP ADDR [5:0] ADDR 06h WRITE ADDR 00h WRITE INITIAL DATA 04h 03h 02h 01h DATE WEEK HOUR 31 SCALE 7 SCALE 12 SCALE TO FOLLOWING COUNTERS YEAR COUNT MONTH COUNT DAY COUNT USEC COUNTER INC ENB INC CLK 00h SECOND 60 SCALE MINUTE 60 SCALE WEEK COUNT HOUR COUNT MIN COUNT SEC COUNT 06h 05h YEAR MONTH 100 SCALE 12 SCALE LEAP YEAR AND DAYS IN MONTH CONTROL
Figure 14. RTC Counter Block Diagram
Definition of Leap Year Periodic Interrupt Function
For this device, the following definition of a leap year is used instead: "A year that can be divided by 4." Note: * Year counter = "00" means year 2000 and is a leap year, because it can be divided by 400. * Actual covered year period is from 1901 to 2099.
Number of Days of Month Control
This function generates interrupt periodically. The timing of the cycle can be selected from 2 Hz (0.5 sec clock pulse), 1 Hz (1 sec clock pulse), 1/60 Hz (minutes), 1/3600 Hz (hour), and month (first day of each month). The cycle is set using the PI2-PI0 value in the periodic interrupt control, PIC register (0Eh). The state when interrupt is generated is indicated at the INTRA bit of PIC register (0Eh). The INT MASK register (1Fh) only masks the periodic interrupt signal. There are two periodic interrupt signal output patterns: 1. Hold the value when the interrupt occurs (level). 2. After the interrupt event happens, assert the interrupt signal in a certain time period and then release it (pulse). In level case, interrupt occurs at each 0 min (1/60 Hz), 0 o'clock (1/3600 Hz), or the first day of the month. Because they happen in long cycles, the value is held at the register. After the CPU checks the state, it is released by writing a "1" to the PIC Bit of the PIC Register. If 2 Hz and 1 Hz, the interrupt is not held because the event happens in short cycles. These event signals output the pulse signal 2 Hz or 1 Hz in the RTC counter directly. The interrupt release operation doesn't affect the interrupt signal in this case.
Stay-Alive Timer
* Months 1, 3, 5, 7, 8, 10, and 12 have 31 days. * Months 4, 6, 9, and 11 have 30 days. * Month 2 has 28 days but has 29 days in a leap year.
Alarm Function
Comparing the RTC counter value with the setting value in the alarm setting register (07h-09h), the alarm condition is detected. Setting of week uses seven bits for each day of the week and works with multiple day settings. There is a delay of 62 s from alarm detection to setting up the AOUT/BOUT registers. The ALA EN flag in the ALARM CONTROL register (0Dh) sets the enable/disable of the alarm detection. The INT register (1Eh) indicates the interrupt signals, ALARM INT of ALA or/ and ALB. The INT MASK register (1Fh) does mask the alarm interrupt signal. The alarm detection state is indicated as AOUT of the ALARM CONTROL register (0Dh), and the alarm can be released by writing a "1" at the bit. Alarm B is controlled the same as Alarm A. Note: Users just need to write a "1" to release the alarm and do not need to write a "0" after the "1." Users do not need to wait 62 s from CS assertion.
This is a counter that increments each 250 ms after RTC RESETIN N is asserted. It holds its value when the counter counts full up. Signal CLK4 is a 4 Hz (250 ms) clock that was generated in the USEC counter. The counter can be reset by writing a "1" at the CLR of the Stay-Alive TIMER CONTROL register (0Fh). The RTC RESETIN N signal is transferred from a logic input circuit that is supplied by VBAT of RESETIN N. Note: Users just need to write a "1" to release the interrupt and do not need to write a "0" after the "1."
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ADP3502
CLK4 TEST RESET RTC RESETIN N D 5-BIT CLRB COUNTER SA [4:0] STAY-ALIVE TIMER
REGISTER STAY-ALIVE TIMER CONTROL REGISTER (0Fh): CLR STAY-ALIVE TIMER CONTROL REGISTER (0Fh): SAx
Figure 15. Stay-Alive Timer Block Diagram
RTC VOLTAGE DETECT
SA CLEAR
CLK4
SA COUNT [4:0]
0
1
2
3
4
5
30
31
0
Figure 16. Stay-Alive Timer Operation Timing
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ADP3502
Table V. Registers
ADDR
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 3Fh
Description
Second Counter Minute Counter Hour Counter Week Counter Day Counter Month Counter Year Counter Alarm A Minute Alarm A Hour Alarm A Week Alarm B Minute Alarm B Hour Alarm B Week Alarm Control Periodic Interrupt Control Stay-Alive Timer Control Charger Control Charger MVBAT Control Charger MVBAT LDO Control 1 Not Available LDO Control 2 LDO Control 3 LDO2 Gain Keypad Column/LED Keypad Row Input GPIO Control GPIO MASK GPIO GPIO INT INT INT MASK DATA IN Power OFF Power ON TEST Register (Option)
D7
D6
D5
S5 M5
D4
S4 M4 H4 D4
D3
S3 M3 H3 D3 MO3 Y3 AM3 AH3 AW3 BM3 BH3 BW3 ALA EN PIC SA3
D2
S2 M2 H2 W2 D2 MO2 Y2 AM2 AH2 AW2 BM2 BH2 BW2 AOUT PI2 SA2
D1
S1 M1 H1 W1 D1 MO1 Y1 AM1 AH1 AW1 BM1 BH1 BW1 ALB EN PI1 SA1 CHI REF0 MV1 LDO5 LDO8 G21 KO1 KI1 GPC1 GPMSK1 GPI1 GPO1 GPINT1 GPRST1 INT1 IRST1 MSK1 DI1
D0
S0 M0 H0 W0 D0 MO0 Y0 AM0 AH0 AW0 BM0 BH0 BW0 BOUT PI0 SA0 CHEN MVEN MV0 LDO4 LDO7 ALLOFF G20 KO0 KI0 GPC0 GPMSK0 GPIO GPO0 GPINT0 GPRST0 INT0 IRST0 MSK0 DI0 PWROFF PWRON TEST
Comments
Note 1, 2 Note 1, 2 Note 1, 2 Note 1, 2 Note 1, 2 Note 1, 2 Note 1, 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 3 Note 3 Note 3 Note 3 Note 4 Note 3 Note 3 Note 3 Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 Note 5, 6 Note 5, 6 Note 5, 6 Note 5, 6 Note 5 Note 5 Note 5 Note 5 Note 2, 7
Y6
Y5 AM5 AW5 BM5 BW5
AW6
BW6
Y4 AM4 AH4 AW4 BM4 BH4 BW4
CLR
SA4
CHV1 CHV0
MV4
MV3
MV2 LDO11 LDO9 G22 KO2 KI2 GPC2 GPMSK2 GPI2 GPO2 GPINT2 GPRST2 INT2 IRST2 MSK2 DI2
SLEEP9
SLEEP7
LDO10 G23 KO3 KI3 GPC3 GPMSK3 GPI3 GPO3 GPINT3 GPRST3 INT3 IRST3 MSK3 DI3
KI5
BL KI4
INT6 INT5 IRST6 INT5 MSK6 MSK5 DI5
INT4 INT4 MSK4 DI4
LDOENB
USENB
NOTES 1. For RTC counter data protection, access should wait for a certain time period (62 s) after the CS signal assertion. (Refer to the RTC Counter Operation section for the wait time). 2. Registers regarding the RTC counter. They are powered by RTCV. 3. Analog block control registers. They control LDO and so on. They are powered by VBAT. 4. Not available. 5. These are the registers for INT, GPIO, KEYPAD I/F, and so on. They are powered by VBAT. 6. The INT reset operation will be valid at 62 s or later after it's set. 7. This is a set register for an internal test and should not be accessed at normal operation.
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ADP3502
APPLICATION INFORMATION Input Voltage Input Capacitor Selection
The input voltage of the ADP3502 is 4.2 V and is optimized for a single Li-Ion cell. The thermal impedance of the ADP3502 is 56.2C/W for 4-layer boards. Power dissipation should be calculated at the maximum ambient temperatures and battery voltage should not exceed the 125C maximum allowable junction temperature. The junction and ambient temperature limits are selected to prevent both catastrophic package material deterioration and excessive device power output degradation. The ADP3502 can deliver the maximum power (0.71 W) up to 85C ambient temperature. Figure 17 shows the maximum power dissipation as a function of ambient temperature.
2.0 1.8 1.6
POWER DISSIPATION - W
For the input (ADAPTER and VBAT) of the ADP3502, a local bypass capacitor is recommended. Use a 10 F, low ESR capacitor. Larger input capacitance and lower ESR provide better supply noise rejection and line-transient response. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size but may not be cost effective. A lower cost alternative may be to use a 10 F tantalum capacitor in parallel with a small (1 F to 2 F) ceramic capacitor (ceramic capacitors will produce the smallest supply ripple).
LDO Capacitor Selection
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -30
Low dropout regulators need capacitors on both their input and output. The input capacitor provides bypassing of the internal amplifier used in the voltage regulation loop. The output capacitor improves the regulator response to sudden load changes. The output capacitor determines the performance of any LDO. The LDO1, LDO4, LDO5, LDO7, LDO8, and LDO11 require a 2.2 F capacitor, and the LDO2, LDO3, LDO6, LDO9, and LDO10 require a 1 F capacitor. Transient response is a function of output capacitance. Larger values of output capacitance decrease peak deviations, providing improved transient response for large load current changes. Choose the capacitors by comparing their lead inductance, ESR, and dissipation factor. Output capacitor ESR affects stability. Note that the capacitance of some capacitor types show wide variations over temperature or with dc voltage. A good quality dielectric, X7R or better, capacitor is recommended. The RTCV LDO can have a rechargeable coin cell or an electric double-layer capacitor as a load, but an additional 0.1 F ceramic capacitor is recommended for stability and optimal performance.
RTCV LDO
0
30 60 AMBIENT TEMPERATURE - C
90
Figure 17. Power Dissipation vs. Temperature
Printed Circuit Board Layout Considerations
Use the following guidelines when designing printed circuit boards: 1. Connect the battery to the VBAT and BVS pins of the ADP3502. Kelvin-connect the BVS pin by running a separate trace to the VBAT pin. Locate the input capacitor, C13, in the Figure 18 as close as possible to these pins. 2. REFO, LDO2, LDO4, LDO8-LDO10, ADAPTER, and NRCAP capacitors should be returned to AGND. 3. LDO1, LDO3, LDO5-LDO7, LDO11, and VBAT capacitors should be returned to DGND. 4. Split the ground connections. Use separate traces or planes for the analog, digital, and power grounds and tie them together at a single point, preferably close to the battery return. 5. Kelvin-connect the charger's sense resistor by running separate traces to the ADAPTER and ISENSE pins. Make sure the traces are terminated as close to the resistor's body as possible. 6. Run a separate trace from the BVS pin to the battery to prevent a voltage drop error in the MVBAT measurement. 7. Use the best industry practice for thermal considerations during the layout of the ADP3502 and charger components. Careful use of the copper area, weight, and multilayer construction all contribute to improved thermal performance.
The RTCV LDO charges a rechargeable coin cell to run the real-time clock module. It has been targeted to charge manganese lithium batteries, such as the ML series (ML621/ML1220) from Sanyo. With high energy density and relatively flat discharge characteristics, the lithium coin cell is widely used in mobile devices, such as cellular phones, digital cameras, and PDAs. The ML621 has a small physical size (6.8 mm diameter) and a nominal capacity of 2.5 mAh, which yields about 250 hours of backup time. The nominal charging voltage is 3.0 V. This precise output voltage regulation charges the cell to more than 90% of its capacity. In addition, it features a very low quiescent of 50 A typically. It requires an external low leakage diode for reverse current protection that is needed when the main battery is removed, and the coin cell supplies the RTCV pin.
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ADP3502
Setting the Charge Current External Pass Transistor Selection
The ADP3502 will control the charging operations when requested by the software. It includes a complete constant current/ voltage single-cell lithium charge controller, as well as input current monitoring for the charger and voltage regulators. The ADP3502 will default to the lowest charge voltage of 3.50 V. To reach final charge on standard lithium batteries, the software must select one of the programmed values from this data sheet. The current comparator of the ADP3502 senses the voltage drop across an external sense resistor to control the average current for charging a battery. The voltage drop can be adjusted from 60 mV to 210 mV, giving a charging current limit from 300 mA to 1.05 A with a 0.2 sense resistor. For lithium batteries, selecting the sense resistor, RSENSE, programs the charge current. Use the following equation to select the current sense resistor, RSENSE. The maximum battery charge current, ICHGR, must be known.
RSENSE 210 mV = ICHGR
The ADP3502 drives an external PNP pass transistor. The BASE pin drives the base of the transistor. The driver can draw up to 35 mA from the base of the pass device. The PNP pass transistor must meet specifications for: * Current gain * Power dissipation * Collector current The current gain, hfe, influences the maximum output current the circuit can deliver. The largest guaranteed output current is given by ICHGR (max) = 35 mA hfe (min). To ensure proper operation, the minimum VBE the ADP3502 can provide must be enough to turn on the PNP. The available base drive voltage can be estimated using the following:
VBE = VADAPTER - VDIODE - VBASE
where VADAPTER (min) is the minimum adapter voltage, VBASE is the base drive voltage, and VSENSE is the maximum high current limit threshold voltage. The difference between the adapter voltage (VADAPTER) and the final battery voltage (VBAT) must exceed the voltage drop due to the blocking diode, the sense resistor, and the saturation voltage of the PNP at the maximum charge current, where:
Similarly, the end of charge current can be calculated from the low current limit threshold of 60 mV.
ILOW = 60 mV RSENSE
VCE(SAT) = VADAPTER - VDIODE - VSENSE - VBAT
The thermal characteristics of the PNP must be considered next. The transistor's rated power dissipation must exceed the actual power dissipated in the transistor. The worst-case dissipation can be determined using:
PDISS = VADAPTER ( MAX ) - VDIODE - VBAT x I CHGR
CHARGER DIODE SELECTION
The diode, D3, shown in the Figure 18, is used to prevent the battery from discharging through the adapter supply. Choose a diode with a low leakage current but with a current rating high enough to handle the battery current and a voltage rating greater than VBAT. The blocking diode is required for lithium battery types.
(
)
It should be noted that the adapter voltage could be either preregulated or nonregulated. When preregulated, the difference between the maximum and minimum adapter voltage is probably not significant. When unregulated, the adapter voltage can have a wide range specified. However, the maximum voltage specified is usually with no load applied. Therefore, the worst-case power dissipation calculation will often lead to an overspecified pass device. In either case, it is best to determine the load characteristics of the adapter to optimize the charger design.
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ADP3502
AC ADPTER D3 BAS116 RSENSE 0.2 C18 10 F VBAT R5 100k OPT1 C19 0.1 F 64 49 C14 2.2 F C17 0.1 F C16 1.0 F RF RX2 C15 1.0 F RF TX RF OPTIONAL Q9 FZT788 C13 10 F Li-ION BATTERY BASEBAND ADC
OPT3
1
OPT1 POWERONKEY ISENSE ADPSUPPLY ADAPTER BASE MVBAT AGND NRCAP BVS LDO 10 VBAT LDO9 AGND LDO8
OPT3
VBAT LDO7 LDO6 VBAT LDO5 LDO4 VBAT
48 RF RX1 BASEBAND CORE VIBRATOR AUDIO BASEBAND AVDD REF0 C11 1.0 F C10 0.1 F C4 2.2 F 33 D2 BAT54 C5 2.2 F C6 1.0 F BASEBAND VDD OPTIONAL C7 2.2 F C8 2.2 F C12 2.2 F C9 1.5 F RTC/COIN-CELL
KEYPADCOL0 KEYPADCOL1 KEYPADCOL2 KEYPADCOL3 KEYPAD INTERFACE
KEYPADROW0 KEYPADROW1 KEYPADROW2 KEYPADROW3 KEYPADROW4 KEYPADROW5
ADP3502
LDO2 REFO AGND LDO3 VBAT LDO1 LDO11
TCXOON SLEEP VBAT R4 D1 1.5k INT 16
TCXOON SLEEP BLIGHT DGND INT
17 X1 C1 10pF 32.7kHz SERIAL I/F C2 10pF
RTCV OSC IN AGND OSC OUT GPIO0 GPIO1 GPIO2 GPIO3 DATA CS CLKIN RESETIN- 32K OUT RESET+ RESETOUT- TEST
VBAT RSTDELAY-
32 C3 0.1 F
R2 1k COIN CELL
GPIO0 GPIO1 GPIO2 GPIO3
RESETIN 32K OUT RESET RESETOUT
Figure 18. Typical Application Circuit
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RSTDELAY
ADP3502
OUTLINE DIMENSIONS 64-Lead Thin Plastic Quad Flat Package [TQFP] 7 x 7 x 1.00 mm Body (SU-64)
Dimensions shown in millimeters
9.00 BSC
0.75 0.60 0.45
1.20 MAX
64 1 PIN 1
7.00 BSC
49 48
SEATING PLANE TOP VIEW
(PINS DOWN)
9.00 BSC
COPLANARITY 0.08 MAX STANDOFF 0.15 MAX 0.05 MIN 0.20 0.09
16 17
33 32
0.40 BSC
0.23 0.18 0.13 7 0
1.05 1.00 0.95 COMPLIANT TO JEDEC STANDARDS MS-026ABD
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C03147-0-2/03(0)
PRINTED IN U.S.A.

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