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(R)
EMIF10-1K010F1
IPADTM
EMI FILTER INCLUDING ESD PROTECTION
MAIN PRODUCT CHARACTERISTICS: Where EMI filtering in ESD sensitive equipment is required : Mobile phones and communication systems Computers, printers and MCU Boards
s s
DESCRIPTION The EMIF10-1K010F1 is a highly integrated devices designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interferences. The EMIF10 flip chip packaging means the package size is equal to the die size. This filter includes an ESD protection circuitry which prevents the device from destruction when subjected to ESD surges up 15kV. BENEFITS EMI symmetrical (I/O) low-pass filter High efficiency in EMI filtering Very low PCB space consuming: 2.57mm x 2.57mm Very thin package: 0.65 mm High efficiency in ESD suppression High reliability offered by monolithic integration High reducing of parasitic elements through integration & wafer level packaging.
s s s s s s s
Flip Chip package PIN CONFIGURATION (ball side)
5
I7 I9 I10 09 010
4
GND
3
GND
2
I3 I5 I4 03 04
1 A
I1 I2 01 02
GND
GND
B C D E
I8 07 08
I6 05 06
COMPLIES WITH THE FOLLOWING STANDARDS: IEC61000-4-2 Level 4 15kV (air discharge) 8 kV (contact discharge) MIL STD 883E - Method 3015-6 Class 3 BASIC CELL CONFIGURATION
Low-pass Filter
Input
Output
Ri/o = 1k Cline = 100pF
GND
TM : IPAD is a trademark of STMicroelectronics.
GND
GND
July 2003 - Ed: 3A
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EMIF10-1K010F1
ABSOLUTE MAXIMUM RATINGS (Tamb = 25 C) Symbol Tj Top Tstg Parameter and test conditions Junction temperature Operating temperature range Storage temperature range Value 125 -40 to + 85 -55 to +150 Unit C C C
ELECTRICAL CHARACTERISTICS (Tamb = 25C) Symbol VBR IRM VRM VCL Rd IPP RI/O Cin Parameters Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Dynamic impedance Peak pulse current Series resistance between Input & Output Input capacitance per line
IPP VCL VBR VRM IRM IR
I
V
Symbol VBR IRM RI/O Cline At 0V bias IR = 1mA
Test conditions VRM = 3V per line
Min 6 900 80
Typ 8 1000 100
Max 10 500 1100 120
Unit V nA pF
Fig. 1: S21(dB) attenuation measurement and Aplac simulation.
0.00 dB - 5.00
Fig. 2: Analog crosstalk measurements.
0
Aplac
- 10.00
-20 -40 -60 -80 -100
Measure
- 15.00 - 20.00 - 25.00 - 30.00 - 35.00 - 40.00 - 45.00 - 50.00 1.0M 3.0M 10.0M 30.0M f/Hz 100.0M 300.0M 1.0G
1
10 100 frequency (MHz)
1,000
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EMIF10-1K010F1
Fig. 3: Digital crosstalk measurement. Fig. 4: ESD response to IEC61000-4-2 (+15kV air discharge) on one input V(in) and on one output (Vout).
VG1
V(in1)
V(out1)
21VG1
Fig. 5: ESD response to IEC61000-4-2 (+15kV air discharge) on one input V(in) and on one output (Vout).
Fig. 6: Line capacitance versus applied voltage.
C(pF)
V(in1)
V(out1)
100 90 80 70 60 50 40 30 20 10 0
F=1MHz Vosc=30mV
VR(V) 1 2 5 10
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EMIF10-1K010F1
Fig. 7: Aplac model single line structure.
GNDi Rs Ls 50pH 50m Ii Oi 50pH 50m Ls Rs
+ Port15 - 50 Rgnd Lgnd
+ cap_line cap_line
+
Port16 50
Lbump
Rbump Rgnd Lgnd Rgnd Lgnd Rgnd Lgnd
Rseries Ii Oi Ii MODEL = demif10 GNDi MODEL = demif10 Oi
Csubump Rsubump + cap_hole
Lhole + sub
Rsub
Rhole
Csubump Rsubump +
sub
Fig. 8: Aplac model parameters.
aplacvar aplacvar aplacvar aplacvar aplacvar aplacvar aplacvar aplacvar aplacvar aplacvar aplacvar aplacvar aplacvar aplacvar aplacvar Cz Rseries cap_line Ls Rbump Lbump Rs Csubump Rsubump Rsub lhole Rhole cap_hole Rgnd Ignd 57pF 960 0.8pF 0.6nH 50m 50pH 0.15 15pF 0.15 0.1 1.2nH opt 0.15 0.15pF 0.25 0.4nH Model demif10 BV = 7 IBV = 1m CJO = Cz M = 0.3333 Rs = 1 VJ = 0.6 TT = 100n
ORDER CODE
EMIF
EMI Filter Number of lines
yy
-
xxx
zz
F
x
1: Pitch = 500m Bump = 315m 2: Leadfree Pitch = 500m Bump = 315m 3: Leadfree Pitch = 400m Bump = 250m 4: Pitch = 500m Bump = 250m Flip Chip
x: resistance value (Ohms) z: capacitance value / 10(pF) or Application (3 letters) and Version (2 digits)
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EMIF10-1K010F1
PACKAGE MECHANICAL DATA FLIP CHIP
500m 50 500m 50 315m 50 650m 65
2.57mm 50m
2.57mm 50m
250m 40
FOOT PRINT RECOMMENDATIONS
Copper pad Diameter : 250m recommended , 300m max
Solder stencil opening : 330m
Solder mask opening recommendation : 340m min for 315m copper pad diameter
MARKING
Dot, ST logo xxx = marking yww = datecode (y = year ww = week)
545 545
400
xxx y ww
100
230
All dimensions in m
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EMIF10-1K010F1
PACKING
Dot identifying Pin A1 location 4 +/- 0.1 O 1.5 +/- 0.1 1.75 +/- 0.1 3.5 +/- 0.1
0.73 +/- 0.05
All dimensions in mm
8 +/- 0.3
ST
ST
ST
xxx yww
User direction of unreeling
xxx yww
xxx yww
4 +/- 0.1
OTHER INFORMATION Ordering code EMIF10-1K010F1 Marking FDT Package Flip Chip Weight 9.2 mg Base qty 5000 Delivery mode Tape & reel (7")
Note: More packing informations are available in the application note AN1235: ''Flip-Chip: Package description and recommandations for use''
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - Printed in Italy - All rights reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 6/6

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