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| RF1K49090 Data Sheet January 2002 3.5A, 12V, 0.050 Ohm, Logic Level, Dual N-Channel LittleFETTM Power MOSFET This Dual N-Channel power MOSFET is manufactured using an advanced MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. It is designed for use in applications such as switching regulators, switching converters, motor drivers, relay drivers, and low voltage bus switches. This product achieves full rated conduction at a gate bias in the 3V - 5V range, thereby facilitating true on-off power control directly from logic level (5V) integrated circuits. Formerly developmental type TA49090. Features * 3.5A, 12V * rDS(ON) = 0.050 * Temperature Compensating PSPICE(R) Model * On-Resistance vs Gate Drive Voltage Curves * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Symbol BRAND RF1K49090 S1(1) G1(2) D1(8) D1(7) Ordering Information PART NUMBER RF1K49090 PACKAGE MS-012AA NOTE: When ordering, use the entire part number. For ordering in tape and reel, add the suffix 96 to the part number, i.e., RF1K4909096. D2(6) D2(5) S2(3) G2(4) Packaging JEDEC MS-012AA BRANDING DASH 5 1 2 3 4 (c)2002 Fairchild Semiconductor Corporation RF1K49090 Rev. B RF1K49090 Absolute Maximum Ratings TA = 25oC Unless Otherwise Specified RF1K49090 Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k, Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Pulse Width = 5s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed (Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating (Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation TA = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 12 12 10 3.5 Refer to Peak Current Curve Refer to UIS Curve 2 0.016 -55 to 150 300 260 W W/oC oC oC oC UNITS V V V A CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications PARAMETER TA = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V, (Figure 13) VGS = VDS, ID = 250A, (Figure 12) VDS = 12V, VGS = 0V VGS = 10V ID = 3.5A, VGS = 5V, (Figures 9, 11) VDD = 6V, ID 3.5A, RL = 1.71, V GS = 5V, RGS = 25 (Figure 10) TA = 25oC TA = 150oC MIN 12 1 VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 9.6V, ID = 3.5A, RL = 2.74 (Figure 15) Pulse width = 1s Device mounted on FR-4 material TYP 18 60 50 60 20 12 0.9 750 700 275 MAX 2 1 50 100 0.050 100 140 25 15 1.2 62.5 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF oC/W Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Resistance Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 5V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction-to-Ambient IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(5) Qg(TH) CISS COSS CRSS RJA VDS = 10V, VGS = 0V, f = 1MHz (Figure 14) Source to Drain Diode Specifications PARAMETER Source to Drain Voltage Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS ISD = 3.5A ISD = 3.5A, dISD/dt = 100A/s MIN TYP MAX 1.25 60 UNITS V ns (c)2002 Fairchild Semiconductor Corporation RF1K49090 Rev. B RF1K49090 Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 0 25 125 50 75 100 TA , AMBIENT TEMPERATURE (oC) 150 0.8 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 25 0.6 0.4 0.2 50 75 100 125 TA, AMBIENT TEMPERATURE (oC) 150 FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE 10 ZJA, NORMALIZED THERMAL IMPEDANCE 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-1 100 101 102 103 t, RECTANGULAR PULSE DURATION (s) 0.01 10-3 10-2 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 100 TA = 25oC ID, DRAIN CURRENT (A) 10 5ms 10ms 1 100ms 1s 0.1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) DC IDM, PEAK CURRENT CAPABILITY (A) TJ = MAX RATED, VDSS MAX = 12V 200 100 FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I VGS = 5V = I25 150 - TA 125 TA = 25oC 10 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 1 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 0.01 0.1 10 1 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY (c)2002 Fairchild Semiconductor Corporation RF1K49090 Rev. B RF1K49090 Typical Performance Curves 20 IAS, AVALANCHE CURRENT (A) (Continued) 25 ID, DRAIN CURRENT (A) 10 STARTING TJ = 25oC 20 VGS = 4V 15 VGS = 10V VGS = 5V VGS = 4.5V STARTING TJ = 150oC If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R) ln [(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 1 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 100 10 VGS = 3V 5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25oC 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) 5 0 NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS 25 ID(ON), ON-STATE DRAIN CURRENT (A) rDS(ON), ON-STATE RESISTANCE (m) 25oC -55oC 150oC 250 VDD = 6V ID = 7.0A 200 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 10V 20 15 150 ID = 3.5A ID = 1.75A 10 100 ID = 0.5A 5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 0 0 3.0 4.5 6.0 1.5 VGS, GATE TO SOURCE VOLTAGE (V) 7.5 50 0 2.5 3.5 4.0 4.5 3.0 VGS, GATE TO SOURCE VOLTAGE (V) 5.0 FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 140 120 SWITCHING TIME (ns) 100 tD(OFF) 80 tf 60 40 tD(ON) 20 0 tr NORMALIZED DRAIN TO SOURCE ON RESISTANCE VDD = 6V, ID = 3.5A, RL = 1.71 2.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 5V, ID = 3.5A 1.5 1.0 0.5 10 20 30 40 RGS, GATE TO SOURCE RESISTANCE () 50 0 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. SWITCHING TIME vs GATE RESISTANCE FIGURE 11. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE (c)2002 Fairchild Semiconductor Corporation RF1K49090 Rev. B RF1K49090 Typical Performance Curves 2.0 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A (Continued) 2.0 ID = 250A 1.5 THRESHOLD VOLTAGE NORMALIZED GATE 1.5 1.0 1.0 0.5 0.5 0 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 0.0 -80 -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) 160 FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 12 VDS , DRAIN-SOURCE VOLTAGE (V) 5.00 VDD = BVDSS 9 VDD = BVDSS 3.75 VGS , GATE-SOURCE VOLTAGE (V) 1200 C, CAPACITANCE (pF) 900 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD CISS COSS 6 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS RL = 3.43 IG(REF) = 0.6mA VGS = 5V I G ( REF ) 20 -----------------------I G ( ACT ) t, TIME (s) I G ( REF ) 80 -----------------------I G ( ACT ) 2.50 600 CRSS 300 3 1.25 0 0 0 2 4 6 8 VDS, DRAIN TO SOURCE VOLTAGE (V) 10 0.00 NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + 0V IAS 0.01 0 tAV FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS (c)2002 Fairchild Semiconductor Corporation RF1K49090 Rev. B RF1K49090 Test Circuits and Waveforms tON td(ON) tr RL VDS + tOFF td(OFF) tf 90% 90% RG DUT - VDD 0 10% 90% 10% VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS CURRENT REGULATOR VDS (ISOLATED SUPPLY) VDD VDS VGS = 10V Qg(5) D VGS VGS = 5V 12V BATTERY 0.2F 50k 0.3F SAME TYPE AS DUT Qg(TOT) G DUT VGS = 1V 0 S Qg(TH) VDS ID CURRENT SAMPLING RESISTOR Ig(REF) 0 Ig(REF) 0 IG CURRENT SAMPLING RESISTOR FIGURE 20. GATE CHARGE TEST CIRCUIT FIGURE 21. GATE CHARGE WAVEFORMS Soldering Precautions The soldering process creates a considerable thermal stress on any semiconductor component. The melting temperature of solder is higher than the maximum rated temperature of the device. The amount of time the device is heated to a high temperature should be minimized to assure device reliability. Therefore, the following precautions should always be observed in order to minimize the thermal stress to which the devices are subjected. 1. Always preheat the device. 2. The delta temperature between the preheat and soldering should always be less than 100oC. Failure to preheat the device can result in excessive thermal stress which can damage the device. 3. The maximum temperature gradient should be less than 5oC per second when changing from preheating to soldering. 4. The peak temperature in the soldering process should be at least 30 oC higher than the melting point of the solder chosen. 5. The maximum soldering temperature and time must not exceed 260oC for 10 seconds on the leads and case of the device. 6. After soldering is complete, the device should be allowed to cool naturally for at least three minutes, as forced cooling will increase the temperature gradient and may result in latent failure due to mechanical stress. 7. During cooling, mechanical stress or shock should be avoided. (c)2002 Fairchild Semiconductor Corporation RF1K49090 Rev. B RF1K49090 PSPICE Electrical Model SUBCKT RF1K49090 2 1 3 ;rev 9/6/94 CA 12 8 9.77e-10 CB 15 14 9.19e-10 CIN 6 8 7.81e-10 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 14.89 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 8 5 10 ESG 6 +8 GATE 1 LGATE RGATE 9 20 EVTO + 18 8 DPLCAP 16 MOS2 21 MOS1 CIN RSOURCE 11 EBREAK RIN 17 18 + DBODY RDRAIN DBREAK LDRAIN DRAIN 2 - 6 VTO - + 7 LSOURCE 3 SOURCE 18 RVTO IT 19 VBAT + LDRAIN 2 5 1e-9 LGATE 1 9 1.233e-9 LSOURCE 3 7 0.452e-9 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 4.91e-3 RGATE 9 20 2.74 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 5e-3 RVTO 18 19 RVTOMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD S1A 12 13 8 S1B S2A 15 14 13 S2B 13 CB 14 + 5 EDS 8 17 RBREAK CA + EGS 6 -8 - - VBAT 8 19 DC 1 VTO 21 6 0.3215 .MODEL DBDMOD D (IS = 7.00e-13 RS = 2.15e-2 TRS1 = 0.5e-3 TRS2 = 3.68e-6 CJO = 1.28e-9 TT = 1.8e-8) .MODEL DBKMOD D (RS = 1.28e-1 TRS1 = 1.69e-3 TRS2 = -2.0e-6) .MODEL DPLCAPMOD D (CJO = 0.84e-9 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 1.6 3KP = 11.5 5IS = 1e-3 0N = 1 0TOX = 1L = 1 uW = 1u) .MODEL RBKMOD RES (TC1 = 9.15e- 4TC2 = 3.13e-7) .MODEL RDSMOD RES (TC1 = 7.00e-4 TC2 = 5.00e-6) .MODEL RVTOMOD RES (TC1 = -2.155e- 3TC2 = -2.7e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.05 VOFF= -4.05) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.05 VOFF= -6.05) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.72 VOFF= 4.28) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 4.28 VOFF= -0.72) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991. (c)2002 Fairchild Semiconductor Corporation RF1K49090 Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM DISCLAIMER FAST (R) FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench (R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER (R) SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET (R) VCXTM STAR*POWER is used under license FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4 |
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