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CY101E383
ECL/TTL/ECL Translator and High-Speed Bus Driver
Features
* BiCMOS for optimum speed/power * High speed (max.) -- 3.0 ns tPD TTL-to-ECL * * * * * * * * * * -- 4 ns tPD ECL-to-TTL Low skew < 1 ns Can operate on single +5V supply Full-duplex ECL/TTL data transmission Internal 2 k ECL pull-down resistors on each ECL output 80-pin PQFP package 84-pin PLCC package VBB ECL reference voltage output Single- or dual-supply operation Capable of greater than 2001V ESD ECL cable/twisted pair driver mance systems. The device contains ten independent TTL-to-ECL and ten independent ECL-to-TTL translators for high-speed full-duplex data transmission, mixed logic, and bus applications. The CY101E383 is especially suited to drive ECL backplanes between TTL boards. The CY101E383 is implemented with differential ECL I/O to provide balanced low noise operation over controlled impedance buses between TTL and/or ECL subsystems. In addition, the device has internal output 2 k pull-down resistors tied to VEE to decrease the number of external components. For system testing purposes or for driving light loads, the 2 k is used as the only termination thereby eliminating up to 20 external resistors. The part meets standard 100K logic levels with the internal pull-down while driving 50 to -2V. The device is designed with ample ground pins to reduce bounce, and has separate ECL and TTL power/ground pins to reduce noise coupling between logic families. The parts can operate in single- or dual-supply configurations while maintaining absolute and 100K level swings. The translators are offered in a standard 100K ECL-compatible version with -5.2V or -4.5V power supply. The TTL I/O is fully TTL compatible. The CY101E383 is packaged in 84-pin surface-mountable PLCCs and CLCCs. To save board space, an 80-pin PQFP package with 25-mil-lead pitch is available.
Functional Description
The CY101E383 is a new-generation TTL-to-ECL and ECL-to-TTL logic level translator designed for high-perfor-
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 July 1990 - Revised April 11, 1997
CY101E383
Logic Block Diagram
VBB D0 D0 DIFFERENTIAL D1 ECL INPUTS D1 ECL SUPPL D2 Y D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 D8 D8 D9 D9 D10 D11 D12 D13 D14 TTL INPUTS D15 TTL SUPPLY D16 D17 D18 D19 ECL D4 ECL D4 ECL D3 ECL D3 ECL D2 ECL D2 ECL D1 ECL D1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q10 Q11 Q11 Q12 Q12 Q13 Q13 Q14 Q14 Q15 DIFFERENTIAL Q15 Q16 ECL OUTPUTS Q16 ECL SUPPLY Q17 Q17 Q18 Q18 Q19 Q19 10 5 7 1 TTL OUTPUTS TTL SUPPLY ECL D5 ECL D5 ECL D6 ECL D6 ECL D7 ECL D7 ECL D8 ECL D8 ECL D9 ECL D9 ECL VBB ECL VCC ECL Q10 ECL Q10 ECL VCC ECL Q11 ECL Q11 ECL VCC ECL Q12 ECL Q12 ECL VCC 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Pin Configurations
PLCC/CLCC Top View
ECL D0 ECL D0 TTL VCC TTL Q9 TTL GND TTL Q7 TTL GND TTL Q6 TTL VCC TTL Q5 TTL GND TTL VCC TTL Q8
11 10 9
876
5
432
1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 TTL GND TTL Q4 TTL VCC TTL Q3 TTL GND TTL Q2 TTL VCC TTL Q1 TTL GND TTL Q0 TTL GND TTL D19 TTL D18 TTL D17 TTL D16 TTL D15 TTL D14 TTL D13 TTL D12 TTL D11 TTL D10
101E383
65 64 63 62 61 60 59 58 57
30 56 31 55 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 ECL Q13 ECL Q13 ECL VEE ECL Q14 ECL Q14 ECL Q15 ECL Q15 ECL VCC ECL Q16 ECL Q16 ECL VCC ECL Q17 ECL Q17 ECL Q18 ECL Q18 ECL VCC ECL Q19 ECL VCC ECL Q19 ECL VCC
TTL GND
Note 1
Note: 1. The PQFP package has one less each TTL VCC and TTL GND pin and two less ECL VCC pins.
ECL VCC
TTL VCC
ECL VEE
E383-1
ECL VCC
E383-2
2
CY101E383
Pin Configurations (continued)
PQFP Top View
ECL D0 ECL D0 TTL VCC TTL Q9 TTL GND TTL GND TTL Q6 TTL VCC TTL Q5 TTL GND ECL D4 ECL D4 ECL D3 ECL D3 ECL D2 ECL D2 ECL D1 ECL D1 TTL Q8 TTL Q7
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 ECL D5 ECL D5 ECL D6 ECL D6 ECL D7 ECL D7 ECL D8 ECL D8 ECL D9 ECL D9 ECL VBB ECL VCC ECL Q10 ECL Q10 ECL VCC ECL Q11 ECL Q11 ECL Q12 ECL Q12 ECL VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 60 59 58 57 56 55 54 TTL Q4 TTL VCC TTL Q3 TTL GND TTL Q2 TTL VCC TTL Q1 TTL GND TTL Q0 TTL GND TTL D19 TTL D18 TTL D17 TTL D16 TTL D15 TTL D14 TTL D13 TTL D12 TTL D11 TTL D10
101E383
53 52 51 50 49 48 47 46 45 44 43
19 42 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
ECL Q13 ECL Q13
ECL VEE ECL Q14 ECL Q14
ECL Q15 ECL Q15
ECL Q16
ECL Q16
ECL VCC ECL Q17 ECL Q17
ECL Q18 ECL Q18 ECL VCC ECL Q19
ECL VCC
ECL VCC
ECL Q19
ECL VCC
E383-3
Selection Guide
101E383-3 Maximum Propagation Delay Time (ns) (TTL to ECL) Maximum Propagation Delay Time (ns) (ECL to TTL) Maximum Operating Current (mA) Sum of IEE and ICC 3 4 300 ECL Output Current .........................................................-50 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... -65C to +150C Ambient Temperature with Power Applied .................................................. -55C to +125C TTL Supply Voltage to Ground Potential .........-0.5V to +7.0V TTL DC Input Voltage .........................................-3.0V to +7.0V ECL Supply Voltage VEE to ECL VCC ..............-7.0V to +0.5V ECL Input Voltage ............................................. VEE to +0.5V
Operating Range
Range I/O Ambient Version Temperature 101E ECL VEE TTL VCC
Commercial 100K
0C to +85C -4.2Vto 5V -5.46V 5%
3
CY101E383
ECL Electrical Characteristics Over the Operating Range[2]
101E383 Parameter VOH VOL VIH VIL VBB VCM[5] VDIFF IIH IIL RPD IEE Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Output Reference Voltage Common Mode Voltage Input Voltage Differential Input HIGH Current Input LOW Current Pull-Down Resistor Supply Current (All inputs and outputs open) Test Conditions 101E, RL = 50 to -2V VIN = VIH Min. or VIL Max. 101E, RL = 50 to -2V VIN = VIH Min. or VIL Max. 101E 101E 101E
[4]
Temperature TA = 0C to 85C TA = 0C to 85C TA = 0C to 85C TA = 0C to 85C TA = 0C to 85C
[3]
Min. -1065 -1900 -1165 -1900 -1.5 150
Max. -700 -1600 -700 -1475 -1.15 1.0 220
Unit mV mV mV mV V V mV A A k mA
VCM with respect to VBB Required for Full Output Swing VIN = VIH Max. VIN = VIL Min. Connected from All ECL Outputs to V EE TA = 0C to 85C -0.5 1.6
170 3.0 -180
TTL Electrical Characteristics Over the Operating Range[2]
101E383 Parameter VOH VOL VIH VIL VCD IOS[7] IIX ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage
[6] [5]
Test Conditions VCC = Min., IOH = -3.2 mA VCC = Max., IOL = 16.0 mA
Min. 2.4
Max. 0.5
Unit V V V V V mA A mA
2.0 0.8 IIN = -10 mA VCC = Max., VOUT = 0.5V GND < VI < VCC VCC = Max., IOUT = 0 mA, f = f max.
[8]
Input Clamp Diode Voltage Output Short-Circuit Current Input Load Current
[9]
-1.5 -180 -250 -40 +20 120
VCC Operating Supply Current
Capacitance[7]
Parameter CIN[7] COUT[7] Description Input Capacitance Output Capacitance Max. 4 5 Unit pF pF
Notes: 2. See AC Test Load and Waveform for test conditions. 3. Commercial grade is specified as ambient temperature with transverse air flow greater than 500 linear feet per minute. 4. Max. IBB = -1 mA. 5. The internal gain of the CY101E383 guarantees that the output voltage will not change for common mode signals to 1V. Therefore, input CMRR is infinite within the common mode range. 6. These are absolute values with respect to device ground. 7. Characterized initially and after any design or process changes that may affect these parameters. 8. Not more than one output should be tested at a time. Duration of the short should not be more than one second. 9. I/O pin leakage is the worst case of IIX (where X = H or L).
4
CY101E383
TTL AC Test Load and Waveform[10]
5V OUTPUT CL pF INCLUDING JIG AND SCOPE Equivalent to: R2170 (236 MIL)
E383-5
R1238 (319 MIL) 3.0V GND 3 ns 90% 10% 90% 10% 3 ns
E383-4
THE VENIN EQUIVALENT (Commercial) OUTPUT 99 2.08V
THEVENIN EQUIVALENT (Military) OUTPUT 136 2.13Vthm
ECL AC Test Load and Waveform[11, 12, 13, 14, 15]
GND ALL INPUT PULSES VCC, V CCO INPUT D OUT VEE 0.01 F VEE RL -2.0V
E383-6 E383-7
VIH VIL 20%
80%
80% 20%
CL
tr
tf
ECL-to-TTL Switching Characteristics Over the Operating Range
101E383-3 Parameter tPLH tPHL Description Propagation Delay Time Propagation Delay Time Test Conditions Dn, Dn to Qn Dn, Dn to Qn Min. 1 1 Max. 4 4 Unit ns ns
TTL-to-ECL Switching Characteristics Over the Operating Range
101E383-3 Parameter tPLH tPHL tR[7] tR[7] Description Propagation Delay Time Propagation Delay Time Output Rise Time Output Fall Time Test Conditions Dn to Qn, Qn Dn to Qn, Qn 20% to 80% 20% to 80% Min. 1 1 0.35 0.35 Max. 3 3 1.7 1.7 Unit ns ns ns ns
Skew Time Switching Characteristics[7] (Same test conditions as TTL-to-ECL and ECL-to-TTL Electrical Characteristics)
Symbol tSKT[7] tSKE[7] Characteristic Data Skew Time ECL-to-TTL Data Skew Time TTL-to-ECL Test Conditions TTLQn to TTLQn+m ECLQn, Qn to ECLQn+m, Qn+m Min. Max. 1 1 Unit ns ns
5
CY101E383
Skew Time Switching Characteristics[7] (Same test conditions as TTL-to-ECL and ECL-to-TTL Electrical Characteristics)
Symbol Characteristic Test Conditions Min. Max. Unit
10. TTL test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL/IOH, and CL = 10 pF. 11. VIL=-1.7V, VIH=-0.9V. 12. ECL RL = 50, CL < 5 pF (includes fixture and stray capacitance). 13. All coaxial cables should be 50 with equal lengths. The delay of the coaxial cables should be "nulled" out of the measurement. 14. t r = tf = 0.7 ns 15. All timing measurements are made from the 50% point of all waveforms.
6
CY101E383
Switching Waveforms
ECL-to- TTLTiming
Dn
50% tPLH
50% tPHL 1.5V
E383-8
Qn
1.5V
TTL-to-ECL Timing
Dn
1.5V tPLH
1.5V tPHL 50% 50%
E383-9
Qn
Skew Test (t SKT) TTL An-to-TTL Qn+m
Qn(TTL)
1.5V tSKT
1.5V tSKT 1.5V 1.5V
E383-10
Qn+m (TTL)
Skew Test (t SKE) ECLQn, Qn-to-ECLQn+m , Qn+m
Qn(ECL) Qn(ECL) Qn+m (ECL) Qn+m (ECL) tSKE 50% tSKE 50%
E383-11
50% tSKE
50% tSKE
7
CY101E383
ECL-to-TTL Truth Table
Inputs ECL Dn Open L H
[16]
Outputs ECL Dn Open H L
[16]
TTL Qn L L H
resistor tied to -5V is now at ground potential. Consideration should be given to the power supply so that adequate bypassing is made to isolate the ECL output switching noise from the supply. Having separate TTL and ECL +5V supply lines will help to reduce the noise. Table 1. CY101E383 Nominal Voltages Applied in 100K System Supply Pin TTL VCC TTL GND Single-Supply System +5.0V 0.0V +5.0V 0.0V Dual-Supply System +5.0V 0.0V 0.0V -4.5V
TTL-to-ECL Truth Table
Inputs TTL Dn L H ECL Qn L H Outputs ECL Qn H L
ECL VCC ECL V EE
Nominal Voltages
The CY101E383 can be used in dual 5V or single +5V supply systems. The supply pins should be connected as shown in Tables 1 and 2. This connection technique involves shifting up all ECL supply pins by 5V. When operating in single-supply systems, the ECL termination voltage level must also be shifted up by adding 5V. For example, if the termination is 50 ohms to -2V in a dual-supply system, the single +5V system should have 50 ohms to +3V. If the termination is a thevenin type, then the resistor tied to ground is now at +5V and the
Table 2. CY101E383 Nominal Voltages Applied in 101K System Supply Pin TTL VCC TTL GND ECL VCC ECL VEE Single-Supply System +5.0V 0.0V +5.0V 0.0V Dual-Supply System +5.0V 0.0V 0.0V -5.2V
Ordering Information
Speed (ns) 3 Ordering Code CY101E383-3JC CY101E383-3NC Package Name J83 N80 Package Type 80-Lead Plastic Quad Flatpack Operating Range
84-Lead Plastic Leaded Chip Carrier Commercial
Note: 16. The ECL inputs will pull to a known logic level if left open.
Document #: 38-A-00023-I
Package Diagrams
84-Lead Plastic Leaded Chip Carrier J83
8
CY101E383
Package Diagrams (continued)
80-Lead Plastic Quad Flatpack N80
(c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY101E383
Package Diagrams (continued)
84-Pin Ceramic Leaded Chip Carrier Y84
10

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