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| SL4050B Hex Buffer/Converter High-Voltage Silicon-Gate CMOS The SL4050B is noninverting hex buffers and feature logic-level conversion using only one supply (voltage (VCC). The input-signal high level (VIH) can exceed the VCC supply voltage when these devices are used for logic-level conversions. These devices are intended for use as CMOS to DTL/TTL converters. * Operating Voltage Range: 3.0 to 18 V * Maximum input current of 1 A at 18 V over full packagetemperature range; 100 nA at 18 V and 25C * Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply * High-to-low level conversion ORDERING INFORMATION SL4050BN Plastic SL4050BD SOIC TA = -55 to 125 C for all packages LOGIC DIAGRAM PIN ASSIGNMENT NC = NO CONNECTION FUNCTION TABLE Inputs A L PINS 13, 16 = NO CONNECTION PIN 1 =VCC PIN 8 = GND H Output Y L H SLS System Logic Semiconductor SL4050B MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN PD PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Power Dissipation per Output Transistor Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +20 V ** CC Unit V V V mA mW mW C C to +18 -0.5 to VCC +0.5 10 750 500 100 -65 to +150 260 Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C ** The IW4050B has high-to-low level voltage conversion capability but not low-to-high level; therefore it is recommended that VIN VCC RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN VOUT TA ** Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min 3.0 V ** CC Max 18 18 VCC +125 Unit V V V C 0 -55 The IW4050B has high-to-low level voltage conversion capability but not low-to-high level; therefore it is recommended that VIN VCC This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. SLS System Logic Semiconductor SL4050B DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Symbol VIH Parameter Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Minimum Output Low (Sink) Current Test Conditions VOUT= VCC - 0.5V VOUT= VCC - 1.0 V VOUT= VCC - 1.5V VOUT= 0.5V VOUT= 1.0 V VOUT= 1.5V VIN= VCC V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 18 5.0 10 15 20 4.5 5 10 15 5.0 5.0 10 15 Guaranteed Limit -55C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 0.1 1 2 4 20 3.3 4 10 26 -2.6 -0.81 -2.0 -5.2 25C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 0.1 1 2 4 20 2.6 3.2 8 24 -2.1 -0.65 -1.65 -4.3 125 C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 1.0 30 60 120 600 1.8 2.4 5.6 18 mA -1.55 -0.48 -1.18 -3.1 Unit V VIL V VOH V VOL VIN=GND V IIN ICC VIN= GND or VCC VIN= GND or VCC A A IOL VIN= GND or VCC UOL=0.4 V UOL=0.4 V UOL=0.5 V UOL=1.5 V mA IOH Minimum Output High VIN= GND or VCC (Source) Current UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V SLS System Logic Semiconductor SL4050B AC ELECTRICAL CHARACTERISTICS(CL=50pF, RL=200k, Input t r=t f=20 ns) VIN Symbol tPLH Parameter Maximum Propagation Delay, Input A to Output Y (Figure 1) V 5 10 10 15 15 5 10 10 15 15 5 10 15 5 10 15 VCC V 5 10 5 15 5 5 10 5 15 5 5 10 15 5 10 15 Guaranteed Limit -55C 140 80 90 60 80 110 55 100 30 100 160 80 60 60 40 30 25C 140 80 90 60 80 110 55 100 30 100 160 80 60 60 40 30 7.5 125C 280 160 180 120 160 220 110 200 60 200 320 160 120 120 80 60 Unit ns tPHL Maximum Propagation Delay, Input A to Output Y (Figure 1) ns tTLH Maximum Output Transition Time, Any Output (Figure 1) Maximum Output Transition Time, Any Output (Figure 1) Maximum Input Capacitance ns tTHL ns CIN pF Figure 1. Switching Waveforms EXPANDED LOGIC DIAGRAM (1/6 of the Device) SLS System Logic Semiconductor |
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