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DATA SHEET
MOS INTEGRATED CIRCUIT
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The PD78F0034B is a member of the PD780034A Subseries in the 78K/0 Series, and is equivalent to the
PD780034A (expanded-specification product) but with flash memory in place of internal ROM.
The PD78F0034BY is a member of the PD780034AY Subseries, featuring flash memory in place of the internal ROM of the PD780034AY. The PD78F0034B(A) and 78F0034BY(A) are products to which a quality assurance program more stringent than that used for the PD78F0034B and 78F0034BY (standard models) is applied (NEC Electronics classifies these products as "special" quality grade models). The PD78F0034B, 78F0034BY, 78F0034B(A), and 78F0034BY(A) incorporate flash memory, which can be programmed and erased while mounted on the board. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing.
PD780024A, 780034A, 780024AY, 780034AY Subseries User's Manual: U14046E
78K/0 Series Instruction User's Manual: U12326E
FEATURES
* Pin-compatible with mask ROM versions (except VPP pin) * Flash memory: * Supply voltage: Note 32 KBNote VDD = 1.8 to 5.5 V * Internal high-speed RAM: 1,024 bytesNote
The flash memory and internal high-speed RAM capacities can be changed with the memory size switching register (IMS).
Remark For the differences between the flash memory and the mask ROM versions, refer to 4. DIFFERENCES BETWEEN PD78F0034B, 78F0034BY, AND MASK ROM VERSIONS.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
Document No. U16369EJ1V0DS00 (1st edition) Date Published January 2003 N CP(K) Printed in Japan
(c)
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
ORDERING INFORMATION
Part Number Package 64-pin plastic LQFP (10 x 10) 64-pin plastic LQFP (14 x 14) 64-pin plastic TQFP (12 x 12) 73-pin plastic FBGA (9 x 9) 64-pin plastic LQFP (10 x 10) 64-pin plastic LQFP (14 x 14) 64-pin plastic TQFP (12 x 12) 64-pin plastic LQFP (10 x 10) 64-pin plastic LQFP (14 x 14) 64-pin plastic TQFP (12 x 12) 73-pin plastic FBGA (9 x 9) 64-pin plastic LQFP (10 x 10) 64-pin plastic LQFP (14 x 14) 64-pin plastic TQFP (12 x 12) Internal ROM Flash memory Flash memory Flash memory Flash memory Flash memory Flash memory Flash memory Flash memory Flash memory Flash memory Flash memory Flash memory Flash memory Flash memory
PD78F0034BGB-8EU PD78F0034BGC-8BS PD78F0034BGK-9ET PD78F0034BF1-CN3 PD78F0034BGB(A)-8EU PD78F0034BGC(A)-8BS PD78F0034BGK(A)-9ET PD78F0034BYGB-8EU PD78F0034BYGC-8BS PD78F0034BYGK-9ET PD78F0034BYF1-CN3 PD78F0034BYGB(A)-8EU PD78F0034BYGC(A)-8BS PD78F0034BYGK(A)-9ET
QUALITY GRADE
Part Number Package 64-pin plastic LQFP (10 x 10) 64-pin plastic LQFP (14 x 14) 64-pin plastic TQFP (12 x 12) 73-pin plastic FBGA (9 x 9) 64-pin plastic LQFP (10 x 10) 64-pin plastic LQFP (14 x 14) 64-pin plastic TQFP (12 x 12) 64-pin plastic LQFP (10 x 10) 64-pin plastic LQFP (14 x 14) 64-pin plastic TQFP (12 x 12) 73-pin plastic FBGA (9 x 9) 64-pin plastic LQFP (10 x 10) 64-pin plastic LQFP (14 x 14) 64-pin plastic TQFP (12 x 12) Quality Grade Standard Standard Standard Standard Special Special Special Standard Standard Standard Standard Special Special Special
PD78F0034BGB-8EU PD78F0034BGC-8BS PD78F0034BGK-9ET PD78F0034BF1-CN3 PD78F0034BGB(A)-8EU PD78F0034BGC(A)-8BS PD78F0034BGK(A)-9ET PD78F0034BYGB-8EU PD78F0034BYGC-8BS PD78F0034BYGK-9ET PD78F0034BYF1-CN3 PD78F0034BYGB(A)-8EU PD78F0034BYGC(A)-8BS PD78F0034BYGK(A)-9ET
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
2
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
CORRESPONDENCE BETWEEN MASK ROM PRODUCTS AND FLASH MEMORY PRODUCTS
* PD780024A, 780034A Subseries
Mask ROM Products Expanded-specification products of PD780021A, 780022A, 780023A, 780024A Expanded-specification products of PD780031A, 780032A, 780033A, 780034A Conventional products of PD780021A, 780022A, 780023A, 780024A Conventional products of PD780031A, 780032A, 780033A, 780034A Expanded-specification products of PD780021A(A), 780022A(A), 780023A(A), 780024A(A) Expanded-specification products of PD780031A(A), 780032A(A), 780033A(A), 780034A(A) Conventional products of PD780021A(A), 780022A(A), 780023A(A), 780024A(A) Conventional products of PD780031A(A), 780032A(A), 780033A(A), 780034A(A) Flash Memory Products
PD78F0034B PD78F0034A PD78F0034B(A) PD78F0034B(A)
Caution The PD78F0034B(A) and conventional products of the PD780021A(A), 780022A(A), 780023A(A), 780024A(A) and PD780031A(A), 780032A(A), 780033A(A), and 780034A(A) differ in the operating frequency ratings. When using the mask ROM versions in place of the flash memory versions, take note of the power supply voltage and operating frequency used. Remarks 1. The PD78F0034B, 78F0034B(A) and 78F0034A differ in the operating frequency ratings and communication mode of the flash memory programming. Refer to 5. DIFFERENCES BETWEEN
PD78F0034B, 78F0034BY AND PD78F0034A, 78F0034AY.
2. The expanded-specification products and conventional products of the mask ROM versions differ in the operating frequency ratings. Refer to the data sheets of the products. 3. The special grade version of the PD78F0034A is not provided (only the standard grade version is provided). * PD780024AY, 780034AY Subseries
Mask ROM Products Flash Memory Products
PD780021AY, 780022AY, 780023AY, 780024AY PD780031AY, 780032AY, 780033AY, 780034AY PD780021AY(A), 780022AY(A), 780023AY(A), 780024AY(A) PD780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
PD78F0034AY PD78F0034BY PD78F0034BY(A)
Remarks 1. The PD78F0034BY, 78F0034BY(A) and 78F0034AY differ in the communication mode of the flash memory programming. Refer to 5. DIFFERENCES BETWEEN PD78F0034B, 78F0034BY AND
PD78F0034A, 78F0034AY.
2. The expanded-specification products of the PD780024AY, 780034AY Subseries are not provided (only the conventional products are provided). 3. The special grade version of the PD78F0034A is not provided (only the standard grade version is provided).
Data Sheet U16369EJ1V0DS
3
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
78K/0 SERIES LINEUP
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production Products under development
Y subseries products are compatible with I2C bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 52-pin 52-pin 64-pin 64-pin 42/44-pin
PD78075B PD78078 PD78070A PD780058 PD78058F PD78054 PD780065 PD780078 PD780034A PD780024A PD780034AS
PD780024AS PD78014H
EMI-noise reduced version of the PD78078
PD78078Y PD78070AY PD780018AY PD780058Y PD78058FY PD78054Y
PD78054 with timer and enhanced external interface
ROMless version of the PD78078 PD78078Y with enhanced serial I/O and limited function
PD78054 with enhanced serial I/O
EMI-noise reduced version of the PD78054
PD78018F with UART and D/A converter, and enhanced I/O PD780024A with expanded RAM PD780034A with timer and enhanced serial I/O PD780078Y PD780034AY PD780024A with enhanced A/D converter PD780024AY PD78018F with enhanced serial I/O 52-pin version of the PD780034A
52-pin version of the PD780024A EMI-noise reduced version of the PD78018F
PD78018F PD78083
Inverter control
PD78018FY
Basic subseries for control On-chip UART, capable of operating at low voltage (1.8 V)
64-pin
PD780988
VFD drive
On-chip inverter control circuit and UART. EMI-noise reduced.
100-pin 80-pin 80-pin 80-pin
PD780208 PD780232 PD78044H PD78044F
LCD drive
PD78044F with enhanced I/O and VFD C/D. Display output total: 53
For panel control. On-chip VFD C/D. Display output total: 53
PD78044F with N-ch open-drain I/O. Display output total: 34
Basic subseries for driving VFD. Display output total: 34
78K/0 Series
100-pin 100-pin 120-pin 120-pin 120-pin 100-pin 100-pin 100-pin
PD780354 PD780344 PD780338 PD780328 PD780318 PD780308 PD78064B PD78064
PD780354Y PD780344Y
PD780344 with enhanced A/D converter PD780308 with enhanced display function and timer. PD780308 with enhanced display function and timer. PD780308 with enhanced display function and timer. PD780308 with enhanced display function and timer.
Segment signal output: 40 pins max. Segment signal output: 40 pins max. Segment signal output: 32 pins max. Segment signal output: 24 pins max.
PD780308Y PD78064Y
PD78064 with enhanced SIO, and expanded ROM and RAM EMI-noise reduced version of the PD78064
Basic subseries for driving LCDs, on-chip UART
Bus interface supported 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin
PD780948 PD78098B PD780702Y PD780703Y PD780833Y
PD780816
Meter control
On-chip CAN controller
PD78054 with IEBusTM controller
On-chip IEBus controller On-chip CAN controller On-chip controller compliant with J1850 (Class 2) Specialized for CAN controller function
100-pin 80-pin 80-pin
PD780958 PD780852 PD780828B
For industrial meter control On-chip automobile meter controller/driver For automobile meter driver. On-chip CAN controller
Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some documents, but the functions of the two are same.
4
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
The major functional differences among the subseries are listed below. * Non-Y subseries
Function Subseries Name Control ROM Timer 8-Bit 10-Bit 8-Bit Capacity (Bytes) 8-Bit 16-Bit Watch WDT A/D A/D D/A 1 ch 1 ch 1 ch 8 ch - Serial Interface I/O VDD External MIN. Value Expansion 1.8 V
PD78075B 32 K to 40 K 4 ch PD78078 PD78070A
48 K to 60 K -
2 ch 3 ch (UART: 1 ch)
88
61 3 ch (time-division UART: 1 ch) 3 ch (UART: 1 ch) 68 69
2.7 V 1.8 V 2.7 V 2.0 V
PD780058 24 K to 60 K 2 ch PD78058F 48 K to 60 K PD78054
16 K to 60 K - 2 ch 1 ch 8 ch - 4 ch 8 ch - 4 ch - - 8 ch
PD780065 40 K to 48 K PD780078 48 K to 60 K
PD780034A 8 K to 32 K PD780024A
PD780034AS PD780024AS
4 ch (UART: 1 ch) 3 ch (UART: 2 ch) 3 ch (UART: 1 ch)
60 52 51
2.7 V 1.8 V
39
-
PD78014H PD78018F 8 K to 60 K PD78083
Inverter control VFD drive 8 K to 16 K - - - 1 ch
2 ch
53
1 ch (UART: 1 ch) - 8 ch - 3 ch (UART: 2 ch)
33 47 4.0 V
- -
PD780988 16 K to 60 K 3 ch Note PD780208 32 K to 60 K 2 ch PD780232 16 K to 24 K 3 ch PD78044H 32 K to 48 K 2 ch PD78044F 16 K to 40 K
1 ch - 1 ch
1 ch - 1 ch
1 ch
8 ch 4 ch 8 ch
-
-
2 ch
74 40
2.7 V 4.5 V 2.7 V
1 ch 2 ch
68
LCD drive
PD780354 24 K to 32 K 4 ch PD780344 PD780338 48 K to 60 K 3 ch PD780328 PD780318 PD780308 48 K to 60 K 2 ch PD78064B 32 K PD78064
16 K to 32 K 2 ch
1 ch
1 ch
1 ch
- 8 ch
8 ch -
-
3 ch (UART: 1 ch)
66
1.8 V
-
2 ch
-
10 ch 1 ch 2 ch (UART: 1 ch)
54 62 70
1 ch
8 ch
-
-
3 ch (time-division UART: 1 ch) 2 ch (UART: 1 ch)
57
2.0 V
Bus interface
PD780948 60 K PD78098B 40 K to 60 K
2 ch 1 ch 2 ch 2 ch
1 ch
1 ch
8 ch
-
- 2 ch
3 ch (UART: 1 ch)
79 69
4.0 V 2.7 V 4.0 V 2.2 V
-
supported PD780816 32 K to 60 K Meter control Dashboard control
12 ch - 1 ch - -
- -
2 ch (UART: 1 ch) 2 ch (UART: 1 ch)
46 69
PD780958 48 K to 60 K 4 ch PD780852 32 K to 40 K 3 ch
PD780828B 32 K to 60 K
-
1 ch
1 ch
1 ch
5 ch
-
-
3 ch (UART: 1 ch)
56 59
4.0 V
-
Note 16-bit timer: 2 channels 10-bit timer: 1 channel
Data Sheet U16369EJ1V0DS
5
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
* Y subseries
Function Subseries Name Control ROM Capacity (Bytes) Timer 8-Bit 10-Bit 8-Bit A/D - D/A 2 ch 3 ch (UART: 1 ch, I2C: 1 ch) 88 61 - 3 ch (I C: 1 ch)
2 2
Serial Interface
I/O
8-Bit 16-Bit Watch WDT A/D 1 ch 1 ch 1 ch 8 ch
VDD External MIN. Value Expansion 1.8 V 2.7 V
PD78078Y 48 K to 60 K 4 ch
PD78070AY
-
PD780018AY 48 K to 60 K
88 68 69 1.8 V 2.7 V 2.0 V
PD780058Y 24 K to 60 K 2 ch
PD78058FY 48 K to 60 K
2 ch 3 ch (time-division UART: 1 ch, I C: 1 ch) 3 ch (UART: 1 ch, I C: 1 ch)
2
PD78054Y 16 K to 60 K
PD780078Y 48 K to 60 K
PD780034AY 8 K to 32 K PD780024AY
2 ch 1 ch 8 ch - 2 ch (I2C: 1 ch) 1 ch 1 ch 1 ch - 8 ch 8 ch - - 4 ch (UART: 1 ch, I C: 1 ch) 3 ch (time-division UART: 1 ch, I2C: 1 ch) 2 ch (UART: 1 ch, I C: 1 ch) 3 ch 2 ch 1 ch 1 ch 16 ch - - 4 ch (UART: 1 ch, I2C: 1 ch) 67
2 2
-
8 ch
-
4 ch (UART: 2 ch, I C: 1 ch)
2
2
52
1.8 V
3 ch (UART: 1 ch, I C: 1 ch) 51
PD78018FY 8 K to 60 K
LCD drive
53 66 1.8 V -
PD780354Y 24 K to 32 K 4 ch PD780344Y PD780308Y 48 K to 60 K 2 ch
57
2.0 V
PD78064Y 16 K to 32 K
Bus PD780701Y 60 K interface PD780703Y supported PD780833Y
3.5 V
-
65
4.5 V
Remark
Functions other than the serial interface are common to both the Y and non-Y subseries.
6
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
OVERVIEW OF FUNCTIONS
Part Number Item Internal memory Memory space General-purpose registers Minimum instruction execution time When main system When subsystem clock selected Instruction set Flash memory High-speed RAM 32 KBNote 1 1,024 bytesNote 1 64 KB 8 bits x 32 registers (8 bits x 8 registers x 4 banks) On-chip minimum instruction execution time cycle variable function 0.166 s/0.333 s/0.666 s/1.33 s/2.66 s (@ 12 MHz operation, VDD = 4.5 to 5.5 V) 122 s (@ 32.768 kHz operation) * * * * 16-bit operation Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjust, etc. 51 0.238 s/0.48 s/0.95 s/1.91 s/3.81 s (@ 8.38 MHz operation, VDD = 4.0 to 5.5 V)
PD78F0034B PD78F0034B(A)
PD78F0034BY PD78F0034BY(A)
I/O ports
Total:
* CMOS input: 8 * CMOS I/O: 39 * N-ch open-drain I/O (5 V withstand voltage): 4 A/D converter Serial interface * 10-bit resolution x 8 channels * Operable over a wide power supply voltage range: AVDD = 1.8 to 5.5 V * UART mode: 1 channel * 3-wire serial I/O mode: 2 channels * * * UART mode: 1 channel 3-wire serial I/O mode: 1 channel I2C bus mode (multimaster supporting): 1 channel
Timers
* * * *
16-bit timer/event counter: 8-bit timer/event counter: Watch timer: Watchdog timer:
1 2 1 1
channel channels channel channel
Timer outputs Clock output
3 (8-bit PWM output capable: 2) * 93.75 kHz, 187.5 kHz, 375 kHz, 750 kHz, 1.25 MHz, 3 MHz, 6 MHz, 12 MHz (@ 12 MHz operation with main system clock) * 32.768 kHz (@ 32.768 kHz operation with subsystem clock) 1.46 kHz, 2.93 kHz, 5.86 kHz, 11.7 kHz (@ 12 MHz operation with main system clock) Maskable Non-maskable Software Internal: 13, external: 5 Internal: 1 1 Internal: 1, external: 1 VDD = 1.8 to 5.5 V TA = -40 to +85C * * * * 64-pin 64-pin 64-pin 73-pin plastic plastic plastic plastic LQFP (10 x 10) LQFP (14 x 14) TQFP (12 x 12) FBGA (9 x 9)Note 2 * 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz (@ 8.38 MHz operation with main system clock) * 32.768 kHz (@ 32.768 kHz operation with subsystem clock) 1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz (@ 8.38 MHz operation with main system clock)
Buzzer output Vectored interrupt sources
Test inputs Supply voltage Operating ambient temperature Package
Notes 1. 2.
The capacities of the flash memory and the internal high-speed RAM can be changed with the memory size switching register (IMS). The special grade version of the 73-pin plastic FBGA (9 x 9) is not provided.
Data Sheet U16369EJ1V0DS
7
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ..............................................................................................
9
2. BLOCK DIAGRAM .......................................................................................................................... 12 3. PIN FUNCTIONS ............................................................................................................................. 13
3.1 3.2 3.3 Port Pins ................................................................................................................................................. Non-Port Pins ......................................................................................................................................... Pin I/O Circuits and Recommended Connection of Unused Pins .................................................. 13 14 16
4. DIFFERENCES BETWEEN PD78F0034B, 78F0034BY, AND MASK ROM VERSIONS ......... 19 5. DIFFERENCES BETWEEN PD78F0034B, 78F0034BY AND PD78F0034A, 78F0034AY ..... 21 6. DIFFERENCES BETWEEN PD78F0034B, 78F0034BY AND PD78F0034B(A), 78F0034BY(A) ..... 22 7. MEMORY SIZE SWITCHING REGISTER (IMS) ............................................................................ 23 8. FLASH MEMORY PROGRAMMING .............................................................................................. 24
8.1 8.2 8.3 Selection of Communication Mode ..................................................................................................... Flash Memory Programming Functions ............................................................................................. Connection of Flashpro III/Flashpro IV .............................................................................................. 24 26 26
9. ELECTRICAL SPECIFICATIONS ................................................................................................... 28
9.1 9.2 9.3
PD78F0034B, 78F0034B(A) ................................................................................................................ PD78F0034BY, 78F0034BY(A) ............................................................................................................
Timing Chart ...........................................................................................................................................
28 46 64
10. PACKAGE DRAWINGS .................................................................................................................. 71 11. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 75 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................. 77 APPENDIX B. RELATED DOCUMENTS ............................................................................................ 85
8
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
1. PIN CONFIGURATION (TOP VIEW)
* 64-pin plastic LQFP (10 x 10) * 64-pin plastic LQFP (14 x 14)
P73/TI51/TO51 P72/TI50/TO50
* 64-pin plastic TQFP (12 x 12)
P67/ASTB
P66/WAIT
P75/BUZ
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P40/AD0
P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15 VSS0 VDD0 P30 P31 P32/SDA0
Note 1
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
P74/PCL
P65/WR
P64/RD
P71/TI01 P70/TI00/TO0 P03/INTP3/ADTRG P02/INTP2 P01/INTP1 P00/INTP0 VSS1 X1 X2 VPP XT1 XT2 RESET AVDD AVREF P10/ANI0
10 11 12 13 14 15
P33/SCL0Note 1 P34/SI31
Note 2
P35/SO31Note 2
16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P36/SCK31Note 2
AVSS
VDD1
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
P21/SO30
P22/SCK30
P23/RxD0
P24/TxD0
Notes 1. 2.
SDA0 and SCL0 are incorporated only in the PD78F0034BY, 78F0034BY(A) Subseries. SI31, SO31, and SCK31 are incorporated only in the PD78F0034B, 78F0034B(A) Subseries.
Cautions 1. Connect the VPP pin directly to VSS0 or VSS1 in normal operation mode. 2. Connect the AVSS pin to VSS0. Remark When the PD78F0034B, 78F0034BY, 78F0034B(A), and 78F0034BY(A) are used in application fields that require reduction of the noise generated from inside the microcontroller, the implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended.
P25/ASCK0
P11/ANI1
P20/SI30
Data Sheet U16369EJ1V0DS
9
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
* 73-pin plastic FBGA (9 x 9)
Top View 9 8 7 6 5 4 3 2 1 ABCDEFGHJ JHGFEDCBA Bottom View
Index mark
Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 Pin Name NC P46/AD6 P44/AD4 P41/AD1 P67/ASTB P65/WR P74/PCL NC NC P51/A9 P47/AD7 P43/AD3 P40/AD0 P66/WAIT P75/BUZ P72/TI50/TO51 P71/TI01 P70/TI00/TO0 Pin No. C1 C2 C3 C4 C5 C6 C7 C8 C9 D1 D2 D3 D4 D5 D6 D7 D8 D9 Pin Name P52/A10 P53/A11 P45/AD5 P42/AD2 P64/RD P73/TI51/TO51 P03/INTP3/ADTRG P01/INTP1 VSS1 P55/A13 P56/A14 P50/A8 NC - - P02/INTP2 VPP X1 Pin No. E1 E2 E3 E4 E5 E6 E7 E8 E9 F1 F2 F3 F4 F5 F6 F7 F8 F9 Pin Name P57/A15 VDD0 P54/A12 - - - P00/INTP0 XT1 X2 P30 P31 VSS0 - - - P14/ANI4 RESET XT2 Pin No. G1 G2 G3 G4 G5 G6 G7 G8 G9 H1 H2 H3 H4 H5 H6 H7 H8 H9 Pin Name P33/SCL0Note 1 P32/SDA0Note 1 P20/SI30 P21/SO30 P24/TxD0 VDD1 P16/ANI6 AVDD NC P34/SI31Note 2 P35/SO31Note 2 P23/RxD0 P22/SCK30 AVSS P15/ANI5 P11/ANI1 P10/ANI0 AVREF Pin No. J1 J2 J3 J4 J5 J6 J7 J8 J9 Pin Name NC P36/SCK31Note 2 NC P25/ASCK0 NC P17/ANI7 P12/ANI2 P13/ANI3 NC
Notes 1. SDA0 and SCL0 are incorporated only in the PD78F0034BY Subseries. 2. SI31, SO31, and SCK31 are incorporated only in the PD78F0034B Subseries. Cautions 1. Connect the VPP pin directly to VSS0 or VSS1 in normal operation mode. 2. Connect the AVSS pin to VSS0. Remarks 1. When the PD78F0034B, 78F0034BY, 78F0034B(A), and 78F0034BY(A) are used in application fields that require reduction of the noise generated from inside the microcontroller, the implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended. 2. The special grade version of the 73-pin plastic FBGA (9 x 9) is not provided.
10
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
A8 to A15: AD0 to AD7: ADTRG: ANI0 to ANI7: ASCK0: ASTB: AVDD: AVREF: AVSS: BUZ: INTP0 to INTP3: NC: P00 to P03: P10 to P17: P20 to P25: P30 to P36: P40 to P47: P50 to P57: P64 to P67: Address bus Address/data bus AD trigger input Analog input Asynchronous serial clock Address strobe Analog power supply Analog reference voltage Analog ground Buzzer clock External interrupt input No connection Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 P70 to P75: PCL: RD: RESET: RxD0: SDA0: SI30, SI31: SO30, SO31: TO0, TO50, TO51: TxD0: VDD0, VDD1: VPP: VSS0, VSS1: WAIT: WR: X1, X2: XT1, XT2: Port 7 Programmable clock Read strobe Reset Receive data Serial data Serial input Serial output Timer output Transmit data Power supply Programming power supply Ground Wait Write strobe Crystal (main system clock) Crystal (subsystem clock)
SCK30, SCK31, SCL0: Serial clock
TI00, TI01, TI50, TI51: Timer input
Data Sheet U16369EJ1V0DS
11
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
2. BLOCK DIAGRAM
TI00/TO0/P70 TI01/P71 TI50/TO50/P72 TI51/TO51/P73
16-bit timer/ event counter 8-bit timer/ event counter 50 8-bit timer/ event counter 51 Watchdog timer Watch timer
Port 0
P00 to P03
Port 1
P10 to P17
Port 2
P20 to P25
Port 3 Flash memory (32 KB)
P30 to P36
SI30/P20 SO30/P21 SCK30/P22 SI31/P34 SO31/P35 SCK31/P36 RxD0/P23 TxD0/P24 ASCK0/P25 SDA0/P32 SCL0/P33 ANI0/P10 to ANI7/P17 AVDD AVSS AVREF INTP0/P00 to INTP3/P03 BUZ/P75 PCL/P74
78K/0 CPU core Serial interface 30
Port 4
P40 to P47
Port 5
P50 to P57
Serial interface 31Note 1 RAM (1,024 bytes)
Port 6
P64 to P67
Port 7
P70 to P75 AD0/P40 to AD7/P47 A8/P50 to A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET X1
UART0
I2C busNote 2
External access
A/D converter
Interrupt control Buzzer output Clock output control
System control
X2 XT1 XT2
VDD0 VDD1 VSS0 VSS1 VPP
Notes 1. 2.
Incorporated only in the PD78F0034B and 78F0034B(A) Incorporated only in the PD78F0034BY and 78F0034BY(A)
12
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
Pin Name I/O Function After Reset Alternate Function INTP0 INTP1 INTP2 INTP3/ADTRG Input Port 1 8-bit input-only port. Port 2 6-bit I/O port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by software. Input ANI0 to ANI7
P00 P01 P02 P03 P10 to P17
I/O
Port 0 4-bit I/O port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by software.
Input
P20 P21 P22 P23 P24 P25 P30 P31 P32 P33 P34 P35 P36 P40 to P47
I/O
Input
SI30 SO30 SCK30 RxD0 TxD0 ASCK0
I/O
Port 3 7-bit I/O port. Input/output can be specified in 1-bit units.
N-ch open-drain I/O port. LEDs can be driven directly.
Input
-
SDA0Note 1 SCL0Note 1 An on-chip pull-up resistor can be specified by software. SI31Note 2 SO31Note 2 SCK31Note 2
I/O
Port 4 8-bit I/O port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by software. Interrupt request flag KRIF is set to 1 by falling edge detection. Port 5 8-bit I/O port. LEDs can be driven directly. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by software. Port 6 4-bit I/O port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by software.
Input
AD0 to AD7
P50 to P57
I/O
Input
A8 to A15
P64 P65 P66 P67
I/O
Input
RD WR WAIT ASTB
Notes 1. 2.
SDA0 and SCL0 are incorporated only in the PD78F0034BY and 78F0034BY(A). SI31, SO31, and SCK31 are incorporated only in the PD78F0034B and 78F0034B(A).
Data Sheet U16369EJ1V0DS
13
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
3.1 Port Pins (2/2)
Pin Name I/O Function After Reset Alternate Function TI00/TO0 TI01 TI50/TO50 TI51/TO51 PCL BUZ
P70 P71 P72 P73 P74 P75
I/O
Port 7 6-bit I/O port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by software.
Input
3.2 Non-Port Pins (1/2)
Pin Name I/O Function After Reset Alternate Function P00 P01 P02 P03/ADTRG Input Serial interface serial data input. Input P20 P34 I/O Output Serial interface serial data input/output Serial interface serial data output. Input Input P32 P21 P35 I/O Serial interface serial clock input/output. Input P22 P36 P33 Input Output Input Input Serial data input for asynchronous serial interface. Serial data output for asynchronous serial interface. Serial clock input for asynchronous serial interface. External count clock input to 16-bit timer/event counter 0. Capture trigger signal input to capture register 01 (CR01) of 16-bit timer/ event counter 0. Capture trigger signal input to capture register 00 (CR00) of 16-bit timer/ event counter 0. External count clock input to 8-bit timer/event counter 50. External count clock input to 8-bit timer/event counter 51. Output 16-bit timer/event counter 0 output. 8-bit timer/event counter 50 output (shared with 8-bit PWM output). 8-bit timer/event counter 51 output (shared with 8-bit PWM output). Output Output I/O Clock output (for trimming of main system clock and subsystem clock). Buzzer output. Lower address/data bus for extending memory externally. Input Input Input Input Input Input Input Input Input P23 P24 P25 P70/TO0
INTP0 INTP1 INTP2 INTP3 SI30 SI31Note 1 SDA0Note 2 SO30 SO31Note 1 SCK30 SCK31Note 1 SCL0Note 2 RxD0 TxD0 ASCK0 TI00
Input
External interrupt request input by which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified.
Input
TI01
P71
TI50 TI51 TO0 TO50 TO51 PCL BUZ AD0 to AD7
P72/TO50 P73/TO51 P70/TI00 P72/TI50 P73/TI51 P74 P75 P40 to P47
Notes 1. 2.
SI31, SO31, and SCK31 are incorporated only in the PD78F0034B and 78F0034B(A). SDA0 and SCL0 are incorporated only in the PD78F0034BY and 78F0034BY(A).
14
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
3.2 Non-Port Pins (2/2)
Pin Name I/O Function After Reset Alternate Function P50 to P57 P64 P65 Input Input P66 P67
A8 to A15 RD WR WAIT ASTB
Output Output
Higher address bus for extending memory externally. Strobe signal output for read operation of external memory. Strobe signal output for write operation of external memory.
Input Input
Input Output
Inserting wait for accessing external memory. Strobe output which externally latches address information output to ports 4 and 5 to access external memory. A/D converter analog input. A/D converter trigger signal input. A/D converter reference voltage input. A/D converter analog power supply. Set the voltage equal to VDD0 or VDD1. A/D converter ground potential. Set the voltage equal to VSS0 or VSS1. System reset input. Connecting crystal resonator for main system clock oscillation.
ANI0 to ANI7 ADTRG AVREF AVDD
Input Input Input -
Input Input - -
P10 to P17 P03/INTP3 - -
AVSS
-
-
-
RESET X1 X2 XT1 XT2 VDD0 VSS0 VDD1 VSS1 VPP
Note
Input Input - Input - - - - - -
- - -
- - - - - - - - - -
Connecting crystal resonator for subsystem clock oscillation.
- -
Positive power supply voltage for ports. Ground potential of ports. Positive power supply (except ports). Ground potential (except ports). Applying high-voltage for program write/verify. Connect to VSS0 or VSS1 in normal operation mode. Not internally connected. Leave open.
- - - - -
NC
-
-
-
Note
NC is incorporated only in the 73-pin plastic FBGA.
Data Sheet U16369EJ1V0DS
15
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the input/output configuration of each type, refer to Figure 3-1 . Table 3-1. Types of Pin I/O Circuits (1/2)
Pin Name P00/INTP0 P01/INTP1 P02/INTP2 P03/INTP3/ADTRG P10/ANI0 to P17/ANI7 P20/SI30 P21/SO30 P22/SCK30 P23/RxD0 P24/TxD0 P25/ASCK0 P30, P31 P32/SDA0Note 1 P33/SCL0Note 1 P34/SI31Note 2 P35/SO31Note 2 P36/SCK31Note 2 P40/AD0 to P47/AD7 8-C 5-H 8-C 5-H Input: Independently connect to VDD0, VDD1, VSS0 or VSS1 via a resistor. Output: Leave open. Input: Independently connect to VDD0 or VDD1 via a resistor. Output: Leave open. Input: Independently connect to VDD0, VDD1, VSS0, or VSS1 via a resistor. Output: Leave open. 5-H 8-C 13-P 13-R Input: Directly connect to VSS0 or VSS1. Output: Leave open at low-level output. 25 8-C 5-H 8-C Input I/O Directly connect to VDD0, VDD1, VSS0, or VSS1. Input: Independently connect to VDD0, VDD1, VSS0, or VSS1 via a resistor. Output: Leave open. I/O Circuit Type 8-C I/O I/O Recommended Connection of Unused Pins Input: Independently connect to VSS0 or VSS1 via a via a resistor. Output: Leave open.
P50/A8 to P57/A15 P64/RD P65/WR P66/WAIT P67/ASTB P70/TI00/TO0 P71/TI01 P72/TI50/TO50 P73/TI51/TO51 P74/PCL P75/BUZ
5-H
8-C
5-H
Notes 1. 2.
SDA0 and SCL0 are incorporated only in the PD78F0034BY and 78F0034BY(A). SI31, SO31, and SCK31 are incorporated only in the PD78F0034B and 78F0034B(A).
16
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Table 3-1. Types of Pin I/O Circuits (2/2)
Pin Name RESET XT1 XT2 AVDD AVREF AVSS VPP Connect to VSS0 or VSS1. - I/O Circuit Type 2 16 - I/O Input Recommended Connection of Unused Pins - Directly connect to VDD0 or VDD1. Leave open. Directly connect to VDD0 or VDD1. Directly connect to VSS0 or VSS1.
Data Sheet U16369EJ1V0DS
17
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Figure 3-1. Pin I/O Circuits
TYPE 2 TYPE 13-R IN/OUT Data Output disable IN VSS0 Schmitt-triggered input with hysteresis characteristics N-ch
TYPE 5-H
VDD0
TYPE 16 Feedback cut-off
Pullup enable Data
P-ch VDD0 P-ch IN/OUT
P-ch
Output disable Input enable TYPE 8-C
N-ch VSS0 XT1 XT2
TYPE 25 VDD0 P-ch P-ch VDD0 P-ch IN/OUT Comparator
+ -
Pullup enable Data
N-ch VSS0 VREF (threshold voltage)
IN
Output disable
N-ch VSS0
Input enable
TYPE 13-P Data Output disable N-ch VSS0
IN/OUT
Input enable
18
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
4. DIFFERENCES BETWEEN PD78F0034B, 78F0034BY, AND MASK ROM VERSIONS
The PD78F0034B and 78F0034BY are products provided with a flash memory which enables writing, erasing, and rewriting of programs with device mounted on the target system. The functions of the PD78F0034B and 78F0034BY (except the functions specified for flash memory) can be made the same as those of the mask ROM versions by setting the memory size switching register (IMS). Tables 4-1 and 4-2 show the differences between the PD78F0034B, 78F0034BY and the mask ROM versions. Table 4-1. Differences Between PD78F0034B and Mask ROM Versions
Item
PD78F0034B
Mask ROM Versions
PD780034A Subseries
Internal ROM structure Internal ROM capacity Flash memory 32 KB Mask ROM
PD780024A SubseriesNote PD780021A: PD780022A: PD780023A: PD780024A: PD780021A: PD780022A: PD780023A: PD780024A:
PD780031A: PD780032A: PD780033A: PD780034A: PD780031A: PD780032A: PD780033A: PD780034A:
8 KB 16 KB 24 KB 32 KB 512 bytes 512 bytes 1,024 bytes 1,024 bytes
8 KB 16 KB 24 KB 32 KB 512 bytes 512 bytes 1,024 bytes 1,024 bytes
Internal high-speed RAM capacity
1,024 bytes
Minimum instruction execution time
Minimum instruction execution time variable function incorporated
When main system clock is selected 0.166 s/0.333 s/0.666 s/1.33 s/2.66 s (@ 12 MHz operation, VDD = 4.5 to 5.5 V) 0.238 s/0.48 s/0.95 s/1.91 s/3.81 s (@ 8.38 MHz operation, VDD = 4.0 to 5.5 V) When subsystem clock is selected Clock output 122 s (32.768 kHz) * 93.75 kHz, 187.5 kHz, 375 kHz, 750 kHz, 1.25 MHz, 3 MHz, 6 MHz, 12 MHz (@ 12 MHz operation with main system clock) * 32.768 kHz (@ 32.768 kHz operation with subsystem clock) * 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz (@ 8.38 MHz operation with main system clock) * 32.768 kHz (@ 32.768 kHz operation with subsystem clock) 1.46 kHz, 2.93 kHz, 5.86 kHz, 11.7 kHz (@ 12 MHz operation with main system clock) * 1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz (@ 8.38 MHz operation with main system clock) 10 bits Not available Not provided Provided Available Provided Not provided 8 bits
Buzzer output
A/D converter resolution Mask option specification of on-chip pull-up resistor for pins P30 to P33 IC pin VPP pin Electrical specifications, recommended soldering conditions
Refer to the data sheet of individual products.
Note
The PD78F0034B can be used as the flash memory version of the PD780024A Subseries.
Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass producing it with the mask ROM version, be sure to conduct sufficient evaluations on the commercial samples (CS) (not engineering samples (ES)) of the mask ROM versions.
Data Sheet U16369EJ1V0DS
19
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Table 4-2. Differences Between PD78F0034BY and Mask ROM Versions
Item
PD78F0034BY
Mask ROM Versions
PD780034AY Subseries
Internal ROM structure Internal ROM capacity Flash memory 32 KB Mask ROM
PD780024AY SubseriesNote
PD780031AY: PD780032AY: PD780033AY: PD780034AY:
8 KB 16 KB 24 KB 32 KB
PD780021AY: PD780022AY: PD780023AY: PD780024AY:
8 KB 16 KB 24 KB 32 KB
Internal high-speed RAM capacity
1,024 bytes
PD780031AY: 512 bytes PD780032AY: 512 bytes PD780033AY: 1,024 bytes PD780034AY: 1,024 bytes
PD780021AY: 512 bytes PD780022AY: 512 bytes PD780023AY: 1,024 bytes PD780024AY: 1,024 bytes
Minimum instruction execution time
Minimum instruction execution time variable function incorporated
When main system clock is selected 0.238 s/0.48 s/0.95 s/1.91 s/3.81 s (operation at 8.38 MHz, VDD = 4.0 to 5.5 V) When subsystem clock is selected Clock output 122 s (32.768 kHz) * 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz (@ 8.38 MHz operation with main system clock) * 32.768 kHz (@ 32.768 kHz operation with subsystem clock) Buzzer output 1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz (@ 8.38 MHz operation with main system clock) 10 bits Not available Available 8 bits
A/D converter resolution Mask option specification of on-chip pull-up resistor for pins P30 and P31 IC pin VPP pin Electrical specifications, recommended soldering conditions
Not provided Provided
Provided Not provided
Refer to the data sheet of individual products.
Note
The PD78F0034BY can be used as the flash memory version of the PD780024AY Subseries.
Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass producing it with the mask ROM version, be sure to conduct sufficient evaluations on the commercial samples (CS) (not engineering samples (ES)) of the mask ROM versions.
20
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
5. DIFFERENCES BETWEEN PD78F0034B, 78F0034BY AND PD78F0034A, 78F0034AY
Table 5-1 shows the differences between the PD78F0034B and PD78F0034A, and Table 5-2 shows differences between the PD78F0034BY and 78F0034AY. Table 5-1. Differences Between PD78F0034B and PD78F0034A
Item Guaranteed operating speed (operating frequency) 4.5 to 5.5 V 4.0 to 5.5 V 3.0 to 5.5 V 2.7 to 5.5 V 1.8 to 5.5 V Maximum instruction execution time When main system clock is selected
PD78F0034B
12 MHz (0.166 s) 8.38 MHz (0.238 s) 8.38 MHz (0.238 s) 5 MHz (0.4 s) 1.25 MHz (1.6 s)
PD78F0034A
8.38 MHz (0.238 s) 8.38 MHz (0.238 s) 5 MHz (0.4 s) 5 MHz (0.4 s) 1.25 MHz (1.6 s)
Minimum instruction execution time variable function incorporated 0.166 s/0.333 s/0.666 s/1.33 s/2.66 s (@ 12 MHz operation, VDD = 4.5 to 5.5 V) 122 s (32.768 kHz) * 93.75 kHz, 187.5 kHz, 375 kHz, 750 kHz, 1.25 MHz, 3 MHz, 6 MHz, 12 MHz (@ 12 MHz operation with main system clock) * 32.768 kHz (@ 32.768 kHz operation with subsystem clock) * 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz (@ 8.38 MHz operation with main system clock) * 32.768 kHz (@ 32.768 kHz operation with subsystem clock) 1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz (@ 8.38 MHz operation with main system clock) * 3-wire serial I/O: 2 channels * UART: 1 channel * Pseudo 3-wire serial I/O: 1 channel
Note
0.238 s/0.48 s/0.95 s/1.91 s/3.81 s (@ 8.38 MHz operation, VDD = 4.0 to 5.5 V)
When subsystem clock is selected Clock output
Buzzer output
1.46 kHz, 2.93 kHz, 5.86 kHz, 11.7 kHz (@ 12 MHz operation with main system clock) * 3-wire serial I/O: 2 channels * UART: 1 channel * Pseudo 3-wire serial I/O: 1 channel
Note
Communication mode of flash memory programming
Electrical specifications, recommended soldering conditions
Refer to the data sheet of individual products.
Note
The PD78F0034B can use one channel (serial interface SIO30) as a handshake mode. The PD78F0034A cannot use a handshake mode.
Remark The operating frequency ratings of the PD78F0034B and the expanded-specification products of the mask ROM versions of the PD780024A, 780034A Subseries are the same. The operating frequency ratings of the PD78F0034A and the conventional products of the mask ROM versions of the
PD780024A, 780034A Subseries are the same.
Data Sheet U16369EJ1V0DS
21
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Table 5-2. Differences Between PD78F0034BY and PD78F0034AY
Item Guaranteed operating speed (operating frequency) 4.5 to 5.5 V 4.0 to 5.5 V 3.0 to 5.5 V 2.7 to 5.5 V 1.8 to 5.5 V Maximum instruction execution time When main system clock is selected
PD78F0034BY
8.38 MHz (0.238 s) 8.38 MHz (0.238 s) 5 MHz (0.4 s) 5 MHz (0.4 s) 1.25 MHz (1.6 s)
PD78F0034AY
Minimum instruction execution time variable function incorporated 0.238 s/0.48 s/0.95 s/1.91 s/3.81 s (@ 8.38 MHz operation, VDD = 4.0 to 5.5 V) 122 s (32.768 kHz) * 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz (@ 8.38 MHz operation with main system clock) * 32.768 kHz (@ 32.768 kHz operation with subsystem clock) 1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz (@ 8.38 MHz operation with main system clock) * 3-wire serial I/O: 2 channels * UART: 1 channel * Pseudo 3-wire serial I/O: 1 channel
Note
When subsystem clock is selected Clock output
Buzzer output
Communication mode of flash memory programming
* 3-wire serial I/O: 2 channels * UART: 1 channel * Pseudo 3-wire serial I/O: 1 channel
Note
Electrical specifications, recommended soldering conditions
Refer to the data sheet of individual products.
Note
The PD78F0034BY can use one channel (serial interface SIO30) as a handshake mode. The PD78F0034AY cannot use a handshake mode.
Remark The operating frequency ratings of the PD78F0034BY, 78F0034AY and the mask ROM versions of the
PD780024AY, 780034AY Subseries are the same.
6. DIFFERENCES BETWEEN PD78F0034B, 78F0034BY AND PD78F0034B(A), 78F0034BY(A)
The PD78F0034(A) and 78F0034BY(A) are products to which a quality assurance program more stringent than that used for the PD780034B and 780034BY (standard models) is applied (NEC Electronics classifies these products as "special" quality grade models). The PD78F0034B, 78F0034BY and PD78F0034B(A), 78F0034BY(A) only differ in the quality grade; there are no differences in functions and electrical specifications. Table 6-1. Differences Between PD78F0034B, 78F0034BY and PD78F0034B(A), 78F0034BY(A)
Item Quality grade Functions and electrical specifications
PD78F0034B, 78F0034BY
Standard No differences.
PD78F0034B(A), 78F0034BY(A)
Special
22
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
7. MEMORY SIZE SWITCHING REGISTER (IMS)
IMS is a register that is set by software and is used to specify a part of the internal memory that is not to be used. By setting memory size switching register (IMS), the internal memory of the PD78F0034B, 78F0034BY, 78F0034B(A), and 78F0034BY(A) can be mapped identically to that of a mask ROM version. IMS is set with an 8-bit memory manipulation instruction. RESET input sets IMS to CFH. Caution The initial value of IMS is setting disabled (CFH). Be sure to set C8H or the value of the target mask ROM version at the moment of initial setting. Figure 7-1. Format of Memory Size Switching Register
7 IMS 6 5 4 0 3 2 1 0 Address FFF0H After reset CFH R/W R/W
RAM2 RAM1 RAM0
ROM3 ROM2 ROM1 ROM0
ROM3 ROM2 ROM1 ROM0 Selection of Internal ROM Capacity 0 0 0 1 0 1 1 0 1 0 1 0 0 0 0 0 8 KB 16 KB 24 KB 32 KB Setting prohibited
Other than above
RAM2 RAM1 RAM0 Selection of Internal High-Speed RAM Capacity 0 1 1 1 0 0 512 bytes 1,024 bytes Setting prohibited
Other than above
Table 7-1 shows the IMS set value to make the memory mapping the same as those of mask ROM versions. Table 7-1. Set Value of Memory Size Switching Register
Target Mask ROM Versions IMS Set Value 42H 44H C6H C8H
PD780021A, 780021AY, 780031A, 780031AY PD780022A, 780022AY, 780032A, 780032AY PD780023A, 780023AY, 780033A, 780033AY PD780024A, 780024AY, 780034A, 780034AY
Data Sheet U16369EJ1V0DS
23
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
8. FLASH MEMORY PROGRAMMING
Writing to flash memory can be performed without removing the memory from the target system (on board programming). Writing is performed with the dedicated flash programmer (Flashpro III (part No.: FL-PR3 and PGFP3)/(Flashpro IV (part No.: FL-PR4 and PG-FP4)) connected to the host machine and the target system. Writing to flash memory can also be performed using flash memory writing adapter connected to Flashpro III/ Flashpro IV. Remark FL-PR3 and FL-PR4 are products of Naito Densei Machida Mfg. Co., Ltd. 8.1 Selection of Communication Mode Writing to a flash memory is performed using Flashpro III/Flashpro IV in a serial communication. Select one of the communication modes in Tables 8-1 and 8-2. The selection of the communication mode is made by using the format shown in Figure 8-1. Each communication mode is selected by the number of VPP pulses shown in Tables 8-1 and 8-2. Table 8-1. List of Communication Mode (PD78F0034B)
Communication Mode 3-wire serial I/O 2 Channels Pin Used SI30/P20 SO30/P21 SCK30/P22 SI31/P34 SO31/P35 SCK31/P36 SI30/P20 SO30/P21 SCK30/P22 HS/P25 UART 1 RxD0/P23 TxD0/P24 P72/TI50/TO50 (serial clock input) P71/TI01 (serial data output) P70/TI00/TO0 (serial data input) 8 0 VPP Pulses
1
3
Pseudo 3-wire serial I/O
1
12
Caution Be sure to select a communication mode using the number of VPP pulses shown in Table 8-1.
24
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Table 8-2. List of Communication Mode (PD78F0034BY)
Communication Mode 3-wire serial I/O 1 Channels Pin Used SI30/P20 SO30/P21 SCK30/P22 SI30/P20 SO30/P21 SCK30/P22 HS/P25 I2C bus 1 SDA0/P32 SCL0/P33 RxD0/P23 TxD0/P24 P72/TI50/TO50 (serial clock input) P71/TI01 (serial data output) P70/TI00/TO0 (serial data input) 0 VPP Pulses
3
4
UART
1
8
Pseudo 3-wire serial I/O
1
12
Caution Be sure to select a communication mode using the number of VPP pulses shown in Table 8-2. Figure 8-1. Format of Communication Mode Selection
VPP pulses 10 V VPP VDD 1 VSS VDD RESET VSS Flash write mode 2 n
Data Sheet U16369EJ1V0DS
25
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
8.2 Flash Memory Programming Functions Operations such as writing to flash memory are performed by various command/data transmission and reception operations according to the selected communication mode. Table 8-3 shows major functions of flash memory programming. Table 8-3. Major Functions of Flash Memory Programming
Function Reset Batch verify Batch erase Batch blank check High-speed write Description Used to stop write operation and detect transmission cycle. Compares the entire memory contents with the input data. Erases the entire memory contents. Checks the deletion status of the entire memory. Performs write to the flash memory based on the write start address and the number of data to be written (number of bytes). Performs continuous write based on the information input with high-speed write operation. Used to confirm the current operating mode and operation end. Sets the frequency of the resonator. Sets the memory erase time. Sets the communication rate for UART mode Sets standard/high-speed mode for I2C bus mode Outputs the device name and memory capacity, and device block information.
Continuous write Status Oscillation frequency setting Erase time setting Baud rate setting I2C mode setting Silicon signature read
8.3 Connection of Flashpro III/Flashpro IV The connection of Flashpro III/Flashpro IV and the PD78F0034B or 78F0034BY differs according to the communication mode (3-wire serial I/O, UART, pseudo 3-wire serial I/O, and I2C bus). The connection for each communication mode is shown in Figures 8-2 to 8-6, respectively. Figure 6-2. Connection of Flashpro III/Flashpro IV in 3-Wire Serial I/O Mode
PD78F0034B, PD78F0034BY
Flashpro III/Flashpro IV VPP VDD RESET SCK SO SI GND
VPP VDD0/VDD1/AVDD RESET SCK3n SI3n SO3n VSS0/VSS1/AVSS/AVREF
Remark PD78F0034B:
n = 0, 1
PD78F0034BY: n = 0
26
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Figure 8-3. Connection of Flashpro III in 3-Wire Serial I/O Mode (Using Handshake)
Flashpro III/Flashpro IV VPP VDD RESET SCK SO SI HS GND
PD78F0034B, PD78F0034BY VPP
VDD0/VDD1/AVDD RESET SCK30 SI30 SO30 HS (P25) VSS0/VSS1/AVSS/AVREF
Figure 8-4. Connection of Flashpro III/Flashpro IV for UART Mode
PD78F0034B, PD78F0034BY
VPP VDD0/VDD1/AVDD RESET RxD0 TxD0 VSS0/VSS1/AVSS/AVREF
Flashpro III/Flashpro IV VPP VDD RESET SO SI GND
Figure 8-5. Connection of Flashpro III/Flashpro IV for Pseudo 3-Wire Serial I/O Mode
Flashpro III/Flashpro IV VPP VDD RESET SCK SO SI GND
PD78F0034B, PD78F0034BY
VPP VDD0/VDD1/AVDD RESET P72 P70 P71
(serial clock input) (serial data input)
(serial data output)
VSS0/VSS1/AVSS/AVREF
Figure 8-6. Connection of Flashpro III/Flashpro IV for I2C Bus Mode (PD78F0034BY only)
Flashpro III/Flashpro IV VPP VDD RESET SO SI GND
PD78F0034BY
VPP VDD0/VDD1/AVDD RESET SCL0 SDA0 VSS0/VSS1/AVSS/AVREF
Data Sheet U16369EJ1V0DS
27
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
9. ELECTRICAL SPECIFICATIONS
9.1 PD78F0034B, 78F0034B(A) Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Symbol VDD VPP AVDD AVREF AVSS Input voltage VI1 P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, X1, X2, XT1, XT2, RESET P30 to P33 N-ch open drain
Note 2
Conditions
Ratings -0.3 to +6.5 -0.3 to +10.5 -0.3 to VDD + -0.3 to VDD + 0.3Note 1 0.3Note 1
Unit V V V V V V
-0.3 to +0.3 -0.3 to VDD + 0.3Note 1
VI2 Output voltage Analog input voltage VO VAN
-0.3 to +6.5 -0.3 to VDD + 0.3Note 1 0.3Note 1
V V V
P10 to P17
Analog input pin
AVSS -0.3 to AVREF + and -0.3 to VDD + 0.3Note 1 -10 -15
Output current, high
IOH
Per pin Total for P00 to P03, P40 to P47, P50 to P57, P64 to P67, P70 to P75 Total for P20 to P25, P30 to P36
mA mA
-15 20
mA mA
Output current, low
IOL
Per pin for P00 to P03, P20 to P25, P34 to P36, P40 to P47, P64 to P67, P70 to P75 Per pin for P30 to P33, P50 to P57 Total for P00 to P03, P40 to P47, P64 to P67, P70 to P75 Total for P20 to P25 Total for P30 to P36 Total for P50 to P57
30 50
mA mA
20 100 100 -40 to +85
mA mA mA C C
Operating ambient temperature Storage temperature
TA
During normal operation
Tstg
-40 to +125
Notes 1. 6.5 V or below (Note 2 is explained on the following page.) Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
28
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Notes 2. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. * When supply voltage rises VPP must exceed VDD 10 s or more after VDD has reached the lower-limit value (1.8 V) of the operating voltage range (see a in the figure below). * When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (1.8 V) of the operating voltage range of VDD (see b in the figure below).
VDD
1.8 V 0V a b
VPP 1.8 V 0V
Capacitance (TA = 25C, VDD = VSS = 0 V)
Parameter Input capacitance I/O capacitance Symbol CIN Conditions f = 1 MHz Unmeasured pins returned to 0 V. f = 1 MHz Unmeasured pins returned to 0 V. P00 to P03, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, P30 to P33 MIN. TYP. MAX. 15 Unit pF
CIO
15
pF
20
pF
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U16369EJ1V0DS
29
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Main System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator Ceramic resonator Recommended Circuit Parameter Oscillation Conditions 4.5 V VDD 5.5 V (fX)Note 1 3.0 V VDD < 4.5 V 1.8 V VDD < 3.0 V After VDD reaches timeNote 2 oscillation voltage range MIN. Crystal resonator
C2 C1 VPP X2 X1
MIN. 1.0 1.0 1.0
TYP.
MAX. 12.0 8.38 5.0 4
Unit MHz
VPP
X2
X1
frequency
C2
C1
Oscillation stabilization Oscillation frequency (fX)Note 1
ms
4.5 V VDD 5.5 V 3.0 V VDD < 4.5 V 1.8 V VDD < 3.0 V 4.0 V VDD 5.5 V 1.8 V VDD < 4.0 V 4.5 V VDD 5.5 V 3.0 V VDD < 4.5 V 1.8 V VDD < 3.0 V 4.5 V VDD 5.5 V 3.0 V VDD < 4.5 V 1.8 V VDD < 3.0 V
1.0 1.0 1.0
12.0 8.38 5.0 10 30
MHz
Oscillation stabilization timeNote 2 External clock X2 X1 X1 input frequency (fX)Note 1 X1 input high-/low-level width (tXH, tXL)
ms MHz
1.0 1.0 1.0 38 50 85
12.0 8.38 5.0 500 500 500
ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Remark For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
30
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator Crystal resonator Recommended Circuit
XT2 R2 C4 C3 XT1VPP
Parameter Oscillation frequency (fXT)Note 1 Oscillation stabilization timeNote 2 X1 input frequency (fXT)Note 1 X1 input high-/low-level width (tXTH, tXTL)
Conditions
MIN. 32
TYP. 32.768
MAX. 35
Unit kHz
4.0 V VDD 5.5 V 1.8 V VDD < 4.0 V 32
1.2
2 10 38.5
s
External clock
XT2
XT1
kHz
12
15
s
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after VDD reaches oscillator voltage MIN. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor to the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
Data Sheet U16369EJ1V0DS
31
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Output current, high Output current, low
Symbol IOH Per pin All pins IOL
Conditions
MIN.
TYP.
MAX. -1 -15 10
Unit mA mA mA
Per pin for P00 to P03, P20 to P25, P34 to P36, P40 to P47, P64 to P67, P70 to P75 Per pin for P30 to P33, P50 to P57 Total for P00 to P03, P40 to P47, P64 to P67, P70 to P75 Total for P20 to P25 Total for P30 to P36 Total for P50 to P57 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V
15 20 10 70 70 0.7VDD 0.8VDD 0.8VDD 0.85VDD 0.7VDD 0.8VDD VDD - 0.5 VDD - 0.2 0.8VDD 0.9VDD 0 0 0 0 0 0 0 0 0 0 0 VDD - 1.0 VDD - 0.5 VDD VDD VDD VDD 5.5 5.5 VDD VDD VDD VDD 0.3VDD 0.2VDD 0.2VDD 0.15VDD 0.3VDD 0.2VDD 0.1VDD 0.4 0.2 0.2VDD 0.1VDD VDD VDD 2.0 0.4 2.0 0.4
mA mA mA mA mA V V V V V V V V V V V V V V V V V V V V V V V V V V
Input voltage, high
VIH1
P10 to P17, P21, P24, P35, P40 to P47, P50 to P57, P64 to P67, P74, P75
VIH2
P00 to P03, P20, P22, P23, P25, P34, P36, P70 to P73, RESET
VIH3
P30 to P33 (N-ch open-drain)
VIH4
X1, X2
VIH5
XT1, XT2
4.0 V VDD 5.5 V 1.8 V VDD < 4.0 V
Input voltage, low
VIL1
P10 to P17, P21, P24, P35, P40 to P47, P50 to P57, P64 to P67, P74, P75
2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 4.0 V VDD 5.5 V 1.8 V VDD < 4.0 V
VIL2
P00 to P03, P20, P22, P23, P25, P34, P36, P70 to P73, RESET
VIL3
P30 to P33
VIL4
X1, X2
VIL5
XT1, XT2
Output voltage, high Output voltage, low
VOH1
4.0 V VDD 5.5 V, IOH = -1 mA 1.8 V VDD < 4.0 V, IOH = -100 A 4.0 V VDD 5.5 V, IOL = 15 mA
VOL1
P30 to P33 P50 to P57
P00 to P03, P20 to P25, P34 to P36, 4.0 V VDD 5.5 V, P40 to P47, P64 to P67, P70 to P75 VOL2 IOL = 400 A IOL = 1.6 mA
0.5
V
Remark
Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
32
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Input leakage current, high Symbol ILIH1 VIN = VDD Conditions P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, RESET X1, X2, XT1, XT2 VIN = 5.5 V VIN = 0 V P30 to P33 P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, RESET X1, X2, XT1, XT2 P30 to P33 VOUT = VDD MIN. TYP. MAX. 3 Unit
A
ILIH2 ILIH3 Input leakage current, low ILIL1
20 3 -3
A A A
ILIL2 ILIL3 Output leakage current, high Output leakage current, low Software pullup resistor ILOH
-20 -3 3
A A A A
k
ILOL
VOUT = 0 V
-3
R
VIN = 0 V, P00 to P03, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75
15
30
90
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U16369EJ1V0DS
33
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Power supply currentNote 1 Symbol IDD1Note 2 Conditions 12.0 MHz VDD = 5.0 V crystal oscillation operating mode 10%Note 3 When A/D converter is stopped When A/D converter is operatingNote 7 When A/D converter is stopped When A/D converter is operatingNote 7 VDD = 3.0 V + 10%Notes 3, 6 When A/D converter is stopped When A/D converter is operatingNote 7 5.00 MHz VDD = 3.0 V 10%Note 3 crystal oscillation operating mode VDD = 2.0 V 10%Note 4 When A/D converter is stopped When A/D converter is operatingNote 7 When A/D converter is stopped When A/D converter is operatingNote 7 IDD2 12.0 MHz VDD = 5.0 V 10%Note 3 crystal oscillation HALT mode 8.38 MHz VDD = 5.0 V 10%Note 3 crystal oscillation HALT mode When peripheral functions are stopped When peripheral functions are operating When peripheral functions are stopped When peripheral functions are operating VDD = 3.0 V + 10%Notes 3, 6 When peripheral functions are stopped When peripheral functions are operating 5.00 MHz VDD = 3.0 V 10%Note 3 crystal oscillation HALT mode VDD = 2.0 V 10%Note 4 When peripheral functions are stopped When peripheral functions are operating When peripheral functions are stopped When peripheral functions are operating
IDD3
MIN.
TYP. 16 17 10.5 11.5 7 8 4.5 5.5 1 2 2
MAX. 32 34 21 23 14 16 9 11 2 6 4 8
Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
8.38 MHz VDD = 5.0 V 10%Note 3 crystal oscillation operating mode
1.2
2.4 5
0.6
1.2 2.4
0.4
0.8 1.7
0.2
0.4 1.1
32.768 kHz crystal oscillation operating modeNote 5
VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10%
115 95 75 30 6 2 0.1 0.05 0.05
230 190 150 60 18 10 30 10 10
A A A A A A A A A
IDD4
32.768 kHz crystal oscillation HALT modeNote 5
IDD5
XT1 = VDD STOP mode When feedback resistor is not used
34
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Notes 1. Total current through the internal power supply (VDD0, VDD1) (except the current through pull-up resistors of ports). 2. IDD1 includes the peripheral operation current. 3. When the processor clock control register (PCC) is set to 00H. 4. When PCC is set to 02H. 5. When main system clock operation is stopped. 6. The values show the specifications when VDD = 3.0 to 3.3 V. The value in the TYP. column show the specifications when VDD = 3.0 V. 7. Includes the current through the AVDD pin.
Data Sheet U16369EJ1V0DS
35
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
AC Characteristics (1) Basic Operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Cycle time (Min. instruction execution time) Symbol TCY Operating with main system clock Conditions 4.5 V VDD 5.5 V 3.0 V VDD 4.5 V 2.7 V VDD 3.0 V 1.8 V VDD 2.7 V Operating with subsystem clock TI00, TI01 input high-/low-level width TI50, TI51 input frequency TI50, TI51 input high-/low-level width Interrupt request input high-/lowlevel width RESET low-level width tRSL tINTH, tINTL INTP0 to INTP3, P40 to P47 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 1 2 10 20 tTIH5, tTIL5 fTI5 tTIH0, tTIL0 3.0 V VDD 5.5 V 2.7 V VDD < 3.0 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V MIN. 0.166 0.238 0.4 1.6 103.9Note 1 2/fsam+0.1Note 2 2/fsam+0.2Note 2 2/fsam+0.5Note 2 0 0 100 1.8 4 275 122 TYP. MAX. 16 16 16 16 125 Unit
s s s s s s s s
MHz kHz ns ns
s s s s
Notes 1. Value when the external clock is used. When a crystal resonator is used, it is 114 s (MIN.). 2. Selection of fsam = fX, fX/4, fX/64 is possible using bits 0 and 1 (PRM00, PRM01) of prescaler mode register 0 (PRM0). However, if the TI00 valid edge is selected as the count clock, the value becomes fsam = fX/8.
36
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
TCY vs. VDD (main system clock operation)
16.0 10.0
Cycle time TCY [ S]
5.0
Operation guaranteed range
2.0 1.6 1.0
0.4 0.238 0.166 0.1 0 1.0 1.8 2.0 2.7 3.0 4.0 4.5 5.0 5.5 6.0
Supply voltage VDD [V]
Data Sheet U16369EJ1V0DS
37
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(2) Read/write operation (TA = -40 to +85C, VDD = 4.0 to 5.5 V)
Parameter ASTB high-level width Address setup time Address hold time Input time from address to data Symbol tASTH tADS tADH tADD1 tADD2 Output time from RD to address Input time from RD to data tRDAD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 Input time from RD to WAIT tRDWT1 tRDWT2 Input time from WR to WAIT WAIT low-level width Write data setup time Write data hold time WR low-level width Delay time from ASTB to RD Delay time from ASTB to WR Delay time from RD to ASTB in external fetch Hold time from RD to address in external fetch Write data output time from RD Write data output time from WR Hold time from WR to address Delay time from WAIT to RD Delay time from WAIT to WR tRDWD tWRWD tWRADH tWTRD tWTWR 40 10 0.8tCY - 15 0.8tCY 0.8tCY 60 1.2tCY + 30 2.5tCY + 25 2.5tCY + 25 ns ns ns ns ns tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST (0.5 + n)tCY + 10 60 6 (1.5 + 2n)tCY - 15 6 2tCY - 15 0.8tCY - 15 1.2tCY 0 (1.5 + 2n)tCY - 33 (2.5 + 2n)tCY - 33 tCY - 43 tCY - 43 tCY - 25 (2 + 2n)tCY 0 Conditions MIN. 0.3tCY 20 6 (2 + 2n)tCY - 54 (3 + 2n)tCY - 60 100 (2 + 2n)tCY - 87 (3 + 2n)tCY - 93 MAX.
(1/3)
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRDADH
0.8tCY - 15
1.2tCY + 30
ns
Caution TCY can only be used when the MIN. value is 0.238 s. Remarks 1. tCY = TCY/4 2. n indicates the number of waits. 3. CL = 100 pF (CL is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB pins.)
38
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(2) Read/write operation (TA = -40 to +85C, VDD = 2.7 to 4.0 V)
Parameter ASTB high-level width Address setup time Address hold time Input time from address to data Symbol tASTH tADS tADH tADD1 tADD2 Output time from RD to address Input time from RD to data tRDAD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 Input time from RD to WAIT tRDWT1 tRDWT2 Input time from WR to WAIT WAIT low-level width Write data setup time Write data hold time WR low-level width Delay time from ASTB to RD Delay time from ASTB to WR Delay time from RD to ASTB in external fetch Hold time from RD to address in external fetch Write data output time from RD Write data output time from WR Hold time from WR to address Delay time from WAIT to RD Delay time from WAIT to WR tRDWD tWRWD tWRADH tWTRD tWTWR 40 20 0.8tCY - 30 0.5tCY 0.5tCY 120 1.2tCY + 60 2.5tCY + 50 2.5tCY + 50 ns ns ns ns ns tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST (0.5 + 2n)tCY + 10 60 10 (1.5 + 2n)tCY - 30 10 2tCY - 30 0.8tCY - 30 1.2tCY 0 (1.5 + 2n)tCY - 40 (2.5 + 2n)tCY - 40 tCY - 75 tCY - 60 tCY - 50 (2 + 2n)tCY 0 Conditions MIN. 0.3tCY 30 10 (2 + 2n)tCY - 108 (3 + 2n)tCY - 120 200 (2 + 2n)tCY - 148 (3 + 2n)tCY - 162 MAX.
(2/3)
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRDADH
0.8tCY - 30
1.2tCY + 60
ns
Caution TCY can only be used when the MIN. value is 0.4 s. Remarks 1. tCY = TCY/4 2. n indicates the number of waits. 3. CL = 100 pF (CL is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB pins.)
Data Sheet U16369EJ1V0DS
39
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(2) Read/write operation (TA = -40 to +85C, VDD = 1.8 to 2.7 V)
Parameter ASTB high-level width Address setup time Address hold time Input time from address to data Symbol tASTH tADS tADH tADD1 tADD2 Output time from RD to address Input time from RD to data tRDAD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 Input time from RD to WAIT tRDWT1 tRDWT2 Input time from WR to WAIT WAIT low-level width Write data setup time Write data hold time WR low-level width Delay time from ASTB to RD Delay time from ASTB to WR Delay time from RD to ASTB in external fetch Hold time from RD to address in external fetch Write data output time from RD Write data output time from WR Hold time from WR to address Delay time from WAIT to RD Delay time from WAIT to WR tRDWD tWRWD tWRADH tWTRD tWTWR 40 40 0.8tCY - 60 0.5tCY 0.5tCY 240 1.2tCY + 120 2.5tCY + 100 2.5tCY + 100 ns ns ns ns ns tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST (0.5 + 2n)tCY + 10 60 20 (1.5 + 2n)tCY - 60 20 2tCY - 60 0.8tCY - 60 1.2tCY 0 (1.5 + 2n)tCY - 92 (2.5 + 2n)tCY - 92 tCY - 350 tCY - 132 tCY - 100 (2 + 2n)tCY 0 Conditions MIN. 0.3tCY 120 20 (2 + 2n)tCY - 233 (3 + 2n)tCY - 240 400 (2 + 2n)tCY - 325 (3 + 2n)tCY - 332 MAX.
(3/3)
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRDADH
0.8tCY - 60
1.2tCY + 120
ns
Caution TCY can only be used when the MIN. value is 1.6 s. Remarks 1. tCY = TCY/4 2. n indicates the number of waits. 3. CL = 100 pF (CL is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB pins.)
40
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(3) Serial Interface (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (a) 3-wire serial I/O mode (SCK3n... Internal clock output)
Parameter SCK3n cycle time Symbol tKCY1 Conditions 4.5 V VDD 5.5 V 3.0 V VDD < 4.5 V 2.7 V VDD < 3.0 V 1.8 V VDD < 2.7 V SCK3n high-/ low-level width SI3n setup time (to SCK3n) tSIK1 tKH1, tKL1 3.0 V VDD 5.5 V 1.8 V VDD < 3.0 V 3.0 V VDD 5.5 V 2.7 V VDD < 3.0 V 1.8 V VDD < 2.7 V SI3n hold time (from SCK3n) Delay time from SCK3n to SO3n output tKSO1 tKSI1 4.5 V VDD 5.5 V 1.8 V VDD < 4.5 V C = 100 pF
Note
MIN. 666 954 1600 3200 tKCY1/2 - 50 tKCY1/2 - 100 100 150 300 300 400
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns ns ns ns
4.5 V VDD 5.5 V 1.8 V VDD < 4.5 V
200 300
ns ns
Note C is the load capacitance of the SCK3n and SO3n output lines. (b) 3-wire serial I/O mode (SCK3n... External clock input)
Parameter SCK3n cycle time Symbol tKCY2 Conditions 4.5 V VDD 5.5 V 3.0 V VDD < 4.5 V 2.7 V VDD < 3.0 V 1.8 V VDD < 2.7 V SCK3n high-/ low-level width tKH2, tKL2 4.5 V VDD 5.5 V 3.0 V VDD < 4.5 V 2.7 V VDD < 3.0 V 1.8 V VDD < 2.7 V SI3n setup time (to SCK3n) SI3n hold time (from SCK3n) Delay time from SCK3n to SO3n output tKSO2 tKSI2 4.5 V VDD 5.5 V 1.8 V VDD < 4.5 V C = 100 pF
Note
MIN. 666 800 1600 3200 333 400 800 1600 100
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns ns
tSIK2
300 400 200 300
ns ns ns ns
4.5 V VDD 5.5 V 1.8 V VDD < 4.5 V
Note C is the load capacitance of the SO3n output line.
Remark n = 0, 1
Data Sheet U16369EJ1V0DS
41
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(c) UART mode (dedicated baud-rate generator output)
Parameter Transfer rate Symbol Conditions 4.5 V VDD 5.5 V 3.0 V VDD < 4.5 V 2.7 V VDD < 3.0 V 1.8 V VDD < 2.7 V MIN. TYP. MAX. 187500 131031 78125 39063 Unit bps bps bps bps
(d) UART mode (external clock input)
Parameter ASCK0 cycle time Symbol tKCY3 Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V ASCK0 high-/low-level width tKH3, tKL3 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V Transfer rate 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V MIN. 800 1600 3200 400 800 1600 39063 19531 9766 TYP. MAX. Unit ns ns ns ns ns ns bps bps bps
(e) UART mode (infrared data transfer mode)
Parameter Transfer rate Allowable bit rate error Output pulse width Input pulse width Symbol Conditions 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 1.2 4/fX MIN. MAX. 131031 0.87 0.24/fbrNote Unit bps %
s s
Note fbr: Specified baud rate
42
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
A/D Converter Characteristics (TA = -40 to +85C, VDD = AVDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall errorNote 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 1.8 V AVREF < 2.7 V Conversion time tCONV 4.5 V AVDD 5.5 V 4.0 V AVDD < 4.5 V 2.7 V AVDD < 4.0 V 1.8 V AVDD < 2.7 V Zero-scale errorNotes 1, 2 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 1.8 V AVREF < 2.7 V Full-scale errorNotes 1, 2 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 1.8 V AVREF < 2.7 V Integral linearity errorNote 1 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 1.8 V AVREF < 2.7 V Differential linearity error 4.0 V AVREF 5.5 V 2.7 V AVREF 4.0 V 1.8 V AVREF < 2.7 V Analog input voltage Reference voltage Resistance between AVREF and AVSS VIAN AVREF RREF During A/D conversion operation 0 1.8 20 40 12 14 17 28 Symbol Conditions MIN. 10 TYP. 10 0.2 0.3 0.6 MAX. 10 0.4 0.6 1.2 96 96 96 96 0.4 0.6 1.2 0.4 0.6 1.2 2.5 4.5 8.5 1.5 2.0 3.5 AVREF AVDD Unit bit %FSR %FSR %FSR
s s s s
%FSR %FSR %FSR %FSR %FSR %FSR LSB LSB LSB LSB LSB LSB V V k
Notes 1. Excluding quantization error (1/2 LSB). 2. Indicated as a ratio to the full-scale value (%FSR). Remark When the PD78F0034B is used as an 8-bit resolution A/D converter, the specifications are the same as for the PD780024A Subseries A/D converter.
Data Sheet U16369EJ1V0DS
43
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Remark The impedance of the analog input pins is shown below. [Equivalent circuit]
R1 ANIn (n = 0 to 3) C1 C2 C3 R2
[Parameter value] (TYP.)
AVDD 2.7 V 4.5 V R1 12 k 4 k R2 8.0 k 2.7 k C1 3.0 pF 3.0 pF C2 3.0 pF 1.4 pF C3 2.0 pF 2.0 pF
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C)
Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillation stabilization wait time Symbol VDDDR IDDDR tSREL tWAIT Release by RESET Release by interrupt request Subsystem clock stop (XT1 = VDD) and feed-back resistor disconnected 0 217/fX Note Conditions MIN. 1.6 0.1 TYP. MAX. 5.5 30 Unit V
A s
s s
Note
Selection of 212/fX and 214/fX to 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS).
44
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Flash Memory Programming Characteristics (TA = +10 to +40C, VDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) (1) Write erase characteristics
Parameter Operating frequency Symbol fX Conditions 4.5 V VDD 5.5 V 3.0 V VDD < 4.5 V 1.8 V VDD < 3.0 V VPP supply voltage VDD supply current VPP2 IDD During flash memory programming When 10 MHz crystal VPP = VPP2 oscillation operating mode VDD = 5.0 V10% MIN. 1.0 1.0 1.0 9.7 10.0 TYP. MAX. 10.0 8.38 1.25 10.3 30 Unit MHz MHz MHz V mA
8.38 MHz crystal VDD = 5.0 V10% oscillation operating mode VPP supply current Step erase time
Note 1 Note 2
24 17 100 0.199 0.2 0.201 20 49.4 50 50.6 60 16 48 50 52 520 20
mA mA mA s s/chip ms Times Times
VDD = 3.0 V10%
IPP Ter Tera Twb Cwb Cerwb Twr
Note 6 Note 7
When VPP = VPP2
Overall erase time Writeback time
When step erase time = 0.2 s
Note 3
Number of writebacks per Note 4 writeback command Number of erases/writebacks Step write time
Note 5
When writeback time = 50 ms
s s
Times
Overall write time per word
Twrw Cerwb
When step write time = 50 s (1 word = 1 byte) 1 erase + 1 write after erase = 1 rewrite
48
Number of rewrites per chip
Notes 1. 2. 3. 4.
The recommended setting value of the step erase time is 0.2 s. The prewrite time before erasure and the erase verify time (writeback time) are not included. The recommended setting value of the writeback time is 50 ms. Writeback is executed once by the issuance of the writeback command. Therefore, the number of retries must be the maximum value minus the number of commands issued. 5. The recommended setting value of the step write time is 50 s. 6. The actual write time per word is 100 s longer. The internal verify time during or after a write is not included. 7. When a product is first written after shipment, "erase write" and "write only" are both taken as one rewrite. Example: P: Write, E: Erase Shipped product PEPEP: 3 rewrites Shipped product EPEPEP: 3 rewrites
(2) Serial write operation characteristics
Parameter VPP set time Set time from VDD to VPP Set time from VPP to RESET VPP count start time from RESET Count execution time VPP counter high-level width VPP counter low-level width VPP counter noise elimination width Symbol tPSRON tDRPSR tPSRRF tRFCF tCOUNT tCH tCL tNFW 8.0 8.0 40 Conditions VPP high voltage VPP high voltage VPP high voltage MIN. 1.0 10 1.0 1.0 2.0 TYP. MAX. Unit
s s s s
ms
s s
ns
Data Sheet U16369EJ1V0DS
45
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
9.2 PD78F0034BY, 78F0034BY(A) Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Symbol VDD VPP AVDD AVREF AVSS Input voltage VI1 P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, X1, X2, XT1, XT2, RESET VI2 Output voltage Analog input voltage VO VAN P10 to P17 Analog input pin P30 to P33 N-ch open drain -0.3 to +6.5 -0.3 to VDD + 0.3Note 1 0.3Note 1 V V V
Note 2
Conditions
Ratings -0.3 to +6.5 -0.3 to +10.5 -0.3 to VDD + -0.3 to VDD + 0.3Note 1 0.3Note 1
Unit V V V V V V
-0.3 to +0.3 -0.3 to VDD + 0.3Note 1
AVSS -0.3 to AVREF + and -0.3 to VDD + 0.3Note 1 -10 -15
Output current, high
IOH
Per pin Total for P00 to P03, P40 to P47, P50 to P57, P64 to P67, P70 to P75 Total for P20 to P25, P30 to P36
mA mA
-15 20
mA mA
Output current, low
IOL
Per pin for P00 to P03, P20 to P25, P34 to P36, P40 to P47, P64 to P67, P70 to P75 Per pin for P30 to P33, P50 to P57 Total for P00 to P03, P40 to P47, P64 to P67, P70 to P75 Total for P20 to P25 Total for P30 to P36 Total for P50 to P57
30 50
mA mA
20 100 100 -40 to +85
mA mA mA C C
Operating ambient temperature Storage temperature
TA
During normal operation
Tstg
-40 to +125
Notes 1. 6.5 V or below (Note 2 is explained on the following page.) Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
46
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Notes 2. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. * When supply voltage rises VPP must exceed VDD 10 s or more after VDD has reached the lower-limit value (1.8 V) of the operating voltage range (see a in the figure below). * When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (1.8 V) of the operating voltage range of VDD (see b in the figure below).
VDD
1.8 V 0V a b
VPP 1.8 V 0V
Capacitance (TA = 25C, VDD = VSS = 0 V)
Parameter Input capacitance I/O capacitance Symbol CIN Conditions f = 1 MHz Unmeasured pins returned to 0 V. f = 1 MHz Unmeasured pins returned to 0 V. P00 to P03, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, P30 to P33 MIN. TYP. MAX. 15 Unit pF
CIO
15
pF
20
pF
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U16369EJ1V0DS
47
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Main System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Recommended Circuit
VPP X2
R1
Resonator Ceramic resonator
Parameter Oscillation
Conditions 4.0 V VDD 5.5 V
MIN. 1.0 1.0
TYP.
MAX. 8.38 5.0 4
Unit MHz ms
X1
frequency Oscillation
(fX)Note 1
Note 2
1.8 V VDD < 4.0 V After VDD reaches oscillation voltage range MIN. 4.0 V VDD 5.5 V 1.8 V VDD < 4.0 V 4.0 V VDD 5.5 V 1.8 V VDD < 4.0 V 4.0 V VDD 5.5 V
C2
C1
stabilization time Crystal resonator
C2 C1
VPP
X2
X1
Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2
1.0 1.0
8.38 5.0 10 30
MHz ms
External clock
X2 X1
X1 input frequency X1 input high-/low-level width (tXH, tXL) (fX)Note 1
1.0 1.0 50 85
8.38 5.0 500 500
MHz ns
1.8 V VDD < 4.0 V 4.0 V VDD 5.5 V 1.8 V VDD < 4.0 V
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Remark For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacture for evaluation.
48
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator Crystal resonator Recommended Circuit
XT2 R2 C4 C3 XT1VPP
Parameter Oscillation frequency (fXT)Note 1 Oscillation stabilization timeNote 2 X1 input frequency (fXT)Note 1 X1 input high-/low-level width (tXTH, tXTL)
Conditions
MIN. 32
TYP. 32.768
MAX. 35
Unit kHz
4.0 V VDD 5.5 V 1.8 V VDD < 4.0 V 32
1.2
2 10 38.5
s
External clock
XT2
XT1
kHz
12
15
s
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after VDD reaches oscillator voltage MIN. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor to the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
Data Sheet U16369EJ1V0DS
49
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Output current, high Output current, low
Symbol IOH Per pin All pins IOL
Conditions
MIN.
TYP.
MAX. -1 -15 10
Unit mA mA mA
Per pin for P00 to P03, P20 to P25, P34 to P36, P40 to P47, P64 to P67, P70 to P75 Per pin for P30 to P33, P50 to P57 Total for P00 to P03, P40 to P47, P64 to P67, P70 to P75 Total for P20 to P25 Total for P30 to P36 Total for P50 to P57 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V
15 20 10 70 70 0.7VDD 0.8VDD 0.8VDD 0.85VDD 0.7VDD 0.8VDD VDD - 0.5 VDD - 0.2 0.8VDD 0.9VDD 0 0 0 0 0 0 0 0 0 0 0 VDD - 1.0 VDD - 0.5 VDD VDD VDD VDD 5.5 5.5 VDD VDD VDD VDD 0.3VDD 0.2VDD 0.2VDD 0.15VDD 0.3VDD 0.2VDD 0.1VDD 0.4 0.2 0.2VDD 0.1VDD VDD VDD 2.0 0.4 2.0 0.4
mA mA mA mA mA V V V V V V V V V V V V V V V V V V V V V V V V V V
Input voltage, high
VIH1
P10 to P17, P21, P24, P35, P40 to P47, P50 to P57, P64 to P67, P74, P75
VIH2
P00 to P03, P20, P22, P23, P25, P34, P36, P70 to P73, RESET
VIH3
P30 to P33 (N-ch open-drain)
VIH4
X1, X2
VIH5
XT1, XT2
4.0 V VDD 5.5 V 1.8 V VDD < 4.0 V
Input voltage, low
VIL1
P10 to P17, P21, P24, P35, P40 to P47, P50 to P57, P64 to P67, P74, P75
2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 4.0 V VDD 5.5 V 1.8 V VDD < 4.0 V
VIL2
P00 to P03, P20, P22, P23, P25, P34, P36, P70 to P73, RESET
VIL3
P30 to P33
VIL4
X1, X2
VIL5
XT1, XT2
Output voltage, high Output voltage, low
VOH1
4.0 V VDD 5.5 V, IOH = -1 mA 1.8 V VDD < 4.0 V, IOH = -100 A 4.0 V VDD 5.5 V, IOL = 15 mA
VOL1
P30 to P33 P50 to P57
P00 to P03, P20 to P25, P34 to P36, 4.0 V VDD 5.5 V, P40 to P47, P64 to P67, P70 to P75 VOL2 IOL = 400 A IOL = 1.6 mA
0.5
V
Remark
Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
50
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Input leakage current, high Symbol ILIH1 VIN = VDD Conditions P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, RESET X1, X2, XT1, XT2 VIN = 5.5 V VIN = 0 V P30 to P33 P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, RESET X1, X2, XT1, XT2 P30 to P33 VOUT = VDD MIN. TYP. MAX. 3 Unit
A
ILIH2 ILIH3 Input leakage current, low ILIL1
20 3 -3
A A A
ILIL2 ILIL3 Output leakage current, high Output leakage current, low Software pullup resistor R ILOH
-20 -3 3
A A A A
k
ILOL
VOUT = 0 V
-3
VIN = 0 V, P00 to P03, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75
15
30
90
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U16369EJ1V0DS
51
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Power supply currentNote 1 Symbol Conditions IDD1Note 2 8.38 MHz VDD = 5.0 V 10%Note 3 crystal oscillation operating mode 5.00 MHz VDD = 3.0 V 10%Note 3 crystal oscillation operating mode VDD = 2.0 V 10%Note 4 MIN. When A/D converter is stopped When A/D converter is operatingNote 6 When A/D converter is stopped When A/D converter is operatingNote 6 When A/D converter is stopped When A/D converter is operatingNote 6 IDD2 8.38 MHz VDD = 5.0 V 10%Note 3 crystal oscillation HALT mode 5.00 MHz VDD = 3.0 V 10%Note 3 crystal oscillation HALT mode VDD = 2.0 V 10%Note 4 When peripheral functions are stopped When peripheral functions are operating When peripheral functions are stopped When peripheral functions are operating When peripheral functions are stopped When peripheral functions are operating
IDD3
TYP. 10.5 11.5 4.5 5.5 1 2 1.2
MAX. 21 23 9 11 2 6 2.4 5
Unit mA mA mA mA mA mA mA mA mA mA mA mA
0.4
0.8 1.7
0.2
0.4 1.1
32.768 kHz crystal oscillation operating modeNote 5
VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10%
Note 2 Note 2 Note 3 Note 2 Note 2 Note 3 Note 2 Note 2 Note 3
115 95 75 30 6 2 0.1 0.05 0.05
230 190 150 60 18 10 30 10 10
A A A A A A A A A
IDD4
32.768 kHz crystal oscillation HALT modeNote 5
IDD5
XT1 = VDD STOP mode When feedback resistor is not used
Notes 1. Total current through the internal power supply (VDD0, VDD1) (except the current through pull-up resistors of ports). 2. IDD1 includes the peripheral operation current. 3. When the processor clock control register (PCC) is set to 00H. 4. When PCC is set to 02H. 5. When main system clock operation is stopped. 6. Includes the current through the AVDD pin.
52
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
AC Characteristics (1) Basic Operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Cycle time (Min. instruction execution time) Symbol TCY Operating with main system clock Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V Operating with subsystem clock TI00, TI01 input high-/low-level width TI50, TI51 input frequency TI50, TI51 input high-/low-level width Interrupt request input high-/lowlevel width RESET low-level width tRSL 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V tINTH, tINTL tTIH5, tTIL5 fTI5 tTIH0, tTIL0 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V INTP0 to INTP3, P40 to P47 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V MIN. 0.238 0.4 1.6 103.9Note 1 2/fsam+0.1Note 2 2/fsam+0.2Note 2 2/fsam+0.5Note 2 0 0 100 1.8 1 2 10 20 4 275 122 TYP. MAX. 16 16 16 125 Unit
s s s s s s s
MHz kHz ns ns
s s s s
Notes 1. Value when the external clock is used. When a crystal resonator is used, it is 114 s (MIN.). 2. Selection of fsam = fX, fX/4, fX/64 is possible using bits 0 and 1 (PRM00, PRM01) of prescaler mode register 0 (PRM0). However, if the TI00 valid edge is selected as the count clock, the value becomes fsam = fX/8.
Data Sheet U16369EJ1V0DS
53
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
TCY vs. VDD (main system clock operation)
16.0 10.0
Cycle time TCY [ S]
5.0
Operation guaranteed range
2.0 1.6 1.0
0.4 0.238 0.1 0 1.0 1.8 2.0 2.7 Supply voltage VDD [V] 3.0 4.0 5.0 5.5 6.0
54
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(2) Read/write operation (TA = -40 to +85C, VDD = 4.0 to 5.5 V)
Parameter ASTB high-level width Address setup time Address hold time Input time from address to data Symbol tASTH tADS tADH tADD1 tADD2 Output time from RD to address Input time from RD to data tRDAD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 Input time from RD to WAIT tRDWT1 tRDWT2 Input time from WR to WAIT WAIT low-level width Write data setup time Write data hold time WR low-level width Delay time from ASTB to RD Delay time from ASTB to WR Delay time from RD to ASTB in external fetch Hold time from RD to address in external fetch Write data output time from RD Write data output time from WR Hold time from WR to address Delay time from WAIT to RD Delay time from WAIT to WR tRDWD tWRWD tWRADH tWTRD tWTWR 40 10 0.8tCY - 15 0.8tCY 0.8tCY 60 1.2tCY + 30 2.5tCY + 25 2.5tCY + 25 ns ns ns ns ns tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST (0.5 + n)tCY + 10 60 6 (1.5 + 2n)tCY - 15 6 2tCY - 15 0.8tCY - 15 1.2tCY 0 (1.5 + 2n)tCY - 33 (2.5 + 2n)tCY - 33 tCY - 43 tCY - 43 tCY - 25 (2 + 2n)tCY 0 Conditions MIN. 0.3tCY 20 6 (2 + 2n)tCY - 54 (3 + 2n)tCY - 60 100 (2 + 2n)tCY - 87 (3 + 2n)tCY - 93 MAX.
(1/3)
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRDADH
0.8tCY - 15
1.2tCY + 30
ns
Caution TCY can only be used when the MIN. value is 0.238 s. Remarks 1. tCY = TCY/4 2. n indicates the number of waits. 3. CL = 100 pF (CL is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB pins.)
Data Sheet U16369EJ1V0DS
55
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(2) Read/write operation (TA = -40 to +85C, VDD = 2.7 to 4.0 V)
Parameter ASTB high-level width Address setup time Address hold time Input time from address to data Symbol tASTH tADS tADH tADD1 tADD2 Output time from RD to address Input time from RD to data tRDAD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 Input time from RD to WAIT tRDWT1 tRDWT2 Input time from WR to WAIT WAIT low-level width Write data setup time Write data hold time WR low-level width Delay time from ASTB to RD Delay time from ASTB to WR Delay time from RD to ASTB in external fetch Hold time from RD to address in external fetch Write data output time from RD Write data output time from WR Hold time from WR to address Delay time from WAIT to RD Delay time from WAIT to WR tRDADH 0.8tCY - 30 1.2tCY + 60 ns tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST (0.5 + 2n)tCY + 10 60 10 (1.5 + 2n)tCY - 30 10 2tCY - 30 0.8tCY - 30 1.2tCY 0 (1.5 + 2n)tCY - 40 (2.5 + 2n)tCY - 40 tCY - 75 tCY - 60 tCY - 50 (2 + 2n)tCY 0 Conditions MIN. 0.3tCY 30 10 (2 + 2n)tCY - 108 (3 + 2n)tCY - 120 200 (2 + 2n)tCY - 148 (3 + 2n)tCY - 162 MAX.
(2/3)
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRDWD tWRWD tWRADH tWTRD tWTWR
40 20 0.8tCY - 30 0.5tCY 0.5tCY 120 1.2tCY + 60 2.5tCY + 50 2.5tCY + 50
ns ns ns ns ns
Caution TCY can only be used when the MIN. value is 0.4 s. Remarks 1. tCY = TCY/4 2. n indicates the number of waits. 3. CL = 100 pF (CL is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB pins.)
56
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(2) Read/write operation (TA = -40 to +85C, VDD = 1.8 to 2.7 V)
Parameter ASTB high-level width Address setup time Address hold time Input time from address to data Symbol tASTH tADS tADH tADD1 tADD2 Output time from RD to address Input time from RD to data tRDAD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 Input time from RD to WAIT tRDWT1 tRDWT2 Input time from WR to WAIT WAIT low-level width Write data setup time Write data hold time WR low-level width Delay time from ASTB to RD Delay time from ASTB to WR Delay time from RD to ASTB in external fetch Hold time from RD to address in external fetch Write data output time from RD Write data output time from WR Hold time from WR to address Delay time from WAIT to RD Delay time from WAIT to WR tRDADH 0.8tCY - 60 1.2tCY + 120 ns tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST (0.5 + 2n)tCY + 10 60 20 (1.5 + 2n)tCY - 60 20 2tCY - 60 0.8tCY - 60 1.2tCY 0 (1.5 + 2n)tCY - 92 (2.5 + 2n)tCY - 92 tCY - 350 tCY - 132 tCY - 100 (2 + 2n)tCY 0 Conditions MIN. 0.3tCY 120 20 (2 + 2n)tCY - 233 (3 + 2n)tCY - 240 400 (2 + 2n)tCY - 325 (3 + 2n)tCY - 332 MAX.
(3/3)
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRDWD tWRWD tWRADH tWTRD tWTWR
40 40 0.8tCY - 60 0.5tCY 0.5tCY 240 1.2tCY + 120 2.5tCY + 100 2.5tCY + 100
ns ns ns ns ns
Caution TCY can only be used when the MIN. value is 1.6 s. Remarks 1. tCY = TCY/4 2. n indicates the number of waits. 3. CL = 100 pF (CL is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB pins.)
Data Sheet U16369EJ1V0DS
57
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(3) Serial Interface (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (a) 3-wire serial I/O mode (SCK30... Internal clock output)
Parameter SCK30 cycle time Symbol tKCY1 Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V SCK30 high-/ low-level width SI30 setup time (to SCK30) tSIK1 tKH1, tKL1 4.0 V VDD 5.5 V 1.8 V VDD < 4.0 V 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V SI3n hold time (from SCK30) Delay time from SCK30 to SO30 output tKSO1 C = 100 pF
Note
MIN. 954 1600 3200 tKCY1/2 - 50 tKCY1/2 - 100 100 150 300 400
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns ns
tKSI1
300
ns
Note C is the load capacitance of the SCK30 and SO30 output lines. (b) 3-wire serial I/O mode (SCK30... External clock input)
Parameter SCK30 cycle time Symbol tKCY2 Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V SCK30 high-/ low-level width tKH2, tKL2 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V SI30 setup time (to SCK30) SI30 hold time (from SCK30) Delay time from SCK30 to SO30 output tKSI2
Note
MIN. 800 1600 3200 400 800 1600 100
TYP.
MAX.
Unit ns ns ns ns ns ns ns
tSIK2
400
ns
tKSO2
C = 100 pF
300
ns
Note C is the load capacitance of the SO30 output line.
58
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(c) UART mode (dedicated baud-rate generator output)
Parameter Transfer rate Symbol Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V MIN. TYP. MAX. 131031 78125 39063 Unit bps bps bps
(d)
UART mode (external clock input)
Parameter Symbol tKCY3 Conditions 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V MIN. 800 1600 3200 400 800 1600 39063 19531 9766 TYP. MAX. Unit ns ns ns ns ns ns bps bps bps
ASCK0 cycle time
ASCK0 high-/low-level width
tKH3, tKL3
4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V 4.0 V VDD 5.5 V 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V
Transfer rate
(e) UART mode (infrared data transfer mode)
Parameter Transfer rate Allowable bit rate error Output pulse width Input pulse width Symbol Conditions 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 4.0 V VDD 5.5 V 1.2 4/fX MIN. MAX. 131031 0.87 0.24/fbrNote Unit bps %
s s
Note
fbr: Specified baud rate
Data Sheet U16369EJ1V0DS
59
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(f) I2C bus mode
Parameter Symbol Standard Mode MIN. SCL0 clock frequency Bus free time (between stop and start condition) Hold timeNote 1 SCL0 clock low-level width SCL0 clock high-level width Start/restart condition setup time Data hold time CBUS compatible master I2C bus Data setup time SDA0 and SCL0 signal rise time SDA0 and SCL0 signal fall time Stop condition setup time Spike pulse width controlled by input filter Capacitive load per each bus line tSU:DAT tR tF tSU:STO tSP Cb fCLK tBUF 0 4.7 MAX. 100 - High-Speed Mode MIN. 0 1.3 MAX. 400 - kHz Unit
s s s s s s s
ns ns ns
tHD:STA tLOW tHIGH tSU:STA tHD:DAT
4.0 4.7 4.0 4.7 5.0 0Note 2 250 - - 4.0 - -
- - - - - - - 1,000 300 - - 400
0.6 1.3 0.6 0.6 - 0Note 2 100Note 4 20 + 0.1CbNote 5 20 + 0.1CbNote 5 0.6 0 -
- - - - - 0.9Note 3 - 300 300 - 50 400
s
ns pF
Notes 1. In the start condition, the first clock pulse is generated after this hold time. 2. To fill in the undefined area of the SCL0 falling edge, it is necessary for the device to internally provide at least 300 ns of hold time for the SDA0 signal (which is VIHmin. of the SCL0 signal). 3. If the device does not extend the SCL0 signal low hold time (tLOW), only maximum data hold time tHD:DAT needs to be fulfilled. 4. The high-speed mode I2C bus is available in a standard mode I2C bus system. At this time, the conditions described below must be satisfied. * If the device does not extend the SCL0 signal low state hold time tSU:DAT 250 ns * If the device extends the SCL0 signal low state hold time Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU:DAT = 1,000 + 250 = 1,250 ns by standard mode I2C bus specification). 5. Cb: Total capacitance per one bus line (unit: pF)
60
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
A/D Converter Characteristics (TA = -40 to +85C, VDD = AVDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall errorNote 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 1.8 V AVREF < 2.7 V Conversion time tCONV 4.5 V AVDD 5.5 V 4.0 V AVDD < 4.5 V 2.7 V AVDD < 4.0 V 1.8 V AVDD < 2.7 V Zero-scale errorNotes 1, 2 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 1.8 V AVREF < 2.7 V Full-scale errorNotes 1, 2 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 1.8 V AVREF < 2.7 V Integral linearity errorNote 1 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 1.8 V AVREF < 2.7 V Differential linearity error 4.0 V AVREF 5.5 V 2.7 V AVREF 4.0 V 1.8 V AVREF < 2.7 V Analog input voltage Reference voltage Resistance between AVREF and AVSS VIAN AVREF RREF During A/D conversion operation 0 1.8 20 40 12 14 17 28 Symbol Conditions MIN. 10 TYP. 10 0.2 0.3 0.6 MAX. 10 0.4 0.6 1.2 96 96 96 96 0.4 0.6 1.2 0.4 0.6 1.2 2.5 4.5 8.5 1.5 2.0 3.5 AVREF AVDD Unit bit %FSR %FSR %FSR
s s s s
%FSR %FSR %FSR %FSR %FSR %FSR LSB LSB LSB LSB LSB LSB V V k
Notes 1. Excluding quantization error (1/2 LSB). 2. Indicated as a ratio to the full-scale value (%FSR). Remark When the PD78F0034BY is used as an 8-bit resolution A/D converter, the specifications are the same as for the PD780024AY Subseries A/D converter.
Data Sheet U16369EJ1V0DS
61
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Remark The impedance of the analog input pins is shown below. [Equivalent circuit]
R1 ANIn (n = 0 to 3) C1 C2 C3 R2
[Parameter value] (TYP.)
AVDD 2.7 V 4.5 V R1 12 k 4 k R2 8.0 k 2.7 k C1 3.0 pF 3.0 pF C2 3.0 pF 1.4 pF C3 2.0 pF 2.0 pF
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C)
Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillation stabilization wait time Symbol VDDDR IDDDR tSREL tWAIT Release by RESET Release by interrupt request Subsystem clock stop (XT1 = VDD) and feed-back resistor disconnected 0 217/fX Note Conditions MIN. 1.6 0.1 TYP. MAX. 5.5 30 Unit V
A s
s s
Note
Selection of 212/fX and 214/fX to 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS).
62
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Flash Memory Programming Characteristics (TA = +10 to +40C, VDD = 1.8 to 5.5 V, VSS = AVSS = 0 V) (1) Write erase characteristics
Parameter Operating frequency Symbol fX Conditions 4.5 V VDD 5.5 V 3.0 V VDD < 4.5 V 1.8 V VDD < 3.0 V VPP supply voltage VDD supply current VPP2 IDD During flash memory programming When 10 MHz crystal VPP = VPP2 oscillation operating mode VDD = 5.0 V10% MIN. 1.0 1.0 1.0 9.7 10.0 TYP. MAX. 10.0 8.38 1.25 10.3 30 Unit MHz MHz MHz V mA
8.38 MHz crystal VDD = 5.0 V10% oscillation operating mode VPP supply current Step erase time
Note 1 Note 2
24 17 100 0.199 0.2 0.201 20 49.4 50 50.6 60 16 48 50 52 520 20
mA mA mA s s/chip ms Times Times
VDD = 3.0 V10%
IPP Ter Tera Twb Cwb Cerwb Twr
Note 6 Note 7
When VPP = VPP2
Overall erase time Writeback time
When step erase time = 0.2 s
Note 3
Number of writebacks per Note 4 writeback command Number of erases/writebacks Step write time
Note 5
When writeback time = 50 ms
s s
Times
Overall write time per word
Twrw Cerwb
When step write time = 50 s (1 word = 1 byte) 1 erase + 1 write after erase = 1 rewrite
48
Number of rewrites per chip
Notes 1. 2. 3. 4.
The recommended setting value of the step erase time is 0.2 s. The prewrite time before erasure and the erase verify time (writeback time) are not included. The recommended setting value of the writeback time is 50 ms. Writeback is executed once by the issuance of the writeback command. Therefore, the number of retries must be the maximum value minus the number of commands issued. 5. The recommended setting value of the step write time is 50 s. 6. The actual write time per word is 100 s longer. The internal verify time during or after a write is not included. 7. When a product is first written after shipment, "erase write" and "write only" are both taken as one rewrite. Example: P: Write, E: Erase Shipped product PEPEP: 3 rewrites Shipped product EPEPEP: 3 rewrites
(2) Serial write operation characteristics
Parameter VPP set time Set time from VDD to VPP Set time from VPP to RESET VPP count start time from RESET Count execution time VPP counter high-level width VPP counter low-level width VPP counter noise elimination width Symbol tPSRON tDRPSR tPSRRF tRFCF tCOUNT tCH tCL tNFW 8.0 8.0 40 Conditions VPP high voltage VPP high voltage VPP high voltage MIN. 1.0 10 1.0 1.0 2.0 TYP. MAX. Unit
s s s s
ms
s s
ns
Data Sheet U16369EJ1V0DS
63
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
9.3 Timing Chart AC Timing Test Point (Excluding X1, XT1 Input)
0.8VDD 0.2VDD
Point of test
0.8VDD 0.2VDD
Clock Timing
1/fX
tXL
tXH VIH4 (MIN.) VIL4 (MAX.)
X1 input
1/fXT
tXTL XT1 input
tXTH VIH5 (MIN.) VIL5 (MAX.)
TI Timing
tTIL0
tTIH0
TI00, TI01
1/fTI5 tTIL5 tTIH5
TI50, TI51
64
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Interrupt Request Input Timing
tINTL
tINTH
INTP0 to INTP3
RESET Input Timing
tRSL
RESET
Data Sheet U16369EJ1V0DS
65
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Read/Write Operation External fetch (no wait):
A8 to A15
Higher 8-bit address tADD1
AD0 to AD7
Lower 8-bit address tADS tADH tASTH
Hi-Z tRDAD tRDD1
Instruction code tRDADH tRDAST
ASTB
RD tASTRD tRDL1 tRDH
External fetch (wait insertion):
A8 to A15
Higher 8-bit address tADD1
AD0 to AD7
Lower 8-bit address tADS tADH tASTH
Hi-Z tRDAD tRDD1
Instruction code tRDADH tRDAST
ASTB
RD tASTRD WAIT tRDWT1 tWTL tWTRD tRDL1 tRDH
66
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
External data access (no wait):
A8 to A15 tADD2 AD0 to AD7 Lower 8-bit address tADS tADH tASTH ASTB Hi-Z tRDAD tRDD2
Higher 8-bit address
Read data
Write data
Hi-Z
tRDH
RD tASTRD WR tASTWR tWRL1 tRDL2 tRDWD tWRWD tWDS tWDH tWRADH
External data access (wait insertion):
A8 to A15 tADD2 AD0 to AD7
Lower 8-bit address
Higher 8-bit address Hi-Z tRDAD tRDH tRDD2 tASTRD Hi-Z
Read data
Write data
tADS tADH tASTH ASTB
RD tRDL2 WR tASTWR WAIT tRDWT2 tWTL tWTRD
tRDWD tWRWD
tWDS
tWDH
tWRL1
tWRADH
tWTL tWRWT tWTWR
Data Sheet U16369EJ1V0DS
67
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Serial Transfer Timing 3-wire serial I/O mode:
tKCYm tKLm tKHm
SCK3n tSIKm tKSIm
SI3n tKSOm
Input data
SO3n
Output data
Remarks 1. m = 1, 2 2. PD78F0034B and 78F0034B(A): n = 0, 1 3. PD78F0034BY and 78F0034BY(A): n = 0 UART mode (external clock input):
tKCY3 t KL3 tKH3
ASCK0
I2C bus mode (PD78F0034BY only):
tLOW SCL0 tF tSU:STA tHD:STA tSP tSU:STO tR
tHD:DAT tHD:STA
tHIGH tSU:DAT
SDA0 tBUF Stop condition Start condition Restart condition Stop condition
68
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation HALT mode STOP mode Operating mode
Data retention mode
VDD STOP instruction execution RESET
VDDDR tSREL
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
HALT mode STOP mode Operating mode
Data retention mode
VDD STOP instruction execution Standby release signal (Interrupt request)
VDDDR tSREL
tWAIT
Data Sheet U16369EJ1V0DS
69
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Flash Memory Write Mode Set Timing
VDD VDD 0V VPPH VPP VPPL 0V tPSRON tPSRRF tCOUNT VDD RESET (input) 0V tCL tDRPSR tRFCF tCH
70
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
10. PACKAGE DRAWINGS
64-PIN PLASTIC LQFP (10x10)
A B
48 49
33 32 S P
detail of lead end
C
D
T
R 64 1 F G H I
M
L U
17 16
Q
J
K S
ITEM A B C D F G H I J K L M N P Q R S T U
MILLIMETERS 12.00.2 10.00.2 10.00.2 12.00.2 1.25 1.25 0.220.05 0.08 0.5 (T.P.) 1.00.2 0.5 0.17 +0.03 -0.07 0.08 1.4 0.10.05 3 +4 -3 1.50.10 0.25 0.60.15 S64GB-50-8EU-2
N
NOTE
S
M
Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
Remark The package and material of ES products are the same as mass produced products.
Data Sheet U16369EJ1V0DS
71
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
64-PIN PLASTIC LQFP (14x14)
A B
48 49
33 32
detail of lead end S P C D
T
R 64 1 F G H I
M
L U
17 16 Q
J
ITEM A B
MILLIMETERS 17.20.2 14.00.2 14.00.2 17.20.2 1.0 1.0 0.37 +0.08 -0.07 0.20 0.8 (T.P.) 1.60.2 0.8 0.17 +0.03 -0.06 0.10 1.40.1 0.1270.075 +4 3 -3 1.7 MAX. 0.25 0.8860.15 P64GC-80-8BS
K S
C D F G H
N
S
M
I J K
NOTE Each lead centerline is located within 0.20 mm of its true position (T.P.) at maximum material condition.
L M N P Q R S T U
Remark The package and material of ES products are the same as mass produced products.
72
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
64-PIN PLASTIC TQFP (12x12)
A B
48 49
33 32 S P
detail of lead end
T C D R
L U
64 1 F G H I
M
17 16
Q
J
ITEM A B MILLIMETERS 14.00.2 12.00.2 12.00.2 14.00.2 1.125 1.125 0.32 +0.06 -0.10 0.13 0.65 (T.P.) 1.00.2 0.5 0.17 +0.03 -0.07 0.10 1.0 0.10.05 3 +4 -3 1.10.1 0.25 0.60.15 P64GK-65-9ET-3
K S M N
NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
C D F G H I J K L M N P Q R S T U
S
Remark The package and material of ES products are the same as mass produced products.
Data Sheet U16369EJ1V0DS
73
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
73-PIN PLASTIC FBGA (9x9)
D
wSA
ZE
ZD
A
B E
9 8 7 6 5 4 3 2 1 JHGFEDCBA
INDEX MARK
wSB
A y1 S A2
(UNIT:mm)
S
ITEM D E w
DIMENSIONS 9.000.10 9.000.10 0.20 1.280.10 0.350.06 0.93 0.80 0.50 +0.05 -0.10 0.08 0.10 0.20 1.30 1.30 P73F1-80-CN3
y
S
e
A1
A A1 A2 e b x y y1 ZD ZE
b
x
M
S AB
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced version.
74
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
11. RECOMMENDED SOLDERING CONDITIONS
The PD78F0034B, 78F0034BY, 78F0034B(A), and 78F0034BY(A) should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. Table 11-1. Surface Mounting Type Soldering Conditions (1/2) (1) PD78F0034BGB-8EU: 64-pin plastic LQFP (10 x 10) 64-pin plastic LQFP (10 x 10)
PD78F0034BGB(A)-8EU:
64-pin plastic LQFP (10 x 10) PD78F0034BYGB-8EU: PD78F0034BYGB(A)-8EU: 64-pin plastic LQFP (10 x 10)
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-107-2
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after 7 days, prebake at 125C for 10 hours) Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after 7 days, prebake at 125C for 10 hours) Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
VPS
VP15-107-2
Partial heating
-
Note
After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
(2) PD78F0034BGC-8BS:
64-pin plastic LQFP (14 x 14) 64-pin plastic LQFP (14 x 14) 64-pin plastic LQFP (14 x 14)
PD78F0034BGC(A)-8BS: PD78F0034BYGC-8BS:
PD78F0034BYGC(A)-8BS: 64-pin plastic LQFP (14 x 14)
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-00-2
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Two times or less Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface temperature) Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
VPS
VP15-00-2
Wave soldering
WS60-00-1
Partial heating
-
Caution Do not use different soldering methods together (except for partial heating).
Data Sheet U16369EJ1V0DS
75
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Table 11-1. Surface Mounting Type Soldering Conditions (2/2) (3) PD78F0034BGK-9ET: 64-pin plastic TQFP (12 x 12) 64-pin plastic TQFP (12 x 12)
PD78F0034BGK(A)-9ET:
64-pin plastic TQFP (12 x 12) PD78F0034BYGK-9ET: PD78F0034BYGK(A)-9ET: 64-pin plastic TQFP (12 x 12)
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-107-2
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after 7 days, prebake at 125C for 10 hours) Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after 7 days, prebake at 125C for 10 hours) Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface temperature), Exposure limit: 7 daysNote (after 7 days, prebake at 125C for 10 hours) Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
VPS
VP15-107-2
Wave soldering
WS60-107-1
Partial heating
-
Note
After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating). (4) PD78F0034BF1-CN3: 73-pin plastic FBGA (9 x 9)
PD78F0034BYF1-CN3: 73-pin plastic FBGA (9 x 9)
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 260C, Time: 60 seconds max. (at 220C or higher), Count: Three times or less, Exposure limit: 3 daysNote (after that, prebake at 125C for 20 hours) Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Three times or less, Exposure limit: 3 daysNote (after that, prebake at 125C for 20 hours) Recommended ConditionSymbol IR60-203-3
VPS
VP15-203-3
Note
After opening the dry pack, store it at 25C or less and 65%RH or less for the allowable storage period.
Caution Do not use different soldering methods together.
76
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD780034B, 780034BY. Also refer to (6) Cautions on Using Development Tools. (1) Software Package
SP78K0 CD-ROM in which various software tools for 78K/0 development are integrated in one package
(2) Language Processing Software
RA78K0 CC78K0 DF780034 CC78K0-L Assembler package common to 78K/0 Series C compiler package common to 78K/0 Series Device file for PD780034A, 780034AY Subseries C compiler library source file common to 78K/0 Series
(3) Flash Memory Writing Tools
Flashpro III (FL-PR3, PG-FP3) Flashpro IV (FL-PR4, PG-FP4) FA-64GB-8EU FA-64GC-8BS-A FA-64GK-9ET FA-73F1-CN3-A Adapter for flash memory writing used connected to the Flashpro III/Flashpro IV. * FA-64GB-8EU: 64-pin plastic LQFP (GB-8EU type) * FA-64GC-8BS-A: 64-pin plastic LQFP (GC-8BS type) * FA-64GK-9ET: 64-pin plastic TQFP (GK-9ET type) * FA-73F1-CN3-A: 73-pin plastic FBGA (F1-CN3 type) Flash programmer dedicated to microcontrollers with on-chip flash memory
Data Sheet U16369EJ1V0DS
77
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(4) Debugging Tools * When using in-circuit emulator IE-78K0-NS
IE-78K0-NS IE-70000-MC-PS-B IE-78K0-NS-PA IE-70000-98-IF-C IE-70000-CD-IF-A IE-70000-PC-IF-C IE-70000-PCI-IF-A IE-780034-NS-EM1 NP-64GC NP-64GC-TQ NP-H64GC-TQ NP-64GK NP-H64GK-TQ NP-H64GB-TQ NP-73F1-CN3Note EV-9200GC-64 Emulation probe for 64-pin plastic LQFP (GB-8EU type) Emulation probe for 73-pin plastic FBGA (F1-CN3 type) Conversion socket to connect the NP64GC and a target system board on which a 64-pin plastic LQFP (GC-8BS type) can be mounted. TGC-064SAP Conversion adapter to connect the NP-64GC-TQ or NP-H64GC-TQ and a target system board on which a 64-pin plastic LQFP (GC-8BS type) can be mounted Conversion adapter to connect the NP-64GK or NP-H64GK-TQ and a target system on which a 64pin plastic TQFP (GK-9ET type) can be mounted Conversion socket to connect the NP-H64GB-TQ and a target system board on which a 64-pin plastic LQFP (GB-8EU type) can be mounted Conversion socket to connect the NP-73F1-CN3 and a target system board on which a 73-pin plastic FBGA (F1-CN3 type) can be mounted Emulation probe for 64-pin plastic TQFP (GK-9ET type) In-circuit emulator common to 78K/0 Series Power supply unit for IE-78K0-NS Performance board to enhance and expand the functions of IE-78K0-NS Adapter required when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported) PC card and interface cable when using notebook PC as host machine (PCMCIA socket supported) Adapter required when using IBM PC/ATTM or compatible as host machine (ISA bus supported) Adapter required when using PC in which PCI bus is incorporated as host machine Emulation board to emulate PD780034A, 780034AY Subseries Emulation probe for 64-pin plastic LQFP (GC-8BS type)
TGK-064SBW
TGB-064SDP
CSICE73A0909N01, LSPACK73A0909N01, CSSOCKET73A0909N01 ID78K0-NS SM78K0 DF780034
Integrated debugger for IE-78K0-NS System simulator common to 78K/0 Series Device file for PD780034A, 780034AY Subseries
Note
The conversion socket (CSICE73A0909N01, LSPACK73A0909N01, or CSSOCKET73A0909N01) is supplied with the emulation probe (NP-73F1-CN3).
78
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
* When using in-circuit emulator IE-78001-R-A
IE-78001-R-A IE-70000-98-IF-C IE-70000-PC-IF-C IE-70000-PCI-IF-A IE-780034-NS-EM1 IE-78K0-R-EX1 EP-78240GC-R EP-78012GK-R EV-9200GC-64 In-circuit emulator common to 78K/0 Series Adapter required when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported) Interface adapter when using IBM PC/AT or compatible as host machine (ISA bus supported) Adapter required when using PC in which PCI bus is incorporated as host machine Emulation board to emulate PD780034A, 780034AY Subseries Emulation probe conversion board necessary when using IE-780034-NS-EM1 on IE-78001-R-A Emulation probe for 64-pin plastic LQFP (GC-8BS type) Emulation probe for 64-pin plastic TQFP (GK-9ET type) Conversion socket to connect the EP-78240GC-R and a target system board on which a 64-pin plastic LQFP (GC-8BS type) can be mounted Conversion adapter to connect the EP-78012GK-R and a target system board on which a 64-pin plastic TQFP (GK-9ET type) can be mounted Integrated debugger for IE-78001-R-A System simulator common to 78K/0 Series Device file for PD780034A, 780034AY Subseries
TGK-064SBW
ID78K0 SM78K0 DF780034
(5) Real-Time OS
RX78K0 Real-time OS for 78K/0 Series
Caution The 64-pin plastic LQFP (GB-8EU type) and 73-pin plastic FBGA (F1-CN3 type) do not support the IE-78001-R-A.
Data Sheet U16369EJ1V0DS
79
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(6) Cautions on Using Development Tools * The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780034. * The CC78K0 and RX78K0 are used in combination with the RA78K0 and the DF780034. * FL-PR3, FL-PR4, FA-64GC-8BS-A, FA-64GB-8EU, FA-64GK-9ET, FA-73F1-CN3-A, NP-64GC, NP-64GCTQ, NP-H64GC-TQ, NP-64GK, NP-H64GK-TQ, NP-H64GB-TQ, and NP-73F1-CN3 are products made by Naito Densei Machida Mfg. Co., Ltd. (+81-45-475-4191). * TGC-064SAP, TGK-064SBW, TGB-064SDP, CSICE73A0909N01, LSPACK73A0909N01, and CSSOCKET73A0909N01 are products made by TOKYO ELETECH CORPORATION. Contact: Daimaru Kogyo, Ltd. Tokyo Electronic Division (+81-3-3820-7112) Osaka Electronic Division (+81-6-6244-6672) * For third-party development tools, see the Single-chip Microcontroller Development Tool Selection Guide (U11069E). * The host machines and OSs supporting each software are as follows.
Host Machine [OS] Software RA78K0 CC78K0 ID78K0-NS ID78K0 SM78K0 RX78K0
PC PC-9800 series [Japanese WindowsTM] IBM PC/AT and compatibles [Japanese/English Windows] Note
Note
EWS HP9000 series 700TM [HP-UXTM] SPARCstationTM [SunOSTM, SolarisTM] - - -
Note
Note
DOS-based software
80
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Conversion Socket Drawing (EV-9200GC-64) and Footprints Figure A-1. EV-9200GC-64 Drawing (For Reference Only)
A E B F M
R
N
O
D
C
S T K
Q
EV-9200GC-64-G0 INCHES 0.74 0.555 0.555 0.74 4-C 0.118 0.031 0.236 0.622 0.728 0.236 0.622 0.728 0.315 0.307 0.098 0.079 0.053 0.014 +0.004 -0.005
EV-9200GC-64
1 No.1 pin index P
G H I ITEM A B C D E F G H I J K L M N O P Q R S T MILLIMETERS 18.8 14.1 14.1 18.8 4-C 3.0 0.8 6.0 15.8 18.5 6.0 15.8 18.5 8.0 7.8 2.5 2.0 1.35 0.35 0.1
J
2.3 1.5
0.091 0.059
L
Data Sheet U16369EJ1V0DS
81
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Figure A-2. EV-9200GC-64 Footprints (For Reference Only)
G
J K
D
E
F
L
C B A EV-9200GC-64-P1E ITEM A B C D E F G H I J K L Caution MILLIMETERS 19.5 14.8 INCHES 0.768 0.583
0.80.02 x 15=12.00.05 0.031+0.002 x 0.591=0.472 +0.003 -0.001 -0.002 0.80.02 x 15=12.00.05 0.031+0.002 x 0.591=0.472 +0.003 -0.001 -0.002 14.8 19.5 6.00 0.08 6.00 0.08 0.5 0.02 0.583 0.768 0.236 +0.004 -0.003 0.236 +0.004 -0.003 0.197 +0.001 -0.002
2.36 0.03 2.2 0.1 1.57 0.03
0.093 +0.001 -0.002 0.087 +0.004 -0.005 0.062 +0.001 -0.002
DimensionsofmountpadforEV-9200andthatfortargetdevice (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E).
82
Data Sheet U16369EJ1V0DS
I
H
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Conversion Adapter Drawing (TGC-064SAP) Figure A-3. TGC-064SAP Drawing (For Reference Only)
I C
A B
J K S
Protrusion height
T QR
D
E F GH
M V W d U j i c Yb a eg f h
ITEM A B C D E F G H I J K L M N O P Q R S T U V W X Y Z MILLIMETERS 14.12 0.8x15=12.0 0.8 20.65 10.0 12.4 14.8 17.2 C 2.0 9.05 5.0 13.35 1.325 1.325 16.0 20.65 12.5 17.5 4- 1.3 1.8 3.55 0.9 INCHES 0.556 0.031x0.591=0.472 0.031 0.813 0.394 0.488 0.583 0.677 C 0.079 0.356 0.197 0.526 0.052 0.052 0.630 0.813 0.492 0.689 4- 0.051 0.071 ITEM a b c d e f g h i j
L O P
N
XZ
MILLIMETERS 1.85 3.5 2.0 6.0 0.25 13.6 1.2 1.2 2.4 2.7
INCHES 0.073 0.138 0.079 0.236 0.010 0.535 0.047 0.047 0.094 0.106
TGC-064SAP-G0E
0.3
(19.65) 7.35 1.2
0.140 0.035 0.012
(0.667) 0.289 0.047
note: Product by TOKYO ELETECH CORPORATION.
Data Sheet U16369EJ1V0DS
83
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Conversion Adapter Drawing (TGK-064SBW) Figure A-4. TGK-064SBW Drawing (For Reference Only) (Unit: mm)
K
A B C
L M S
Protrusion height
X
T
U
V
GFED
HI
J
Q
W R
Z e d c b f Y k j i
a
N O P h
g
ITEM A B C D E F G H I J K L M N O P Q R S T U V W X Y Z MILLIMETERS 18.4 0.65x15=9.75 0.65 7.75 10.15 12.55 14.95 0.65x15=9.75 11.85 18.4 C 2.0 12.45 10.25 7.7 10.02 14.92 11.1 1.45 1.45 4- 1.3 1.8 5.0 INCHES 0.724 0.026x0.591=0.384 0.026 0.305 0.400 0.494 0.589 0.026x0.591=0.384 0.467 0.724 C 0.079 0.490 0.404 0.303 0.394 0.587 0.437 0.057 0.057 4- 0.051 0.071 0.197 ITEM a b c d e f g h i j k MILLIMETERS INCHES
0.3
1.85 3.5 2.0 3.9 1.325 1.325 5.9 0.8 2.4 2.7
0.012
0.073 0.138 0.079 0.154 0.052 0.052 0.232 0.031 0.094 0.106 TGK-064SBW-G1E
5.3
4-C 1.0
0.209
4-C 0.039
3.55 0.9
0.140 0.035
note: Product by TOKYO ELETECH CORPORATION.
84
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
APPENDIX B. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices
Document Name Document No. U14046E U14042E U15131E
PD780024A, 780034A, 780024AY, 780034AY Subseries User's Manual PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY Data Sheet PD780021A(A), 780022A(A), 780023A(A), 780024A(A), 780021AY(A), 780022AY(A), 780023AY(A),
780024AY(A) Data Sheet
PD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY Data Sheet PD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A),
780034AY(A) Data Sheet
U14044E U15132E
PD78F0034A, 78F0034AY Data Sheet PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A) Data Sheet
78K/0 Series User's Manual Instruction
U14040E This document U12326E
Documents Related to Development Software Tools (User's Manuals)
Document Name RA78K0 Assembler Package Operation Language Structured Assembly Language CC78K0 C Compiler Operation Language SM78K Series System Simulator Ver. 2.30 or Later Operation (Windows Based) External Part User Open Interface Specifications ID78K Series Integrated Debugger Ver. 2.30 or Later RX78K0 Real-time OS Operation (Windows Based) Fundamentals Installation Project Manager Ver. 3.12 or Later (Windows Based) Document No. U14445E U14446E U11789E U14297E U14298E U15373E U15802E U15185E U11537E U11536E U14610E
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
Data Sheet U16369EJ1V0DS
85
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Documents Related to Development Hardware Tools (User's Manuals)
Document Name IE-78K0-NS In-Circuit Emulator IE-78K0-NS-A In-Circuit Emulator IE-780034-NS-EM1 Emulation Board IE-78001-R-A In-Circuit Emulator IE-78K0-R-EX1 In-Circuit Emulator Document No. U13731E U14889E U14642E U14142E To be prepared
Documents Related to Flash Memory Writing
Document Name PG-FP3 Flash Memory Programmer User's Manual PG-FP4 Flash Memory Programmer User's Manual Document No. U13502E U15260E
Other Related Documents
Document Name SEMICONDUCTORS SELECTION GUIDE - Products & Packages Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Document No. X13769E C10535E C11531E C10983E C11892E
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
86
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
[MEMO]
Data Sheet U16369EJ1V0DS
87
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Note: Purchase of NEC Electronics I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
FIP and IEBus are trademarks of NEC Electronics Corporation. Windows is either a registered trademark or trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc.
88
Data Sheet U16369EJ1V0DS
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics America, Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
* Filiale Italiana Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 * Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 Fax: 040-244 45 80 * Tyskland Filial Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 * United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Europe) GmbH
Duesseldorf, Germany Tel: 0211-65 03 01 Fax: 0211-65 03 327 * Sucursal en Espana Madrid, Spain Tel: 091-504 27 87 Fax: 091-504 28 60 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China Tel: 021-6841-1138 Fax: 021-6841-1137
NEC Electronics Taiwan Ltd.
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 6253-8311 Fax: 6250-3583
J02.11
Data Sheet U16369EJ1V0DS
89
PD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
* The information in this document is current as of September, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
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