View HD74SSTV16857_471508.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HD74SSTV16857
1:1 14-bit SSTL_2 Registered Buffer
ADE-205-336F (Z) Rev.6 June. 2001 Description
The HD74SSTV16857 is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input. Data flow from D to Q is controlled by differential clock pins (CLK, CLK) and the RESET. Data is triggered on the positive edge of the positive clock (CLK), and the negative clock (CLK) must be used to maintain noise margins. When RESET is low, all registers are reset and all outputs are low. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.
Features
* Supports LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input * Differential SSTL_2 (Stub series terminated logic) CLK signal * Flow through architecture optimizes PCB layout * Package type
Package type TSSOP-48 pin TVSOP-48 pin Package code TTP-48DB TTP-48DEV Package suffix T N Taping code EL (1,000 pcs / Reel) EL (1,000 pcs / Reel)
HD74SSTV16857
Function Table
Inputs RESET L H H H H: L: X: : : Note: CLK X L or H CLK X H or L D X H L X L H L Q0
*1
Output Q
High level Low level Immaterial Low to high transition High to low transition 1. Output level before the indicated steady state input conditions were established.
Rev.6, Jun. 2001, page 2 of 15
HD74SSTV16857
Pin Arrangement
Q1 1 Q2 2 GND 3 V DDQ 4 Q3 5 Q4 6 Q5 7 GND 8 V DDQ 9 Q6 10 Q7 11 V DDQ 12 GND 13 Q8 14 Q9 15 V DDQ 16 GND 17 Q10 18 Q11 19 Q12 20 V DDQ 21 GND 22 Q13 23 Q14 24
48 D1 47 D2 46 GND 45 V CC 44 D3 43 D4 42 D5 41 D6 40 D7 39 CLK 38 CLK 37 V CC 36 GND 35 V REF 34 RESET 33 D8 32 D9 31 D10 30 D11 29 D12 28 V CC 27 GND 26 D13 25 D14
(Top view)
Rev.6, Jun. 2001, page 3 of 15
HD74SSTV16857
Absolute Maximum Ratings
Item Supply voltage Input voltage
*1 *1, 2
Symbol VCC or VDDQ VI VO IIK IOK IO ICC, IDDQ or IGND PT Tstg
Ratings -0.5 to 3.6 -0.5 to VDDQ+0.5 -0.5 to VDDQ+0.5 50 50 50 100 115 -65 to +150
Unit V V V mA mA mA mA C / W C
Conditions
Output voltage
Input clamp current Output clamp current Continuous output current VCC, VDDQ or GND current / pin Maximum power dissipation at Ta = 55C (in still air) Storage temperature Notes:
VI < 0 or VI > VCC VO < 0 or VO > VDDQ VO = 0 to VDDQ TSSOP
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This current will flow only when the output is in the high state and VO > VDDQ.
Rev.6, Jun. 2001, page 4 of 15
HD74SSTV16857
Recommended Operating Conditions
Item Supply voltage Output supply voltage Reference voltage Termination voltage Input voltage AC high level input voltage AC low level input voltage DC high level input voltage DC low level input voltage High level input voltage Low level input voltage Differential input voltage (Minimum peak to
peak input)
Symbol Min VCC VDDQ VREF VTT VI VIH VIL VIH VIL VIH VIL VPP IOH IOL Ta VDDQ 2.3 1.15 VREF-40 mV 0 -- -- 1.7 -0.3 0.97 360 -- -- 0
Typ 2.5 2.5 1.25 VREF -- -- -- -- -- -- -- -- -- --
Max 2.7 2.7 1.35 VREF+40 mV VCC -- VREF-310 mV -- VREF-150 mV VDDQ+0.3 0.7 1.53 -- -20 20 70
Unit Conditions V V V V V V V V V V V V mV mA mA C D D D D RESET RESET CLK, CLK CLK, CLK VREF = 0.5 x VDDQ
VREF+310 mV -- VREF+150 mV --
(Common mode range) VCMR
High level output current Low level output current Operating temperature
Note: The RESET input of the device must be held at VDDQ or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is low.
Rev.6, Jun. 2001, page 5 of 15
HD74SSTV16857
Logic Diagram
*1
RESET CLK CLK D1
34 38 39 48
VREF
35
1D C1 R
1
Q1
To thirteen other channels
Note:
1.
RESET input gate is connected to VDDQ.
Rev.6, Jun. 2001, page 6 of 15
HD74SSTV16857
Electrical Characteristics
Item Input diode voltage Output voltage
Symbol VCC (V)
Min -- 1.95 0 -- -- -- --
Typ -- -- -- -- -- -- -- --
Max -1.2 -- VDDQ 0.2 0.35 5 45 10 90
Unit Test Conditions V V IIN = -18 mA IOH = -100 A IOH = -16 mA IOL = 100 A IOL = 16 mA A mA A VIN = 2.7 V or 0 VIN = VIH(AC) or VIL(AC), IO = 0 RESET = GND
VIK VOH VOL
2.3 2.3 2.3
2.3 to 2.7 VCC-0.2 -- 2.3 to 2.7 -- 2.7
Input current Standby current
(All inputs)
IIN ICC
*2
Quiescent supply current Dynamic operating clock only
2.7 2.7 2.7
ICC (stdy) ICCD
*2
A/ RESET = VCC, clock VI = VIH(AC) or VIL(AC), MHz CLK and CLK switching 50% duty cycle A/ clock MHz / data input
*4 *4
Dynamic operating per each ICCD data input
*2
2.7
--
--
15
RESET = VCC, VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle.
Output high Output low
*3
rOH rOL rO() Data inputs CIN
CLK and CLK
2.3 to 2.7 7 2.3 to 2.7 7 2.5 2.5
*1
-- -- -- -- -- 3.0
22 22 4 3.5 3.5 --
pF
IOH = -20 mA IOL = 20 mA IO = 20 mA, Ta = 25C VI = VREF310 mV
VCMR = 1.25 V, VPP = 360 mV
*3
rOH - rOL each *3 separate bit Input capacitance Notes: 1. 2. 3. 4.
-- 2.5 2.5 --
RESET
VI = VCC or GND
All typical values are at VCC = 2.5 V, Ta = 25C. Total ICC (max) = ICC + {ICCD (clock)xf(clock)} + {ICCD (Data)x1/2f(clock)x14} This is effective in the case that it did terminate by resistance. See figure. 1, 2
Rev.6, Jun. 2001, page 7 of 15
HD74SSTV16857
Switching Characteristics
Item
*1 *4, 6 *5, 6 *4, 6 *5, 6
Symbol
VCC = 2.5 0.2 V Min Max 200 -- -- -- -- -- -- -- 0.75 0.9 0.75 0.9 22 22
Unit
Test Condition
Clock frequency Setup time Hold time
fclock Fast slew rate Slow slew rate Fast slew rate Slow slew rate tsu th tact tinact
MHz ns ns ns ns Data before CLK, CLK Data after CLK, CLK Data inputs must be low after RESET high. Data and clock inputs must be held at valid levels (not floating) after RESET low. CLK, CLK "H" or "L"
Differential inputs active time Differential inputs inactive time
Pulse width Output slew
*3
tw tSL
2.5 1
-- 4
ns volt/ns
(CL = 30 pF, RL = 50 , VREF = VTT = VDDQ x 0.5)
Item Symbol VCC = 2.5 0.2 V Min Maximum clock frequency Propagation delay time
*2
Unit Max -- 2.8 5.0 MHz ns
FROM (Input)
TO (Output)
Typ -- -- --
fmax tPLH, tPHL tPHL
200 1.1 --
CLK, CLK Q RESET Q
Notes: 1. Although the clock is differential, all timing is relative to CLK going high and CLK going low. 2. This timing relationship is specified into test load (see waveforms - 3, 4) with all of the outputs switching. 3. Assumes into an equivalent, distributed load to the address net structure defined in the application information provided in this specification. 4. For data signal input slew rate 1 V/ns. 5. For data signal input slew rate 0.5 V/ns and < 1 V/ns. 6. CLK, CLK signals input slew rates are 1 V/ns.
Rev.6, Jun. 2001, page 8 of 15
HD74SSTV16857
Test Circuit
VTT
*2
50 Test point
*1
C L = 30 pF
Notes:
1. 2.
CL includes probe and jig capacitance. VTT = VREF = VDDQ x 0.5
Waveforms - 1
LVCMOS RESET Input VCC VCC /2 tinact
*1
VCC /2 0V tact 90 % 10 % I CCH I CCL
I CC
Rev.6, Jun. 2001, page 9 of 15
HD74SSTV16857
Waveforms - 2
tw VIH Input VREF VREF VIL
Timing input
VCMR
VPP
tsu
th VIH
Input
VREF
VREF VIL
Waveforms - 3
Timing input
VCMR
VCMR
VPP
tPLH
tPHL V OH
Output
VTT
VTT VOL
Rev.6, Jun. 2001, page 10 of 15
HD74SSTV16857
Waveforms - 4
LVCMOS RESET Input VIH VCC /2 VIL tPHL VOH Output VTT VOL
Notes:
1. 2. 3. 4. 5. 6. 7.
ICC tested with clock and data inputs held at VCC or GND, and IO = 0 mA. All input pulses are supplied by generators having the following characteristics : PRR 10 MHz, Zo = 50 , input slew rate = 1 V/ns 20% (unless otherwise specified). The outputs are measured one at a time with one transition per measurement. VTT = VREF = VDDQ/2 VIH = VREF+310 mV (AC voltage levels) for differential inputs. VIH = VCC for LVCMOS input. VIL = VREF-310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. tPLH and tPHL are the same as tpd
Rev.6, Jun. 2001, page 11 of 15
HD74SSTV16857
Application Data
* Pull-down
100
80
Current (Amps)
60
40
20
Min Max
0 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Voltage (V)
Figure . 1
* Pull-up
Voltage (V)
0.0 0 0.5 1.0 1.5 2.0 2.5 Min Max 3.0
-20
Current (Amps)
-40
-60
-80
-100
Figure . 2
Rev.6, Jun. 2001, page 12 of 15
HD74SSTV16857
Curve Data
Voltage (V) Pull-down I (mA) Min 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 0 6 10 15 19 23 27 30.5 34 36.5 38.5 40 42 43 44 44 45 45 45 45 45 46 46 46 46 46 46 46 I (mA) Max 0 7 15 22 29 35.5 41.5 48 54 59 65 70 75 79 82 84.5 87 89 90 90 91 91 91 91 91.5 92 92 92 Pull-up I (mA) Min 0 -5 -10 -15 -19 -23.5 -28 -31.5 -35 -38 -41 -44 -46 -48 -50 -51 -52 -52 -52.5 -53 -53 -53.5 -54 -54 -54 -54.5 -55 -55 I (mA) Max 0 -7 -13 -19 -25 -31 -37 -42 -47 -53 -58 -62 -66 -71 -74 -77 -81 -84 -86 -89 -91 -92 -93 -94 -95 -96.5 -98 -99
Rev.6, Jun. 2001, page 13 of 15
HD74SSTV16857
Package Dimensions
Unit: mm
12.5 12.7 Max 48 25
6.10
1 *0.21 +0.04 -0.05 0.19 +0.03 -0.05
0.50
24
0.08 M 8.10 0.20 0 - 8
*0.17 0.05 0.15 0.04 0.13 0.05
1.0
0.65 Max
1.20 Max
0.50 0.1
0.10
*Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Mass (reference value)
TTP-48DB 0.20 g
Unit: mm
9.70 9.90 Max 48 25
1 *0.18 0.05
0.40
24
0.07 M 6.40 0.20 0 - 8
4.40
1.0
0.40 Max
*0.15 0.05
0.08
0.10 0.05
1.20 Max
0.50 0.10
*Pd plating
Hitachi Code JEDEC JEITA Mass (reference value)
TTP-48DEV -- -- --
Rev.6, Jun. 2001, page 14 of 15
HD74SSTV16857
Disclaimer
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Sales Offices
Hitachi, Ltd.
Semiconductor & Integrated Circuits Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica Europe Asia Japan
: : : :
http://semiconductor.hitachi.com/ http://www.hitachi-eu.com/hel/ecg http://sicapac.hitachi-asia.com http://www.hitachi.co.jp/Sicd/indx.htm
Hitachi Asia Ltd. Hitachi Tower 16 Collyer Quay #20-00 Singapore 049318 Tel : <65>-538-6533/538-8577 Fax : <65>-538-6933/538-3877 URL : http://www.hitachi.com.sg Hitachi Asia Ltd. (Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://www.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852>-(2)-735-9218 Fax : <852>-(2)-730-0281 URL : http://semiconductor.hitachi.com.hk
For further information write to:
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe Ltd. Electronic Components Group Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 585200 Hitachi Europe GmbH Electronic Components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00
Copyright (c) Hitachi, Ltd., 2001. All rights reserved. Printed in Japan.
Colophon 4.0
Rev.6, Jun. 2001, page 15 of 15

▲Up To Search▲

Price & Availability of HD74SSTV16857

	To Download HD74SSTV16857 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .