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(R)
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
DESCRIPTION:
Integrated Device Technology, Inc.
IDT54/74FCT821A/B/C IDT54/74FCT823A/B/C IDT54/74FCT824A/B/C IDT54/74FCT825A/B/C
FEATURES:
* Equivalent to AMD's Am29821-25 bipolar registers in pinout/function, speed and output drive over full temperature and voltage supply extremes * IDT54/74FCT821A/823A/824A/825A equivalent to FASTTM speed * IDT54/74FCT821B/823B/824B/825B 25% faster than FAST * IDT54/74FCT821C/823C/824C/825C 40% faster than FAST * Buffered common Clock Enable (EN) and asynchronous Clear input (CLR) * IOL = 48mA (commercial) and 32mA (military) * Clamp diodes on all inputs for ringing suppression * CMOS power levels (1mW typ. static) * TTL input and output compatibility * CMOS output level compatible * Substantially lower input current levels than AMD's bipolar Am29800 series (5A max.) * Product available in Radiation Tolerant and Radiation Enhanced versions * Military product compliant to MIL-STD-883, Class B
The IDT54/74FCT800 series is built using an advanced dual metal CMOS technology. The IDT54/74FCT820 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The IDT54/ 74FCT821 are buffered, 10-bit wide versions of the popular `374 function. The IDT54/74FCT823 and IDT54/74FCT824 are 9-bit wide buffered registers with Clock Enable (EN) and Clear (CLR) - ideal for parity bus interfacing in high-performance microprogrammed systems. The IDT54/74FCT825 are 8-bit buffered registers with all the `823 controls plus multiple enables (OE1, OE2, OE3) to allow multiuser control of the interface, e.g., CS, DMA and RD/WR. They are ideal for use as an output port requiring HIGH IOL/IOH. All of the IDT54/74FCT800 high-performance interface family are designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes and all outputs are designed for low-capacitance bus loading in high-impedance state.
FUNCTIONAL BLOCK DIAGRAMS
IDT54/74FCT821/823/825
D0 EN DN
IDT54/74FCT824
D0 EN DN
CLR D CL Q D CL Q
CLR D CL Q D CL Q
CP Q
CP Q
CP Q
CP Q
CP
CP
OE Y0
The IDT logo is a registered trademark of Integrated Device Technology, Inc. FAST is a trademark of National Semiconductor Co.
OE
YN
2608 cnv* 01
Y0
YN
2608 cnv* 02
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1992 Integrated Device Technology, Inc.
MAY 1992
DSC-4618/2
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IDT54/74FCT821/823/824/825A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT54/74FCT821 10-BIT REGISTER
OE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 GND 1 2 3 4 P24-1 5 D24-1 6 E24-1 & 7 SO24-2 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 CP
D1 D0 OE NC VCC Y0 Y1
LOGIC SYMBOLS
INDEX
D2 D3 D4 NC D5 D6 D7
432 1 28 27 26 5 25 6 24 7 23 8 22 L28-1 9 21 20 10 19 11 1213 14 15 16 17 18
D8 D9 GND NC CP Y9 Y8
10 Y2 Y3 Y4 NC Y5 Y6 Y7 D D CP CP OE 10 Q Y
DIP/SOIC/CERPACK TOP VIEW
LCC TOP VIEW
2608 cnv* 03
IDT54/74FCT823/824 9-BIT REGISTERS
OE D0 D1 D2 D3 D4 D5 D6 D7 D8 CLR GND 1 2 3 4 P24-1 5 D24-1 6 SO24-2 & 7 E24-1 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 EN CP
D2 D3 D4 NC D5 D6 D7
432 1 28 27 26 5 25 6 24 7 23 8 22 L28-1 9 21 10 20 11 19 1213 14 15 16 17 18
D1 D0 OE NC VCC Y0 Y1
INDEX
Y2 Y3 Y4 NC Y5 Y6 Y7
D
9
Q CP EN CLR
D
9 Y
CP EN CLR OE
DIP/SOIC/CERPACK TOP VIEW
D8 CLR GND NC CP EN Y8
LCC TOP VIEW
2608 cnv* 04
IDT54/74FCT825 8-BIT REGISTER
OE1 OE2 D0 D1 D2 D3 D4 D5 D6 D7 CLR GND 1 2 3 4 P24-1 5 D24-1 6 E24-1 & 7 8 SO24-2 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC OE3 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 EN CP INDEX
D0 OE2 OE1 NC VCC OE3 Y0
D D1 D2 D3 NC D4 D5 D6 1 28 27 26 5 25 6 24 7 23 8 22 L28-1 9 21 10 20 11 19 1213 14 15 16 17 18 432 Y1 Y2 Y3 NC Y4 Y5 Y6
8
Q CP EN CLR
D
8
Y
CP EN CLR OE1 OE2 OE3
D7 CLR GND NC CP
DIP/SOIC/CERPACK TOP VIEW
LCC TOP VIEW
EN Y7
2608 cnv* 05
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IDT54/74FCT821/823/824/825A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PRODUCT SELECTOR GUIDE
Device 10-Bit
Non-inverting Inverting
FUNCTION TABLE(1) IDT54/74FCT821/823/825
8-Bit
OE CLR
9-Bit
54/74FCT824A/B/C
Inputs
EN
54/74FCT821A/B/C 54/74FCT823A/B/C 54/74FCT825A/B/C
DI L H X X X X L H L H
CP X X X X
Internal/ Outputs QI YI L H L L NC NC L H L H Z Z Z L Z NC Z Z L H
2608 tbl 01
H H H L H L H H L L
H H L L H H H H H H
L L X X H H L L L L
Function High Z Clear Hold Load
PIN DESCRIPTION
Name DI
CLR
I/O
I I
Description The D flip-flop data inputs. For both inverting and non-inverting registers, when the clear input is LOW and OE is LOW, the QI outputs are LOW. When the clear input is HIGH, data can be entered into the register. Clock Pulse for the Register; enters data into the register on the LOW-toHIGH transition. The register three-state outputs. Clock Enable. When the clock enable is LOW, data on the D I input is transferred to the QI output on the LOW-to-HIGH clock transition. When the clock enable is HIGH, the QI outputs do not change state, regardless of the data or clock input transitions. Output Control. When the OE input is HIGH, the Y I outputs are in the high impedance state. When the OE input is LOW, the TRUE register data is present at the Y I outputs.
2608 tbl 10
CP
I
NOTE: 2608 tbl 02 1. H = HIGH, L = LOW, X = Don't Care, NC = No Change, = LOW-to-HIGH Transition, Z = High Impedance
YI , YI
EN
O I
FUNCTION TABLE(1) IDT54/74FCT824
Inputs
OE CLR EN
DI L H X X X X L H L H
CP X X X X
Internal/ Outputs QI YI H L L L NC NC H L H L Z Z Z L Z NC Z Z H L
H H H L H L H H L L
H H L L H H H H H H
L L X X H H L L L L
Function High Z Clear Hold Load
OE
I
NOTE: 2608 tbl 03 1. H = HIGH, L = LOW, X = Don't Care, NC = No Change, = LOW-toHIGH Transition, Z = High Impedance
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IDT54/74FCT821/823/824/825A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Commercial -0.5 to +7.0 VTERM (2) Terminal Voltage with Respect to GND VTERM (3) Terminal Voltage -0.5 to VCC with Respect to GND TA Operating 0 to +70 Temperature TBIAS Temperature -55 to +125 Under Bias TSTG Storage -55 to +125 Temperature PT Power Dissipation 0.5 IOUT DC Output Current 120 Military -0.5 to +7.0 Unit V
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol
CIN COUT
-0.5 to VCC
V
Parameter(1) Input Capacitance Output Capacitance
Conditions VIN = 0V VOUT = 0V
Typ. 6 8
Max. 10 12
Unit
pF pF
-55 to +125 -65 to +135 -65 to +150 0.5 120
C C C
W mA
NOTE: 2608 tbl 05 1. This parameter is measured at characterization but not tested.
NOTES: 2608 tbl 04 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC - 0.2V Commercial: TA = 0C to +70C, VCC = 5.0V 5%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol VIH VIL II H II L IOZH IOZL VIK IOS VOH Clamp Diode Voltage Short Circuit Current Output HIGH Voltage VCC = Min., IN = -18mA VCC = Max.(3) , VO = GND IOH = -300A IOH = -15mA MIL. IOH = -24mA COM'L. VOL Output LOW Voltage VCC = 3V, VIN = VLC or VHC, IOL = 300A VCC = Min. VIN = VIH or VIL IOL = 300A IOL = 32mA MIL. IOL = 48mA COM'L. VCC = 3V, VIN = VLC or VHC, IOH = -32A VCC = Min. VIN = VIH or VIL Parameter Input HIGH Level Input LOW Level Input HIGH Current Input LOW Current Off State (High Impedance) Output Current VCC = Max. Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = VCC VI = 2.7V VI = 0.5V VI = GND VO = VCC VO = 2.7V VO = 0.5V VO = GND Min. 2.0 -- -- -- -- -- -- -- -- -- -- -75 VHC VHC 2.4 2.4 -- -- -- -- Typ.(2) -- -- -- -- -- -- -- -- -- -- -0.7 -120 VCC VCC 4.3 4.3 GND GND 0.3 0.3 Max. -- 0.8 5 5(4) -5(4) -5 10 10(4) -10(4) -10 -1.2 -- -- -- -- -- VLC VLC(4) 0.5 0.5
2608 tbl 06
Unit V V
A
A
V mA V
V
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. This parameter is guaranteed but not tested. 7.19
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IDT54/74FCT821/823/824/825A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = VCC - 0.2V
Symbol ICC ICC ICCD Parameter Quiescent Power Supply Current Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Test Conditions(1) VCC = Max. VIN VHC; V IN VLC VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open OE = EN = GND One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle OE = EN = GND One Bit Toggling at f i = 5MHz 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle OE = EN = GND Eight Bits Toggling at f i = 2.5MHz 50% Duty Cycle Min. -- -- VIN VHC VIN VLC -- Typ.(2) 0.2 0.5 0.15 Max. 1.5 2.0 0.25 Unit mA mA mA/ MHz
IC
Total Power Supply Current (6)
VIN VHC VIN VLC (FCT) VIN = 3.4V VIN = GND
--
1.7
4.0
mA
--
2.2
6.0
VIN VHC VIN VLC (FCT) VIN = 3.4V VIN = GND
--
4.0
7.8 (5)
--
6.2
16.8 (5)
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz.
2608 tbl 07
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IDT54/74FCT821/823/824/825A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT821A/ 823A/824A/825A Test Parameter Description Propagation Delay CP to Y I (OE = LOW) Conditions (1) Com'l.
Min.
(2)
IDT54/74FCT821B/ 823B/824B/825B Com'l.
(2)
IDT54/74FCT821C/ 823C/824C/825C Com'l.
(2)
Mil.
(2)
Mil.
(2)
Mil.
(2)
Max. Min.
Max. Min.
Max. Min.
Max. Min.
Max. Min.
Max.
Unit
tPLH tPHL
CL = 50pF RL = 500 CL = 300pF(3) RL = 500 CL = 50pF RL = 500
-- -- 4.0 2.0 4.0 2.0 -- 6.0 7.0 6.0
10.0 20.0 -- -- -- -- 14.0 -- -- -- 12.0 23.0 7.0 8.0
-- -- 4.0 2.0 4.0 2.0 -- 7.0 7.0 7.0 -- -- -- --
11.5 20.0 -- -- -- -- 15.0 -- -- -- 13.0 25.0 8.0 9.0
-- -- 3.0 1.5 3.0 0 -- 6.0 6.0 6.0 -- -- -- --
7.5 15.0 -- -- -- -- 9.0 -- -- -- 8.0 15.0 6.5 7.5
-- -- 3.0 1.5 3.0 0 -- 6.0 6.0 6.0 -- -- -- --
8.5 16.0 -- -- -- -- 9.5 -- -- -- 9.0 16.0 7.0 8.0
-- -- 3.0 1.5 3.0 0 -- 6.0 6.0 6.0 -- -- -- --
6.0 12.5 -- -- -- -- 8.0 -- -- -- 7.0 12.5 6.2 6.5
-- -- 3.0 1.5 3.0 0 -- 6.0 6.0 6.0 -- -- -- --
7.0 13.5 -- -- -- -- 8.5 -- -- -- 8.0 13.5 6.2 6.5
ns
tSU tH tSU tH tPHL
Set-up Time HIGH or LOW D i to CP Hold Time HIGH or LOW D I to CP Set-up Time HIGH or LOW
EN
ns ns ns ns ns ns ns ns ns
to CP
Hold Time HIGH or LOW EN to CP Propagation Delay, CLR to YI Recovery Time CLR to CP CP Pulse Width HIGH or LOW Pulse Width LOW
CLR
tREM tW tW tPZH tPZL
Output Enable Time OE to YI
CL = 50pF RL = 500 CL = 300pF(3) RL = 500 CL = 5pF(3) RL = 500 CL = 50pF RL = 500
-- -- -- --
tPHZ tPLZ
Output Disable Time OE to YI
ns
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not tested.
2608 tbl* 08
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IDT54/74FCT821/823/824/825A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
VCC 500 VIN Pulse Generator RT D.U.T. 50pF CL 500 V OUT 7.0V
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open
DEFINITIONS: 2608 tbl 09 CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
SET-UP, HOLD AND RELEASE TIMES
DATA INPUT t SU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. t REM 3V 1.5V 0V 3V 1.5V 0V tH 3V 1.5V 0V 3V 1.5V 0V
PULSE WIDTH
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
1.5V
t SU
tH
PROPAGATION DELAY
3V 1.5V tPLH OUTPUT t PLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V t PHL 0V VOH 1.5V VOL
ENABLE AND DISABLE TIMES
ENABLE CONTROL INPUT t PZL OUTPUT NORMALLY SWITCH LOW CLOSED t PZH OUTPUT SWITCH NORMALLY OPEN HIGH 3.5V 1.5V 0.3V t PHZ 0.3V 1.5V 0V V OH 0V t PLZ DISABLE 3V 1.5V 0V 3.5V V OL
SAME PHASE INPUT TRANSITION
NOTES 2608 drw 01 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0 MHz; ZO 50; tF 2.5ns; tR 2.5ns.
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IDT54/74FCT821/823/824/825A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION 2523 cnv*XX 11 IDT
Temp. Range FCT XXXX Device Type X Package X Process Blank B P D E L SO 821A 821B 821C 823A 823B 823C 824A 824B 824C 825A 825B 825C 54 74 Commercial MIL-STD-883, Class B Plastic DIP CERDIP CERPACK Leadless Chip Carrier Small Outline IC 10-Bit Non-Inverting Register Fast 10-Bit Non-Inverting Register Super Fast 10-Bit Non-Inverting Register 9-Bit Non-Inverting Register Fast 9-Bit Non-Inverting Register Super Fast 9-Bit Non-Inverting Register 9-Bit Inverting Register Fast 9-Bit Inverting Register Super Fast 9-Bit Inverting Register 8-Bit Non-Inverting Register Fast 8-Bit Non-Inverting Register Super Fast 8-Bit Non-Inverting Register -55C to +125C 0C to +70C
2608 cnv* 11
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