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VND830LSP-E
DOUBLE CHANNEL HIGH SIDE DRIVER
Table 1. General Features
Type VND830LSP-E RDS(on) 60m (*)
Figure 1. Package
Iout
18A (*)
VCC
36V
(*) Per each channel
s
CMOS COMPATIBLE INPUTS OPEN DRAIN STATUS OUTPUTS s ON STATE OPEN LOAD DETECTION s OFF STATE OPEN LOAD DETECTION s SHORTED LOAD PROTECTION s UNDERVOLTAGE AND OVERVOLTAGE SHUTDOWN s LOSS OF GROUND PROTECTION s VERY LOW STAND-BY CURRENT
s
10
1
PowerSO-10TM
REVERSE BATTERY PROTECTION (**) s IN COMPLIANCE WITH THE 2002/95/EC EUROPEAN DIRECTIVE
s
DESCRIPTION The VND830LSP-E is a monolithic device made by using STMicroelectronics VIPower M0-3 Technology, intended for driving any kind of load with one side connected to ground. Active V CC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient
compatibility table). Active current limitation combined with thermal shutdown and automatic restart protects the device against overload. The device detects open load condition both in on and off state. The openload threshold is aimed at detecting the 5W/12V standard bulb as an openload fault in the on state. Device automatically turns off in case of ground pin disconnection.
Table 2. Order Codes
Package PowerSO-10TM
Note: (**) See application schematic at page 9
Tube VND830LSP-E
Tape and Reel VND830LSPTR-E
Rev. 1 October 2004 1/20
VND830LSP-E
Figure 2. Block Diagram
VCC
VCC CLAMP
OVERVOLTAGE UNDERVOLTAGE
GND INPUT1 STATUS1
CLAMP 1 OUTPUT1 DRIVER 1 CLAMP 2 CURRENT LIMITER 1 OVERTEMP. 1 LOGIC OPENLOAD ON 1 CURRENT LIMITER 2 DRIVER 2 OUTPUT2
INPUT2 OPENLOAD OFF 1 STATUS2 OPENLOAD OFF 2 OVERTEMP. 2 OPENLOAD ON 2
Table 3. Absolute Maximum Ratings
Symbol VCC Parameter Value Unit
DC Supply Voltage Reverse DC Supply Voltage DC Reverse Ground Pin Current DC Output Current Reverse DC Output Current DC Input Current DC Status Current Electrostatic Discharge R=1.5K; C=100pF) - INPUT (Human Body Model:
41 - 0.3 - 200 Internally Limited -6 +/- 10 +/- 10
V V mA A A mA mA
- VCC - IGND IOUT - IOUT IIN ISTAT
4000 4000 5000 5000 74 52 Internally Limited - 40 to 150 - 55 to 150
V V V V W mJ C C C
VESD
- STATUS - OUTPUT - VCC
Ptot EMAX Tj Tc Tstg
Power Dissipation TC=25C Maximum Switching Energy (L=0.14mH; RL=0; Vbat=13.5V; Tjstart=150C; IL=14A) Junction Operating Temperature Case Operating Temperature Storage Temperature
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Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins
GROUND INPUT 1 STATUS 1 STATUS 2 INPUT 2
6 7 8 9 10 11 VCC
5 4 3 2 1
OUTPUT 1 OUTPUT 1 N.C. OUTPUT 2 OUTPUT 2
Connection / Pin Status Floating X To Ground
N.C. X X
Output X
Input X Through 10K resistor
Figure 4. Current and Voltage Conventions
IS IIN1 INPUT 1 VIN1 VSTAT1 ISTAT1 STATUS 1 IIN2 INPUT 2 VIN2 ISTAT2 STATUS 2 VSTAT2 GND IGND OUTPUT 2 IOUT2 VOUT2 OUTPUT 1 VOUT1 VCC IOUT1
VF1 (*)
VCC
(*) VFn = VCCn - VOUTn during reverse battery condition
Table 4. Thermal Data
Symbol Rthj-case Rthj-amb Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient Value 2 52 (1) 37 (2) Unit C/W C/W
Note: 1. When mounted on a standard single-sided FR-4 board with 0.5 cm 2 of Cu (at least 35m thick). Horizontal mounting and no artificial air flow.
Note: 2. When mounted on a standard single-sided FR-4 board with 6 cm 2 of Cu (at least 35m thick). Horizontal mounting and no artificial air flow.
3/20
VND830LSP-E
ELECTRICAL CHARACTERISTICS (8VSymbol VCC (**) Parameter Test Conditions Min. Typ. Max. Unit
Operating Supply Voltage Undervoltage Shut-down Overvoltage Shut-down On State Resistance IOUT =2A; Tj=25C IOUT =2A; VCC> 8V Off State; VCC=13V; VIN=VOUT=0V
5.5 3 36
13 4
36 5.5
V V V
VUSD (**) VOV (**) RON
60 120 12 12 5 0 -75 40 25 7 50 0 5 3
m m A A mA A A A A
IS (**)
Supply Current
Off State; VCC=13V; Tj =25C; VIN=VOUT =0V On State; VCC=13V
IL(off1) IL(off2) IL(off3) IL(off4)
Off State Output Current Off State Output Current Off State Output Current Off State Output Current
VIN=VOUT=0V; VCC=36V; Tj=125C VIN=0V; VOUT =3.5V VIN=VOUT=0V; VCC=13V; Tj =125C VIN=VOUT=0V; VCC=13V; Tj =25C
Note: (**) Per device.
Table 6. Protection (see note 1)
Symbol TTSD Parameter Test Conditions Min. Typ. Max. Unit
Shut-down Temperature Reset Temperature Thermal Hysteresis Status Delay in Overload Conditions Current limitation Turn-off Output Clamp Voltage
150 135 7
175
200
C C
TR Thyst tSDL Ilim Vdemag
15 20
C s A A V
Tj>TTSD
VCC=13V 5.5V < VCC < 36V IOUT =2A; L= 6mH VCC-41 18 23
29 29
VCC-48 VCC-55
Note: 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles
Table 7. VCC - Output Diode
Symbol VF Parameter Forward on Voltage Test Conditions -IOUT=1.3A; Tj=150C Min Typ Max 0.6 Unit V
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VND830LSP-E
ELECTRICAL CHARACTERISTICS (continued) Table 8. Status Pin
Symbol VSTAT ILSTAT CSTAT VSCL Parameter Test Conditions Status Low Output Voltage ISTAT = 1.6 mA Status Leakage Current Normal Operation; VSTAT= 5V Status Pin Input Normal Operation; VSTAT= 5V Capacitance ISTAT = 1mA Status Clamp Voltage ISTAT = - 1mA Min Typ Max 0.5 10 100 6 6.8 -0.7 8 Unit V A pF V V
Table 9. Switching (V CC=13V)
Symbol td(on) td(off) Parameter Turn-on Delay Time Turn-off Delay Time Test Conditions RL=13 from VIN rising edge to VOUT=1.3V RL=13 from VIN falling edge to VOUT=11.7V RL=13 from VOUT=1.3V to VOUT=10.4V RL=13 from VOUT=11.7V to VOUT=1.3V Min Typ 30 30 See relative diagram See relative diagram Max Unit s s V/s
dVOUT /dt(on) Turn-on Voltage Slope
dVOUT /dt(off) Turn-off Voltage Slope
V/s
Table 10. Openload Detection
Symbol IOL tDOL(on) VOL TDOL(off) Parameter Openload ON State Detection Threshold Openload ON State Detection Delay Openload OFF State Voltage Detection Threshold Openload Detection Delay at Turn Off Test Conditions VIN=5V IOUT=0A VIN=0V 1.5 2.5 Min 0.6 Typ 0.9 Max 1.2 200 Unit A s V s
3.5 1000
Table 11. Logic Input
Symbol VIL IIL VIH IIH VI(hyst) VICL Parameter Input Low Level Low Level Input Current Input High Level High Level Input Current Input Hysteresis Voltage Input Clamp Voltage Test Conditions VIN = 1.25V VIN = 3.25V IIN = 1mA IIN = -1mA 0.5 6 6.8 -0.7 Min 1 3.25 10 8 Typ Max 1.25 Unit V A V A V V V
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Figure 5.
OPEN LOAD STATUS TIMING (with external pull-up)
VOUT > VOL VINn IOUT< IOL Tj > TTSD VINn
OVER TEMP STATUS TIMING
VSTATn
VSTATn tSDL tDOL(off) tDOL(on) tSDL
Table 12. Truth Table
CONDITIONS Normal Operation INPUT L H L H H L H L H L H L H L H OUTPUT L H L X X L L L L L L H H L H SENSE H H H (Tj < TTSD) H (Tj > TTSD) L H L X X H H L H H L
Current Limitation
Overtemperature Undervoltage Overvoltage Output Voltage > VOL Output Current < IOL
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VND830LSP-E
Figure 6. Switching Time Waveforms
VOUTn 90% 80%
dVOUT/dt(on)
dVOUT/dt(off)
10% t VINn
td(on)
td(off)
t
Table 13. Electrical Transient Requirements On V CC Pin
ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 CLASS C E I -25 V +25 V -25 V +25 V -4 V +26.5 V II -50 V +50 V -50 V +50 V -5 V +46.5 V TEST LEVELS III -75 V +75 V -100 V +75 V -6 V +66.5 V TEST LEVELS RESULTS II III C C C C C C C C C C E E IV -100 V +100 V -150 V +100 V -7 V +86.5 V Delays and Impedance 2 ms 10 0.2 ms 10 0.1 s 50 0.1 s 50 100 ms, 0.01 400 ms, 2
I C C C C C C
IV C C C C C E
CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device.
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VND830LSP-E
Figure 7. Waveforms
NORMAL OPERATION INPUTn OUTPUT VOLTAGEn STATUSn UNDERVOLTAGE VCC VUSD INPUTn OUTPUT VOLTAGEn STATUSn undefined VUSDhyst
OVERVOLTAGE VCCVOL VOL VCC>VOV
OPEN LOAD without external pull-up INPUTn OUTPUT VOLTAGEn STATUSn OVERTEMPERATURE Tj INPUTn OUTPUT CURRENTn STATUSn TTSD TR
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VND830LSP-E
Figure 8. Application Schematic
+5V +5V +5V VCC Rprot STATUS1 Dld C Rprot INPUT1 OUTPUT1 Rprot STATUS2
Rprot
INPUT2
GND
OUTPUT2
RGND VGND
DGND
GND PROTECTION REVERSE BATTERY
NETWORK
AGAINST
resistor then the ST suggests to utilize Solution 2 (see below). Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1k) should be inserted in parallel to DGND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected.
Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND 600mV / IS(on)max. 2) RGND (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device's datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same
LOAD DUMP PROTECTION
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table.
C I/Os PROTECTION:
If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up.
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VND830LSP-E
The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 65k.
Recommended Rprot value is 10k.
OPEN LOAD DETECTION IN OFF STATE
Off state open load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements:
1) no false open load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition VOUT=(VPU/(RL+RPU))RLFigure 9. Open Load detection in off state
V batt.
VPU
VCC RPU INPUT DRIVER + LOGIC OUT + R STATUS VOL RL IL(off2)
GROUND
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VND830LSP-E
Figure 10. Off State Output Current
IL(off1)
1.35 1.2 1.05 0.9 3.75 0.75 3 0.6 2.25 0.45 0.3 0.15 0 -50 -25 0 25 50 75 100 125 150 175 1.5 0.75 0 -50 -25 0 25 50 75 100 125 150 175
Figure 13. High Level Input Current
Iih (A)
6 5.25
Off State Vcc=13V Vin=Vout=0V
Vin=3.25V
4.5
Tc (C)
Tc (C)
Figure 11. Input Clamp Voltage
Vicl (V)
8 7.75
Figure 14. Status Leakage Current
Ilstat (A)
0.07
0.06
Iin=1mA
7.5
0.05
Vstat=5V
7.25
0.04
7
0.03
6.75 6.5 6.25 6 -50 -25 0 25 50 75 100 125 150 175
0.02
0.01
0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 12. Status Low Output Voltage
Vstat (V)
0.8 0.7
Figure 15. Status Clamp Voltage
Vscl (V)
8 7.75
Istat=1.6mA
0.6 0.5 0.4 0.3 0.2 0.1 0 -50 -25 0 25 50 75 100 125 150 175 7.5 7.25 7 6.75 6.5 6.25 6 -50
Istat=1mA
-25
0
25
50
75
100
125
150
175
Tc (C)
Tc (C)
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VND830LSP-E
Figure 16. On State Resistance Vs Tcase
Ron (mOhm)
100 90 80 70 60 50 40 30 40 20 10 0 -50 -25 0 25 50 75 100 125 150 175 20 0 0 5 10 15 20 25 30 35 40 100 80 60
Figure 19. On State Resistance Vs VCC
Ron (mOhm)
160 140
Iout=2A Vcc=13V
Iout=2A
120
Tc=150C
Tc=25C Tc= -40C
Tc (C)
Vcc (V)
Figure 17. Openload On State Detection Threshold
Iol (A)
2 1.75
Figure 20. Openload Off State Detection Threshold
Vol (V)
5 4.5
Vin=5V
1.5
Vin=0V
4 3.5
1.25 1 0.75 0.5
3 2.5 2 1.5 1
0.25 0 -50 -25 0 25 50 75 100 125 150 175
0.5 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 18. Input High Level
Vih (V)
4 3.8 3.6
Figure 21. Input Low Level
Vil (V)
2.25 2.125 2
3.4 3.2 3 2.8 2.6 1.5 2.4 2.2 2 -50 -25 0 25 50 75 100 125 150 175 1.375 1.25 -50 -25 0 25 50 75 100 125 150 175 1.875 1.75 1.625
Tc (C)
Tc (C)
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VND830LSP-E
Figure 22. Input Hysteresis Voltage
Vihyst (V)
1.4 1.3 1.2 1.1 42.5 1 40 0.9 37.5 0.8 0.7 0.6 0.5 -50 -25 0 25 50 75 100 125 150 175 35 32.5 30 -50 -25 0 25 50 75 100 125 150 175
Figure 25. Overvoltage Shutdown
Vov
50 47.5 45
Tc (C)
Tc (C)
Figure 23. Turn-on Voltage Slope
dVout/dt(on) (V/ms)
800 700 600 500 400 300 200 100 0 -50 -25 0 25 50 75 100 125 150 175
Figure 26. Turn-off Voltage Slope
dVout/dt(off) (V/ms)
800 700 600 500 400 300 200 100 0 -50 -25 0 25 50 75 100 125 150 175
Vcc=13V Rl=6.5Ohm
Vcc=13V Rl=6.5Ohm
Tc (C)
Tc (C)
Figure 24. ILIM Vs Tcase
Ilim (A)
35 32.5
Vcc=13V
30 27.5 25 22.5 20 17.5 15 12.5 10 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
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VND830LSP-E
Figure 27. Maximum turn off current versus load inductance
ILMAX (A) 100
10
A B C
1 0.01
0.1
1 L(mH)
10
100
A = Single Pulse at TJstart=150C B= Repetitive pulse at T Jstart=100C C= Repetitive Pulse at T Jstart=125C Conditions: VCC=13.5V
Values are generated with R L=0 In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C.
VIN, IL Demagnetization Demagnetization Demagnetization
t
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VND830LSP-E
PowerSO-10TM Thermal Data Figure 28. PowerSO-10TM PC Board
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm, Cu thickness=35m, Copper areas: from minimum pad lay-out to 8cm2).
Figure 29. Rthj-amb Vs PCB copper area in open box free air condition
RTHj_amb (C/W)
55
Tj-Tamb=50C
50 45 40 35 30
0 2 4 6 8 10
PCB Cu heatsink area (cm^2)
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VND830LSP-E
Figure 30. PowerSO-10 Thermal Impedance Junction Ambient Single Pulse
ZTH (C/W) 1000
100
Footprint 6 cm2
10
1
0.1
0.01 0.0001 0.001 0.01 0.1 1 Time (s) 10 100 1000
Figure 31. Thermal fitting model of a double channel HSD in PowerSO-10
Pulse calculation formula
Z TH = R TH + Z THtp ( 1 - )
where
= tp T
Table 14. Thermal Parameter
Tj_1
Pd1 C1 C2 C1 C2 C3 C4 C5 C6
R1
R2
R3
R4
R5
R6
Tj_2
R1 Pd2
R2
T_amb
Area/island (cm2) R1 (C/W) R2 (C/W) R3( C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1 (W.s/C) C2 (W.s/C) C3 (W.s/C) C4 (W.s/C) C5 (W.s/C) C6 (W.s/C)
Footprint 0.05 0.3 0.3 0.8 12 37 0.001 5.00E-03 0.02 0.3 0.75 3
6
22
5
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VND830LSP-E
PACKAGE MECHANICAL Table 15. PowerSO-10TM Mechanical Data
Symbol A A (*) A1 B B (*) C C (*) D D1 E E2 E2 (*) E4 E4 (*) e F F (*) H H (*) h L L (*) a (*)
Note: (*) Muar only POA P013P
millimeters Min 3.35 3.4 0.00 0.40 0.37 0.35 0.23 9.40 7.40 9.30 7.20 7.30 5.90 5.90 1.27 1.25 1.20 13.80 13.85 0.50 1.20 0.80 0 2 1.80 1.10 8 8 1.35 1.40 14.40 14.35 Typ Max 3.65 3.6 0.10 0.60 0.53 0.55 0.32 9.60 7.60 9.50 7.60 7.50 6.10 6.30
Figure 32. PowerSO-10TM Package Dimensions
B
0.10 A B
10
H
E
E2
E4
1
SEATING PLANE e
0.25
B
DETAIL "A"
A
C D = D1 = = = SEATING PLANE
h
A F A1
A1
L DETAIL "A"
P095A
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VND830LSP-E
Figure 33. PowerSO-10TM Suggested Pad Layout And Tube Shipment (No Suffix)
14.6 - 14.9 10.8 - 11 6.30
A A C C
CASABLANCA
B
MUAR
0.67 - 0.73 1 2 3 4 5 10 9 8 7 6 0.54 - 0.6
B
9.5
All dimensions are in mm.
1.27
Base Q.ty Bulk Q.ty Tube length ( 0.5) Casablanca Muar 50 50 1000 1000 532 532
A
B
C ( 0.1) 0.8 0.8
10.4 16.4 4.9 17.2
Figure 34. Tape And Reel Shipment (suffix "TR") REEL DIMENSIONS
Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 600 600 330 1.5 13 20.2 24.4 60 30.4
All dimensions are in mm.
TAPE DIMENSIONS
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) 24 4 24 1.5 1.5 11.5 6.5 2
End
All dimensions are in mm.
Start Top cover tape 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min No components Components No components
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VND830LSP-E
REVISION HISTORY
Date Oct. 2004 Revision 1 - First Issue. Description of Changes
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VND830LSP-E
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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