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Hyundai Micro Electronics
GMS81C2020/GMS81C2120
GMS81C2020 / GMS81C2120
CMOS Single-Chip 8-Bit Microcontroller with A/D Converter & VFD Driver
1. OVERVIEW
1.1 Description
The GMS81C2020 and GMS81C2120 are an advanced CMOS 8-bit microcontroller with 20K/12K bytes of ROM. These are a powerful microcontroller which provides a highly flexible and cost effective solution to many VFD applications. These provide the following standard features: 20K/12K bytes of ROM, 448 bytes of RAM, 8-bit timer/counter, 8-bit A/D converter, 10-bit High Speed PWM Output, Programmable Buzzer Driving Port, 8-bit Basic Interval Timer, 7-bit Watch dog Timer, 8-bit, Serial Peripheral Interface, on-chip oscillator and clock circuitry. They also come with high voltage I/O pins that can directly drive a VFD(Vacuum Fluorescent Display). In addition, the GMS81C2020 and GMS81C2120 support power saving modes to reduce power consumption. This document is only explained for the base of GMS81C2020(GMS81C2120), the eliminated functions are same as below. Device name
GMS81C2020 GMS81C2012 *GMS87C2020 GMS81C2120 GMS81C2112 *GMS87C2120
ROM Size
20Kbytes 12Kbytes 20Kbytes (EPROM) 20Kbytes 12Kbytes 20Kbytes (EPROM)
RAM Size
448bytes 448bytes 448bytes 448bytes 448bytes 448bytes
Ports
R0,R1,R2,R3,R4,R5,R6,R7 R0,R2,R3,R5,R6 R0,R1,R2,R3,R4,R5,R6,R7 R0,R1,R2,R3,R4,R5,R6,R7 R0,R2,R3,R5,R6 R0,R1,R2,R3,R4,R5,R6,R7
Package
64 SDIP, 64MQFP, 64LQFP, 64TQFP 64SDIP, 64MQFP, 64LQFP, 64TQFP 64SDIP, 64MQFP, 64LQFP, 64TQFP 42SDIP, 44MQFP, 40PDIP 42SDIP, 44MQFP, 40PDIP 42SDIP, 44MQFP, 40PDIP
[The * Mark Devices are OTP Version]
Nov. 1999 Ver 0.0
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Hyundai Micro Electro nics
1.2 Features
* 20K/12K bytes ROM(EPROM) * 448 Bytes of On-Chip Data RAM (Including STACK Area) * Minimum Instruction Execution time : - 1uS at 4MHz ( 2cycle NOP Instruction ) * One 8-Bit Basic Interval Timer * One 7-Bit Watch Dog Timer * Two 8-Bit Timer/Counters * 10-Bit High Speed PWM Output * One 8-bit Serial Peripheral Interface * Two external interrupt ports * One Programmable 6-Bit Buzzer Driving port * 60 I/O Lines - 56 Programmable I/O pins 30 high-voltage pins (40V,max) - 3 Input Only pins : 1 high-voltage pin - 1 Output Only pin * Eight Interrupt Sources - 2 By External Sources (INT0, INT1) - 2 By Timer/Counter Sources (Timer0, Timer1) Device name
GMS81C2020 GMS81C2012 GMS81C2120 GMS81C2112
- 4 By Functional Sources (SPI,ADC,WDT,BIT) * 12-Channel 8-Bit On-Chip Analog to Digital Converter * Oscillatior : - Crystal - Ceramic Resonator - External RC Oscillator - Internal RCWDT Oscillatior * Low Power Dissipation Modes - STOP mode - Wake-up Timer Mode - Standby Mode - Watch Mode - Subactive Mode * Operating Voltage : 4.0V ~ 5.5V (at 4.5MHz) : * Operating Frequency : 0.4MHz ~ 4.5MHz * Subclock : 32.768KHz Crystal Oscillator * Enhanced EMS Improvement Power Fail Processor ( Noise Immunity Circuit )
Total I/O
60 pins 60 pins 38 pins 38 pins
Normal I/O
26 pins 26 pins 13 pins 13 pins
High Voltage I/O
30 pins 30 pins 21 pins 21 pins
Input Only
3 pins 3 pins 3 pins 3 pins
Output Only
1 pins 1 pins 1 pins 1 pins
*w here, T otal I/O is all ports except pow er and ground ports
Development Tools
The GMS800 family is supported by a full-featured macro assembler, an in-circuit emulators CHOICE-Dr.TM, and add-on board type OTP writer Dr.WriterTM .
In Circuit Emulator Assembler OTP Writer
CHOICE-Dr. HME Macro Assembler Dr.Writer
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GMS81C2020/GMS81C2120
2. BLOCK DIAGRAM (GMS81C2020)
R07 R06 R05 R04 R03/BUZO R02/EC0 R01/INT1 R00/INT0
ADC Power Supply AVDD AVSS
R10~R17
R20~R27
R30~R35
Vdisp/RA
Driver Buzzer
R0
R1
R2
R3
PSW
ALU
Accumulator
Stack Pointer
PC Data Memory (448 bytes) Program Memory Data Table
Interrupt Controller
S yste m c o n tro lle r S yste m C lo ck C o n tro lle r S u b S yste m C lo ck C o n tro lle r T im in g g e n e ra to r C lo c k G e n e ra to r
8-b it B a sic In te rva l T im e r Watchdog Timer 8-bit Timer/ Counter 8-bit serial Interface 8-bit PWM 8-bit ADC PC
R4
R5
R6
R7
RESETB
R40 / T0O R41 R42 R43
Power Supply
R50 R51 R52 R53 / SCLK R54 / SIN R55 / SOUT R56 / PWM1O/T1O R57
R60 / AN0 R61 / AN1 R62 / AN2 R63 / AN3 R64 / AN4 R65 / AN5 R66 / AN6 R67 / AN7
R70 / AN8 R71 / AN9 R72 / AN10 R73 / AN11
XO
SXO
XI
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VDD VSS
SXI
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3. PIN ASSIGNMENT (GMS81C2020)
64SDIP
R40 R41 R42 R43 R50 R51 R52 R53 SCLK SIN R54 SOUT R55 PWM1O/T1O R56 R57 RESETB XI XO VSS R74 SXI R75 SXO AVSS R60 AN0 R61 AN1 R62 AN2 R63 AN3 R64 AN4 R65 AN5 R66 AN6 R67 AN7 R70 AN8 R71 AN9 R72 AN10 R73 AN11 AVDD T0O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RA R35 R34 R33 R32 R31 R30 R27 R26 R25 R24 R23 R22 R21 R20 R17 R16 R15 R14 R13 R12 R11 R10 R07 R06 R05 R04 R03 R02 R01 R00 VDD Vdisp
BUZO EC0 INT1 INT0
64MQFP
R27 R26 R25 R24 R23 R22 R21 R20 R17 R16 R15 R14 R13 R12 R11 R10 R07 R06 R05 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Vdisp T0O
4
SCLK SIN SOUT PWM1O/T1O
R52 R53 R54 R55 R56 R57 RESETB XI XO VSS SXI R74 SXO R75 AVSS AN0 R60 AN1 R61 AN2 R62 AN3 R63 R64 AN4 AN5 R65
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
R30 R31 R32 R33 R34 R35 RA R40 R41 R42 R43 R50 R51
52 53 54 55 56 57 58 59 60 61 62 63 64
32 31 30 29 28 27 26 25 24 23 22 21 20
R04 R03 R02 R01 R00 VDD AVDD R73 R72 R71 R70 R67 R66
BUZO EC0 INT1 INT0
AN11 AN10 AN9 AN8 AN7 AN6
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GMS81C2020/GMS81C2120
64LQFP
R26 R25 R24 R23 R22 R21 R20 R17 R16 R15 R14 R13 R12 R11 R10 R07 R27 R30 R31 R32 R33 R34 R35 RA R40 R41 R42 R43 R50 R51 R52 R53 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
Vdisp T0O
SCLK
R06 R05 R04 R03 R02 R01 R00 VDD AVDD R73 R72 R71 R70 R67 R66 R65
BUZO EC0 INT1 INT0 AN11 AN10 AN9 AN8 AN7 AN6 AN5
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SIN SOUT PWM1O/T1O
R54 R55 R56 R57 RESETB XI XO VSS R74 SXI R75 SXO AVSS R60 AN0 R61 AN1 R62 AN2 R63 AN3 R64 AN4
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4. BLOCK DIAGRAM (GMS81C2120)
R07 R06 R05 R04 R03/BUZO R02/EC0 R01/INT1 R00/INT0
ADC Power Supply AVDD AVSS
R20~R27
R30~R34
Vdisp/RA
Driver Buzzer
R0
R2
R3
PSW
ALU
Accumulator
Stack Pointer
PC Data Memory (448 bytes) Program Memory Data Table
Interrupt Controller
S yste m c o n tro lle r S yste m C lo ck C o n tro lle r S u b S yste m C lo ck C o n tro lle r T im in g g e n e ra to r C lo c k G e n e ra to r
8-b it B a sic In te rva l T im e r Watchdog Timer 8-bit Timer/ Counter 8-bit serial Interface 8-bit PWM 8-bit ADC PC
R5
R6
Power Supply
R53 / SCLK R54 / SIN R55 / SOUT R56 / PWM1O/T1O R57
R60 / AN0 R61 / AN1 R62 / AN2 R63 / AN3 R64 / AN4 R65 / AN5 R66 / AN6 R67 / AN7
XO
RESETB
SXO
XI
6
VDD VSS
SXI
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GMS81C2020/GMS81C2120
5. PIN ASSIGNMENT (GMS81C2120)
42PDIP
Vdisp SCLK SIN SOUT PWM1O/T1O RA R53 R54 R55 R56 R57 RESETB XI XO VSS AVSS R60 AN0 R61 AN1 R62 AN2 R63 AN3 R64 AN4 R65 AN5 R66 AN6 R67 AN7 AVDD VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 R34 R33 R32 R31 R30 R27 R26 R25 R24 R23 R22 R21 R20 R07 R06 R05 R04 R03 R02 R01 R00
BUZO EC0 INT1 INT0
44 43 42 41 40 39 38 37 36 35 34
NC R56 R55 R54 R53 RA R34 R33 R32 R31 R30
PWM1O/T1O SOUT SIN SCLK
44MQFP
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INT0 INT1 EC0 BUZO
AN5 AN6 AN7
R65 R66 R67 AVDD VDD R00 R01 R02 R03 R04 NC
12 13 14 15 16 17 18 19 20 21 22
R57 RESETB XI XO VSS AVSS R60 AN0 AN1 R61 R62 AN2 R63 AN3 AN4 R64
1 2 3 4 5 6 7 8 9 10 11
33 32 31 30 29 28 27 26 25 24 23
R27 R26 R25 R24 R23 R22 R21 R20 R07 R06 R05
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40PDIP
Vdisp SCLK SIN SOUT PWM1O/T1O RA R53 R54 R55 R56 R57 RESETB XI XO VSS R60 AN0 R61 AN1 R62 AN2 R63 AN3 R64 AN4 R65 AN5 R66 AN6 R67 AN7 VDD R00 INT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 R34 R33 R32 R31 R30 R27 R26 R25 R24 R23 R22 R21 R20 R07 R06 R05 R04 R03 R02 R01
BUZO EC0 INT1
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6. PACKAGE DIMENSION
64SDIP
UNIT: INCH
2.280 2.260 0.205 max. 0.750 BSC 0.680 0.660
0.140 0.120
min. 0.015
0.022 0.016
0.050 0.030
0.070 BSC
0-15
0.012 0.008
64MQFP
24.15 23.65 20.10 19.90
UNIT: MM
18.15 17.65 14.10 13.90
0-7 SEE DETAIL "A" 0.36 0.10 1.03 0.73 1.95 REF 0.50 0.35 1.00 BSC DETAIL "A" 0.23 0.13
3.18 max.
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64LQFP
12.00 BSC 10.00 BSC
UNIT: MM
12.00 BSC
10.00 BSC
1.45 1.35
0-7 SEE DETAIL "A" 0.15 0.05 0.75 0.45 1.00 REF DETAIL "A"
1.60 max. 0.38 0.22 0.50 BSC
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7. PIN DESCRIPTIONS (GMS81C2020)
VDD: Supply voltage. VSS: Circuit ground. AVDD: Supply voltage to the ladder resistor of ADC circuit. To enhance the resolution of analog to digital converter, use independent power source as well as possible, other than digital power source. AVSS: ADC circuit ground. RESETB: Reset the MCU. XI: Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XO: Output from the inverting oscillator amplifier. SXI: Input to the internal subsystem clock operating circuit. In addition, SXI serves the R74 pin when selected by the code option. SXO: Output from the inverting subsystem oscillator amplifier. In addition, SXO serves the R75 pin when selected by the code option. RA(Vdisp): RA is one-bit high-voltage input only port pin. In addition, RA serves the functions of the Vdisp special features. Vdisp is used as a high-voltage input power supply pin when selected by the mask option..
Port pin RA Alternate function
I/O port. R3 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. R40~R43: R4 is an 8-bit CMOS bidirectional I/O port. R4 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R4 serves the functions of the following special features.
Port pin R40 Alternate function T0O (Timer/Counter 0 output)
R50~R57: R5 is an 8-bit CMOS bidirectional I/O port. R5 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R5 serves the functions of the various following special features.
Port pin R53 R54 R55 R56 Alternate function SCLK (Serial clock) SIN (Serial data input) SOUT (Serial data output) PWM1O (PWM1 Output) T1O (Timer/Counter 1 output)
R60~R67: R6 is an 8-bit CMOS bidirectional I/O port. R6 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R6 is shared with the ADC input.
Port pin R60 R61 R62 R63 R64 R66 R66 R67 Alternate function AN0 (Analog Input 0) AN1 (Analog Input 1) AN2 (Analog Input 2) AN3 (Analog Input 3) AN4 (Analog Input 4) AN5 (Analog Input 5) AN6 (Analog Input 6) AN7 (Analog Input 7)
Vdisp (High-voltage input power supply)
R00~R07: R0 is an 8-bit high-voltage CMOS bidirectional I/O port. R0 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R0 serves the functions of the various following special features.
Port pin R00 R01 R02 R03 Alternate function INT0 (External interrupt 0) INT1 (External interrupt 1) EC0 (Event counter input) BUZO (Buzzer driver output)
R70~R73: R7 is an 8-bit CMOS bidirectional I/O port. R6 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R7 is shared with the ADC input.
R10~R17: R1 is an 8-bit high-voltage CMOS bidirectional I/O port. R1 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. R20~R27: R2 is an 8-bit high-voltage CMOS bidirectional I/O port. R2 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. R30~R35: R3 is an 6-bit high-voltage CMOS bidirectional
Port pin R70 R71 R72 R73
Alternate function AN8 (Analog Input 8) AN9 (Analog Input 9) AN10 (Analog Input 10) AN11 (Analog Input 11)
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PIN NAME VDD VSS RA (Vdisp) RESETB XI XO R00 (INT0) R01 (INT1) R02 (EC0) R03 (BUZO) R04~R07 R10~R17 R20~R27 R30~R35 R40 (T0O) R41~R43 R50~R52 R53 (SCLK) R54 (SIN) R55 (SOUT) R56 (PWM1O/T1O) R57 R60~R67 (AN0~AN7) R70~R73 (AN8~AN11) AVDD AVSS
In/Out I(I) I I O I/O (I) I/O (I) I/O (I) I/O (O) I/O I/O I/O I/O I/O (O) I/O I/O I/O (I/O) I/O (I) I/O (O) I/O (O) I/O I/O (I) I/O (I) 8-bit general I/O ports 4-bit general I/O ports Supply voltage input pin for ADC Ground level input pin for ADC 8-bit general I/O ports 8-bit high-voltage I/O ports 8-bit high-voltage I/O ports 6-bit high-voltage I/O ports 4-bit general I/O ports 8-bit high-voltage I/O ports Supply voltage Circuit ground 1-bit high-voltage Input only port Reset signal input Oscillation input Oscillation output
Function
High-voltage input power supply pin
External interrupt 0 input External interrupt 1 input Timer/Counter 0 external input Buzzer driving output
Timer/Counter 0 output
Serial clock source Serial data input Serial data output PWM 1 pulse output /Timer/Counter 1 output
Analog voltage input
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GMS81C2020/GMS81C2120
8. PIN DESCRIPTIONS (GMS81C2120)
VDD: Supply voltage. VSS: Circuit ground. AVDD: Supply voltage to the ladder resistor of ADC circuit. To enhance the resolution of analog to digital converter, use independent power source as well as possible, other than digital power source. AVSS: ADC circuit ground. RESETB: Reset the MCU. XI: Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XO: Output from the inverting oscillator amplifier. RA(Vdisp): RA is one-bit high-voltage input only port pin. In addition, RA serves the functions of the Vdisp special features. Vdisp is used as a high-voltage input power supply pin when selected by the mask option..
Port pin RA Alternate function Port pin R53 R54 R55 R56 Alternate function SCLK (Serial clock) SIN (Serial data input) SOUT (Serial data output) PWM1O (PWM1 Output) T1O (Timer/Counter 1 output)
tions of the various following special features.
R60~R67: R6 is an 8-bit CMOS bidirectional I/O port. R6 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R6 is shared with the ADC input.
Port pin R60 R61 R62 R63 R64 R66 R66 R67 Alternate function AN0 (Analog Input 0) AN1 (Analog Input 1) AN2 (Analog Input 2) AN3 (Analog Input 3) AN4 (Analog Input 4) AN5 (Analog Input 5) AN6 (Analog Input 6) AN7 (Analog Input 7)
Vdisp (High-voltage input power supply)
R00~R07: R0 is an 8-bit high-voltage CMOS bidirectional I/O port. R0 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R0 serves the functions of the various following special features.
Port pin R00 R01 R02 R03 Alternate function INT0 (External interrupt 0) INT1 (External interrupt 1) EC0 (Event counter input) BUZO (Buzzer driver output)
R20~R27: R2 is an 8-bit high-voltage CMOS bidirectional I/O port. R2 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. R53~R57: R5 is an 5-bit CMOS bidirectional I/O port. R5 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R5 serves the func-
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PIN DESCRIPTIONS (GMS81C2120) PIN NAME VDD VSS RA (Vdisp) RESETB XI XO R00 (INT0) R01 (INT1) R02 (EC0) R03 (BUZO) R04~R07 R20~R27 R30~R34 R53 (SCLK) R54 (SIN) R55 (SOUT) R56 (PWM1O/T1O) R57 R60~R67 (AN0~AN7) AVDD AVSS In/Out I(I) I I O I/O (I) I/O (I) I/O (I) I/O (O) I/O I/O I/O I/O (I/O) I/O (I) I/O (O) I/O (O) I/O I/O (I) 8-bit general I/O ports Supply voltage input pin for ADC Ground level input pin for ADC Analog voltage input 5-bit general I/O ports 8-bit high-voltage I/O ports 5-bit high-voltage I/O ports Serial clock source Serial data input Serial data output PWM 1 pulse output /Timer/Counter 1 output 8-bit high-voltage I/O ports Supply voltage Circuit ground 1-bit high-voltage Input only port Reset signal input Oscillation input Oscillation output External interrupt 0 input External interrupt 1 input Timer/Counter 0 external input Buzzer driving output High-voltage input power supply pin Function
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9. PORT STRUCTURES
* RESETB
VDD Mask version only Internal RESETB
VSS
* XI, XO (Crystal Oscillator)
VDD
Internal System clock
XO
VSS VDD VDD
XI
stop or mainclk off VSS
* XI, XO (RC Oscillator)
VDD
Internal System clock
XO
VSS VDD VDD
XI
stop or mainclk off VSS
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* SXI, SXO (Sub Oscillator)
VDD
Internal System clock
SXO
VSS VDD VDD
SXI
stop or subclk off VSS
* R40 / T0O
Fu n co ut [T0O]
1
VDD
Data Bus
Data Register
0
Function Select Data Bus Direction Register
V DD
VSS Data Bus
Metal Option
Read
* R41~R43, R50~R52, R57
Data Bus
Data Register
Data Bus
Direction Register
V DD
Data Bus
Metal Option
Read
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* R53 / SCLK
Funcout_sel F un co u t [SCLKOUT]
1
Funcin_sel
VDD
Data Bus
Data Register N-MOS Open Drain sel.
0
Data Bus
Direction Register VSS
V DD
Read Data Bus
Metal Option
Funcin [SCLKIN]
* R54 / SIN
Funcin_sel VDD
Data Bus
Data Register N-MOS Open Drain sel.
Data Bus
Direction Register VSS
V DD
Read Data Bus
Metal Option
Funcin [SIN]
* R55 / SOUT
Funcout_sel F u n co ut [SOUT]
1
VDD
Data Bus
Data Register N-MOS Open Drain sel.
0
Data Bus
Direction Register VSS
Read IOSWB Data Bus
V DD
Metal Option
Funcin [IOSWIN]
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* R56 / PWM1O / T1O
Funcout_sel F u nco u t [PWM1O/T1O]
1
VDD
Data Bus
Data Register N-MOS Open Drain sel.
0
Data Bus
Direction Register VSS
Read
V DD
Data Bus
Metal Option
* R60~R67 [AN0 ~ AN7], R70~R74 [AN8 ~ AN11]
VDD
Data Bus
Data Register
Data Bus
Direction Register
V DD
VSS
Data Bus Read To A/D Converter [AN11 ~ AN0] Analog Input Mode [ANSEL11 ~ 0] Analog Ch. Selection [ADCM.5 ~ ADCM.2]
Metal Option
* RA / Vdisp
VDD Read Data Bus
Vdisp
Metal option
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* R00 / INT0, R01 / INT1, R02 / EC0
Funcin_sel VDD
Data Bus
Data Register
Data Bus
Direction Register
Read Data Bus Funcin [INT0, INT1, EC0]
Vdisp [Metal Option]
* R03 / BUZO
Funcout_sel F un co ut [BUZO]
1
VDD
Data Bus
Data Register
0
Data Bus
Direction Register
Read Data Bus
Vdisp [Metal Option]
* R04 ~ R07, R10 ~ R17, R20 ~ R27, R30 ~ R35
VDD
Data Bus
Data Register
Data Bus
Direction Register
Read Data Bus
Vdisp [Metal Option]
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Pull-down Resistor
Pull-down Resistor
Pull-down Resistor
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10. ELECTRICAL CHARACTERISTICS
* Absolute Maximum Ratings
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these of any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage : VDD . . . . . . . . . . . . . . . - 0.3 to + 7.0V Storage Temperature : TSTG . . . . . . . . . . -40 to + 125 C Voltage on any pin with respect to Ground ( VSS ) . . . . . . -0.3 to VDD + 0.3V IOL per I/O Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Recommended Operating Conditions
Specification Min 4.0 0.4 -40 Max 5.5 4.5 125
Parameter Supply Voltage Operating Frequency Operating Temperature
Symbol VDD fXI TOPR
Condition fXI = 4.5 MHz VDD = VDD
Unit V MHz
C
10.1 A/D Converter Characteristics
(TA=25C, VDD=5V, VSS=0V, AVDD=5.12V, AVSS=0V @fXI =4MHz)
Specifications Parameter Analog Power Supply Input Voltage Range Analog Input Voltage Range Current Following Between AVDD and AVSS Overall Accuracy Non-Linearity Error Differential Non-Linearity Error Zero Offset Error Full Scale Error Gain Error Conversion Time Symbol AVDD VAN IAVDD CAIN NNLE NDNLE NZOE NFSE NNLE TCONV fXI=4MHz Condition Min. Typ. Max. AVDD AVDD+0.3 - 1.0 1.0 1.0 0.5 0.25 1.0 200 1.5 1.5 1.5 1.5 0.5 1.5 20 V V uA LSB LSB LSB LSB LSB LSB us Unit
AVSS AVSS-0.3
-
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GMS81C2020/GMS81C2120
DC Characteristics for Standard Pins( 5V )
( VDD = 5.0V 10%, VSS = 0V, TA = -40 ~ 125C, fXI = 4 MHz, Vdisp=VDD-40V to VDD) Specification Min 0.9VDD 0.8VDD 0.7VDD -0.3 -0.3 -0.3 IOH = -0.5mA VDD-0.5 Typ Max VDD+0.3 VDD+0.3 VDD+0.3 0.1VDD 0.2VDD 0.3VDD V V V
Parameter XI, SXI Input High Voltage
Pin
Symbol VIH1 VIH2 VIH3 VIL1 VIL2 VIL3 VOH
Test Condition
Unit
RESETB,SIN,R55,SCLK, INT0&1,EC0 R40~R43,R5,R6,R70~R73 XI, SXI
Input Low Voltage
RESETB,SIN,R55,SCLK, INT0&1,EC0 R40~R43,R5,R6,R70~R73
Output High Voltage Output Low Voltage Input High Leakage Current Input Low Leakage Current Input Pull-up Current(*Option) Power Fail Detect Voltage
R40~R43,R5,R6,R70~R73 BUZO,T0O,PWM1O/T1O, SCLK,SOUT R40~R43,R5,R6,R70~R73 BUZO,T0O,PWM1O/T1O, SCLK,SOUT R40~R43,R5,R6,R70~R73 XI R40~R43,R5,R6,R70~R73 XI R40~R43,R5,R6,R70~R73 VDD
VOL1 VOL2 IIH1 IIH2 IIL1 IIL2 IPU VPFD IDD ISTBY ISUB IWTC ISTOP VT+~VTTRCWDT fRCOSC
IOL = 1.6mA IOL = 10mA
0.4 2 1
V
uA 1 -1 uA -1 50 100 2.7 fXI=4.2MHz fXI=4.2MHz fXI=Off fSXI=32.7KHz fXI=Off fSXI=32.7KHz fXI=Off fSXI=32.7KHz 0.4 10 R= 60K 1.5 2 25 2.5 5 2 100 20 10 180 uA V mA mA uA uA uA V MHz MHz
Current dissipation VDD in active mode Current dissipation in standby mode Current dissipation in subactive mode Current dissipation in watch mode Current dissipation in stop mode Hysteresis Internal RC WDT Frequency RC Oscillation Frequency VDD VDD VDD VDD RESETB,SIN,R55,SCLK, INT0,INT1,EC0 XO XO
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DC Characteristics for High-Voltage Pins
( VDD = 5.0V 10%, VSS = 0V, TA = -40 ~ 125C, fXI = 4 MHz, Vdisp=VDD-40V to VDD) Specification Min 0.7VDD VDD-40 IOH = -15mA IOH = -10mA IOH = - 4mA Vdisp=VDD-40 150K atVDD-40 VIN=VDD-40V to VDD Vdisp=VDD-35V VIN=VDD 200 600 VDD-3.0 VDD-2.0 VDD-1.0 VDD-37 VDD-37 20 1000 Typ Max VDD+0.3 0.3VDD
Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input High Leakage Current Input Pull-down Current(*Option)
Pin R0,R1,R2,R30~R35,RA R0,R1,R2,R30~R35,RA R0,R1,R2,R30~R35
Symbol VIH VIL VOH
Test Condition
Unit V V V
R0,R1,R2,R30~R35 R0,R1,R2,R30~R35,RA R0,R1,R2,R30~R35
VOL IIH IPD
V uA uA
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10.2 AC Characteristics
(TA=-40~ 125C, VDD=5V10%, VSS=0V)
Specifications Parameter Operating Frequency External Clock Pulse Width External Clock Transition Time Oscillation Stabilizing Time External Input Pulse Width External Input Pulse Transiton Time RESET Input Width Symbol fCP tCPW tRCP,tFCP tST tEPW tREP,tFEP tRST Pins Min. XI XI XI XI, XO INT0, INT1, EC0 INT0, INT1, EC0 RESETB 1 80 2 8 Typ. Max. 8 20 20 20 MHz nS nS mS tSYS nS tSYS Unit
1/fCP
tCPW
tCPW VDD-0.5V
XI
tSYS tRCP tFCP
0.5V
tRST
RESETB
0.2VDD
tEPW
tEPW 0.8VDD 0.2VDD
INT0, INT1 EC0
tREP
tFEP
Figure 10-1 Timing Chart
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10.3 Typical Characteristics
This graphs and tables provided in this section are for design guidance only and are not tested or guranteed.
In some graphs or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for imformation only and divices are guranteed to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. "Typical" represents the mean of the distribution while "max" or "min" represents (mean + 3) and (mean - 3) respectively where is standard deviation
Operating Area
fXI (MHz) Ta= 25C 10 8 6 4 2 0 2 3 4 5 6 VDD (V) IDD (mA) 8 6 4
Normal Operation IDD-VDD
Ta=25C
fXI = 8MHz 4MHz
2 0 2 3 4 5 VDD 6 (V)
Wake-up Timer Mode IWKUP-VDD
IDD (mA) 2.0 1.5 fXI = 8MHz 1.0 0.5 0 2 3 4 5 10 5 Ta=25C IDD (A) 20 15
RC-WDT in Stop Mode IRCWDT-VDD
Ta=25C
fXI = 8MHz
4MHz VDD 6 (V)
4MHz 0 2 3 4 5 VDD 6 (V)
**** FOR MODIFIED ****
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IOL-VOL, VDD=5V
IOL (mA) 40 -25C 25C 85C 30 -15 IOH (mA) -20
IOH-VOH, VDD=5V
-25C 25C 85C
20
-10
10 0 1 2 3 4 VOL 5 (V)
-5 0 2 3 4 5 VOH 6 (V)
VIH1 (V) 4 3 2 1 0
VDD-VIH1 XI, RESETB
fXI=4MHz Ta=25C
VDD-VIH2
VIH2 (V) 4 3 2 1 VDD 6 (V) 0 2 3 f X I =4M H z Ta=25C
Hysteresis input
VIH3 (V) 4 3 2 1 VDD 6 (V) 0
VDD-VIH3
f X I =4M H z Ta=25C
Normal input
1
2
3
4
5
4
5
2
3
4
5
VDD 6 (V)
VIL1 (V) 4 3 2 1 0
VDD-VIL1 XI, RESETB
fXI=4MHz Ta=25C
VDD-VIL2
VIL2 (V) 4 3 2 1 VDD 6 (V) 0 2 3 f X I =4M H z Ta=25C
Hysteresis input
VIL3 (V) 4 3 2 1 VDD 6 (V) 0
VDD-VIL3
f X I =4M H z Ta=25C
Normal input
1
2
3
4
5
4
5
2
3
4
5
VDD 6 (V)
**** FOR MODIFIED ****
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11. MEMORY ORGANIZATION
The GMS81C2020 and GMS81C2120 have separate address spaces for Program memory and Data Memory. Program memory can only be read, not written to. It can be up to 20K/12K bytes of Program memory. Data memory can be read and written to up to 448 bytes including the stack area.
11.1 Registers
This device has six registers that are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register.
A X Y SP PCH PCL PSW ACCUMULATOR X REGISTER Y REGISTER STACK POINTER PROGRAM COUNTER PROGRAM STATUS WORD Stack Address ( 0100H ~ 01FFH ) 15 8 7 SP 0
Generally, SP is automatically updated when a subroutine call is executed or an interrupt is accepted. However, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. The stack can be located at any position within 00H to FFH of the internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of "FFH " is used.
01H
Figure 11-1 Configuration of Registers
Hardware fixed
Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc. The Accumulator can be used as a 16-bit register with Y Register as shown below.
Y
Y A
Note: The Stack Pointer must be initialized by software because its value is undefined after RESET. Example: To initialize the SP LDX #0FFH TXSP ; SP FFH
A
Two 8-bit Registers can be used as a "YA" 16-bit Register
Program Counter: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH). Program Status Word: The Program Status Word (PSW) contains several bits that reflect the current state of the CPU. The PSW is described in Figure 11-3 . It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag. [Carry flag C] This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction. [Zero flag Z] This flag is set when the result of an arithmetic operation or data transfer is "0" and is cleared by any other result.
Figure 11-2 Configuration of YA 16-bit Register
X, Y Registers: In the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators. Stack Pointer: The Stack Pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. Stack Pointer identifies the location in the stack to be accessed (save or restore).
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MSB PSW NEGATIVE FLAG OVERFLOW FLAG DIRECT PAGE FLAG BREAK FLAG
LSB
N
V
G
B
H
I
Z
C
[RESET VALUE : 00H CARRY FLAG RECEIVES CARRY OUT ZERO FLAG INTERRUPT ENABLE FLAG HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS
Figure 11-3 PSW (Program Status Word) Register
[Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All interrupts are disabled when cleared to "0". This flag immediately becomes "0" when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction. [Half carry flag H] After operation, this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V). [Break flag B] This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector address [Direct Page flag G]
This flag assign direct page(0-page, 1-page) for direct addressing mode. When G-flag is "0", the direct addressing space is in 0-page(0000h ~ 00FFH). When G-flag is "1", the direct addressing space is in 1-page(0100h ~ 01FFH). It is set and clreared by SETG, CLRG instruction. [Overflow flag V] This flag is set to "1" when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127(7FH ) or -128(80H ). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag.
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11.2 Program Memory
A 16-bit program counter is capable of addressing up to 64K bytes, but these devices have 20K/12K bytes program memory space only physically implemented. Accessing a location above FFFFH will cause a wrap-around to 0000H. Figure 11-4 , shows a map of Program Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFEH and FFFFH as shown in Figure 11-5 . As shown in Figure 11-4 , each area is assigned a fixed location in Program Memory. Program Memory area contains the user program. Example: Usage of TCALL
LDA #5 TCALL 0FH : : ;1BYTE INSTRUCTION ;INSTEAD OF 3 BYTES ;NORM AL CALL
B000H
; ;TABLE CALL ROUTINE ; FUNC_A: LDA LRG0 RET ; FUNC_B: LDA LRG1 2 RET ; ;TABLE CALL ADD. AREA ; ORG 0FFC0H DW FUNC_A DW FUNC_B
1
;TCALL ADDRESS AREA
GMS81C2020 D000H GMS81C2012 FEFFH FF00H FFC0H FFDFH FFE0H FFFFH PROGRAM MEMORY
TCALL AREA INTERRUPT VECTOR AREA
PCALL AREA
The interrupt causes the CPU to jump to specific location, where it commences the execution of the service routine. The External interrupt 0, for example, is assigned to location 0FFFAH. The interrupt service locations spaces 2-byte interval: 0FFF8H and 0FFF9H for External Interrupt 1, 0FFFAH and 0FFFBH for External Interrupt 0, etc. As for the area from 0FF00H to 0FFFFH, if any area of them is not going to be used, its service location is available as general purpose Program Memory.
Address Vector Area Memory Serial Peripheral Interface Interrupt Vector Area Basic Interval Interrupt Vector Area Watchdog Timer Interrupt Vector Area A/D Converter Interrupt Vector Area Timer/Counter 1 Interrupt Vector Area Timer/Counter 0 Interrupt Vector Area External Interrupt 1 Vector Area External Interrupt 0 Vector Area RESET Vector Area
Figure 11-4 Program Memory Map
0FFE0H E2 E4 E6 E8 EA EC EE F0 F2 F4 F6 F8 FA FC FE
Page Call (PCALL) area contains subroutine program to reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called, it is more useful to save program byte length. Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences the execution of the service routine. The Table Call service area spaces 2-byte for every TCALL: 0FFC0H for TCALL15, 0FFC2H for TCALL14, etc., as shown in Figure 11-6 .
NOTE: "-" means reserved area.
Figure 11-5 Interrupt Vector Area
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Address 0FFC0H C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
Program Memory TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK *
Address 0FF00H
PCALL Area Memory
PCALL Area (256 Bytes)
0FFFFH
NOTE: * means that the BRK software interrupt is using same address with TCALL0.
Figure 11-6 PCALL and TCALL Memory Area
PCALL rel
4F35 PCALL 35H
TCALL n
4A TCALL 4
4F 35
4A
01001010
~ ~ ~ ~
0F125H NEXT
~ ~
Reverse
~ ~
0FF00H 0FF35H NEXT
PC: 11111111 11010110 FH FH D H 6H
0FF00H 0FFD6H 25 F1
A
A
0FFFFH
0FFD7H 0FFFFH
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Example: The usage software example of Vector address and the initialize part.
ORG DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW ORG 0FFE0H NOT_USED; (0FFE0) NOT_USED; (0FFE2) SPI_INT; (0FFE4) Serial Peripheral Interface BIT_INT; (0FFE6) Basic Interval Timer WDT_INT; (0FFE8) Watchdog Timer AD_INT; (0FFEA) A/D Converter NOT_USED; (0FFEC) NOT_USED; (0FFEE) NOT_USED; (0FFF0) NOT_USED; (0FFF2) TMR1_INT; (0FFF4) Timer-1 TMR0_INT; (0FFF6) Timer-0 INT1; (0FFF8) Int.1 INT0; (0FFFA) Int.0 NOT_USED; (0FFFC) RESET; (0FFFE) Reset 0F000H
;******************************************** ; MAIN PROGRAM * ;******************************************* ; RESET: DI ;Disable All Interrupts LDX #0 RAM_CLR: LDA #0;RAM Clear(!0000H->!00BFH) STA {X}+ CMPX #0C0H BNE RAM_CLR ; LDX #01FFH;Stack Pointer Initialize TXSP ; CALL INITIAL; ; LDM R0, #0;Normal Port 0 LDM R0IO,#1000_0010B;Normal Port Direction LDM R1, #0;Normal Port 1 LDM R1IO,#1000_0010B;Normal Port Direction : : LDM PFDR,#0;Enable Power Fail Detector : :
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11.3 Data Memory (GMS81C2020)
Figure 11-7 shows the internal Data Memory space available. Data Memory is divided into two groups, a user RAM(including Stack) and control registers.
0000H USER MEMORY PAGE0 00BFH 00C0H 00FFH 0100H USER MEMORY ( including STACK ) 01FFH PAGE1 CONTROL REGISTERS
Address 0C0H 0C1H 0C2H 0C3H 0C4H 0C5H 0C6H 0C7H 0C8H 0C9H 0CAH 0CBH 0CCH 0CDH 0CEH 0CFH 0D0H 0D1H
Symbol R0 R0IO R1 R1IO R2 R2IO R3 R3IO R4 R4IO R5 R5IO R6 R6IO R7 R7IO TM0 T0 TDR0 CDR0 TM1 TDR1 T1PPR T1 CDR1 T1PDR PWM1HR BUR SIOM SIOR IENH IENL IRQH IRQL IEDS ADCM ADCR BITR CKCTLR WDTR WDTR PFDR R0FUNC R4FUNC R5FUNC R6FUNC R7FUNC R5NODR SCMR RA
R/W R/W W R/W W R/W W R/W W R/W W R/W W R/W W R/W W R/W R W R R/W W W R R R/W W W R/W R/W R/W R/W R/W R/W R/W R/W R R W R W R/W W W W W W W R/W R
RESET Value Undefined 0000_0000 Undefined 00000000 Undefined 0000_0000 Undefined --00_0000 Undefined ----_0000 Undefined 0000_0000 Undefined 0000_0000 Undefined ----_0000 --00_0000 0000_0000 1111_1111 0000_0000 0000_0000 1111_1111 1111_1111 0000_0000 0000_0000 0000_0000 ----_0000 1111_1111 0000_0001 Undefined 0000_---0000_---0000_---0000_-------_0000 -000_0001 Undefined 0000_0000 -001_0111 0000_0000 0111_1111 ----_-100 ----_0000 ----_--00 0000_0000 0000_0000 ----_0000 0000_0000 ---0_0000 Undefined
Addressing mode byte, bit1 byte2 byte, bit byte byte, bit byte byte, bit byte byte, bit byte byte, bit byte byte, bit byte byte, bit byte byte, bit byte byte byte byte, bit byte byte byte byte byte, bit byte byte byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte byte byte byte byte byte, bit byte byte byte byte byte byte byte -
Figure 11-7 Data Memory Map
0D1H 0D1H
User Memory The GMS81C2020 has 448 x 8 bits for the user memory (RAM). Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converter, basic interval timer, serial peripheral interface, watchdog timer, buzzer driver and I/O ports. The control registers are in address range of 0C0H to 0FFH. Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. More detailed informations of each register are explained in each peripheral section.
Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction.
0D2H 0D3H
0D3H
0D4H
0D4H 0D4H
0D5H 0DEH 0E0H 0E1H 0E2H 0E3H 0E4H 0E5H 0E6H 0EAH 0EBH 0ECH
0ECH
0EDH
0EDH
0EFH 0F4H 0F5H 0F6H 0F7H 0F8H 0F9H 0FAH 0FBH
Table 11-1 Control Registers
Example; To write at CKCTLR
LDM CKCTLR,#09H ;Divide ratio /16
1. "byte, bit" means that register can be addressed by not only bit but byte manipulation instruction. 2. "byte" means that register can be addressed by only byte manipulation instruction. On the other hand, do not use any read-modify-write instruction such as bit manipulation for clearing bit.
Note: Several names are given at same address. Refer to
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below table.
When read Addr. D1H D3H D4H ECH T1
Timer Mode Capture Mode PWM Mode
When write
Timer Mode PWM Mode
Stack Area The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the program counter and flags. The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save.
T0
CDR0 CDR1 BITR
-
TDR0 TDR1
T1PPR T1PDR
T1PDR
-
CKCTLR
Table 11-2 Various Register Name in Same Address
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Address C0H C1H C2H C3H C4H C5H C6H C7H C8H C9H CAH CBH CCH CDH CEH CFH D0H D1H D2H D3H D4H D5H DEH E0H E1H E2H E3H E4H E5H E6H EAH EBH ECH
ECH
Name R0 R0IO R1 R1IO R2 R2IO R3 R3IO R4 R4IO R5 R5IO R6 R6IO R7 R7IO TM0 T0/TDR0/ CDR0 TM1 TDR1/ T1PPR T1/CDR1/ T1PDR PWM1HR BUR SIOM SIOR IENH IENL IRQH IRQL IEDS ADCM ADCR BITR1 CKCTLR1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R0 Port Data Register (Bit[7:0]) R0 Port Direction Register (Bit[7:0]) R1 Port Data Register (Bit[7:0]) R1 Port Direction Register (Bit[7:0]) R2 Port Data Register (Bit[7:0]) R2 Port Direction Register (Bit[7:0]) R3 Port Data Register (Bit[5:0]) R3 Port Direction Register (Bit[5:0]) R4 Port Data Register (Bit[3:0]) R4 Port Direction Register (Bit[3:0]) R5 Port Data Register (Bit[7:0]) R5 Port Direction Register (Bit[7:0]) R6 Port Data Register (Bit[7:0]) R6 Port Direction Register (Bit[7:0]) R7 Port Data Register (Bit[5:0]) R7 Port Direction Register (Bit[5:0]) CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST
Timer0 Register / Timer0 Data Register / Capture0 Data Register POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST
Timer1 Data Register / PWM1 Period Register Timer1 Register / Capture1 Data Register / PWM1 Duty Register PWM1 High Register(Bit[3:0]) BUCK1 POL BUCK0 IOSW BUR5 SM1 BUR4 SM0 BUR3 SCK1 BUR2 SCK0 BUR1 SIOST BUR0 SIOSF
SPI DATA REGISTER INT0E ADE INT0IF ADIF INT1E WDTE INT1IF WDTIF T0E BITE T0IF BITIF T1E SPIE T1IF SPIIF IED1H ADEN ADS3 ADS2 ADS1 IED1L ADS0 IED0H ADST IED0L ADSF -
ADC Result Data Register Basic Interval Timer Data Register WAKEUP RCWDT WDTON BTCL BTS2 BTS1 BTS0
Table 11-3 Control Registers of GMS81C2020
These registers of shaded area can not be accessed by bit manipulation instruction as " SET1, CLR1 ", but should be accessed by register operation instruction as " LDM dp,#imm ".
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Address EDH EFH F4H F5H F6H F7H F8H F9H FAH FBH
Name WDTR PFDR2 R0FUNC R4FUNC R5FUNC R6FUNC R7FUNC R5NODR SCMR RA
Bit 7 WDTCL AN7 NODR7 -
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
7-bit Watchdog Counter Register PWM1O/ T1O AN6 NODR6 SOUT AN5 NODR5 SIN AN4 NODR4 CS1 BUZO SCLK AN3 AN11 NODR3 CS0 PFDIS EC0 AN2 AN10 NODR2 SUBOFF PFDM INT1 AN1 AN9 NODR1 CLKSEL PFDS INT0 T0O AN0 AN8 NODR0 MAINOFF RA0
Table 11-3 Control Registers of GMS81C2020
These registers of shaded area can not be accessed by bit manipulation instruction as " SET1, CLR1 ", but should be accessed by register operation instruction as " LDM dp,#imm ". 1.The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR. 2.The register PFDR only be implemented on devices, not on In-circuit Emulator.
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11.4 Data Memory (GMS81C2120)
Figure 11-8 shows the internal Data Memory space available. Data Memory is divided into two groups, a user RAM(including Stack) and control registers.
0000H USER MEMORY PAGE0 00BFH 00C0H 00FFH 0100H USER MEMORY ( including STACK ) 01FFH PAGE1 CONTROL REGISTERS
Address 0C0H 0C1H 0C4H 0C5H 0C6H 0C7H 0CAH 0CBH 0CCH 0CDH
Symbol R0 R0IO R2 R2IO R3 R3IO R5 R5IO R6 R6IO
R/W R/W W R/W W R/W W R/W W R/W W
RESET Value Undefined 0000_0000 Undefined 0000_0000 Undefined ---0_0000 Undefined 0000_0--Undefined 0000_0000
Addressing mode byte, bit1 byte2 byte, bit byte byte, bit byte byte, bit byte byte, bit byte
0D0H 0D1H Figure 11-8 Data Memory Map
0D1H 0D1H
User Memory The GMS81C2120 has 448 x 8 bits for the user memory (RAM). Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converter, basic interval timer, serial peripheral interface, watchdog timer, buzzer driver and I/O ports. The control registers are in address range of 0C0H to 0FFH. Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. More detailed informations of each register are explained in each peripheral section.
Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction.
0D2H 0D3H
0D3H
0D4H
0D4H 0D4H
0D5H 0DEH 0E0H 0E1H 0E2H 0E3H 0E4H 0E5H 0E6H 0EAH 0EBH 0ECH
0ECH
TM0 T0 TDR0 CDR0 TM1 TDR1 T1PPR T1 CDR1 T1PDR PWM1HR BUR SIOM SIOR IENH IENL IRQH IRQL IEDS ADCM ADCR BITR CKCTLR WDTR WDTR PFDR R0FUNC R5FUNC R6FUNC R5NODR SCMR RA
R/W R W R R/W W W R R R/W W W R/W R/W R/W R/W R/W R/W R/W R/W R R W R W R/W W W W W R/W R
--00_0000 0000_0000 1111_1111 0000_0000 0000_0000 1111_1111 1111_1111 0000_0000 0000_0000 0000_0000 ----_0000 1111_1111 0000_0001 Undefined 0000_---0000_---0000_---0000_-------_0000 -000_0001 Undefined 0000_0000 -001_0111 0000_0000 0111_1111 ----_-100 ----_0000 0000_0--0000_0000 0000_0-----0_0000 Undefined
byte, bit byte byte byte byte, bit byte byte byte byte byte, bit byte byte byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte byte byte byte byte byte, bit byte byte byte byte byte -
0EDH
0EDH
0EFH 0F4H 0F6H 0F7H 0F9H 0FAH 0FBH
Table 11-4 Control Registers
Example; To write at CKCTLR
LDM CKCTLR,#09H ;Divide ratio /16
1. "byte, bit" means that register can be addressed by not only bit but byte manipulation instruction. 2. "byte" means that register can be addressed by only byte manipulation instruction. On the other hand, do not use any read-modify-write instruction such as bit manipulation for clearing bit.
Note: Several names are given at same address. Refer to
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below table.
When read Addr. D1H D3H D4H ECH T1
Timer Mode Capture Mode PWM Mode
When write
Timer Mode PWM Mode
Stack Area The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the program counter and flags. The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save.
T0
CDR0 CDR1 BITR
-
TDR0 TDR1
T1PPR T1PDR
T1PDR
-
CKCTLR
Table 11-5 Various Register Name in Same Address
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Address C0H C1H C4H C5H C6H C7H CAH CBH CCH CDH D0H D1H D2H D3H D4H D5H DEH E0H E1H E2H E3H E4H E5H E6H EAH EBH ECH
ECH
Name R0 R0IO R2 R2IO R3 R3IO R5 R5IO R6 R6IO TM0 T0/TDR0/ CDR0 TM1 TDR1/ T1PPR T1/CDR1/ T1PDR PWM1HR BUR SIOM SIOR IENH IENL IRQH IRQL IEDS ADCM ADCR BITR1 CKCTLR1 WDTR PFDR2 R0FUNC R4FUNC R5FUNC
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R0 Port Data Register (Bit[7:0]) R0 Port Direction Register (Bit[7:0]) R2 Port Data Register (Bit[7:0]) R2 Port Direction Register (Bit[7:0]) R3 Port Data Register (Bit[4:0]) R3 Port Direction Register (Bit[4:0]) R5 Port Data Register (Bit[7:3]) R5 Port Direction Register (Bit[7:3]) R6 Port Data Register (Bit[7:0]) R6 Port Direction Register (Bit[7:0]) CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST
Timer0 Register / Timer0 Data Register / Capture0 Data Register POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST
Timer1 Data Register / PWM1 Period Register Timer1 Register / Capture1 Data Register / PWM1 Duty Register PWM1 High Register(Bit[3:0]) BUCK1 POL BUCK0 IOSW BUR5 SM1 BUR4 SM0 BUR3 SCK1 BUR2 SCK0 BUR1 SIOST BUR0 SIOSF
SPI DATA REGISTER INT0E ADE INT0IF ADIF INT1E WDTE INT1IF WDTIF T0E BITE T0IF BITIF T1E SPIE T1IF SPIIF IED1H ADEN ADS3 ADS2 ADS1 IED1L ADS0 IED0H ADST IED0L ADSF -
ADC Result Data Register Basic Interval Timer Data Register WDTCL WAKEUP RCWDT WDTON BTCL BTS2 BTS1 BTS0
EDH EFH F4H F5H F6H
7-bit Watchdog Counter Register PWM1O/ T1O SOUT SIN BUZO SCLK PFDIS EC0 PFDM INT1 PFDS INT0 T0O -
Table 11-6 Control Registers of GMS81C2120
These registers of shaded area can not be accessed by bit manipulation instruction as " SET1, CLR1 ", but should be accessed by register operation instruction as " LDM dp,#imm ".
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Address F7H F8H F9H FAH FBH
Name R6FUNC R7FUNC R5NODR SCMR RA
Bit 7 AN7 NODR7 -
Bit 6 AN6 NODR6 -
Bit 5 AN5 NODR5 -
Bit 4 AN4 NODR4 CS1 -
Bit 3 AN3 AN11 NODR3 CS0 -
Bit 2 AN2 AN10 NODR2 SUBOFF -
Bit 1 AN1 AN9 NODR1 CLKSEL -
Bit 0 AN0 AN8 NODR0 MAINOFF RA0
Table 11-6 Control Registers of GMS81C2120
These registers of shaded area can not be accessed by bit manipulation instruction as " SET1, CLR1 ", but should be accessed by register operation instruction as " LDM dp,#imm ". 1.The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR. 2.The register PFDR only be implemented on devices, not on In-circuit Emulator.
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11.5 Addressing Mode
The GMS87C1404 and GMS87C1408 uses six addressing modes; * Register addressing * Immediate addressing * Direct page addressing * Absolute addressing * Indexed addressing
~ ~ ~ ~
C5 35 0035H data
(3) Direct Page Addressing dp In this mode, a address is specified within direct page. Example;
C535 LDA 35H ;A RAM[35H]
A * Register-indirect addressing
data A
0F550H 0F551H
(1) Register Addressing Register addressing accesses the A, X, Y, C and PSW. (2) Immediate Addressing #imm In this mode, second byte (operand) is accessed as a data immediately. Example:
0435 ADC #35H
MEMORY
(4) Absolute Addressing !abs Absolute addressing sets corresponding memory data to Data , i.e. second byte(Operand I) of command becomes lower level address and third byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area. ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY
04 35
A+35H+C A
Example;
0735F0 ADC !0F035H ;A ROM[0F035H]
E45535
LDM
35H,#55H
0F035H
data
A
~ ~
~ ~
0F100H 0F101H 0035H data data 55H 0F102H 07 35 F0
A+data+C A
address: 0F035
~ ~
~ ~
0F100H 0F101H 0F102H E4 55 35
A
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The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135H .
983500 INC !0035H ;A RAM[035H]
X indexed direct page, auto increment {X}+ In this mode, a address is specified within direct page by the X register and the content of X is increased by 1. LDA, STA Example; X=35H
DB LDA {X}+
0035H
data
A
~ ~
~ ~
0F100H 0F101H 0F102H 98 35 00
A
data+1 data
35H
data
A
~ ~
data A
address: 0035
~ ~
DB
36H X
(5) Indexed Addressing X indexed direct page (no offset) {X} In this mode, a address is specified by the X register. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example; X=15H
D4 LDA {X} ;ACCRAM[X].
X indexed direct page (8 bit offset) dp+X This address value is the second byte (Operand) of command plus the data of -register. And it assigns the memory in Direct page. ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR Example; X=015H
15H
data
C645
LDA
45H+X
A
~ ~
data A
~ ~
0E550H D4
5AH data
A
~ ~
0E550H 0E551H C6 45
~ ~
A
45H+15H=5AH
data A
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Y indexed direct page (8 bit offset) dp+Y This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of X. Y indexed absolute !abs+Y Sets the value of 16-bit absolute address plus Y-register data as Memory. This addressing mode can specify memory in whole area. Example; Y=55H
D500FA LDA !0FA00H+Y
3F35
JMP
[35H]
35H 36H
0A E3
~ ~
0E30AH NEXT
~ ~
A jump to address 0E30AH
~ ~
0FA00H 3F 35
~ ~
0F100H 0F101H 0F102H
D5 00 FA
0FA00H+55H=0FA55H
X indexed indirect [dp+X] Processes memory data as Data, assigned by 16-bit pair memory which is determined by pair data [dp+X+1][dp+X] Operand plusX-register data in Direct page. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; X=10H
1625 ADC [25H+X]
~ ~
0FA55H data
~ ~
A
data A
A
(6) Indirect Addressing Direct page indirect [dp] Assigns data address to use for accomplishing command which sets memory data(or pair memory) by Operand. Also index can be used with Index register X,Y. JMP, CALL Example;
0FA00H 35H 36H 05 E0
~ ~
0E005H data
~ A 0E005H ~
~ ~
25 + X(10) = 35H
~ ~
16 25
A A + data + C A
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Y indexed indirect [dp]+Y Processes momory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Direct pageplus Y-register data. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; Y=10H
1725 ADC [25H]+Y
Absolute indirect [!abs] The program jumps to address specified by 16-bit absolute address. JMP Example;
1F25E0 JMP [!0C025H]
PROGRAM MEMORY
25H 26H
05 E0
0E025H 0E026H
25 E7
~ ~
0E015H data
~ ~
A
0E005H + Y(10) = 0E015H
~ ~
~ ~
NEXT
A
jump to address 0E30AH
~ ~
0E725H
~ ~
0FA00H 17 25
~ ~
0FA00H 1F 25
~ ~
A A + data + C A
E0
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12. I/O PORTS
The GMS81C2020 has eight ports, R0, R1, R2, R3, R4, R5, R6 and R7. The GMS81C2120 has five ports, R0, R2, R3, R5 and R6. These ports pins may be multiplexed with an alternate function for the peripheral features on the device. In general, when a initial reset state, all ports are used as a general purpose input port. All pins have data direction registers which can set these ports as output or input. A "1" in the port direction register defines the corresponding port pin as output. Conversely, write "0" to the corresponding bit to specify as an input pin. For example, to use the even numbered bit of R0 as output ports and the odd numbered bits as input ports, write "55 H" to address C1H (R0 direction register) during initial setting as shown in Figure 12-1 . Reading data register reads the status of the pins whereas writing to it will write to the port latch..
WRITE "55H" TO PORT RA DIRECTION REGISTER R0 Function Selection Register R0FUNC C0H C1H C2H C3H R0 DATA R0 DIRECTION R1 DATA R1 DIRECTION I O IO I O I O 7 6 5 4 3 2 1 0 PORT I : INPUT PORT O : OUTPUT PORT 01010101 76543210 BIT
-
port can directly drive a vacuum fluorescent display. R03 port is multiplexed with Buzzer Output Port(BUZO), R02 port is multiplexed with Event Counter Input Port (EC0), and R01~R00 are multiplexed with External Interrupt Input Port(INT1, INT0).
R0 Data Register R0 ADDRESS : C0H RESET VALUE : Undefined
R07
R06
R05
R04
R03
R02
R01
R00
INPUT / OUTPUT DATA ADDRESS : C1H RESET VALUE : 00000000
R0 Direction Register R0IO
DIRECTION SELECT 0 : INPUT PORT 1 : OUTPUT PORT ADDRESS : F4H RESET VALUE : ----0000
BUZO EC0 INT1 INT0
0 : R03 1 : BUZO 0 : R02 1 : EC0
0 : R00 1 : INT0 0 : R01 1 : INT1
Figure 12-2 Registers of Port R0
Figure 12-1 Example of port I/O assignment
12.1 RA(Vdisp) register
RA is one-bit high-voltage input only port pin. In addition, RA serves the functions of the Vdisp special features. Vdisp is used as a high-voltage input power supply pin when selected by the mask option..
RA Data Register RA ADDRESS : FBH RESET VALUE : Undefined
The control register R0FUNC (address F4H) controls to select alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alternate function such as Buzzer Output, External Event Counter Input and External Interrupt Input, write "1" to the corresponding bit of R0FUNC. Regardless of the direction register R0IO, R0FUNC is selected to use as alternate functions, port pin can be used as a corresponding alternate features (BUZO, EC0, INT1, INT0)
PORT R03/ BUZO R02/ EC0 R01/ INT1 R0FUNC [3:0] 0 1 0 1 0 1 Description R00 (Normal I/O Port) BUZO (Buzzer Output Port) R01 (Normal I/O Port) EC0 (Event Counter Input Port) R01 (Normal I/O Port) INT1 (External interrupt 1 Input Port)
-
-
-
-
-
-
-
RA0
INPUT DATA
Port pin RA
Alternate function
Vdisp (High-voltage input power supply)
12.2 R0 and R0IO registers
R0 is an 8-bit high-voltage CMOS bidirectional I/O port (address C0H). Each port can be set individually as input and output through the R0IO register (address C1 H). Each
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R00/ INT0
0 1
R00 (Normal I/O Port) INT0 (External interrupt 0 Input Port)
(address C6H). Each port can be set individually as input and output through the R3IO register (address C7H). Each port can directly drive a vacuum fluorescent display..
R3 Data Register R3 ADDRESS : C6H RESET VALUE : Undefined
12.3 R1 and R1IO registers
R1 is an 8-bit high-voltage CMOS bidirectional I/O port (address C2H). Each port can be set individually as input and output through the R1IO register (address C3 H). Each port can directly drive a vacuum fluorescent display..
R1 Data Register R1 ADDRESS : C2H RESET VALUE : Undefined
-
-
R35
R34
R33
R32
R31
R30
INPUT / OUTPUT DATA R3 Direction Register R3IO ADDRESS : C7H RESET VALUE : --000000
R17
R16
R15
R14
R13
R12
R11
R10
DIRECTION SELECT 0 : INPUT PORT 1 : OUTPUT PORT
INPUT / OUTPUT DATA A D D R E SS : C 3H R E SE T V A LU E : 00000 000
R1 Direction Register R1IO
Figure 12-5 Registers of Port R3
12.6 R4 and R4IO registers
DIREC TION SELEC T 0 : IN P U T P O R T 1 : O U T P U T PO R T
R4 is an 4-bit bidirectional I/O port (address C8H). Each port can be set individually as input and output through the R4IO register (address C9H). R40 port is multiplexed with Timer 0 Output Port(T0O), r
Figure 12-3 Registers of Port R1
R4 Data Register ADDRESS : C8H RESET VALUE : Undefined
12.4 R2 and R2IO registers
R2 is an 8-bit high-voltage CMOS bidirectional I/O port (address C4H). Each port can be set individually as input and output through the R2IO register (address C5 H). Each port can directly drive a vacuum fluorescent display..
R4
-
-
-
-
R43
R42
R41
R40
INPUT / OUTPUT DATA ADDRESS : C9H RESET VALUE : ----0000
R4 Direction Register R2 Data Register R2 ADDRESS : C4H RESET VALUE : Undefined R4IO
R27
R26
R25
R24
R23
R22
R21
R20
INPUT / OUTPUT DATA R4 Function Selection Register R2 Direction Register R2IO ADDRESS : C5H RESET VALUE : 00000000 R4FUNC
-
DIRECTION SELECT 0 : INPUT PORT 1 : OUTPUT PORT ADDRESS : F5H RESET VALUE : -------0
T0O
0 : R40 1 : T0O DIRECTION SELECT 0 : INPUT PORT 1 : OUTPUT PORT
Figure 12-6
Registers of Port R4
Figure 12-4 Registers of Port R2
12.5 R3 and R3IO registers
R1 is an 6-bit high-voltage CMOS bidirectional I/O port
The control register R4FUNC (address F5H) controls to select alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alternate function such as Timer 0 Output, write "1" to the corresponding bit of R4FUNC. Regardless of the direction register R4IO, R4FUNC is selected to use as alternate functions, port pin
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can be used as a corresponding alternate features (T0O)
PORT R40/ T0O R4FUNC [0] 0 1 Description R40 (Normal I/O Port) T0O (Timer 0 Compare Output Port)
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12.7 R5 and R5IO registers
R5 is an 8-bit bidirectional I/O port (address CAH). Each pin can be set individually as input and output through the R5IO register (address CBH).In addition, Port R5 is multiplexed with Serial Peripheral Interface (SPI). The control register R5FUNC (address F6H) controls to select Serial Peripheral Interface function.After reset, the R5IO register value is "0", port may be used as general I/O ports. To select Serial Peripheral Interface function, write "1" to the corresponding bit of R5FUNC.
R5 Data Register R5 ADDRESS : CAH RESET VALUE : Undefined
12.8 R6 and R6IO registers
R6 is an 8-bit bidirectional I/O port (address CCH). Each port can be set individually as input and output through the R6IO register (address CDH). R67~R60 ports are multiplexed with Analog Input Port ( AN7~AN0 )..
R6 Data Register R6 ADDRESS : CCH RESET VALUE : Undefined
R67
R66
R65
R64
R63
R62
R61
R60
INPUT / OUTPUT DATA R6 Direction Register R6IO ADDRESS : CDH RESET VALUE : 00000000
R57
R56
R55
R54
R53
R52
R51
R50
INPUT / OUTPUT DATA R5 Direction Register R5IO R6 Function Selection Register DIRECTION SELECT 0 : INPUT PORT 1 : OUTPUT PORT R5 Function Selection Register R5FUNC
PWM1O SOUT SIN
ADDRESS : CBH RESET VALUE : 00000000
DIRECTION SELECT 0 : INPUT PORT 1 : OUTPUT PORT
R6FUNC
ADDRESS : F7H RESET VALUE : 00000000
ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0
ADDRESS : F6H RESET VALUE : -0000--SCLK -
0 : R56 1 : PWM1O/T1O 0 : R55 1 : SOUT
0 : R53 1 : SCLK 0 [R5IO.3] : SCLKO 1 [R5IO.3] : SCLKI 0 : R54 1 : SIN
0 : R64 1 : AN4 0 : R65 1 : AN5 0 : R66 1 : AN6 0 : R67 1 : AN7
0 : R60 1 : AN0 0 : R61 1 : AN1 0 : R62 1 : AN2 0 : R63 1 : AN3
Figure 12-7 Registers of Port R5 R5FUNC [6:3] 0 1 0 1 0 1 0 R53/SCLK 0 [R5IO.3] SCLKO 1 [R5IO.3] SCLKI
Figure 12-8 Registers of Port R6
PORT R56/ PWM1O/ T1O R55/SOUT
Description R56 (Normal I/O Port) PWM1 Data Output / Timer 1 Data Output R55 (Normal I/O Port) SPI Serial Data Output R54 (Normal I/O Port) SPI Serial Data Input R53 (Normal I/O Port) SPI Synchronous Clock Output SPI Synchronous Clock Input
R54/SIN
Table 12-1 Registers of Port R5FUNC
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The control register R6FUNC (address F7H) controls to select alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alternate function such as Analog Input, write "1" to the corresponding bit of R6FUNC. Regardless of the direction register R6IO, R6FUNC is selected to use as alternate functions, port pin can be used as a corresponding alternate features (AN7~AN0)
PORT R67/AN7 R6FUNC [7:0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description
AN11~AN8 )..
R7 Data Register R7 ADDRESS : CEH RESET VALUE : Undefined
-
-
-
-
R73
R72
R71
R70
INPUT / OUTPUT DATA ADDRESS : CFH RESET VALUE : ----0000
R7 Direction Register R7IO
R67 ( Normal I/O Port ) AN7 ( ADS3~0=0111 ) R66 ( Normal I/O Port ) AN6 ( ADS3~0=0110 ) R65 ( Normal I/O Port ) AN5 ( ADS3~0=0101 ) R64 ( Normal I/O Port ) AN4 ( ADS3~0=0100 ) R63 ( Normal I/O Port ) AN3 ( ADS3~0=0011 ) R62 ( Normal I/O Port ) AN2 ( ADS3~0=0010 ) R61 ( Normal I/O Port ) AN1 ( ADS3~0=0001 ) R60 ( Normal I/O Port ) AN0 ( ADS3~0=0000 ) Figure 12-9 Registers of Port R6
R7 Function Selection Register R7FUNC DIRECTION SELECT 0 : INPUT PORT 1 : OUTPUT PORT ADDRESS : F8H RESET VALUE : ----0000
ANSEL11 ANSEL10 ANSEL9 ANSEL8
R66/AN6
R65/AN5
-
-
-
-
R64/AN4
R63/AN3
0 : R70 1 : AN8 0 : R71 1 : AN9 0 : R72 1 : AN10 0 : R73 1 : AN11
R62/AN2
R61/AN1
R60/AN0
12.9 R7 and R7IO registers
R7 is an 4-bit bidirectional I/O port (address CEH). Each port can be set individually as input and output through the R7IO register (address CFH). R73~R70 ports are multiplexed with Analog Input Port
The control register R7FUNC (address F8H) controls to select alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alternate function such as Analog Input, write "1" to the corresponding bit of R7FUNC. Regardless of the direction register R7IO, R7FUNC is selected to use as alternate functions, port pin can be used as a corresponding alternate features.
PORT R73/AN11 R7FUNC [7:0] 0 1 0 1 0 1 0 1 Description R73 ( Normal I/O Port ) AN11 ( ADS3~0=1011 ) R72 ( Normal I/O Port ) AN10 ( ADS3~0=1010 ) R71 ( Normal I/O Port ) AN9 ( ADS3~0=1001 ) R70 ( Normal I/O Port ) AN8 ( ADS3~0=1000 )
R72/AN10
R71/AN9
R70/AN8
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13. CLOCK GENERATOR
The clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and peripheral hardware. The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator
CLKSEL CS[1:0]
connected to the XI and XO pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the XI pin and open the XO pin.
OSCILLATION CIRCUIT SUB OSCILLATION CIRCUIT
fXI
0 1 fXI/ 4 fXI/ 8 fXI/32 MUX CLOCK PULSE GENERATOR
Internal system clock
fSXI
PRESCALER STOP WAKEUP
/1
/2
/4
/8
/16
/32
/64
/128
/256
/512
/1024 /2048 /4096
Peripheral clock
System Clock Mode Register SCMR CS1 CS0 SUBOFF CLKSEL MAINOFF ADDRESS : FAH RESET VALUE : ---00000
CS[1:0]
Clock selection enable bits 00 : fXI / 210 : fXI /16 01 : fXI / 811 : fXI / 64 Sub clock control bit 0: On sub clock 1: Off sub clock
CLKSEL
Clock selection bit 0 : Main clock selection 1 : Sub clock selection Main clock control bit 0: On main clock 1: Off main clock
SUBOFF
MAINOFF
Figure 13-1 Block Diagram of Clock Pulse Generator
13.1 Oscillation Circuit
XI and XO are the input and output, respectively, a inverting amplifier which can be set for use as an on-chip oscillator, as shown in Figure 13-2 .
XO
Figure 13-2 Oscillator Connections
SXI and SXO are the input and output, respectively, a inverting amplifier which can be set for use as an on-chip os-
C1 C2
XI Vss
Recommended: C1, C2 = 30pF10pF for Crystals
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cillator, as shown in Figure 13-2 .
SXO
C1 C2
Oscillation circuit is designed to be used either with a external RC oscillator. Since External RC oscillator has their own characteristic, the user should figure out the appropriate value of external resister. (Please refer the DC Spec)
XO
SXI Vss
REXT
XI
Recommended: C1, C2 = 20pF4pF for Crystals
Vss
Figure 13-3 Sub Oscillator Connections
To drive the device from an external clock source, XO should be left unconnected while XI is driven as shown in Figure 13-4 . There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.
OPEN XO
Figure 13-4 External R Connection
Note: When using a system clock oscillator, carry out wiring in the broken line area in Figure 13-2 to prevent any effects from wiring capacities. - Minimize the wiring length. - Do not allow wiring to intersect with other signal conductors. - Do not allow wiring to come near changing high current. - Set the potential of the grounding position of the oscillator capacitor to that of VSS. Do not ground to any ground pattern where high current is present. - Do not fetch signals from the oscillator.
External Clock Source
XI Vss
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14. Basic Interval Timer
The GMS81C2020 and GMS81C2120 has one 8-bit Basic Interval Timer that is free-run, can not stop. Block diagram is shown in Figure 14-1 .The 8-bit Basic interval timer register (BITR) is increased every internal count pulse which is divided by prescaler. Since prescaler has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of the oscillator frequency. As the count overflows from FFH to 00H, this overflow causes to generate the Basic interval timer interrupt. The BITIF is interrupt request flag of Basic interval timer. When write "1" to bit BTCL of CKCTLR, BITR register is cleared to "0" and restart to count-up. The bit BTCL becomes "0" after one machine cycle by hardware. If the STOP instruction executed after writing "1" to bit WAKEUP of CKCTLR, it goes into the wake-up timer mode. In this mode, all of the block is halted except the osWAKEUP STOP BTS[2:0] RCWDT BTCL Clear
MUX 0 BITR ( 8-BIT ) 1 BITIF
cillator, prescaler ( only fXI/2048 ) and Timer0. If the STOP instruction executed after writing "1" to bit RCWDT of CKCTLR, it goes into the internal RC oscillated watchdog timer mode. In this mode, all of the block is halted except the internal RC oscillator, Basic Interval Timer and Watchdog Timer. More detail informations are explained in Power Saving Function. The bit WDTON decides Watchdog Timer or the normal 7-bit timer
Note: All control bits of Basic interval timer are in CKCTLR register which is located at same address of BITR (address ECH). Address ECH is read as BITR, written to CKCTLR. Therefore, the CKCTLR can not be accessed by bit manipulation instruction.
.
fXI
/8 / 16 / 32 / 64 / 128 / 256 / 512 /1024
Internal RC OSC
To Watchdog Timer
Basic Interval Timer Interrupt
Figure 14-1 Block Diagram of Basic Interval Timer
Clock Control Register CKCTLR WAKEUP RCWDT WDTON BTCL BTS2 BTS1 BTS0 ADDRESS : ECH RESET VALUE : -0010111 Bit Manipulation Not Available
Basic Interval Timer Clock Selection Symbol WAKEUP RCWDT WDTON BTCL Function Description 1: Enables Wake-up Timer 0: Disables Wake-up Timer 1: Enables Internal RC Watchdog Timer 0: Disables Internal RC Watchdog Timer 1: Enables Watchdog Timer 0: Operates as a 7-bit Timer 1: BITR is cleared and BTCL becomes "0" automatically after one machine cycle, and BITR continue to count-up 001 : fXI / 16 010 : fXI / 32 011 : fXI / 64 100 : fXI / 128 101 : fXI / 256 110 : fXI / 512 111 : fXI / 1024 000 : fXI / 8
Figure 14-2 CKCTLR : Clock Control Register
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15. TIMER / COUNTER
The GMS81C2020 and GMS81C2120 has two Timer/ Counter registers. Each module can generate an interrupt to indicate that an event has occurred (i.e. timer match). Timer 0 and Timer 1 can be used either the two 8-bit Timer/Counter or one 16-bit Timer/Counter by combining them. In the "timer" function, the register is increased every internal clock input. Thus, one can think of it as counting internal clock input. Since a least clock consists of 2 and most clock consists of 2048 oscillator periods, the count rate is 1/2 to 1/2048 of the oscillator frequency in Timer0. And Timer1 can use the same clock source too. In addition, Timer1 has more fast clock source ( 1/1 to 1/8 ). In the "counter" function, the register is increased in response to a 0-to-1 (rising & falling edge) transition at its corresponding external input pin, EC0(Timer 0). In addition the "capture" function, the register is increased in response external interrupt same with timer function. When external interrupt edge input, the count register is captured into capture data register CDRx. Timer1 is shared with "PWM" function and "Compare output" function It has seven operating modes: "8-bit timer/counter", "16bit timer/counter", "8-bit capture", "16-bit capture", "8-bit compare output", "16-bit compare output" and "10-bit PWM" which are selected by bit in Timer mode register TMx as shown in Figure 15-1 and Table 12-1 .
Timer 0 Mode Register TM0 CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST ADDRESS : D0H RESET VALUE : --000000
CAP0
Capture mode selection bit. 0 : Disables Capture 1 : Enables Capture Input clock selection 000 : fXI / 2100 : fXI / 128 001 : fXI / 4101 : fXI / 512 010 : fXI / 8110 : fXI / 2048
T0CN
Continue control bit 0 : Stop counting 1 : Start counting continuously Start control bit 0 : Stop counting 1 : Counter register is cleared and start again
T0CK[2:0]
T0ST
011 : fXI / 32111 : External Event (EC0) Timer 1 Mode Register TM1 POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST ADDRESS : D2H RESET VALUE : 00000000
POL
PWM Output Polarity 0 :Duty active low 1 : Duty active high 16-bit mode selection 0 : 8-bit mode 1 : 16-bit mode PWM enable bit 0 : Disables PWM 1 : Enables PWM Capture mode selection bit. 0 : Disables Capture 1 : Enables Capture
T1CK[2:0]]
Input clock selection 00 : fXI 10 : fXI / 8
01 : fXI / 211 : using the Timer 0 clock
16BIT
T1CN
Continue control bit 0 : Stop counting 1 : Start counting continuously Start control bit 0 : Stop counting 1 : Counter register is cleared and start again
PWM1E
T1ST
CAP1
Figure 15-1 Timer Mode Register ( TMx , x = 0~1 )
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16BIT 0 0 0 0 1 1 1 1
CAP0 0 0 1 X1 0 0 1 0
CAP1 0 1 0 0 0 0 X 0
PWM1E 0 0 0 1 0 0 0 0
T0CK[2:0] XXX 111 XXX XXX XXX 111 XXX XXX
T1CK[1:0] XX XX XX XX 11 11 11 11
PWMO 0 0 1 1 0 0 0 1
TIMER 0 8-bit Timer 8-bit Event Counter 8-bit Capture 8-bit Timer/Counter 16-bit Timer 16-bit Event Counter 16-bit Capture 16-bit Compare output
TIMER1 8-bit Timer 8-bit Capture 8-bit Compare output 10-bit PWM
Table 15-1 Operating Modes of Timer 0 and Timer 1
1. X : The value "0" or "1" corresponding your operation.
15.1 8-bit Timer/Counter Mode
The GMS81C2020 and GMS81C2120 has four 8-bit Timer/Counters, Timer 0, Timer 1 as shown in Figure 15-2 . The "timer" or "counter" function is selected by mode registers TMx as shown in Figure 15-1 and Table 15-1 . To use as an 8-bit timer/counter mode, bit CAP0 of TM0 is cleared to "0" and bits 16BIT of TM1 should be cleared to "0"(Table 15-1 ).
TM0
-
16BIT 0
CAP0 0 PWM1E 0 T0CK[2:0]
T0CK2 X CAP1 0
T0CK1 X T1CK1 X
T0CK0 X T1CK0 X
T0CN X T1CN X
T0ST X T1ST X
ADDRESS : D0H RESET VALUE : --000000
TM1
POL X
ADDRESS : D2H RESET VALUE : 00000000
X : The value "0" or "1" corresponding your operation.
T0ST 0 : Stop 1 : Clear and Start F/F R40/T0O R4FUNC.0 T0IF T0CN TDR0 ( 8-bit )
COMPARATOR
Edge Detector
EC0
fXI
/2 /4 /8 / 32 / 128 / 512 / 2048 /1 /2 /8
MUX
T0CK
1
T0 ( 8-bit )
CLEAR
TIMER 0 INTERRUPT
T1CK[1:0]
T1ST 0 : Stop 1 : Clear and Start
1
F/F R56/PWM1O/T1O R5FUNC.6 T1IF TIMER 1 INTERRUPT
MUX
T1 ( 8-bit )
CLEAR
T1CN TDR1 ( 8-bit )
COMPARATOR
Figure 15-2 8-bit Timer / Counter Mode
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These timers have each 8-bit count register and data register. The count register is increased by every internal or external clock input. The internal clock has a prescaler divide ratio option of 2, 4, 8, 32,128, 512, 2048 (selected by control bits T0CK2, T0CK1 and T0CK0 of register TM0) and 1, 2, 8 (selected by control bits T1CK1 and T1CK0 of register TM1). In the Timer 0, timer register T0 increases from 00H until it matches TDR0 and then reset to 00H. The match output of Timer 0 generates Timer 0 interrupt
(latched in T0IF bit). As TDRx and Tx register are in same address, when reading it as a Tx, written to TDRx. In counter function, the counter is increased every 0-to1(1-to-0) (rising & falling edge) transition of EC0 pin. In order to use counter function, the bit EC0 of the R0 Function Selection Register (R0FUNC.2) is set to "1". The Timer 0 can be used as a counter by pin EC0 input, but Timer 1 can not.
TDR1
n n-1
up -c ou nt
9 8 7 6
PCP
~ ~
~ ~
~ ~
2 1 0
5 4 3
TIME
Interrupt period = PCP x (n+1)
Timer 1 (T1IF) Interrupt
Occur interrupt
Occur interrupt
Occur interrupt
Figure 15-3 Counting Example of Timer Data Registers
TDR1
disable enable
clear & start stop
up -c ou n
t
~ ~
~ ~
TIME Timer 1 (T1IF) Interrupt
Occur interrupt Occur interrupt
T1ST Start & Stop
T1ST = 0
T1ST = 1
T1CN Control count
T1CN = 0 T1CN = 1
Figure 15-4 Timer Count Operation
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15.2 16-bit Timer/Counter Mode
The Timer register is being run with 16 bits. A 16-bit timer/ counter register T0, T1 are increased from 0000H until it matches TDR0, TDR1 and then resets to 0000 H . The match output generates Timer 0 interrupt not Timer 1 interrupt. The clock source of the Timer 0 is selected either internal or external clock by bit T0CK2, T0CK1 and T0CK0. In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1 should be set to "1" respectively.
TM0
-
16BIT 1
CAP0 0 PWM1E 0
T0CK2 X CAP1 0
T0CK1 X T1CK1 1
T0CK0 X T1CK0 1
T0CN X T1CN X
T0ST X T1ST X
ADDRESS : D0H RESET VALUE : --000000
TM1
POL X
ADDRESS : D2H RESET VALUE : 00000000
X : The value "0" or "1" corresponding your operation.
T0CK[2:0] Edge Detector T0CN T1CK[1:0] T0ST 0 : Stop 1 : Clear and Start
11
1
EC0
fXI
/2 /4 /8 / 32 / 128 / 512 / 2048
MUX
XX
T1 ( 8-bit )
T0 ( 8-bit )
CLEAR
F/F R40/T0O R4FUNC.0 T0IF TIMER 0 INTERRUPT
fXI
/1 /2 /8
TDR1 ( 8-bit )
COMPARATOR
TDR0 ( 8-bit )
Figure 15-5 16-bit Timer / Counter Mode
15.3 8-bit Compare Output ( 16-bit )
The GMS81C2020 and GMS81C2120 has a function of Timer Compare Output. To pulse out, the timer match can goes to port pin(T0O, T1O) as shown in Figure 15-2 and Figure 15-5 . Thus, pulse out is generated by the timer match. These operation is implemented to pin, T0O, PWM1O/T1O. This pin output the signal having a 50 : 50 duty square wave, and output frequency is same as below equation.
= ----------------------------------------------------------------------------------------- x
x ( + )
In this mode, the bit PWM1O/T1O of R5 function register (R5FUNC.6) should be set to "1", and the bit PWM1E of timer1 mode register ( TM1 ) should be set to "0". In addition, 16-bit Compare output mode is available, also.
15.4 8-bit Capture Mode
The Timer 0 capture mode is set by bit CAP0 of timer mode register TM0 (bit CAP1 of timer mode register TM1 for Timer 1) as shown in Figure 15-6 . As mentioned above, not only Timer 0 but Timer 1 can also be used as a capture mode. The Timer/Counter register is increased in response internal or external input. This counting function is same with normal timer mode, and Timer interrupt is generated when
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timer register T0 (T1) increases and matches TDR0 (TDR1). This timer interrupt in capture mode is very useful when the pulse width of captured signal is more wider than the maximum period of Timer. For example, in Figure 15-8 , the pulse width of captured signal is wider than the timer data value (FF H ) over 2 times. When external interrupt is occured, the captured value (13H) is more little than wanted value. It can be obtained correct value by counting the number of timer overflow occurence. Timer/Counter still does the above, but with the added feature that a edge transition at external input INTx pin causes the current value in the Timer x register (T0,T1), to be cap-
tured into registers CDRx (CDR0, CDR1), respectively. After captured, Timer x register is cleared and restarts by hardware. It has three transition modes: "falling edge", "rising edge", "both edge" which are selected by interrupt edge selection register IEDS (Refer to External interrupt section). In addition, the transition at INTx pin generate an interrupt.
Note: The CDRx, TDRx and Tx are in same address. In the capture mode, reading operation is read the CDRx, not Tx because path is opened to the CDRx, and TDRx is only for writing operation.
TM0
-
16BIT 0
CAP0 1 PWM1E 0 T0CK[2:0]
T0CK2 X CAP1 1
T0CK1 X T1CK1 X
T0CK0 X T1CK0 X
T0CN X T1CN X T0ST
T0ST X T1ST X
ADDRESS : D0H RESET VALUE : --000000
TM1
POL X
ADDRESS : D2H RESET VALUE : 00000000
Edge Detector
0 : Stop 1 : Clear and Start T0CK
1
EC0
fXI
/2 /4 /8 / 32 / 128 / 512 / 2048
MUX
T0 ( 8-bit )
CLEAR
CAPTURE
T0IF
COMPARATOR
T0CN CDR0 ( 8-bit )
TIMER 0 INTERRUPT
TDR0 ( 8-bit )
INT0IF INT0 IEDS[1:0] T0ST 0 : Stop 1 : Clear and Start
INT 0 INTERRUPT
/1 /2 /8
1
MUX
T1 ( 8-bit )
CLEAR
CAPTURE
T1IF
COMPARATOR
T1CK[1:0] IEDS[3:2]
T1CN CDR1 ( 8-bit )
TIMER 1 INTERRUPT
TDR1 ( 8-bit )
INT1IF INT1
INT 1 INTERRUPT
Figure 15-6 8-bit Capture Mode
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T0
up -c ou nt
n n-1
This value is loaded to CDR0
~ ~
~ ~
9 8 7 6
5 4 3 2 1 0
~ ~
TIME
Ext. INT0 Pin
Interrupt Request ( INT0F ) Interrupt Interval Period
Ext. INT0 Pin
Interrupt Request ( INT0F ) Capture ( Timer Stop )
Delay Clear & Start
Figure 15-7 Input Capture Operation
Ext. INT0 Pin
Interrupt Request ( INT0F ) Interrupt Interval Period = FFH + 01H + FFH +01H + 13H = 213H Interrupt Request ( T0F ) FFH T0 13H 00H 00H FFH
Figure 15-8 Excess Timer Overflow in Capture Mode
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15.5 16-bit Capture Mode
16-bit capture mode is the same as 8-bit capture, except that the Timer register is being run will 16 bits. The clock source of the Timer 0 is selected either internal or external clock by bit T0CK2, T0CK1 and T0CK0.
ADDRESS : D0H RESET VALUE : --000000
In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1 should be set to "1" respectively.
TM0
-
16BIT 1
CAP0 1 PWM1E 0
T0CK2 X CAP1 X
T0CK1 X T1CK1 1
T0CK0 X T1CK0 1
T0CN X T1CN X
T0ST X T1ST X
TM1
POL X
ADDRESS : D2H RESET VALUE : 00000000
X : The value "0" or "1" corresponding your operation.
T0CK[2:0] Edge Detector T0CN T1CK[1:0] T0ST 0 : Stop 1 : Clear and Start
11
1
EC0
fXI
/2 /4 /8 / 32 / 128 / 512 / 2048
MUX
XX
T0 + T1 ( 16-bit )
CLEAR
fXI
/1 /2 /8
CAPTURE
T0IF
COMPARATOR
TIMER 0 INTERRUPT
CDR1 CDR0 TDR1 TDR0 ( 8-bit ) ( 8-bit ) ( 8-bit ) ( 8-bit ) INT0IF INT 0 INTERRUPT
INT0 IEDS[1:0]
Figure 15-9 16-bit Capture Mode
15.6 PWM Mode
The GMS81C2020 and GMS81C2120 has a high speed PWM (Pulse Width Modulation) functions which shared with Timer1. In PWM mode, pin R56/PWM1O/T1O outputs up to a 10bit resolution PWM output. This pin should be configured as a PWM output by setting "1" bit PWM1O in R5FUNC.6 register. The period of the PWM output is determined by the T1PPR (PWM1 Period Register) and PWM1HR[3:2] (bit3,2 of PWM1 High Register) and the duty of the PWM output is determined by the T1PDR (PWM1 Duty Register) and PWM1HR[1:0] (bit1,0 of PWM1 High Register). The user writes the lower 8-bit period value to the T1PPR and the higher 2-bit period value to the PWM1HR[3:2]. And writes duty value to the T1PDR and the PWM1HR[1:0] same way. The T1PDR is configured as a double buffering for glitchless PWM output. In Figure 15-10 , the duty data is transfered from the master to the slave when the period data matched to the counted value. ( i.e. at the beginning of next duty cycle )
PWM Period = [ PWM1HR[3:2]T1PPR ] X Source Clock PWM Duty = [ PWM1HR[1:0]T1PDR ] X Source Clock
The relation of frequency and resolution is in inverse proportion. Table 15-2 shows the relation of PWM frequency vs. resolution.
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If it needed more higher frequency of PWM, it should be reduced resolution.
Frequency Resolution 10-bit 9-bit 8-bit 7-bit T1CK[1:0] = 00(250nS) 3.9KHz 7.8KHz 15.6KHz 31.2KHz T1CK[1:0] = 01(500nS) 0.98KHZ 1.95KHz 3.90KHz 7.81KHz T1CK[1:0] = 10(2uS) 0.49KHZ 0.97KHz 1.95KHz 3.90KHz
The bit POL of TM1 decides the polarity of duty cycle. If the duty value is set same to the period value, the PWM output is determined by the bit POL ( 1: High, 0: Low ). And if the duty value is set to "00H", the PWM output is determined by the bit POL ( 1: Low, 0: High ). It can be changed duty value when the PWM output. Howerver the changed duty value is output after the current period is over. And it can be maintained the duty value at present output when changed only period value shown as Figure 15-12 . As it were, the absolute duty time is not changed in varying frequency. But the changed period value must greater than the duty value.
Table 15-2 PWM Frequency vs. Resolution at 4MHz
TM1
POL X
16BIT 0 -
PWM1E 1 -
CAP1 0 -
T1CK1 X
T1CK0 X
T1CN X
T1ST X
ADDRESS : D2H RESET VALUE : 00000000
PWM1HR
-
PWM1HR3PWM1HR2PWM1HR1PWM1HR0 X X X Duty High X
ADDRESS : D5H RESET VALUE : ----0000 Bit Manipulation Not Available
Period High PWM1HR[3:2] T1ST T0 clock source [T0CK] 0 : Stop 1 : Clear and Start T1PPR(8-bit)
X : The value "0" or "1" corresponding your operation.
COMPARATOR
R56/ PWM1O/T1O SQ
1
CLEAR
fXI
/1 /2 /8
MUX
(2-bit)
R PWM1O [R5FUNC.6] POL
T1 ( 8-bit )
COMPARATOR
T1CK[1:0]
T1CN Slave T1PDR(8-bit)
PWM1HR[1:0] Master
T1PDR(8-bit)
Figure 15-10 PWM Mode
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~ ~
~ ~
fXI
~~ ~~
~~~ ~~~
T1 PWM POL=1 PWM POL=0
00 01
02
03
04
05
7F
80
81
3FF
00 01
02
03
Duty Cycle [ 80H x 250nS = 32uS ] Period Cycle [ 3FFH x 250nS = 255.75uS, 3.9KHz ] T1CK[1:0] = 00 ( fXI ) PWM1HR = 0CH T1PPR = FFH T1PDR = 80H
Duty PWM1HR1PWM1HR0 0 0 T1PDR (8-bit) 80H
~ ~
Period PWM1HR3PWM1HR2 1 1
T1PPR (8-bit) FFH
Figure 15-11 Example of PWM at 4MHz
T 1C K [1:0] = 10 ( 1uS ) P W M 1H R = 00H T 1P P R = 0E H T 1P D R = 05H Source clock T1 PWM POL=1 Duty Cycle [ 05H x 2uS = 10uS ] Period Cycle [ 0EH x 2uS = 28uS, 35.5KHz ] Duty Cycle [ 05H x 2uS = 10uS ] Duty Cycle [ 05H x 2uS = 10uS ]
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 01 02 03 04 05 06 07 08 09 0A 01 02 03 04 05
Write T1PPR to 0AH
~ ~
Period changed Period Cycle [ 0AH x 2uS = 20uS, 50KHz ]
Figure 15-12 Example of Changing the Period in Absolute Duty Cycle (@4MHz)
~ ~
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16. Serial Peripheral Interface
The Serial Peripheral Interface (SPI) module is a serial interface useful for communicating with other peripheral of microcontroller devices. These peripheral devices may be
SPI Mode Control Register SIOM POL IOSW SM1 SM0 SCK1 SCK0 SIOST SIOSF ADDRESS : E0H RESET VALUE : 00000000
serial EEPROMs, shift registers, display drivers, A/D converters, etc.
POL
Serial Clock Polarity Selection bit. 0 : Data Transmission at falling edge ( Received data latch at rising edge ) 1 : Data Transmission at rising edge ( Received data latch at falling edge ) Serial Input Pin Selection bit 0 : SIN(R54) Pin Selection 1 : SOUT(R55) Pin Selection Serial Operation Mode Selection bits 00 : Normal Port ( R55, R54, R53 ) 01 : Transmit Mode ( SOUT,R54, SCLK ) 10 : Receive Mode ( R55, SIN, SCLK ) 11 : Transmit & Receive Mode ( SOUT, SIN, SCLK )
SCK[1:0]
Serial Clock Selection bits 00 : fXI / 4
01 : fXI / 16 10 : TMR0OV ( Overflow of Timer 0 ) 11 : External Clock
IOSW
SIOST
Serial Transmit Start bit 0 : Disable 1 : Start ( After one SCLK, becomes "0" ) Serial Transmit Status bit 0 : During Transmission 1 : Finished
SM[1:0]
SIOSF
SPI Data Register SIOR ADDRESS : E1H RESET VALUE : Undefined
T0CK[2:0]
POL [SIOM.7]
SIOST
0 : Disable 1 : Clear and Start
SIOSF
0 : Process 1 : Completed
fXI
/4 /16
MUX
SPI Control Circuit Octal Counter ( 3-Bit ) SPIIF
TMR0OV (Timer 0 overflow) 1 0 R53/SCLK
SPI INTERRUPT
SCLKI SCLKO MSB LSB
SIOR ( 8-Bit ) R54/SIN IOSW IOSW R55/SOUT
SCLK [R5FUNC.3]
Figure 16-1 SPI Registers and Block Diagram
The SPI allows 8-bits of data to be synchronously transmitted and received. To accomplish communication, typically three pins are used: - Serial Data In - Serial Data Out - Serial Clock R54/SIN R55/SOUT R53/SCLK
The serial data transfer operation mode is decided by setting the SM1 and SM0 of SPI Mode Control Register, and the transfer clock rate is decided by setting the SCK1 and SCK0 of SPI Mode Control Register as shown in Figure 16-1 . And the polarity of transfer clock is selected by set-
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ting the POL..
SIOST SCLK (POL=1) SCLK (POL=0) SOUT SIN SPIIF (SPI Int. Req)
D0 D1 D2 D3 D4 D5 D6 D7
D0
D1
D2
D3
D4
D5
D6
D7
76543210 "0" C 76543210
C
SIOR (Data Output :SOUT)
SIOR (Data Input :SIN)
Figure 16-2 SPI Timing Diagram
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17. Buzzer Output function
The buzzer driver consists of 6-bit binary counter, the buzzer register BUR and the clock selector. It generates square-wave which is very wide range frequency (480 Hz~250 KHz at fxin = 4 MHz) by user programmable counter. Pin R03 is assigned for output port of Buzzer driver by setting the bit BUZO of R0FUNC to "1". The 6-bit buzzer counter is cleared and start the counting by writing signal to the register BUR. It is increased from 00H until it matches 6-bit register BUR. Also, it is cleared by counter overflow and count up to output the square wave pulse of duty 50%. The bit 0 to 5 of BUR determines output frequency for buzzer driving. Frequency calculation is following as shown below.
Oscillator Frequency ( ) = ----------------------------------------------------------------------------------- x Prescaler Ratio x ( + )
The bits BUCK1, BUCK0 of BUR selects the source clock from prescaler output.
BUR
BUCK1
BUCK0
BUR5
BUR4
BUR3
BUR2
BUR1
BUR0
ADDRESS : DEH RESET VALUE : 11111111 Bit Manipulation Not Available
Input clock selection 00 : fXI / 8 01 : fXI / 16
Buzzer Period Data
10 : fXI / 32 11 : fXI / 64
fXI
/8 / 16 / 32 / 64
MUX
Counter ( 6-bit )
Overflow Detector Writing to BUR[5:0]
F/F R03/BUZO BUZO [R0FUNC.3]
BUCK[1:0] BUR ( 6-bit )
RESET
Figure 17-1 Buzzer Driver
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18. ANALOG TO DIGITAL CONVERTER
The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 8-bit digital value. The A/D module has twelve analog inputs, which are multiplexed into one sample and hold. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The A/D module has two registers which are the control register ADCM and A/D result register ADCR. The ADCM register, shown in Figure 18-2 , controls the operation of the A/D converter module. The port pins can be configured as analog inputs or digital I/O. To use analog inputs, each port is assigned analog input port by setting the bit ANSEL[7:0] in R6FUNC register. Also it is assigned analog input port by setting the bit ANADS[3:0] R6FUNC[7:0] R7FUNC[3:0]
SEL[11:8] in R7FUNC register. And selected the corresponding channel to be converted by setting ADS[3:0]. The processing of conversion is start when the start bit ADST is set to "1". After one cycle, it is cleared by hardware. The register ADCR contains the results of the A/D conversion. When the conversion is completed, the result is loaded into the ADCR, the A/D conversion status bit ADSF is set to "1", and the A/D interrupt flag ADIF is set. The block diagram of the A/D module is shown in Figure 18-1 . The A/D status bit ADSF is set automatically when A/D conversion is completed, cleared when A/D conversion is in process. The conversion time takes maximum 20 uS (at fXI=4 MHz).
R67/AN7 ANSEL7 R66/AN6 ANSEL6 R65/AN5 ANSEL5 R64/AN4 ANSEL4 R63/AN3 ANSEL3 R62/AN2 ANSEL2 R61/AN1 ANSEL1 R60/AN0 ANSEL0
0111
1011 ANSEL11
R73/AN11
0110
1010 ANSEL10
R72/AN10
0101
1001 ANSEL9
R71/AN9
0100
1000 ANSEL8
R70/AN8
0011
0010
A/D Result Register ADCR(8-bit) ADDRESS : EBH RESET VALUE : Undefined
0001
Sample & Hold COMPARATOR
0000
S/H
Successive Approximation Circuit
A D IF
A/D Interrupt
AVDD
Resistor Ladder Circuit ADEN [ADCM.6]
Figure 18-1 A/D Converter Block Diagram
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A/D Control Register ADCM Reserved Analog Channel Select 0000 : Channel 0 ( R60/AN0 ) 0001 : Channel 1 ( R61/AN1 ) 0010 : Channel 2 ( R62/AN2 ) 0011 : Channel 3 ( R63/AN3) 0100 : Channel 4 ( R64/AN4 ) 0101 : Channel 5 ( R65/AN5 ) 0110 : Channel 6 ( R66/AN6 ) 0111 : Channel 7 ( R67/AN7 ) 1000 : Channel 8 ( R64/AN8 ) 1001 : Channel 9 ( R65/AN9 ) 1010 : Channel 10 ( R66/AN10 ) 1011 : Channel 11 ( R67/AN11 ) ADEN ADS3 ADS2 ADS1 ADS0 ADST ADSF ADDRESS : EAH RESET VALUE : -0000001 A/D Status bit 0 : A/D Conversion is in process 1 : A/D Conversion is completed A/D Start bit 1 : A/D Conversion is started After 1 cycle, cleared to "0" 0 : Bit force to zero
A/D Enable bit 1 : A/D Conversion is enable 0 : A/D Converter module shut off and consumes no operation current
A/D Result Data Register ADCR ADCR7 ADCR6 ADCR5 ADCR4 ADCR3 ADCR2 ADCR1 ADCR0 ADDRESS : EBH RESET VALUE : Undefined
Figure 18-2 A/D Converter Registers
A/D Converter Cautions
ENABLE A/D CONVERTER
(1) Input range of AN11 to AN0 The input voltages of AN11 to AN0 should be within the specification range. In particular, if a voltage above AVDD
A/D INPUT CHANNEL SELECT
ANALOG REFERENCE SELECT
or below AVSS is input (even if within the absolute maximum rating range), the conversion value for that channel can not be indeterminate. The conversion values of the other channels may also be affected.
(2) Noise countermeasures
A/D START ( ADST = 1 )
In order to maintain 8-bit resolution, attention must be paid to noise on pins AVDD and AN11 to AN0. Since the effect in-
creases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected
externally as shown in Figure 18-4 in order to reduce noise.
NOP
ADSF = 1 NO YES
Analog Input 100~1000pF
AN11~AN0
READ ADCR
Figure 18-4 Analog Input Pin Connecting Capacitor Figure 18-3 A/D Converter Operation Flow
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(3) Pins AN11/R73 to AN8/R70 and AN7/R67 to AN0/ R60 The analog input pins AN11 to AN0 also function as input/ output port (PORT R7 and R6) pins. When A/D conversion is performed with any of pins AN11 to AN0 selected, be sure not to execute a PORT input instruction while conversion is in progress, as this may reduce the conversion resolution. Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected A/D conversion value may not be obtainable due to coupling
noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion.
(4) AVDD pin input impedance A series resistor string of approximately 10K is connected between the AVDD pin and the AVSS pin.
Therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection to the
series resistor string between the AVDD pin and the AVSS pin, and there will be a large reference voltage error.
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19. INTERRUPTS
The GMS81C2020 and GMS81C2120 interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Interrupt Edge Selection Register (IEDS), priority circuit and Master enable flag("I" flag of PSW). The configuration of interrupt circuit is shown in Figure and Interrupt priority is shown in Table 19-1 . The External Interrupts INT0 and INT1 can each be transition-activated (1-to-0, 0-to-1 and both transiton). The flags that actually generate these interrupts are bit INT0IF and INT1IF in Register IRQH. When an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. The Timer 0 and Timer 1 Interrupts are generated by T0IF and T1IF, which are set by a match in their respective timer/counter register. The AD converter Interrupt is generated by ADIF which is set by finishing the analog to digital conversion. The Watch dog timer Interrupt is generated by WDTIF which set by a match in Watch dog timer register (when the bit WDTON is set to "0"). The Basic Interval Timer Interrupt is generated by BITIF which is set by a overflowing of the Basic Interval Timer Register(BITR). The Serial Peripheral Interface (SPI) is generated by SPIIF which is set by communicating with other peripheral of microcontroller devices (by finishing the data transmission).
Internal bus line I-flag is in PSW, it is cleared by "DI", set by "EI" instruction.When it goes interrupt service, I-flag is cleared by hardware, thus any other interrupt are inhibited. When interrupt service is completed by "RETI" instruction, I-flag is set to "1" by hardware.
IEDS[3:0]
IRQH 7 6 5 4
IENH[7:4]
Interrupt Enable Register (Higher byte)
External Int. 0 External Int. 1 Timer 0 Timer 1
INT0IF INT1IF T0IF T1IF
Release STOP
To CPU I Flag
IRQH[7:4] IRQL[7:4] A/D Converter WDT BIT SPI
ADIF WDTIF BITIF SPIIF
Priority Control
7 6 5 4
Interrupt Master Enable Flag[PSW.2]
Interrupt Vector Address Generator
IRQL
IENL[7:4]
Interrupt Enable Register (Lower byte)
Internal bus line
Figure 19-1 Block Diagram of Interrupt Function
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The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW), the interrupt enable register (IENH, IENL) and the interrupt request flags (in IRQH, IRQL) except Power-on reset and software BRK interrupt. Interrupt enable registers are shown in Figure 19-2 . These registers are composed of interrupt enable flags of each interrupt source, these flags determines whether an interrupt will be accepted or not. When enable flag is "0", a corresponding interrupt source is prohibited. Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once.
Reset/Interrupt Hardware Reset External Interrupt 0 External Interrupt 1 Timer 0 Timer 1 A/D Converter Watch Dog Timer Basic Interval Timer Serial Interface
Symbol RESET INT0 INT1 Timer 0 Timer 1 A/D C WDT BIT SPI
Priority 1 2 3 4 5 6 7 8
Vector Addr. FFFEH FFFAH FFF8H FFF6H FFF4H FFF2H FFF0H FFEEH FFECH FFEAH FFE8H FFE6H
Table 19-1 Interrupt Priority
Interrupt Enable Register High IENH INT0E INT1E T0E T1E ADDRESS : E2H RESET VALUE : 0000----
Interrupt Enable Register Low IENL ADE WDTE BITE SPIE ADDRESS : E3H RESET VALUE : 0000----
Enables or disables the interrupt individually If flag is cleared, the interrupt is disabled. 0 : Disable 1 : Enable Interrupt Request Register High IRQH INT0IF INT1IF T0IF T1IF ADDRESS : E4H RESET VALUE : 0000----
Interrupt Request Register Low IRQL ADIF WDTIF BITIF SPIIF ADDRESS : E5H RESET VALUE : 0000----
Shows the interrupt occurrence 0 : Not occurred 1 : Interrupt request is occurred
Figure 19-2 Interrupt Enable Registers and Interrupt Request Registers
When an interrupt is occured, the I-flag is cleared and disable any further interrupt, the return address and PSW are pushed into the stack and the PC is vectored to. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt request flag bits.
The interrupt request flag bit(s) must be cleared by software before re-enabling interrupts to avoid recursive interrupts. The Interrupt Request flags are able to be read and written.
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19.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to "0" by a reset or an instruction. Interrupt acceptance sequence requires 8 f OSC (2 s at fXI=4MHz) after the completion of the current instruction execution. The interrupt service task is terminated upon execution of an interrupt return instruction [RETI]. Interrupt acceptance 1. The interrupt master enable flag (I-flag) is cleared to "0" to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. Interrupt request flag for the interrupt source accepted is cleared to "0". 3. The contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. The stack pointer decreases 3 times. 4. The entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. The instruction stored at the entry address of the interrupt service program is executed.
System clock
Instruction Fetch Address Bus
PC SP SP-1 SP-2 V.L. V.H. New PC
Data Bus Internal Read Internal Write
Not used
PCH
PCL
PSW
V.L.
ADL
ADH
OP code
Interrupt Processing Step V.L. and V.H. are vector addresses. ADL and ADH are start addresses of interrupt service routine as vector contents.
Interrupt Service Task
Figure 19-3 Timing chart of Interrupt Acceptance and Interrupt Return Instruction
Basic Interval Timer Vector Table Address
Entry Address
When nested interrupt service is required, the I-flag should be set to "1" by "EI" instruction in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. Saving/Restoring General-purpose Register During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. These registers are saved by the software if necessary. Also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory area for saving registers.
0FFE6H 0FFE7H
012H 0E3H
0E312H 0E313H
0EH 2EH
Correspondence between vector table address for BIT interrupt and the entry address of the interrupt service program.
A interrupt request is not accepted until the I-flag is set to "1" even if a requested interrupt has higher priority than that of the current interrupt being serviced.
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The following method is used to save/restore the generalpurpose registers. Example: Register save using push and pop instructions
INTxx: PUSH PUSH PUSH A X Y ;SAVE ACC. ;SAVE X REG. ;SAVE Y REG.
General-purpose register save/restore using push and pop instructions;
main task acceptance of interrupt interrupt service task saving registers
interrupt processing
POP POP POP RETI
Y X A
;RESTORE Y REG. ;RESTORE X REG. ;RESTORE ACC. ;RETURN
restoring registers interrupt return
19.2 BRK Interrupt
Software interrupt can be invoked by BRK instruction, which has the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0. Each processing step is determined by B-flag as shown in Figure 19-4 .
BRK or TCALL0
B-FLAG =1 BRK INTERRUPT ROUTINE RETI
=0
TCALL0 ROUTINE
RET
Figure 19-4 Execution of BRK/TCALL0
19.3 Multi Interrupt
If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the interrupt are received at the same time simultaneously, an internal polling sequence determines by hardware which request is serviced. However, multiple processing through software for special features is possible. Generally when an interrupt is accepted, the I-flag is cleared to disable any further interrupt. But as user sets I-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress.
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Main Program service
Example: Even though Timer1 interrupt is in progress, INT0 interrupt serviced without any suspend.
TIMER 1 service INT0 service
enable INT0 disable other EI
Occur TIMER1 interrupt
Occur INT0
TIMER1: PUSH PUSH PUSH LDM LDM EI : : : : : : LDM LDM POP POP POP RETI
A X Y IENH,#80H IENL,#0
;Enable INT0 only ;Disable other ;Enable Interrupt
enable INT0 enable other
IENH,#0FFH ;Enable all interrupts IENL,#0F0H Y X A
In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENL and master enable "EI" in the TIMER1 routine.
Figure 19-5 Execution of Multi Interrupt
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19.4 External Interrupt
The external interrupt on INT0 and INT1 pins are edge triggered depending on the edge selection register IEDS (address 0E6H) as shown in Figure 19-6 . The edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge. Example: To use as an INT0, INT1
: : ;**** Set port as an input port R00,R01 LDM R0IO,#1111_1100B ; ;**** Set port as an interrupt port LDM R0FUNC,#03H ; ;**** Set Falling-edge Detection LDM IEDS,#0000_0101B : : :
INT0 pin
INT0IF
INT0 INTERRUPT
edge selection
INT1 pin
INT1IF
INT1 INTERRUPT
Response Time The INT0 and INT1 edge are latched into INT0IF and INT3IF at every machine cycle. The values are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The DIV itself takes twelve cycles. Thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. shows interrupt response timings.
IEDS [0E6H]
Figure 19-6 External Interrupt Block Diagram
Ext. Interrupt Edge Selection Register W IEDS
ADDRESS : 0E6H RESET VALUE : ----0000 W W W
INT1 edge select 00: Int. disable 01: falling 10: rising 11: both
INT0 edge select 00: Int. disable 01: falling 10: rising 11: both
max. 12 fOSC
8 fOSC
Interrupt Interrupt goes latched active
Interrupt processing
Interrupt routine
Figure 19-7 Interrupt Response Timing Diagram
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20. WATCHDOG TIMER
The purpose of the watchdog timer is to detect the malfunction (runaway) of program due to external noise or other causes and return the operation to the normal condition. The watchdog timer has two types of clock source. The first type is an on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the external oscillator of the Xin pin. It means that the watchdog timer will run, even if the clock on the Xin pin of the device has been stopped, for example, by entering the STOP mode. The other type is a prescaled system clock. The watchdog timer consists of 7-bit binary counter and the watchdog timer data register. When the value of 7-bit binary counter is equal to the lower 7 bits of WDTR, the interrupt request flag is generated. This can be used as WDT interrupt or reset the CPU in accordance with the bit WDTON .
Note: Because the watchdog timer counter is enabled after clearing Basic Interval Timer, after the bit WDTON set to "1", maximum error of timer is depend on prescaler ratio of Basic Interval Timer.
The 7-bit binary counter is cleared by setting WDTCL(bit7 of WDTR) and the WDTCL is cleared automatically after 1 maching cycle. The RC oscillated watchdog timer is activated by setting the bit RCWDT as shown below.
: LDM LDM STOP NOP NOP : CKCTLR,#3FH; enable the RC-osc WDT WDTR,#0FFH; set the WDT period ; enter the STOP mode ; RC-osc WDT running
The RCWDT oscillation period is vary with temperature, VDD and process variations from part to part (approximately, 40~120uS ). The following equation shows the RCWDT oscillated watchdog timer time-out. T R C W D T = C L K R C W D T x28x[W D T R .6~ 0]+ (C L K R C W D T x28)/2 w here, C L K R C W D T = 40~ 120uS In addition, this watchdog timer can be used as a simple 7bit timer by interrupt WDTIF. The interval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is as below. TWDT = [WDTR.6~0] x Interval of BIT
Clock Control Register CKCTLR WAKEUP RCWDT 0 X WDTON 1 BTCL X BTS2 X BTS1 X BTS0 X ADDRESS : ECH RESET VALUE : -0010111 Bit Manipulation Not Available
Watchdog Timer Register WDTR WDTCL
7-bit Watchdog Counter Register
ADDRESS : EDH RESET VALUE : 01111111 Bit Manipulation Not Available
WAKEUP STOP
RCWDT
WDTCL WDTR (7-bit) WDTCL RESET WDTON
fXI
/8 / 16 / 32 / 64 / 128 / 256 / 512 /1024
BTCL Clear
MUX 0 BITR (8-BIT) 1 7-bit Counter
1
OFD
To RESET
0 Overflow Detection Watchdog Timer Interrupt Request
BTS[2:0]
BITIF Internal RC OSC
Basic Interval Timer Interrupt
Figure 20-1 Block Diagram of Watchdog Timer
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21. Power Saving Mode
For applications where power consumption is a critical factor, device provides four kinds of power saving functions, STOP mode, Subactive mode and Wake-up Timer mode(Standby mode, Watch mode). Table 21-1 shows the status of each Power Saving Mode.
Wake-up Timer Mode Standby Mode RAM Control Registers I/O Ports CPU Timer0 Oscillation Sub Oscillation Prescaler Entering Condition [WAKEUP] Retain Retain Retain Stop Stop Stop Stop Stop 0 Retain Retain Retain Operation Operation Stop Oscillation Operation 0 Table 21-1 Power Saving Mode Retain Retain Retain Stop Operation Oscillation Stop / 2048 only 1 Watch Mode Retain Retain Retain Stop Operation Stop Oscillation / 2048 only 1
Peripheral
STOP Mode
Subactive Mode
The power saving function is activated by execution of STOP instruction and by execution of STOP instruction after setting the corresponding status (WAKEUP) of CKCTLR.
Subactive Mode O O O X
we shows the release sources from each Power Saving Mode
Release Source RESET RCWDT EXT.INT EXT.INT1 Timer0
STOP Mode O O O X
Wake-up Timer Mode Standby Mode O O O O Watch Mode O O O O
Table 21-2 Release Sources from Power Saving Mode
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21.1 Operating Mode
SUB-ACTIVE Mode
fXI fSXI fSYS fSUB cpu tmr peri
: main clock frequency : sub clock frequency : fXI/2,fXI/8,fXI/16,fXI/64 : fSXI/2,fSXI/8,fSXI/16,fSXI/64 : system clock : timer0 clock : peripheral clock
SCMR.1 = 1 SCMR.0 = 0/1 fXI : stop fSXI : oscillation cpu : fSUB tmr : fSUB peri : fSUB
CKCTLR[10] + STOP
CKCTLR = CKCTLR[6:5] SCMR.0 = 0 + SCMR.1 = 0 SCMR.1 = 1
TIMER0 EXT_INT RESET RC_WDT
STANDBY Mode SCMR.1 = 0 fXI : oscillation fSXI : oscillation cpu : stop tmr : ps11(fXI) peri : stop
CKCTLR[10] + STOP
ACTIVE Mode SCMR.1 = 0 fXI : oscillation fSXI : oscillation cpu : fSYS tmr : fSYS peri : fSYS
WATCH Mode SCMR.1 = 1 fXI : stop fSXI : oscillation cpu : stop tmr : ps11(fSXI) peri : stop
TIMER0 EXT_INT RESET RC_WDT
CKCTLR[00] + STOP
EXT_INT RESET RC_WDT
STOP Mode SCMR.2 = 1 (SUB_CLK OFF) fXI : stop fSXI : stop cpu : stop tmr : stop peri : stop
CKCTLR[00] + STOP
EXT_INT RESET RC_WDT
System Clock Mode Register SCMR CS1 CS0 SUBOFF CLKSEL MAINOFF ADDRESS : FAH RESET VALUE : ---00000
CS[1:0]
Clock selection enable bits 00 : fXI / 210 : fXI /16 01 : fXI / 811 : fXI / 64
CLKSEL
Clock selection bit 0 : Main clock selection 1 : Sub clock selection Main clock control bit 0: On main clock 1: Off main clock
SUBOFF
Sub clock control bit 0: On sub clock 1: Off sub clock
MAINOFF
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21.2 Stop Mode
In the Stop mode, the on-chip oscillator is stopped. With the clock frozen, all functions are stopped, but the on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. Oscillator stops and the systems internal operations are all held up. * The states of the RAM, registers, and latches valid immediately before the system is put in the STOP state are all held. * The program counter stop the address of the instruction to be executed after the instruction "STOP" which starts the STOP operating mode. The Stop mode is activated by execution of STOP instruction after clearing the bit WAKEUP of CKCTLR to "0". ( This register should be written by byte opereation. If this register is set by bit manipulation instrunction, for example "set1" or "clr1" instruction, it may be undesired operation ) In the Stop mode of operation, VDD can be reduced to minimize power consumption. Care must be taken, however, to ensure that VDD is not reduced before the Stop mode is invoked, and that VDD is restored to its normal operating level, before the Stop mode is terminated. The reset should not be activated before VDD is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize.
Note: After STOP instruction, at least two or more NOP instruction should be written Ex) LDM CKCTLR,#0000_1110B STOP NOP NOP
Release the STOP mode The exit from STOP mode is hardware reset or external interrupt. Reset re-defines all the Control registers but does not change the on-chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. If Iflag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine. ( refer to Figure 21-1 ) When exit from Stop mode by external interrupt, enough oscillation stabilization time is required to normal operation. Figure 21-4 shows the timing diagram. When release the Stop mode, the Basic interval timer is activated on wake-up. It is increased from 00H until FFH . The count overflow is set to start normal operation. Therefore, before STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized. By reset, exit from Stop mode is shown in Figure 21-5 .
STOP INSTRUCTION STOP Mode
Interrupt Request =0
Corresponding Interrupt Enable Bit (IENH, IENL)
IEXX =1
STOP Mode Release
In the STOP operation, the dissipation of the power associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (VDD/VSS); however, when the input level gets higher than the power voltage level (by approximately 0.3 to 0.5V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring to fix the level by pull-up or other means.
Master Interrupt Enable Bit PSW[2]
I-FLAG =1
=0
Interrupt Service Routine
Next INSTRUCTION
Figure 21-1 STOP Releasing Flow by Interrupts
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Minimizing Current Consumption The Stop mode is designed to reduce power consumption. To minimize current drawn during Stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical.
Note: In the STOP operation, the power dissipation associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (VDD/VSS); however, when the input level becomes higher than the power voltage level (by approximately 0.3V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring it to fix the level
by pull-up or other means.
It should be set properly that current flow through port doesn't exist. First conseider the setting to input mode. Be sure that there is no current flow after considering its relationship with external circuit. In input mode, the pin impedance viewing from external MCU is very high that the current doesn't flow. But input voltage level should be VSS or VDD. Be careful that if unspecified voltage, i.e. if unfirmed voltage level (not VSSor VDD) is applied to input pin, there can be little current (max. 1mA at around 2V) flow. If it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. Setting to High or Low is decided considering its relationship with external circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to High, and if there is external pull-down register, it is set to low.
VDD INPUT PIN internal pull-up OPEN INPUT PIN VDD VDD i=0
VDD
O
O
i GND VDD
i
Very weak current flows
X
Weak pull-up current flows
X
OPEN
i=0
GND
O
O
When port is configured as an input, input level should be closed to 0V or 5V to avoid power consumption.
* Pull-up is Metal Option
Figure 21-2 Application Example of Unused Input Port
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OUTPUT PIN ON OPEN ON OFF i GND ON OFF VDD OFF
OUTPUT PIN VDD L ON OFF i GND ON i=0 GND L VDD
O
OFF
X
X O
O
In the left case, Tr. base current flows from port to GND. To avoid power consumption, there should be low output to the port .
In the left case, much current flows from port to GND.
Figure 21-3 Application Example of Unused Input Port
Minimizing Current Consumption in Stop Mode The Stop mode is designed to reduce power consumption. To minimize current drawn during Stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical. Weak pull-ups on port pins should be turned off, if possible. All inputs should be either as
VSS or at VDD (or as close to rail as possible). An intermediate voltage on an input pin causes the input buffer to draw a significant amount of current.
~ ~
Oscillator (XI pin) Internal Clock External Interrupt
~ ~
STOP Instruction Execution
~~ ~~ ~ ~
Clear Basic Interval Timer
~ ~ ~ ~ ~ ~
BIT Counter
N-2
N-1
N
N+1
N+2
00
01
FE
FF
00
00
~ ~
Normal Operation
STOP Mode
Stabilization Time tST > 20mS
Normal Operation
Figure 21-4 Timing of STOP Mode Release by External Interrupt
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STOP Mode
~ ~
Oscillator (XI pin) Internal Clock RESETB Internal RESETB
~ ~
STOP Instruction Execution Time can not be control by software
Figure 21-5 Timing of STOP Mode Release by RESET
~~ ~~ ~ ~ ~ ~
Stabilization Time tST = 64mS @4MHz
~~ ~~ ~ ~
21.3 Wake-up Timer Mode
In the Wake-up Timer mode, the on-chip oscillator is not stopped. Except the Prescaler( only 2048 devided ratio ) and Timer0, all functions are stopped, but the on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. The Wake-up Timer mode is activated by execution of STOP instruction after setting the bit WAKEUP of CKCTLR to "1". ( This register should be written by byte opereation. If this register is set by bit manipulation instrunction, for example "set1" or "clr1" instruction, it may be undesired operation )
Note: After STOP instruction, at least two or more NOP instruction should be written Ex) LDM TDR0,#0FFH LDM TM0,#0001_1011B LDM CKCTLR,#0100_1110B STOP NOP NOP
In addition, the clock source of timer0 should be selected to 2048 devided ratio. Otherwise, the wake-up function can not work. And the timer0 can be operated as 16-bit timer with timer1. ( refer to timer function )The period of wake-up function is varied by setting the timer data register 0, TDR0. Release the Wake-up Timer mode The exit from Wake-up Timer mode is hardware reset, Timer0 overflow or external interrupt. Reset re-defines all the Control registers but does not change the on-chip RAM. External interrupts and Timer0 overflow allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. If Iflag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine.( refer to Figure 21-1 ) When exit from Wake-up Timer mode by external interrupt or timer0 overflow, the oscillation stabilization time is not required to normal operation. Because this mode do not stop the on-chip oscillator shown as Figure 21-6 .
~ ~
Oscillator (XI pin) CPU Clock Interrupt Request
STOP Instruction Execution
~~ ~~ ~ ~
Normal Operation
Wake-up Timer Mode ( stop the CPU clock )
Normal Operation Do not need Stabilization Time
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Figure 21-6 Wake-up Timer Mode Releasing by External Interrupt or Timer0 Interrupt
21.4 Internal RC-Oscillated Watchdog Timer Mode
In the Internal RC-Oscillated Watchdog Timer mode, the on-chip oscillator is stopped. But internal RC oscillation circuit is oscillated in this mode. The on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. The Internal RC-Oscillated Watchdog Timer mode is activated by execution of STOP instruction after setting the bit WAKEUP and RCWDT of CKCTLR to " 01 ". ( This register should be written by byte opereation. If this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction, it may be undesired operation )
Note: Caution : After STOP instruction, at least two or more NOP instruction should be written Ex) LDM WDTR,#1111_1111B LDM CKCTLR,#0010_1110B STOP NOP NOP
If I-flag = 1, the normal interrupt response takes place. In this case, if the bit WDTON of CKCTLR is set to "0" and the bit WDTE of IENH is set to "1", the device will execute the watchdog timer interrupt service routine.(Figure 21-7 ) However, if the bit WDTON of CKCTLR is set to "1", the device will generate the internal RESET signal and execute the reset processing. (Figure 21-8 ) If I-flag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine.( refer to Figure 21-1 ) When exit from Internal RC-Oscillated Watchdog Timer mode by external interrupt, the oscillation stabilization time is required to normal operation. Figure 21-7 shows the timing diagram. When release the Internal RC-Oscillated Watchdog Timer mode, the basic interval timer is activated on wake-up. It is increased from 00H until FFH . The count overflow is set to start normal operation. Therefore, before STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized. By reset, exit from internal RC-Oscillated Watchdog Timer mode is shown in Figure 21-8 .
The exit from Internal RC-Oscillated Watchdog Timer mode is hardware reset or external interrupt. Reset re-defines all the Control registers but does not change the onchip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values.
~ ~
Oscillator (XI pin) Internal RC Clock
~ ~
~ ~ ~ ~
Internal Clock External Interrupt ( or WDT Interrupt )
~ ~
STOP Instruction Execution
~ ~
Clear Basic Interval Timer
~ ~ ~ ~
BIT Counter
N-2
N-1
N
N+1
N+2
00
01
FE
FF
00
00
~ ~
Normal Operation
RCWDT Mode
Stabilization Time tST > 20mS
Normal Operation
Figure 21-7 Internal RCWDT Mode Releasing by External Interrupt or WDT Interrupt
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RCWDT Mode
~ ~
Oscillator (XI pin) Internal RC Clock
~ ~
~ ~ ~ ~
Internal Clock RESET RESET by WDT Internal RESET
~ ~
STOP Instruction Execution Time can not be control by software
Figure 21-8 Internal RCWDT Mode Releasing by RESET
~ ~ ~ ~
Stabilization Time tST = 64mS @4MHz
~ ~ ~ ~
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22. RESET
The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, while the oscillator running. After reset, 64ms (at 4 MHz) add with 7 oscillator periods are required to start execution as shown in Figure 26-2 . Internal RAM is not affected by reset. When VDD is turned on, the RAM content is indeterminate. Therefore, this RAM should be initialized before reading or testing it. Initial state of each register is shown as Table 11-3 .
1
2
3
4
5
6
7
~ ~
Oscillator (XI pin) RESET
~ ~ ~ ~
ADDRESS BUS DATA BUS
?
?
?
?
FFFE FFFF Start
~~ ~~
?
?
?
?
FE
ADL
ADH
OP
Stabilization Time tST = 64mS at 4MHz
Figure 22-1 Timing Diagram after RESET
~ ~
MAIN PROGRAM RESET Process Step
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23. POWER FAIL PROCESSOR
The GMS81C2020 and GMS81C2120 has an on-chip power fail detection circuitry to immunize against power noise. A configuration register, PFDR, can enable (if clear/ programmed) or disable (if set) the Power-fail Detect circuitry. If VDD falls below 2.4~3.0V range for longer than 50 nS, the Power fail situation may reset MCU according to PFDM bit of PFDR. As below PFDR register is not implemented on the in-circuit emulator, user can not experiment with it. Therefore, after final development of user program, this function may be experimented.
Note: Power fail processor function is not available on 3V operation, because this function will detect power fail all the time.
Power Fail Detector Register PFDR Reserved Power Fail Status 0 : Normal Operate 1 : This bit force to "1" when Power fail was detected Operation Mode 0 : Normal operation regardless of power fail 1 : MCU will be reset during power fail Disable Flag 0 : Power fail detection enable 1 : Power fail detection disable PFDIS PFDM PFS ADDRESS : EFH RESET VALUE : -----100
Figure 23-1 Power Fail Detector Register
RESET VECTOR
PFS =1 NO RAM CLEAR INITIALIZE RAM DATA
YES
Skip the initial routine
INITIALIZE ALL PORTS INITIALIZE REGISTERS
FUNTION EXECUTION
Figure 23-2 Example S/W of RESET by Power fail
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VDD 64mS
PFVDDMAX PFVDDMIN
Internal RESET VDD When PFDM = 1 Internal RESET VDD t < 64mS
64mS
PFVDDMAX PFVDDMIN
PFVDDMAX PFVDDMIN 64mS
Internal RESET
Figure 23-3 Power Fail Processor Situations
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24. OTP PROGRAMMING
24.1 DEVICE CONFIGURATION AREA
The Device Configuration Area can be programmed or left unprogrammed to select device configuration such as security bit. sixteen memory locations ( 7030H ~ 703FH ) are designated as Customer ID recording locations where the user can store check-sum or other customer identification numbers. This area is not accessible during normal execution but is readable and writable during program / verify.
7030H DEVICE CONFIGURATION AREA 703FH ID ID ID ID ID ID ID ID ID ID ID ID ID ID ID CONFIG 7030H 7031H 7032H 7033H 7034H 7035H 7036H 7037H 7038H 7039H 703AH 703BH 703CH 703DH 703EH 703FH
Configuration Register CONFIG SXB / R7 PFD1 PFD0 CODE PROTECT EXTERNAL RCOSC ADDRESS :703FH
-
-
-
PFD LEVEL SELECTION 0 0 : PFD1 = 2.7V 0 1 : PFD1 = 2.7V 1 0 : PFD2 = 3.0V 1 1 : PFD3 = 2.4V SXB / R7 0 : SUB CLOCK 1 : R74, R75
EXTERNAL RCOSC 0 : Crystal Oscillator 1 : External RC Oscillator
CODE PROTECT 0 : ALLOW CODE READ OUT 1 : LOCK CODE READ OUT
Figure 24-1 Device Configuration Area
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64SDIP
CTL3 CTL2 CTL1 CTL0 VPP EPROM Enable VSS
A_D0 A_D1 A_D2 A_D3 A_D4 A_D5 A_D6 A_D7
R40 R41 R42 R43 R50 R51 R52 R53 R54 R55 R56 R57 RESETB XI XO VSS SXI SXO AVSS R60 R61 R62 R63 R64 R65 R66 R67 R70 R71 R72 R73 AVDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
RA/Vdisp R35 R34 R33 R32 R31 R30 R27 R26 R25 R24 R23 R22 R21 R20 R17 R16 R15 R14 R13 R12 R11 R10 R07 R06 R05 R04 R03 R02 R01 R00 VDD
VDD
Figure 24-2 Pin Assignmen (64SDIP)t User Mode Pin No. Pin Name
8 9 10 11 13 14 15 16 20 21 22 23 24 25 26 27 33 R53 R54 R55 R56 RESETB XI XO VSS R60 R61 R62 R63 R64 R65 R66 R67 VDD
EPROM MODE Pin Name
CTL3 CTL2 CTL1 CTL0 VPP EPROM Enable NC VSS A_D0 A_D1 A_D2 A_D3 A_D4 A_D5 A_D6 A_D7 VDD Connect to VDD (6.0V) Address Input Data Input/Output Address Input Data Input/Output Read/Write Control Address/Data Control Write 8Bytes Control Write 4Bytes Control Programming Power (0V, 12.75V) High Active, Latch Address in falling edge No connection Connect to VSS (0V) A8 A9 A10 A11 A12 A13 A14 A15 A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 D6 D7
Description
P_Vb D_Ab PGM8 PGM4
Table 24-1 Pin Description in EPROM Mode (GMS81C2020)
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42PDIP
CTL3 CTL2 CTL1 CTL0 VPP EPROM Enable VSS A_D0 A_D1 A_D2 A_D3 A_D4 A_D5 A_D6 A_D7 VDD
RA R53 R54 R55 R56 R57 RESETB XI XO VSS AVSS R60 R61 R62 R63 R64 R65 R66 R67 AVDD VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
R34 R33 R32 R31 R30 R27 R26 R25 R24 R23 R22 R21 R20 R07 R06 R05 R04 R03 R02 R01 R00
Figure 24-3 Pin Assignmen (42SDIP)t User Mode Pin No. Pin Name
2 3 4 5 7 8 9 10 12 13 14 15 16 17 18 19 21 R53 R54 R55 R56 RESETB XI XO VSS R60 R61 R62 R63 R64 R65 R66 R67 VDD
EPROM MODE Pin Name
CTL3 CTL2 CTL1 CTL0 VPP EPROM Enable NC VSS A_D0 A_D1 A_D2 A_D3 A_D4 A_D5 A_D6 A_D7 VDD Connect to VDD (6.0V) Address Input Data Input/Output Address Input Data Input/Output Read/Write Control Address/Data Control Write 8Bytes Control Write 4Bytes Control Programming Power (0V, 12.75V) High Active, Latch Address in falling edge No connection Connect to VSS (0V) A8 A9 A10 A11 A12 A13 A14 A15 A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 D6 D7
Description
P_Vb D_Ab PGM8 PGM4
Table 24-2 Pin Description in EPROM Mode (GMS81C2120)
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TSET1
THLD1
TDLY1
THLD2
TDLY2
~ ~
EPROM Enable
TVPPS VIHP
~ ~ ~ ~
~ ~
VPP
TVDDS TVPPR
CTL0/1
0V TCD1 VDD1H
~~ ~~
~~ ~~
VDD1H TCD1
CTL2 CTL3 A_D7~ A_D0
0V
~ ~
0V
TCD1
TCD1
~ ~
~ ~
~ ~
HA VDD1H
LA
DATA IN
DATA OUT
LA
DATA IN
DATA OUT
~ ~
~ ~
VDD
High 8bit Address Input Low 8bit Address Input Write Mode Verify Low 8bit Address Input Write Mode Verify
Figure 24-4 Timing Diagram in Program (Write & Verify) Mode
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After input a high address, output data following low address input
TSET1 THLD1 TDLY1 THLD2 TDLY2
Anothe high address step
EPROM Enable
TVPPS VIHP
VPP
TVDDS
CTL0/1
0V
TVPPR VDD2H
CTL2 CTL3 A_D7~ A_D0
0V
TCD2 VDD2H TCD1
TCD2
0V
TCD1
HA VDD2H
LA
DATA
LA
DATA
HA
LA
DATA
VDD
High 8bit Address Input Low 8bit Address Input DATA Output Low 8bit Address Input DATA Output High 8bit Address Input Low 8bit Address Input DATA Output
Figure 24-5 Timing Diagram in READ Mode Parameter Programming Supply Current Supply Current in EPROM Mode VPP Level during Programming VDD Level in Program Mode VDD Level in Read Mode CTL3~0 High Level in EPROM Mode CTL3~0 Low Level in EPROM Mode A_D7~A_D0 High Level in EPROM Mode A_D7~A_D0 Low Level in EPROM Mode VDD Saturation Time VPP Setup Time VPP Saturation Time EPROM Enable Setup Time after Data Input EPROM Enable Hold Time after TSET1 Symbol IVPP IVDDP VIHP VDD1H VDD2H VIHC VILC VIHAD VILAD TVDDS TVPPR TVPPS TSET1 THLD1 MIN 11.5 5 0.8VDD 0.9VDD 1 1 TYP 12.0 6 2.7 200 500 MAX 50 20 12.5 6.5 0.2VDD 0.1VDD 1 Unit mA mA V V V V V V V mS mS mS nS nS
Table 24-3 AC/DC Requirements for Program/Read Mode
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EPROM Enable Delay Time after THLD1 EPROM Enable Hold Time in Write Mode EPROM Enable Delay Time after THLD2 CTL2,1 Setup Time after Low Address input and Data input CTL1 Setup Time before Data output in Read and Verify Mode
TDLY1 THLD2 TDLY2 TCD1 TCD2
200 100 200 100 100
nS nS nS nS nS
Table 24-3 AC/DC Requirements for Program/Read Mode
START
Set VDD=VDD1H Verify fof all address Report Verify failure NO
Set VPP=VIHP
Report Programming failure NO
Verify OK YES
Verify blank YES First Address Location Next address location
Report Programming OK
VDD=VPP=0v N=1 Report Programming failure NO EPROM Write 100uS program time YES Verify pass END
Verify pass YES Apply 3N program cycle
NO
NO Last address YES
Figure 24-6 Programming Flow Chart
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START
Set VDD=VDD2H
Verify fof all address
Set VPP=VIHP
First Address Location Next address location NO
Last address YES Report Read OK
VDD=0V VPP=0V
END
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GMS81C2 Series [GMS81C2020/12] Option List
Package 64SDIP 64MQFP 64LQFP 64TQFP Date of Order Customer Department RA / Vdisp RA Without pull-down resistance Vdisp *Note : In the I/O options list, you must select Vdisp even if only one pin is selected with pull-down resistance. ROM Code Option List : 703FH Bit7 0 1 Bit6 SXB / R7 0 1 Bit5 PFD1 0 1 Bit4 PFD0 0 1 0 Bit3 1 0 Bit2 1 Bit1 LOW VOLTAGE 0 1 Bit0 RCOSC 0 1 Name ROM Code Name Check sum ROM Size 20KBytes 12KBytes 1999 / 2000. . .
* Refer to Device Configuration Area
I/O Option [VFD Driving Port] Bit I/O I/O Option On R00/INT0 I/O R01/INT1 I/O R02/EC0 I/O R03/BUZO I/O R04 R05 R06 R07 I/O I/O I/O I/O Off R10 R11 R12 R13 R14 R15 R16 R17 I/O I/O I/O I/O I/O I/O I/O I/O Bit I/O I/O Option On Off R20 R21 R22 R23 R24 R25 R26 R27 I/O I/O I/O I/O I/O I/O I/O I/O Bit I/O I/O Option On Off R30 R31 R32 R33 R34 R35 I/O I/O I/O I/O I/O I/O Bit I/O I/O Option On Off
* On : with pull-down resistance * Off : without pull-down resistance I/O Option [Normal Port] Bit I/O I/O Option On R40/T0O I/O R41 R42 R43 I/O I/O I/O Off R50 R51 R52 R54/SIN I/O I/O I/O I/O Bit I/O I/O Option On Off R60/AN0 I/O R61/AN1 I/O R62/AN2 I/O R63/AN3 I/O R64/AN4 I/O R65/AN5 I/O R66/AN6 I/O R67/AN7 I/O Bit I/O I/O Option On Off R70/AN8 I/O R71/AN9 I/O R72/AN10 I/O R73/AN11 I/O R74 R75 I/O I/O Bit I/O I/O Option On Off
R53/SCLK I/O R55/SOUT I/O R56/PWM1OI/O R57 I/O
* On : with pull-up * Off : without pull-up
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GMS81C2 Series [GMS81C2120/12] Option List
Package 42SDIP 40PDIP 44MQFP Date of Order Customer Department RA / Vdisp RA Without pull-down resistance Vdisp *Note : In the I/O options list, you must select Vdisp even if only one pin is selected with pull-down resistance. ROM Code Option List : 703FH Bit7 0 1 0 Bit6 1 Bit5 PFD1 0 1 Bit4 PFD0 0 1 0 Bit3 1 0 Bit2 1 Bit1 LOW VOLTAGE 0 1 Bit0 RCOSC 0 1 Name ROM Code Name Check sum ROM Size 20KBytes 12KBytes 1999 / 2000. . .
* Refer to Device Configuration Area
I/O Option [VFD Driving Port] Bit I/O I/O Option On R00/INT0 I/O R01/INT1 I/O R02/EC0 I/O R03/BUZO I/O R04 R05 R06 R07 I/O I/O I/O I/O Off R20 R21 R22 R23 R24 R25 R26 R27 I/O I/O I/O I/O I/O I/O I/O I/O Bit I/O I/O Option On Off R30 R31 R32 R33 R34 I/O I/O I/O I/O I/O Bit I/O I/O Option On Off
* On : with pull-down resistance * Off : without pull-down resistance I/O Option [Normal Port] Bit I/O I/O Option On R53/SCLK I/O R54/SIN I/O R55/SOUT I/O R56/PWM1OI/O R57 I/O Off R60/AN0 I/O R61/AN1 I/O R62/AN2 I/O R63/AN3 I/O R64/AN4 I/O R65/AN5 I/O * On : with pull-up * Off : without pull-up R66/AN6 I/O R67/AN7 I/O Bit I/O I/O Option On Off
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