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| SPICE Device Model SI7941DP Vishay Siliconix Dual P-Channel 30-V (D-S) MOSFET CHARACTERISTICS * P-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71669 31-May-04 www.vishay.com 1 SPICE Device Model SI7941DP Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Conditions Simulated Data 1.9 205 0.022 0.033 10 -0.82 Measured Data Unit VGS(th) ID(on) rDS(on) gfs VSD VDS = VGS, ID = - 250 A VDS = -5 V, VGS = -10 V VGS = -10 V, ID = -9 A VGS = -4.5 V, ID = -5 A VDS = -15 V, ID = -2.5 A IS = -2.9 A, VGS = 0 V V A 0.022 0.032 14 -0.80 S V Drain-Source On-State Resistancea Forward Transconductancea Diode Forward Voltagea Dynamicb Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Source-Drain Reverse Recovery Time Qg Qgs Qgd td(on) tr td(off) tf trr IF = -2.9 A, di/dt = 100 A/s VDD = -15 V, RL = 15 ID -1 A, VGEN = -10 V, RG = 6 VDS = -15 V, VGS = -10 V, ID = -9 A 41 8.5 7.5 20 28 32 58 40 42 8.5 7.5 18 29 65 27 50 ns nC Notes a. Pulse test; pulse width 300 s, duty cycle 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 71669 31-May-04 SPICE Device Model SI7941DP Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25c UNLESS OTHERWISE NOTED) Document Number: 71669 31-May-04 www.vishay.com 3 |
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