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| HT6576A Advanced SCSI CHIP Features * * * * Support the ANSI X3.131-1986 standard Asynchronous transfer rate to 5 Mbyte/sec Support initiator and target mode 0.8um CMOS process * * * On chip 48mA single-ended drivers and receivers Non internal clock needed 44pins PLCC package Block Diagram 1 14th July '97 HT6576A Pin Diagram Pin Description Host Interface Signal Pin No 14~16 17 11 9 24~28, 20~22 10 19 18 8 13 7 Pin Name A0~A2 CS DACK DRQ D0~D7 EOP IOR IOW IRQ READY RESET I/O I I I O I/O I I I O O I Address Lines Chip Select, active low Description DMA Acknowledge, active low DMA Request Data Lines End of Process, active low I/O Read, active low I/O Write, active low Interrupt Request Ready Reset, active low 2 14th July '97 HT6576A SCSI Interface Signals Pin No 33 6 4 30 32 29 34 2 37~41, 43, 44, 1 35 5 VSS Pin Name ACK ATN BSY C/D I/O MSG REQ RST DB0-DB7 DBP SEL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Description Acknowledge, active low Attention, active low Busy, active low Control/Data, active low Input/Output, active low Message, active low Request, active low Reset, active low SCSI Data Bus, active low SCSI Parity Bit, active low Select, active low 3, 12, 31, 36, 42 VDD 23 Registers Address 0 Current SCSI data register(READ ONLY) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 The SCSI bus parity is checked at the beginning of the read cycle. Output data register(WRITE ONLY) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 3 14th July '97 HT6576A Address 1: Initiator command register WRITE 7 6 5 4 ASSERT ACK 3 ASSERT BSY 2 ASSERT SEL 1 ASSERT ATN 0 ASSERT DATA ASSERT TRI-STATE RESERVED RST * BIT 7: ASSERT RST WHEN SET, THE RST SIGNAL IS ASSERTED ON THE SCSI BUS * BIT 6: TRI-STATE (TEST MODE) * BIT 5: RESERVED (0) * BIT 4: ASSERT ACK WHEN SET, THE ACK SIGNAL IS ASSERTED ON THE SCSI BUS * BIT 3: ASSERT BSY WHEN SET, THE BSY SIGNAL IS ASSERTED ON THE SCSI BUS * BIT 2: ASSERT SEL WHEN SET, THE SEL SIGNAL IS ASSERTED ON THE SCSI BUS * BIT 1: ASSERT ATN WHEN SET, THE ATN SIGNAL IS ASSERTED ON THE SCSI BUS * BIT 0: ASSERT DATA WHEN SET, This bit allows the contents of the output data register to be enabled as chip outputs on SCSI signal DB0-DB7 READ 7 RET 6 ARBIT PROGRESS 5 LOST ARBIT 4 ACK 3 BSY 2 SEL 1 ATN 0 ASSERT DATA Address 2: Mode register READ/WRITE 7 LOCK DMA 6 TARGET MODE 5 ENABLE PARITY 4 ENABLE PARITY 3 ENABLE EOP 2 MONITOR CHECK BUSY 1 DMA IRQ MODE 0 ARBIT * BIT 7: BLOCK MODE DMA * BIT 6: TARGET MODE When set, the chip operates as an SCSI bus target device. * BIT 5: ENABLE PARITY CHECKING When set, data received on the SCSI data bus is checked for odd parity. 4 14th July '97 HT6576A * BIT 4: ENABLE PARITY INTERRUPT When set, this bit causes the IRQ signal to be asserted if a parity error is detected. * BIT 3: ENABLE EOP INTERRUPT When set, this bit causes the IRQ signal to be asserted if EOP is received from the DMA controller. * BIT 2: MONITOR BUSY When set, this bit causes the IRQ signa asserted when BSY changes to the inactive state for at least a bus settle delay. * BIT 1: DMA MODE * BIT 0: Arbitrate When set, this bit starts the arbitration process. Address 3: Target command register 7 LAST BYTE R 6 X 5 X 4 X 3 ASSERT REQ R/W 2 ASSERT MSG R/W 1 ASSERT C/D R/W 0 ASSERT I/O R/W * BIT 7: LAST BYTE SEND (READ ONLY) * BIT 3: ASSERT REQ WHEN SET, THE REQ SIGNAL IS ASSERTED ON THE SCSI BUS (IN TARGET MODE) * BIT 2: ASSERT MSG WHEN SET, THE MSG SIGNAL IS ASSERTED ON THE SCSI BUS (IN TARGET MODE) * BIT 1: ASSERT C/D WHEN SET, THE C/D SIGNAL IS ASSERTED ON THE SCSI BUS (IN TARGET MODE) * BIT 0: ASSERT I/O WHEN SET, THE I/O SIGNAL IS ASSERTED ON THE SCSI BUS (IN TAGRTE MODE) Address 4: Current SCSI Bus Register READ 7 RST 6 BSY 5 REQ 4 MSG 3 C/D 2 I/O 1 SEL 0 DBP WRITE 7 SID7 -SELECT ENABLE REGISTER 6 SID6 5 SID5 4 SID4 3 SID3 2 SID2 1 SID1 0 SID0 5 14th July '97 HT6576A Address 5: Bus And Status READ 7 END DMA 6 DMA REQUEST 5 PARITY ERROR 4 IRQ 3 PHASE MATCH 2 BUS ERROR 1 ATN 0 ACK WRITE 7 X -START DMA SEND 6 X 5 X 4 X 3 X 2 X 1 X 0 X Address 6: Input Data READ 7 LDB7 6 LDB6 5 LDB5 4 LDB4 3 LDB3 2 LDB2 1 LDB1 0 LDB0 LATCH SCSI DATA. The register represent the complement of the active low SCSI data bus. WRITE 7 X Address 7: -START DMA TARGET RECEIVE 6 X 5 X 4 X 3 X 2 X 1 X 0 X READ 7 X -RESET PARITY/INTERRUPT 6 X 5 X 4 X 3 X 2 X 1 X 0 X WRITE 7 X -START DMA INITIATOR RECEIVE 6 X 5 X 4 X 3 X 2 X 1 X 0 X 6 14th July '97 HT6576A Interrupts SELECTION/RESELECTION * SEL= ACTIVE LOW * BSY IS FALSE FOR AT LEAST 400NS * HT6576A DEVICE ID (SELECT REGISTER) is active on the SCSI bus will generate IRQ. END OF PROCESS (EOP) INTERRUPT * EOP= ACTIVE LOW * DACK= ACTIVE LOW * IOR OR IOW= ACTIVE LOW * DMA MODE * ENABLE EOP IRQ GENERATE EOP IRQ SCSI BUS RST/IRQ When An SCSI RST active low, the IRQ is generated. PARITY ERROR IRQ An IRQ is generated for a received parity error if enable parity checking bit and the enable parity interrupt bit are set. BUS PHASE MISMATCH IRQ If the DMA MODE bit is active and a phase mismatch occurs when REQ from false to true, an interrupt is generated LOSS OF BSY/IRQ * MONITOR BSY bit= 1 * BSY= ACTIVE LOW FOR 400ns WILL GENERATE IRQ 7 14th July '97 HT6576A Electrical Characteristics D.C. Characteristics Absolute Maximum Ratings (Ta=25C) Symbol Tstg VDD VIN ESD Parameter Storage Temperature Supply Voltage Input Voltage Electrostatic Discharge Min. -55 -0.5 VSS-0.5 -5000 Max. 150 7.0 VDD+0.5 5000 Unit C V V V (Ta=25C) Operating Conditions Symbol VDD IDD Ta SCSI Signals Parameter Supply Voltage Supply Current Operating Free-Air Min. 4.75 -- 0 Max. 5.25 20 70 Unit V mA C (Ta=25C) Symbol VIH VIL VOL VHYS IOL IIH IIL Characteristic Input High Voltage Input Low Voltage Output Low Voltage Hysteresis Output Low Current Input High Leakage Input Low Leakage Condition -- -- IOL=48mA -- VOL=0.5 VIH= 5.25V VIL=VSS Min. 2.0 VSS-0.5 VSS 200 48 -- -- Max. VDD+0.5 0.8 0.5 450 -- 50 -50 Unit V V V mV mA A A 8 14th July '97 HT6576A Microprocessor Data Bus D0-D7 (Ta=25C) Symbol VIH VIL VOH VOL IOH IOL IIH IIL ITL Characteristic Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output High Current Output Low Current Input High Leakage Input Low Leakage Tri-State Leakage Condition -- -- IOH=-4.0mA IOL=8.0mA VOH=VDD-0.5V VOL=0.4V VIH=5.25V VIL=VSS -- Min. 2.0 VSS-0.5 2.4 VSS -4.0 8.0 -- -- -10 Max. VDD+0.5 0.8 VDD 0.4 -- -- 10 -10 10 Unit V V V V mA mA A A A A0~A2, CS, EOP, IOR, IOW, RESET (Ta=25C) Symbol VIH VIL IIH IIL Characteristic Input High Voltage Input Low Voltage Input High Leakage Input Low Leakage Condition -- -- VIH=5.25V VIL=VSS Min. 2.0 VSS-0.5 10 -10 Max. VDD+0.5 0.8 -- -- Unit V V A A DRQ, IRQ, READY, Symbol VOH VOL IOH IOL Characteristic Output High Voltage Output Low Voltage Output High Current Output Low Current Condition IOH=-4.0mA IOL=8.0mA VOH=VDD-0.5V VOL=0.4V Min. 2.4 VSS -4.0 8.0 Max. VDD 0.4 -- -- Unit V V mA mA 9 14th July '97 HT6576A Timing Diagram Initiator Send Name t1 t2 t3 t4 t5 t6 Description SCSI Data setup time to ACK active Data Bus held time from IOW inactive IOW active time DACK active, to DRQ inactive ACK active to next DRQ active EOP active time Min. 40 10 30 -- -- 30 Max. -- -- -- 20 45 -- Unit ns ns ns ns ns ns 10 14th July '97 HT6576A Initiator Receive Name t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Description IOR inactive to next REQ active REQ active to ACK active IOR inactive to ACK inactive ACK inactive time Data Bus hold time from IOR inactive Data Bus valid time from IOR active REQ active to DRQ active DACK active to DRQ inactive DACK inactive to next DRQ active EOP active time Min. 50 50 10 50 10 -- -- -- 20 30 Max. -- -- -- -- -- 20 25 20 -- -- Unit ns ns ns ns ns ns ns ns ns ns 11 14th July '97 HT6576A Target Send (Non-block mode) Name t1 t2 t3 t4 t5 t6 t7 t8 t9 Description SCSI data hold time from IOW inactive SCSI data setup time to REQ active ACK active to REQ inactive Data Bus setup time to IOW inactive Data Bus hold time from IOW inactive IOW active time DACK active to DRQ inactive IOW inactive to DACK inactive ACK active to next DRQ active Min. -- 40 -- 10 10 30 -- 0 -- Max. 30 -- 30 -- -- -- 20 -- 45 Unit ns ns ns ns ns ns ns ns ns 12 14th July '97 HT6576A Target Receive (Non-block mode) Name t1 t2 t3 t4 t5 t6 t7 t8 Description ACK inactive to next REQ active ACK active to REQ inactive IOR inactive to next REQ active Data Bus setup time to IOR active Data Bus hold time from IOR inactive IOR active time DACK active to DRQ inactive IOR inactive to DACK inactive Min. 50 -- 50 -- 10 30 -- 0 Max. -- 30 -- 20 -- -- 20 -- Unit ns ns ns ns ns ns ns ns 13 14th July '97 HT6576A PIO Timing t1 D7~0 t2 t3 t2 A2~0 CS IOR IOW RESET DACK DRQ t4 t4 Name t1 t2 t3 t4 Description Data valid time from IOR active Data hold time from IOR inactive Data setup time to IOW inactive IOR or IOW active time Min. -- 10 10 30 Max. 20 -- -- -- Unit ns ns ns ns 14 14th July '97 |
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