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| Dat a Sh eet , DS2 , Ju ly 20 00 DuSLIC Dual Channel Subscriber Line Interface Circuit PEB PEB PEB PEB PEB 3264/-2 Version 1.2 4264/-2 Version 1.1 3265 Version 1.2 4265/-2 Version 1.1 4266 Version 1.1 W ir e d C o m mu n i ca t io n s Never stop thinking. Edition 2000-07-14 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany (c) Infineon Technologies AG 8/16/00. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Dat a Sh eet , DS2 , Ju ly 20 00 Interface Circuit PEB PEB PEB PEB PEB W ir e d C o m mu n i ca t io n s Never stop thinking. P re li 3264/-2 Version 1.2 4264/-2 Version 1.1 3265 Version 1.2 4265/-2 Version 1.1 4266 Version 1.1 m in ar Dual Channel Subscriber Line y DuSLIC DuSLIC Preliminary Revision History: Previous Version: Page Page 15 Page 33 Page 94 Page 107 Page 132 Page 137 Page 162 Page 174 Page 204 Page 228 Page 317 Page 342 Page 367 2000-07-14 Data Sheet DS1 DS2 Subjects (major changes since last revision) Usage of the term SLICOFI-2x as synonym used for all codec versions SLICOFI-2/-2S/-2S2. Chapter 3.1 "Functional Overview" completely updated. Chapter 4.7.2 "Power Dissipation of SLICOFI-2": Power dissipation tables were replaced by cross-references to Chapter 7. Chapter 4.8 "Integrated Test and Diagnosis Functions" replaces the former chapter "Test Modes". Chapter 4.9 "Signal Path and Test Loops": updated figures. Chapter 4.10 "Caller ID Buffer Handling of SLICOFI-2" added. Figure 70 "Interface SLICOFI-2 and SLIC-P": Pin IO1A on PEB 3265 was replaced by pin IO2A. Register XCR: Bit PLL-LOOP removed. Register LMCR2: Description for bit LM-NOTCH changed. Chapter 6.2.3 "POP Commands": General update and partially renaming of POP commands. Chapter 7: Electrical characteristics and AC transmission performance completely updated. Chapter 7.4.6 "Digital Interface": Test condition current I0 for Low-output voltage VOLDU for PEB 3264/-2 was lowered to I0 = - 30 mA. Chapter 8 "Application Circuits" completely overworked. For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com. DuSLIC Table of Contents 1 1.1 1.2 1.3 2 2.1 2.2 3 3.1 3.1.1 3.1.2 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.3.8 3.4 3.4.1 3.4.2 3.4.3 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6 3.5.7 3.6 3.7 3.7.1 3.7.2 3.7.2.1 3.8 3.8.1 3.8.2 Data Sheet Page 16 19 20 22 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Pin Diagram SLIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Pin Diagram SLICOFI-2/-2S/-2S2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic Functions available for all DuSLIC Chip Sets . . . . . . . . . . . . . . . Additional Functions available for DuSLIC-E/-E2/-P Chip Sets . . . . . . . Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristic Feeding Zones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Constant Current Zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resistive Zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Constant Voltage Zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Voltage and Current Range of DC Characteristic . . . . . SLIC Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Necessary Voltage Reserve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Battery Feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Transmission Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ringer Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ring Trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ringing Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DuSLIC Ringing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Balanced Ringing via SLICs . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Unbalanced Ringing with SLIC-P . . . . . . . . . . . . . . . . . . . . . . . External Unbalanced Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signaling (Supervision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Metering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Metering by 12/16 kHz Sinusoidal Bursts . . . . . . . . . . . . . . . . . . . . . . . Metering by Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soft Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DuSLIC Enhanced Signal Processing Capabilities . . . . . . . . . . . . . . . . . . DTMF Generation and Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Caller ID Generation (only DuSLIC-E/-E2/-P) . . . . . . . . . . . . . . . . . . . . 5 33 33 33 34 36 40 41 42 43 44 45 46 47 48 49 50 50 51 52 52 52 53 54 57 58 59 59 61 61 62 62 63 64 66 2000-07-14 DuSLIC Table of Contents 3.8.3 3.8.4 3.8.5 3.9 3.10 3.10.1 3.11 4 4.1 4.2 4.3 4.4 4.5 4.5.1 4.5.2 4.6 4.7 4.7.1 4.7.2 4.7.3 4.7.3.1 4.7.3.2 4.7.3.3 4.7.3.4 4.7.3.5 4.8 4.8.1 4.8.1.1 4.8.1.2 4.8.2 4.8.2.1 4.8.2.2 4.8.2.3 4.8.2.4 4.8.2.5 4.8.2.6 4.8.2.7 4.8.2.8 4.8.2.9 4.8.2.10 4.8.2.11 4.8.2.12 Data Sheet Page 69 70 71 72 74 75 76 Line Echo Cancelling (LEC) (only DuSLIC-E/-E2/-P) . . . . . . . . . . . . . . Universal Tone Detection (UTD) (only DuSLIC-E/-E2/-P) . . . . . . . . . . . MIPS Requirements for EDSP Capabilities . . . . . . . . . . . . . . . . . . . . . . Message Waiting Indication (only DuSLIC-E/-E2/-P) . . . . . . . . . . . . . . . . Three-party Conferencing (only DuSLIC-E/-E2/-P) . . . . . . . . . . . . . . . . . . Conferencing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 kHz Mode on PCM Highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Operating Modes for the DuSLIC Chip Set . . . . . . . . . . . . . . . . . . . . . . . . 78 Operating Modes for the DuSLIC-S/-S2 Chip Set . . . . . . . . . . . . . . . . . . . 82 Operating Modes for the DuSLIC-E/-E2 Chip Set . . . . . . . . . . . . . . . . . . . 84 Operating Modes for the DuSLIC-P Chip Set . . . . . . . . . . . . . . . . . . . . . . 86 Reset Mode and Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Hardware and Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Operating Modes and Power Management . . . . . . . . . . . . . . . . . . . . . . . . 93 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Power Dissipation of the SLICOFI-2x . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Power Dissipation of the SLIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 SLIC Power Consumption Calculation in Active Mode . . . . . . . . . . . 96 Ringing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 SLIC Power Consumption Calculation in Ringing Mode . . . . . . . . . 103 Integrated Test and Diagnosis Functions (ITDF) . . . . . . . . . . . . . . . . . . . 107 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Conventional Line Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 DuSLIC Line Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Line Test Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Integrated Signal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Result Register Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Using the Levelmeter Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 DC Levelmeter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 AC Levelmeter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Levelmeter Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Current Offset Error Compensation . . . . . . . . . . . . . . . . . . . . . . . . . 122 Loop Resistance Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Line Resistance Tip/GND and Ring/GND . . . . . . . . . . . . . . . . . . . . 125 Capacitance Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Line Capacitance Measurements Ring and Tip to GND . . . . . . . . . 129 6 2000-07-14 DuSLIC Table of Contents Page 129 132 132 134 137 138 138 138 142 143 145 148 152 152 153 156 159 163 166 167 167 167 172 224 227 228 228 232 262 264 264 265 267 267 267 272 308 311 312 314 314 4.8.2.13 Foreign- and Ring Voltage Measurements . . . . . . . . . . . . . . . . . . . 4.9 Signal Path and Test Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9.1 Test Loops DuSLIC-E/-E2/-P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9.2 Test Loops DuSLIC-S/-S2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 Caller ID Buffer Handling of SLICOFI-2 . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.1 5.1.1 5.1.2 5.1.3 5.2 5.2.1 5.2.2 5.3 5.4 5.5 5.6 6 6.1 6.2 6.2.1 6.2.1.1 6.2.1.2 6.2.2 6.2.2.1 6.2.3 6.2.3.1 6.2.4 6.2.5 6.2.6 6.2.6.1 6.2.6.2 6.3 6.3.1 6.3.1.1 6.3.1.2 6.3.2 6.3.2.1 6.3.3 6.3.4 6.3.4.1 Data Sheet Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM Interface with a Serial Microcontroller Interface . . . . . . . . . . . . . . . PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control of the Active PCM Channels . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Interface Monitor Transfer Protocol . . . . . . . . . . . . . . . . . . . . . SLICOFI-2x Identification Command (only IOM-2 Interface) . . . . . . . . TIP/RING Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLICOFI-2S/-2S2 and SLIC-S/-S2 Interface . . . . . . . . . . . . . . . . . . . . . . SLICOFI-2 and SLIC-E/-E2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . SLICOFI-2 and SLIC-P Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLICOFI-2x Command Structure and Programming . . . . . . . . . . . . . Overview of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLICOFI-2 Command Structure and Programming . . . . . . . . . . . . . . . . . SOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOP Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOP Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRAM Programming Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POP Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POP Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Interface Command/Indication Byte . . . . . . . . . . . . . . . . . . . . . Programming Examples of the SLICOFI-2 . . . . . . . . . . . . . . . . . . . . . Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLICOFI-2S/-2S2 Command Structure and Programming . . . . . . . . . . . SOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOP Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOP Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRAM Programming Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Interface Command/Indication Byte . . . . . . . . . . . . . . . . . . . . . Programming Examples of the SLICOFI-2S/-2S2 . . . . . . . . . . . . . . . . Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2000-07-14 DuSLIC Table of Contents 6.3.4.2 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.6 7.7 7.7.1 7.7.2 Data Sheet Page IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 Electrical Characteristics PEB 4264/-2 (SLIC-S/-S2) . . . . . . . . . . . . . . . 317 Absolute Maximum Ratings PEB 4264/-2 (SLIC-S/-S2) . . . . . . . . . . . 317 Operating Range PEB 4264/-2 (SLIC-S/-S2) . . . . . . . . . . . . . . . . . . . 319 Thermal Resistances PEB 4264/-2 (SLIC-S/-S2) . . . . . . . . . . . . . . . . 319 Electrical Parameters PEB 4264/-2 (SLIC-S/-S2) . . . . . . . . . . . . . . . . 320 Power Calculation PEB 4264/-2 (SLIC-S/-S2) . . . . . . . . . . . . . . . . . . . 322 Power Up Sequence PEB 4264/-2 (SLIC-S/-S2) . . . . . . . . . . . . . . . . . 323 Electrical Characteristics PEB 4265/-2 (SLIC-E/-E2) . . . . . . . . . . . . . . . 324 Absolute Maximum Ratings PEB 4265/-2 (SLIC-E/-E2) . . . . . . . . . . . 324 Operating Range PEB 4265/-2 (SLIC-E/-E2) . . . . . . . . . . . . . . . . . . . 325 Thermal Resistances PEB 4265/-2 (SLIC-E/-E2) . . . . . . . . . . . . . . . . 325 Electrical Parameters PEB 4265/-2 (SLIC-E/-E2) . . . . . . . . . . . . . . . . 326 Power Calculation PEB 4265/-2 (SLIC-E/-E2) . . . . . . . . . . . . . . . . . . . 328 Power Up Sequence PEB 4265/-2 (SLIC-E/-E2) . . . . . . . . . . . . . . . . . 329 Electrical Characteristics PEB 4266 (SLIC-P) . . . . . . . . . . . . . . . . . . . . . 330 Absolute Maximum Ratings PEB 4266 (SLIC-P) . . . . . . . . . . . . . . . . . 330 Operating Range PEB 4266 (SLIC-P) . . . . . . . . . . . . . . . . . . . . . . . . . 332 Thermal Resistances PEB 4266 (SLIC-P) . . . . . . . . . . . . . . . . . . . . . . 332 Electrical Parameters PEB 4266 (SLIC-P) . . . . . . . . . . . . . . . . . . . . . 333 Power Calculation PEB 4266 (SLIC-P) . . . . . . . . . . . . . . . . . . . . . . . . 336 Power Up Sequence PEB 4266 (SLIC-P) . . . . . . . . . . . . . . . . . . . . . . 337 Electrical Characteristics PEB 3265/PEB 3264/PEB 3264-2 (SLICOFI-2/-2S/2S2) 338 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 Power Dissipation PEB 3265 (SLICOFI-2) . . . . . . . . . . . . . . . . . . . . . 340 Power Dissipation PEB 3264, PEB 3264-2 (SLICOFI-2S/-2S2) . . . . . 341 Power Up Sequence for Supply Voltages . . . . . . . . . . . . . . . . . . . . . . 341 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 AC Transmission DuSLIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 Gain Tracking (Receive or Transmit) . . . . . . . . . . . . . . . . . . . . . . . . . . 352 Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 Out-of-Band Signals at Analog Output (Receive) . . . . . . . . . . . . . . . . 354 Out-of-Band Signals at Analog Input (Transmit) . . . . . . . . . . . . . . . . . 355 Total Distortion Measured with Sine Wave . . . . . . . . . . . . . . . . . . . . . 356 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 DuSLIC Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 MCLK/FSC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 PCM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 8 2000-07-14 DuSLIC Table of Contents 7.7.2.1 7.7.2.2 7.7.3 7.7.4 7.7.4.1 7.7.4.2 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.2 8.3 9 10 10.1 11 Page 361 362 364 365 365 366 367 367 368 369 370 371 372 374 Single-Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Double-Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microcontroller Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Double-Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Ringing (Balanced/Unbalanced) . . . . . . . . . . . . . . . . . . . . . . . . . Circuit Diagram Internal Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Circuit for SLIC-E/-E2 and SLIC-S . . . . . . . . . . . . . . . . . . . Protection Circuit for SLIC-P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bill of Materials (Including Protection) . . . . . . . . . . . . . . . . . . . . . . . . . External Unbalanced Ringing with DuSLIC-E/-E2/-S/-S2/-P . . . . . . . . . . DuSLIC Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 Data Sheet 9 2000-07-14 DuSLIC List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Data Sheet Page 18 20 20 21 23 28 35 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 56 57 58 61 62 63 63 68 69 70 72 73 74 89 96 98 99 DuSLIC Chip Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol SLIC-S / SLIC-S2 / SLIC-E / SLIC-E2 . . . . . . . . . . . . . . Logic Symbol SLIC-P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol SLICOFI-2/-2S/-2S2 . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration SLIC-S/-S2, SLIC-E/-E2, SLIC-P (top view) . . . . . . Pin Configuration SLICOFI-2/-2S/-2S2 (top view) . . . . . . . . . . . . . . . . Line Circuit Functions included in the DuSLIC-S/-S2 . . . . . . . . . . . . . Line Circuit Functions included in the DuSLIC-E/-E2/-P . . . . . . . . . . . Block Diagram SLIC-S/-S2 (PEB 4264/-2). . . . . . . . . . . . . . . . . . . . . . Block Diagram SLIC-E/-E2 (PEB 4265/-2). . . . . . . . . . . . . . . . . . . . . . Block Diagram SLIC-P (PEB 4266) . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram SLICOFI-2/-2S/-2S2 (PEB 3265, PEB 3264/-2) . . . . . Signal Paths - DC Feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Feeding Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Constant Current Zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resistive Zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Constant Voltage Zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TTX Voltage Reserve Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Feeding Characteristics (ACTH, ACTR) . . . . . . . . . . . . . . . . . . . . Signal Paths - AC Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Flow in Voice Channel (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nyquist Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Ringer Loads of 1 and 5 REN Used in US . . . . . . . . . . . . . . . External Ringing Zero Crossing Synchronization . . . . . . . . . . . . . . . . Balanced Ringing via SLIC-E/-E2, SLIC-S and SLIC-P . . . . . . . . . . . . Unbalanced Ringing Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Teletax Injection and Metering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soft Reversal (Example for Open Loop) . . . . . . . . . . . . . . . . . . . . . . . DuSLIC AC Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DuSLIC EDSP Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bellcore On-hook Caller ID Physical Layer Transmission . . . . . . . . . . Line Echo Cancelling Unit - Block Diagram . . . . . . . . . . . . . . . . . . . . . UTD Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MWI Circuitry with Glow Lamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conference Block for One DuSLIC Channel . . . . . . . . . . . . . . . . . . . . DuSLIC Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit Diagram for Power Consumption . . . . . . . . . . . . . . . . . . . . . . . SLIC-E/-E2 Power Dissipation with Switched Battery Voltage. . . . . . . SLIC-P Power Dissipation (Switched Battery Voltage, Long Loops) . . 10 2000-07-14 DuSLIC List of Figures Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70 Figure 71 Figure 72 Figure 73 Figure 74 Figure 75 Figure 76 Figure 77 Figure 78 Figure 79 Figure 80 Figure 81 Figure 82 Figure 83 Figure 84 Data Sheet Page 101 103 109 110 111 111 123 124 127 130 132 133 134 135 136 139 141 143 144 145 146 147 148 150 151 155 158 162 208 259 261 264 264 314 314 342 343 350 351 351 352 352 SLIC-P Power Dissipation (Switched Battery Voltage, Short Loops). Circuit Diagram for Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Blockdiagram Levelmeter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Measurement Sequence (AC&DC Levelmeter) . . . . . . . . . . . Continuous Measurement Sequence (DC Levelmeter) . . . . . . . . . . . Continuous Measurement Sequence (AC Levelmeter) . . . . . . . . . . . Example Resistance Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Resistance Measurement . . . . . . . . . . . . . . . . . . . . . . . . Capacitance Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Foreign Voltage Measurement Principle . . . . . . . . . . . . . . . . . . . . . . AC Test Loops DuSLIC-E/-E2/-P . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Test Loops DuSLIC-E/-E2/-P. . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Test Loops DuSLIC-S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Test Loops DuSLIC-S2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Test Loops DuSLIC-S/-S2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General PCM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting of Slopes in Register PCMC1 . . . . . . . . . . . . . . . . . . . . . . . . Serial Microcontroller Interface Write Access . . . . . . . . . . . . . . . . . . Serial Microcontroller Interface Read Access . . . . . . . . . . . . . . . . . . IOM-2 Int. Timing for up to 16 Voice Channels (Per 8-kHz Frame) . . IOM-2 Interface Timing (DCL = 4096 kHz, Per 8-kHz Frame) . . . . . . IOM-2 Interface Timing (DCL = 2048 kHz, Per 8-kHz Frame) . . . . . . IOM-2 Interface Monitor Transfer Protocol . . . . . . . . . . . . . . . . . . . . State Diagram of the SLICOFI-2x Monitor Transmitter . . . . . . . . . . . State Diagram of the SLICOFI-2x Monitor Receiver . . . . . . . . . . . . . Interface SLICOFI-2S/-2S2 and SLIC-S/-S2 . . . . . . . . . . . . . . . . . . . Interface SLICOFI-2 and SLIC-E/-E2. . . . . . . . . . . . . . . . . . . . . . . . . Interface SLICOFI-2 and SLIC-P . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example for Switching Between Different Ring Offset Voltages . . . . Example for UTD Recognition Timing . . . . . . . . . . . . . . . . . . . . . . . . Example for UTD Tone End Detection Timing . . . . . . . . . . . . . . . . . . Waveform of Programming Example SOP-Write to Channel 0 . . . . . Waveform of Programming Example SOP Read from Channel 0 . . . Waveform of Programming Example SOP Write to Channel 0 . . . . . Waveform of Programming Example SOP Read from Channel 0 . . . Hysteresis for Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Definitions Transmit, Receive . . . . . . . . . . . . . . . . . . . . . . . . . Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency Response Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency Response Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain Tracking Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain Tracking Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2000-07-14 DuSLIC List of Figures Figure 85 Figure 86 Figure 87 Figure 88 Figure 89 Figure 90 Figure 91 Figure 92 Figure 93 Figure 94 Figure 95 Figure 96 Figure 97 Figure 98 Figure 99 Figure 100 Figure 101 Figure 102 Figure 103 Figure 104 Page 353 354 355 356 356 357 360 361 362 364 365 366 368 369 370 372 373 375 376 377 Group Delay Distortion Receive and Transmit. . . . . . . . . . . . . . . . . . Out-of-Band Signals at Analog Output (Receive) . . . . . . . . . . . . . . . Out-of-Band Signals at Analog Input (Transmit) . . . . . . . . . . . . . . . . Total Distortion Transmit (LX = 0 dBr) . . . . . . . . . . . . . . . . . . . . . . . . Total Distortion Receive (LR = - 7 dBr) . . . . . . . . . . . . . . . . . . . . . . . Total Distortion Receive (LR = 0 dBr) . . . . . . . . . . . . . . . . . . . . . . . . MCLK / FSC-Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM Interface Timing - Single-Clocking Mode . . . . . . . . . . . . . . . . . PCM Interface Timing - Double-Clocking Mode . . . . . . . . . . . . . . . . Microcontroller Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Interface Timing - Single-Clocking Mode . . . . . . . . . . . . . . . . IOM-2 Interface Timing - Double-Clocking Mode . . . . . . . . . . . . . . . Application Circuit, Internal Ringing (Balanced & Unbalanced) . . . . . Typical Overvoltage Protection for SLIC-E/-E2 and SLIC-S . . . . . . . Typical Overvoltage Protection for SLIC-P . . . . . . . . . . . . . . . . . . . . Application Circuit, External Unbalanced Ringing . . . . . . . . . . . . . . . Application Circuit, External Unbalanced Ringing for Long Loops. . . DuSLIC Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . PEB426x (SLIC-S/-S2, SLIC-E/-E2, SLIC-P). . . . . . . . . . . . . . . . . . . PEB 3264, PEB 3264-2, PEB 3265 (SLICOFI-2x) . . . . . . . . . . . . . . . Data Sheet 12 2000-07-14 DuSLIC List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Data Sheet Page DuSLIC Chip Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Pin Definitions and Functions SLIC-S/-S2 and SLIC-E/-E2 . . . . . . . . . 24 Pin Definitions and Functions SLIC-P . . . . . . . . . . . . . . . . . . . . . . . . . 26 Pin Definitions and Functions SLICOFI-2/-2S/-2S2 . . . . . . . . . . . . . . . 29 DC Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Ringing Options with SLIC-S, SLIC-E/-E2 and SLIC-P . . . . . . . . . . . . 54 Performance Characteristics of the DTMF Decoder Algorithm . . . . . . 65 FSK Modulation Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 MIPS Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Conference Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Possible Modes in PCM/C Interface Mode . . . . . . . . . . . . . . . . . . . . 76 Overview of DuSLIC Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . 78 DuSLIC-S/-S2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 DuSLIC-E/-E2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 DuSLIC P Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Typical Buffer Voltage Drops (Sum) for ITRANS (IT or IR) . . . . . . . . . . 95 Line Feed Conditions for Power Calculation of SLIC-E/-E2. . . . . . . . . 97 SLIC-E/-E2 Typical Total Power Dissipation . . . . . . . . . . . . . . . . . . . . 97 Line Feed Conditions for Power Calculation for SLIC-P . . . . . . . . . . . 98 SLIC-P PEB 4266 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 99 Line Feed Conditions for Power Calculation for SLIC-P . . . . . . . . . . 100 SLIC-P PEB 4266 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 100 SLIC-E/-E2 Balanced Ringing Power Dissipation (typical) . . . . . . . . 104 SLIC-P Balanced Ringing Power Dissipation (typical) . . . . . . . . . . . . 105 SLIC-P Unbalanced Ringing Power Dissipation (typical). . . . . . . . . . 106 Levelmeter Result Value Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Selecting DC Levelmeter Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 KINTDC Setting Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 NSamples Setting Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Levelmeter Results with and without Integrator Function . . . . . . . . . 115 Selecting AC Levelmeter Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 KINTAC Setting Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 KTG Setting Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Threshold Setting Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Measurement Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 SLICOFI-2x PCM Interface Configuration . . . . . . . . . . . . . . . . . . . . . 140 Active PCM Channel Configuration Bits . . . . . . . . . . . . . . . . . . . . . . 142 IOM-2 Time Slot Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 SLIC-S/-S2 Interface Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 SLIC-S/-S2 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 SLIC-E/-E2 Interface Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 13 2000-07-14 DuSLIC List of Tables Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Table 80 Table 81 Table 82 Table 83 Page 156 159 159 160 164 178 200 208 226 227 237 237 240 241 242 243 243 244 244 245 245 247 257 262 294 310 311 312 322 323 323 328 329 329 336 337 337 344 353 358 371 SLIC-E/-E2 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLIC-P Interface Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLIC-P Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLIC-P Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M2, M1, M0: General Operating Mode . . . . . . . . . . . . . . . . . . . . . . . Valid DTMF Keys (Bit DTMF-KEY4 = 1) . . . . . . . . . . . . . . . . . . . . . . DTMF Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Usage for the three Ring Offsets . . . . . . . . . . . . . . . . . . . . . . CRAM Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRAM Programming Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ranges of GDTMF[dB] dependent on "e" . . . . . . . . . . . . . . . . . . . . . Example for DTMF-GAIN Calculation . . . . . . . . . . . . . . . . . . . . . . . . Characteristic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ranges of GLEC-XI[dB] Dependent on "e" . . . . . . . . . . . . . . . . . . . . Example for LEC-GAIN-XI Calculation . . . . . . . . . . . . . . . . . . . . . . . Ranges of GLEC-RI[dB] Dependent on "e" . . . . . . . . . . . . . . . . . . . . Example for LEC-GAIN-RI Calculation . . . . . . . . . . . . . . . . . . . . . . . Ranges of GLEC-X0[dB] Dependent on "e" . . . . . . . . . . . . . . . . . . . . Example for LEC-GAIN-X0 Calculation . . . . . . . . . . . . . . . . . . . . . . . Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UTD Inband/Outband Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . M2, M1, M0: General Operating Mode . . . . . . . . . . . . . . . . . . . . . . . DTMF Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRAM Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRAM Programming Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M2, M1, M0: General Operating Mode . . . . . . . . . . . . . . . . . . . . . . . PI Calculation PEB 4264/-2 (SLIC-S/-S2) . . . . . . . . . . . . . . . . . . . . . PG Calculation PEB 4264/-2 (SLIC-S/-S2). . . . . . . . . . . . . . . . . . . . . PO Calculation PEB 4264/-2 (SLIC-S/-S2). . . . . . . . . . . . . . . . . . . . . PI Calculation PEB 4265/-2 (SLIC-E/-E2) . . . . . . . . . . . . . . . . . . . . . PG Calculation PEB 4265/-2 (SLIC-E/-E2). . . . . . . . . . . . . . . . . . . . . PO Calculation PEB 4265/-2 (SLIC-E/-E2). . . . . . . . . . . . . . . . . . . . . PI Calculation PEB 4266 (SLIC-P) . . . . . . . . . . . . . . . . . . . . . . . . . . . PG Calculation PEB 4266 (SLIC-P) . . . . . . . . . . . . . . . . . . . . . . . . . . PO Calculation PEB 4266 (SLIC-P) . . . . . . . . . . . . . . . . . . . . . . . . . AC Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Group Delay Absolute Values: Signal level 0 dBm0 . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Components in Application Circuit for DuSLIC-E/-E2/-S/-P. Data Sheet 14 2000-07-14 DuSLIC Preliminary Preface This document describes the DuSLIC chip set comprising a programmable dual channel SLICOFI-2x codec and two single channel high-voltage SLIC chips. For more DuSLIC related documents please see our webpage at http://www.infineon.com/duslic. To simplify matters, the following synonyms are used: SLICOFI-2x: SLIC: Synonym used for all codec versions SLICOFI-2/-2S/-2S2 Synonym used for all SLIC versions SLIC-S/-S2, SLIC-E/-E2 and SLIC-P Organization of this Document This Data Sheet is divided into eleven chapters. It is organized as follows: * Chapter 1, Overview A general description of the product, its key features, and some typical applications. * Chapter 2, Pin Descriptions * Chapter 3, Functional Description The main functions are presented following a functional block diagram. * Chapter 4, Operational Description A brief description of the three operating modes: power down, active and ringing (plus signal monitoring techniques). * Chapter 5, Interfaces Connection information including standard IOM-2 and PCM interface timing frames and pins. * Chapter 6, SLICOFI-2x command structure A general brief about the SLICOFI-2x command structure. * Chapter 7, Electrical Characteristics Parameters, symbols and limit values. * Chapter 8, Application Circuits External components and layout recommendations. Illustrations of balanced ringing, unbalanced ringing and protection circuits. * Chapter 9, Package Outlines Illustrations and dimensions of the package outlines. * Chapter 10, Glossary List of abbreviations and description of symbols. * Chapter 11, Index Data Sheet 15 2000-07-14 DuSLIC Preliminary Overview 1 Overview DuSLIC is a chip set, comprising one dual channel SLICOFI-2x codec and two single channel SLIC chips. It is a highly flexible codec/SLIC solution for an analog line circuit and is widely programmable via software. Users can now serve different markets with a single hardware design that meets all different standards worldwide. The interconnections between the single channel high-voltage SLIC and the dual channel SLICOFI-2x codec (advanced CMOS process) ensure a seamless fit. This guarantees maximum transmission performance with minimum line circuit component count. DuSLIC family chip sets: Table 1 Chip Set DuSLIC Chip Sets DuSLIC-S DuSLIC-S2 SLICOFI-2S2/ SLIC-S2 PEB 3264-2/ PEB 4264-21) 60 dB 50 mA 2 1 no no no no DuSLIC-E SLICOFI-2/ SLIC-E PEB 3265/ PEB 4265 53 dB 32 mA 2 1 85 Vrms yes 2.5 Vrms yes DuSLIC-E2 SLICOFI-2/ SLIC-E2 PEB 3265/ PEB 4265-22) 60 dB 50 mA 2 1 85 Vrms yes 2.5 Vrms yes DuSLIC-P SLICOFI-2/ SLIC-P PEB 3265/ PEB 4266 53 dB 32 mA 2/3 0 85 Vrms bal., 50 Vrms unbal. yes 2.5 Vrms yes Marketing Name SLICOFI-2S/ SLIC-S Product ID Longitudinal Balance Maximum DC feeding Neg. Battery Voltages Add. positive Voltages Internal Ringing ITDF3) TTX Add-Ons4) 1) 2) 3) 4) PEB 3264/ PEB 4264 53 dB 32 mA 2 1 45 Vrms no 1.2 Vrms no Nevertheless marked on the chip as PEB 4264 Nevertheless marked on the chip as PEB 4265 Integrated Test and Diagnosis Functions The add-on functions are DTMF detection, Caller ID generation, Message Waiting lamp support, Three Party Conferencing, Universal Tone Detection (UTD), Line Echo Cancellation (LEC) and Sleep Mode. Data Sheet 16 2000-07-14 DuSLIC Preliminary The DuSLIC family comprises five different chip sets (see Table 1): - Three basic DuSLIC chip sets optimized for different applications: DuSLIC-S (Standard), DuSLIC-E (Enhanced), DuSLIC-P (Power Management). - Two different performance versions of the basic DuSLIC-E and DuSLIC-S chip sets: DuSLIC-E2 (using SLIC-E2 PEB 4265-2 compared to DuSLIC-E) DuSLIC-S2 (using SLIC-S2 PEB 4264-2 and codec PEB 3264-2) The codec devices SLICOFI-2, SLICOFI-2S and SLICOFI-2S2 are manufactured in an advanced 0.35 m 3.3 V CMOS process. The SLIC-E, SLIC-E2 and SLIC-P devices are manufactured in Infineon Technologies robust and well proven 170 V Smart Power technology. The SLIC-S and SLIC-S2 devices are manufactured in Infineon Technologies 90 V Smart Power technology and offer further cost reduction. Overview Usage of Codecs and SLICs: DuSLIC-E, DuSLIC-E2 and DuSLIC-P comprise the same SLICOFI-2 codec with full EDSP (Enhanced Digital Signal Processor) features like DTMF detection, Caller ID generation, Universal Tone Detection (UTD) and Line Echo Cancellation. DuSLIC-S comprises the SLICOFI-2S codec without EDSP features. DuSLIC-S2 comprises the SLICOFI-2S2 codec based on the SLICOFI-2S but without Teletax metering (TTX) and internal ringing capability. The respective SLIC variant for each chip set featured in Table 1 has been selected according to performance and application requirements: SLIC-S/-S2 (PEB 4264 / PEB 4264-2) and SLIC-E/-E2 (PEB 4265 / PEB 4265-2) are optimized for access network requirements, while the power management SLIC-P (PEB 4266) is an enhanced version for extremely power-sensitive applications or for applications where internal unbalanced ringing is required. DuSLIC Architecture Unlike traditional designs, DuSLIC splits the SLIC function into high-voltage SLIC functions and low-voltage SLIC functions. The low-voltage functions are handled in the SLICOFI-2x device. The partitioning of the functions is shown in Figure 1. For further information see Chapter 3.1. Data Sheet 17 2000-07-14 DuSLIC Preliminary Overview SLIC SLICOFI-2x SLIC PCM C IOM(R)-2 HV SLIC Functions Voltage feeding Transversal current sensing Longitudinal current sensing Overload protection Battery switching Ring amplification On-hook transmission Polarity reversal LV SLIC Functions Programmable DC feeding Ring generation Supervision Teletax generation Teletax notch filter Ring trip detection Ground key detection Hook switch detection Codec Filter Functions Filtering PCM compression/expansion Programmable gain Programmable frequency Impedance matching Hybrid balance DTMF generation DTMF detection FSK generation (Caller ID) Linear mode support (16-bit uncompressed voice data) IOM-2 and PCM/C interface Integrated Test and Diagnosis Functions (IDTF) Line Echo Cancelling (LEC) Universal Tone Detection (UTD) Three-party conferencing Message waiting lamp support ezm14034.wmf Figure 1 DuSLIC Chip Set Data Sheet 18 2000-07-14 Dual Channel Subscriber Line Interface Circuit DuSLIC PEB 3264/-2 PEB 3265 PEB 4264/-2 PEB 4265/-2 PEB 4266 Version 1.2 1.1 Features * Internal unbalanced/balanced ringing capability up to 85 Vrms * Programmable Teletax (TTX) generation * Programmable battery feeding with capability for driving longer loops * Fully programmable dual-channel codec P-MQFP-64-1,-2 * Ground/loop start signaling * Polarity reversal * Integrated Test and Diagnosis Functions (IDTF) * On-hook transmission * Integrated DTMF generator * Integrated DTMF decoder * Integrated Caller ID (FSK) generator * Integrated fax/modem detection (Universal Tone Detection (UTD)) P-DSO-20-5 * Integrated Line Echo Cancellation unit (LEC) * Optimized filter structure for modem transmission * Three-party conferencing (in PCM/C mode) * Message waiting lamp support (PBX) * Power optimized architecture * Power management capability (integrated battery switches) * 8 and 16 kHz PCM Transmission * Specification in accordance with ITU-T Recommendation Q.552 for interface Z and applicable LSSGR Type PEB 3264/-2 PEB 4264/-2 PEB 3265 PEB 4265/-2 PEB 4266 Package P-MQFP-64-1 P-DSO-20-5 P-MQFP-64-1 P-DSO-20-5 P-DSO-20-5 Data Sheet 19 2000-07-14 DuSLIC Preliminary Overview 1.2 Logic Symbols Tip/Ring interface TIP RING VCMS CEXT Line current PEB 4264 PEB 4264-2 PEB 4265 VDD AGND PEB 4265-2 VHR BGND VBATL VBATH IT IL ACP ACN DCP DCN AC & DC feeding Power supply C1 C2 Logic control ezm14094.emf Figure 2 Logic Symbol SLIC-S / SLIC-S2 / SLIC-E / SLIC-E2 VCMS CEXT Tip/Ring interface TIP RING IT IL Line current PEB 4266 VDD AGND Power supply ACP ACN DCP DCN AC & DC feeding BGND VBATL VBATH VBATR C1 C2 C3 Logic control ezm14095.emf Figure 3 Data Sheet Logic Symbol SLIC-P 20 2000-07-14 DuSLIC Preliminary Overview Line current ITA ITB ITACA ITACB ILA ILB VCMITA VCMITB DCPA DCPB DCNA DCNB CDCPA CDCNA CDCPB CDCNB VCM VCMS ACPA ACPB ACNA ACNB C1A C1B C2A C2B IO1A IO2A IO3A IO4A IO1B IO2B IO3B IO4B PCM/IOM-2 INT TS0/DIN TS1/DCLK TS2/CS DU/DOUT DD/DRB SEL24/DRA DCL/PCLK FSC MCLK DXA DXB TCA TCB IOM-2 interface C-interface DC loop PEB 3265 PEB 3264 PEB 3264-2 PCM interface AC loop RSYNC RESET TEST CREF SELCLK VDDA VDDB GNDA GNDB VDDR GNDR VDDD GNDD VDDPLL GNDPLL Logic control Power supply I/O feeding ezm14096.emf Figure 4 Logic Symbol SLICOFI-2/-2S/-2S2 Data Sheet 21 2000-07-14 DuSLIC Preliminary Overview 1.3 * * * * * * * * * * Typical Applications Digital Loop Carrier (DLC) Wireless Local Loop Fiber in the Loop Private Branch Exchange Intelligent NT (Network Termination) for ISDN ISDN Terminal Adapter Central Office Cable Modem XDSL NT Router Data Sheet 22 2000-07-14 DuSLIC Preliminary Pin Descriptions 2 2.1 Pin Descriptions Pin Diagram SLIC S L IC -P S LIC -E /-E 2 S LIC -S /-S 2 P E B 4266 P E B 426 5/-2 P E B 426 4/-2 IT IL C1 C2 C3 DCP DCN ACP ACN VCM S IT IL C1 C2 N .C . DCP DCN ACP ACN VCMS IT IL C1 C2 N .C . DCP DCN ACP ACN VCMS 20 1 2 19 18 3 17 4 PEB 4264/-2 16 5 PEB 4265/-2 1 5 PEB 4266 6 14 7 13 8 12 9 11 10 R IN G T IP BGND VHR VDD VBATL VBATH N .C . AGND CEXT R IN G T IP BGND VHR VDD VBATL VBATH N .C . AGND CEXT R IN G T IP BGND N .C . VDD VBATL VBATH VBATR AGND CEXT ezm29017.emf Figure 5 Pin Configuration SLIC-S/-S2, SLIC-E/-E2, SLIC-P (top view) Note: The SLIC is only available in a P-DSO-20-5 package with heatsink on top. Please note that the pin counting for the P-DSO-20-5 package is clockwise (top view) in contrast to similar type packages which mostly count counterclockwise. Data Sheet 23 2000-07-14 DuSLIC Preliminary Table 2 Pin Descriptions Pin Definitions and Functions SLIC-S/-S2 and SLIC-E/-E2 Pin Symbol Input (I) Function No. Output (O) 1 2 3 4 5 6 7 RING TIP BGND VHR VDD VBATL VBATH I/O I/O Power Power Power Power Power Subscriber loop connection RING Subscriber loop connection TIP Battery ground: TIP, RING, VBATH, VBATL and VHR refer to this pin Auxiliary positive battery supply voltage used in ringing mode Positive supply voltage (+ 5 V), referred to AGND Negative battery supply voltage (- 15 V VBATL VBATH) Negative battery supply voltage: SLIC-S / SLIC-S2: - 20 V VBATH - 65 V SLIC-E / SLIC-E2: - 20 V VBATH - 85 V Not connected Analog ground: VDD, and all signal and control pins with the exception of TIP and RING refer to AGND Output of voltage divider defining DC line potentials; an external capacitance allows supply voltage filtering (output resistance about 30 k) Reference voltage for differential two-wire interface, typical 1.5 V Differential two-wire AC input voltage; multiplied by - 6 and related to (VHI + VBI)/2, ACN appears at TIP and ACP at RING output, respectively (VHI &VBI are internal voltages) Differential two-wire DC input voltage; multiplied by a factor (- 30 in ACTH and ACTL mode, - 60 in ACTR mode) and related to (VHI + VBI)/2, DCN appears at TIP and DCP at RING output, respectively Not connected Ternary logic input, controlling the operation mode Ternary logic input, controlling the operation mode; in case of thermal overload (chip temperature exceeding 165 C) this pin sinks a current of typically 150 A 8 9 10 N.C. AGND CEXT - Power O 11 VCMS I I 12, ACN, 13 ACP 14, DCN 15 DCP I 16 17 18 N.C. C2 C1 - I I/O Data Sheet 24 2000-07-14 DuSLIC Preliminary Table 2 Pin Descriptions Pin Definitions and Functions SLIC-S/-S2 and SLIC-E/-E2 (cont'd) Pin Symbol Input (I) Function No. Output (O) 19 20 IL IT O O Current output: longitudinal line current scaled down by a factor of 100 Current output representing the transversal current scaled down by a factor of 50 Note: The SLIC is only available in a P-DSO-20-5 package with heatsink on top. Please note that the pin counting for the P-DSO-20-5 package is clockwise (top view) in contrast to similar type packages which mostly count counterclockwise. Data Sheet 25 2000-07-14 DuSLIC Preliminary Table 3 Pin Definitions and Functions SLIC-P Pin Descriptions Pin Symbol Input (I) Function No. Output (O) 1 2 3 4 5 6 7 8 RING TIP BGND N.C. VDD VBATL VBATH VBATR I/O I/O Power - Power Power Power Power Subscriber loop connection RING Subscriber loop connection TIP Battery ground: TIP, RING, VBATH, VBATL and VBATR refer to this pin Not connected Positive supply voltage (3.1 V VDD 5.5 V), referred to AGND Negative battery supply voltage (- 15 V VBATL - 140 V) Negative battery supply voltage (- 20 V VBATH - 145 V, VBATL VBATH) Negative battery supply voltage used as on-hook voltage in power sensitive applications with external ringing or for the extended battery feeding option. (- 25 V VBATR - 150 V, VBATL VBATH VBATR) Analog ground: VDD, and all signal and control pins with the exception of TIP and RING refer to AGND Output of voltage divider defining DC line potentials; an external capacitance allows supply voltage filtering (output resistance about 30 k) Reference voltage for differential two-wire interface, typical 1.5 V Differential two-wire AC input voltage; multiplied by - 6 and related to VBI/2, ACN appears at TIP and ACP at RING output, respectively (VBI is an internal voltage) Differential two-wire DC input voltage; multiplied by a factor (- 30 in ACTH & ACTL mode, - 60 in ACTR mode) and related to VBI/2, DCN appears at TIP and DCP at RING output, respectively Binary logic input, controlling the operation mode Ternary logic input, controlling the operation mode Ternary logic input, controlling the operation mode; in case of thermal overload (chip temperature exceeding 165 C) this pin sinks a current of typically 150 A 9 10 AGND CEXT Power O 11 VCMS I I 12, ACN, 13 ACP 14, DCN, 15 DCP I 16 17 18 C3 C2 C1 I I I/O Data Sheet 26 2000-07-14 DuSLIC Preliminary Table 3 Pin Definitions and Functions SLIC-P (cont'd) Pin Descriptions Pin Symbol Input (I) Function No. Output (O) 19 20 IL IT O O Current output: longitudinal line current scaled down by a factor of 100 Current output representing the transversal current scaled down by a factor of 50 Note: The SLIC is only available in a P-DSO-20-5 package with heatsink on top. Please note that the pin counting for the P-DSO-20-5 package is clockwise (top view) in contrast to similar type packages which mostly count counterclockwise. Data Sheet 27 2000-07-14 DuSLIC Preliminary Pin Descriptions 2.2 Pin Diagram SLICOFI-2/-2S/-2S2 CDCNA CDCPA C1A ILA ITACA ITA VCMITA VDDR GNDR VCMS VCM CREF SELCLK VCMITB ITB ITACB ILB PEB 3265 PEB 3264 PEB 3264-2 17 TS0 / DIN TS1 / DCLK TS2 / CS IO1B IO2B IO3B ACPB CDCPB CDCNB GNDB DCPB ACNB DCNB VDDB IO4B C1B 1 C2B Figure 6 Pin Configuration SLICOFI-2/-2S/-2S2 (top view) Data Sheet 28 33 RSYNC PCM/IOM-2 VDDPLL GNDPLL TCB DXB DXA TCA VDDD GNDD FSC MCLK SEL24 / DRA DD / DRB DCL / PCLK DU / DOUT INT ezm22005.emf RESET GNDA DCNA ACNA VDDA DCPA ACPA TEST IO1A IO2A IO3A IO4A C2A 49 2000-07-14 DuSLIC Preliminary Table 4 Pin Definitions and Functions SLICOFI-2/-2S/-2S2 Pin Descriptions Pin Symbol Input (I) Function No. Output (O) 1 2 3 4 5 6 7 8 9 10 C2B DCPB CDCPB DCNB ACPB ACNB VDDB GNDB IO1B O O I/O O O O Power Power I/O Ternary logic output for controlling the SLIC operation mode (channel B) Two-wire output voltage (DCP) (channel B) External capacitance for filtering (channel B) External capacitance for filtering (channel B) Two-wire output voltage (DCN) (channel B) Differential two-wire AC output voltage controlling the RING pin (channel B) Differential two-wire AC output voltage controlling the TIP pin (channel B) + 3.3 V analog supply voltage (channel B) Analog ground (channel B) User-programmable I/O pin (channel B) with relay-driving capability. In external ringing mode IO1 is used to automatically control and drive the ring relay. User-programmable I/O pin (channel B) with relay-driving capability. SLICOFI-2 and SLIC-P: connected to pin C3 of SLIC-P, when two supply voltages for voice transmission and internal ringing are used.1) User-programmable I/O pin (channel B) with analog input functionality User-programmable I/O pin (channel B) with analog input functionality PCM/IOM-2 = 0 (IOM-2 interface): Time slot selection pin 0 PCM/IOM-2 = 1 (C interface): Data in PCM/IOM-2 = 0 (IOM-2 interface): Time slot selection pin 1 PCM/IOM-2 = 1 (C interface): Data clock PCM/IOM-2 = 0 (IOM-2 interface): Time slot selection Pin 2 PCM/IOM-2 = 1 (C interface): Chip select, low active PCM/IOM-2 = 0 (IOM-2 interface): not connected PCM/IOM-2 = 1 (C interface): Interrupt pin, low active CDCNB I/O 11 IO2B I/O 12 13 14 15 16 IO3B IO4B TS0 DIN TS1 DCLK TS2 CS I/O I/O I I I I I I O 17 INT Data Sheet 29 2000-07-14 DuSLIC Preliminary Table 4 Pin Descriptions Pin Definitions and Functions SLICOFI-2/-2S/-2S2 (cont'd) Pin Symbol Input (I) Function No. Output (O) 18 DU DOUT 19 DCL PCLK DD DRB SEL24 O O I I I I I PCM/IOM-2 = 0 (IOM-2 interface): Data upstream, open drain PCM/IOM-2 = 1 (C interface): Data out, push/pull PCM/IOM-2 = 0 (IOM-2 interface): Data clock PCM/IOM-2 = 1 (PCM interface): 128 kHz to 8192 kHz PCM clock PCM/IOM-2 = 0 (IOM-2 interface): Data downstream PCM/IOM-2 = 1 (PCM interface): Receive data input for PCM highway B PCM/IOM-2 =0 (IOM-2 interface): SEL24 = 0: DCL = 2048 kHz selected SEL24 = 1: DCL = 4096 kHz selected PCM/IOM-2 =1 (PCM-interface): Receive Data input for PCM-highway A PCM/IOM-2 = 0 (IOM-2 interface): not connected PCM/IOM-2 = 1 (PCM interface): master clock when PCM/ C interface is used, clock rates are 512 kHz, 1536 kHz, 2048 kHz, 4096 kHz, 7168 kHz, 8192 kHz Frame synchronization clock for PCM/C or IOM-2 interface, 8 kHz, identifies the beginning of the frame, individual time slots are referenced to this input signal. Digital ground + 3.3 V digital supply voltage Transmit control output for PCM highway A, active low during transmission, open drain Transmit data output for PCM highway A (goes tristate when inactive) Transmit data output for PCM highway B (goes tristate when inactive) Transmit control output for PCM highway B, active low during transmission, open drain Digital ground PLL + 3.3 V supply voltage PLL 20 21 DRA 22 MCLK I I 23 FSC I 24 25 26 27 28 29 30 31 GNDD VDDD TCA DXA DXB TCB Power Power O O O O GNDPLL Power VDDPLL Power Data Sheet 30 2000-07-14 DuSLIC Preliminary Table 4 Pin Descriptions Pin Definitions and Functions SLICOFI-2/-2S/-2S2 (cont'd) Pin Symbol Input (I) Function No. Output (O) 32 33 34 35 36 37 38 PCM/ IOM-2 RSYNC RESET TEST IO4A IO3A IO2A I I I I I/O I/O I/O PCM/IOM-2 = 1: PCM/C interface selected PCM/IOM-2 = 0: IOM-2 interface selected External ringing synchronization pin Reset pin, low active Testpin for production test, has to be connected to GNDD User-programmable I/O Pin (channel A) with analog input functionality User-programmable I/O Pin (channel A) with analog input functionality User-programmable I/O Pin (channel A) with relay-driving capability. SLICOFI-2 and SLIC-P: connected to pin C3 of SLIC-P, when two supply voltages for voice transmission and internal ringing are used.1) User-programmable I/O Pin (channel A) with relay-driving capability. In external ringing mode IO1 is used to automatically control and drive the ring relay. Analog ground (channel A) + 3.3 V analog supply voltage (channel A) Differential two-wire AC output voltage controlling the TIP pin (channel A) Differential two-wire AC output voltage controlling the RING pin (channel A) Two-wire output voltage (DCN) (channel A) External capacitance for filtering (channel A) External capacitance for filtering (channel A) Two-wire output voltage (DCP) (channel A) Ternary logic output for controlling the SLIC operation mode (channel A) Ternary logic output, controlling the SLIC operation mode (channel A); indicating thermal overload of SLIC if a current of typically 150 A is drawn out Longitudinal current input (channel A) Transversal current input (AC) (channel A) 31 2000-07-14 39 IO1A I/O 40 41 42 43 44 45 46 47 48 49 GNDA VDDA ACNA ACPA DCNA CDCPA DCPA C2A C1A Power Power O O O I/O O O I/O CDCNA I/O 50 51 ILA ITACA I I Data Sheet DuSLIC Preliminary Table 4 Pin Descriptions Pin Definitions and Functions SLICOFI-2/-2S/-2S2 (cont'd) Pin Symbol Input (I) Function No. Output (O) 52 53 54 55 56 57 58 59 ITA VDDR GNDR VCMS VCM CREF I Power Power O O I/O Transversal current input (AC + DC) (channel A) Reference pin for trans./long. current sensing (channel A) + 3.3 V analog supply voltage (bias) Analog ground (bias) Reference voltage for differential two-wire interface, typical 1.5 V Reference voltage for input pins IT, IL, ITAC An external capacitor of 68 nF has to be connected to GNDR Master clock select. Should be set to GND (internal master clock generation). For test purposes, external master clock generation can be selected (SELCLK = 1). In this case a clock of nominal 32.768 Mhz with a jitter time of less than 1 ns has to be applied to the MCLK pin. Reference pin for transversal/longitudinal current sensing (channel B) Transversal current input (AC + DC) (channel B) Transversal current input (AC) (channel B) Longitudinal current input (channel B) Ternary logic output, controlling the SLIC operation mode (channel B); indicating thermal overload of SLIC if a current of typically 150 A is drawn out VCMITA I SELCLK I 60 61 62 63 64 VCMITB I ITB ITACB ILB C1B I I I I/O 1) If SLIC-P is selected, IO2 cannot be controlled by the user, but is utilized by the SLICOFI-2 to control the C3 pin of SLIC-P. Data Sheet 32 2000-07-14 DuSLIC Preliminary Functional Description 3 3.1 3.1.1 Functional Description Functional Overview Basic Functions available for all DuSLIC Chip Sets The functions described in this chapter are integrated in all DuSLIC chip sets (see Figure 7 for DuSLIC-S/-S2 and Figure 8 for DuSLIC-E/-E2/-P). All BORSCHT functions are integrated: * Battery feed * Overvoltage protection (realized by the robust high-voltage SLIC technology and additional circuitry) * Ringing1) * Signaling (supervision) * Coding * Hybrid for 2/4-wire conversion * Testing An important feature of the DuSLIC design is the fact that all the SLIC and codec functions are programmable via the IOM-2 or PCM/C-interface of the dual channel SLICOFI-2x device: * * * * * * * * * DC (battery) feed characteristics AC impedance matching Transmit gain Receive gain Hybrid balance Frequency response in transmit and receive direction Ring frequency and amplitude1) Hook thresholds TTX modes2) Because signal processing within the SLICOFI-2x is completely digital, it is possible to adapt to the requirements listed above by simply updating the coefficients that control DSP processing of all data. This means, for example, that changing impedance matching or hybrid balance requires no hardware modifications. A single hardware is now capable of meeting the requirements for different markets. The digital nature of the filters and gain stages also assures high reliability, no drifts (over temperature or time) and minimal variations between different lines. 1) 2) For DuSLIC-S2 chip set external ringing is supported Not available with DuSLIC-S2 chip set Data Sheet 33 2000-07-14 DuSLIC Preliminary Functional Description The characteristics for the two voice channels within SLICOFI-2x can be programmed independently of each other. The DuSLICOS software is provided to automate calculation of coefficients to match different requirements. DuSLICOS also verifies the calculated coefficients. 3.1.2 Additional Functions available for DuSLIC-E/-E2/-P Chip Sets The following line circuit functions are integrated only in the DuSLIC-E/-E2/-P chip sets (see Figure 8): * Teletax metering For pulse metering, a 12/16 kHz sinusoidal metering burst has to be transmitted. The DuSLIC chip set generates the metering signal internally and has an integrated notch filter. * DTMF DuSLIC has an integrated DTMF generator comprising two tone generators and a DTMF decoder. The decoder is able to monitor the transmit or receive path for valid tone pairs and outputs the corresponding digital code for each DTMF tone pair. * Caller ID Frequency Shift Keying (FSK) Modulator DuSLIC has an integrated FSK modulator capable of sending Caller ID information. The Caller ID modulator complies with all requirements of ITU-T recommendation V.23 and Bell 202. * LEC (Line Echo Cancellation) DuSLIC contains an adaptive line echo cancellation unit for the cancellation of near end echos (up to 8 ms cancelable echo delay time). * UTD (Universal Tone Detection) DuSLIC has an integrated Universal Tone Detection unit to detect special tones in the receive or transmit path (e.g. fax or modem tones). Data Sheet 34 2000-07-14 DuSLIC Preliminary Functional Description SLIC-S/-S2 Current Sensor & Offhook Detection TIP RING VBAT/VH switch Control Logic Gain SLICOFI-2S/-2S2 TTX Metering* Supervision Channel A Prefilter Postfilter ADC DAC Hardware Filters Programmable Filters and Gain Digital Signal Processing (DSP) ADC DAC Hardware Filters Programmable Filters and Gain A-Law or -Law Compander A-Law or -Law PCM / IOM-2 Interface PCM Interface IOM-2 Interface SLIC-S/-S2 Current Sensor & Offhook Detection TIP RING VBAT/VH switch Control Logic Gain Channel B Prefilter Postfilter SLIC-S/-S2 Interface Control Ringing* Controller DCCTL Serial C Interface * not available with SLICOFI-2S2 one SLICOFI-2S/-2S2 channel both SLICOFI-2S/-2S2 channels ezm22020.emf Figure 7 Line Circuit Functions included in the DuSLIC-S/-S2 SLIC-E/-E2/-P Current Sensor & Offhook Detection TIP RING VBAT/VH switch Control Logic Gain SLICOFI-2 Level Metering TTX Metering CID Generation UTD LEC Supervision DTMF Channel A Prefilter Postfilter ADC DAC Hardware Filters Programmable Filters and Gain Digital Signal Processing (DSP) ADC DAC Hardware Filters Programmable Filters and Gain A-Law or -Law Compander A-Law or -Law PCM / IOM-2 Interface PCM Interface IOM-2 Interface SLIC-E/-E2/-P Current Sensor & Offhook Detection TIP RING VBAT/VH switch Control Logic Gain Channel B Prefilter Postfilter SLIC-E/-E2/-P Interface Control Ringing Controller DCCTL Serial C Interface one SLICOFI-2 channel both SLICOFI-2 channels ezm22007.emf Figure 8 Line Circuit Functions included in the DuSLIC-E/-E2/-P Data Sheet 35 2000-07-14 DuSLIC Preliminary Functional Description 3.2 Block Diagrams Figure 9, Figure 10 and Figure 11 show the basic functional blocks and circuits for all SLIC versions of the DuSLIC chip set. PEB 4264/-2 BGND PDRHL PDRH ITO 60k 5k TIP IT VBI SymFi 2k + + Off-hook (IRO + ITO ) / 10 (IR + IT ) / 100 VHI VHR VH Switch BGND IT IL Current Sensor (IR - IT ) / 200 VHI - 10k 2k 2k S1 ACN DCN CEXT VHI RING IR 5k 60k I RO PDRHL PDRH DCP S2 ACP 2k - 10k S1, S2 closed: ACTR, HIT, HIR VCMS VBATL VBATH (Sub) VBAT Switch C1 C2 VBI BIAS Logic AGND VDD (+5V) ezm29012.emf Figure 9 Block Diagram SLIC-S/-S2 (PEB 4264/-2) Data Sheet 36 2000-07-14 DuSLIC Preliminary Functional Description PEB 4265/-2 BGND PDRHL PDRH ITO 5k VHI TIP IT VBI SymFi 2k + + Offhook Current Sensor (IRO + ITO) / 10 (IR + IT) / 100 (IR - IT) / 200 60k - VHI VH Switch VHR BGND IT IL 10k 2k 2k S1 ACN DCN CEXT VHI RING IR 5k IRO PDRHL PDRH 60k DCP S2 2k - 10k S1, S2 closed: ACTR, HIT, HIR, HIRT ACP VCMS VBATL VBATH (Sub) VBAT Switch C1 C2 VBI BIAS Logic AGND VDD (+5V) ezm20002.emf Figure 10 Block Diagram SLIC-E/-E2 (PEB 4265/-2) Data Sheet 37 2000-07-14 DuSLIC Preliminary Functional Description PEB 4266 BGND PDRR PDRRL PDRH PDRHL 5k TIP IT VBI SymFi 2k + + Off-hook (IR0 + IT0) / 10 BGND (IR + IT) / 100 IT IL Current sensor IT0 BGND (IR - IT) / 200 60k - 10k 2k 2k 2k S1 ACN DCN CEXT DCP S2 ACP RING IR 5k IR0 PDRR PDRRL VBATL VBATH VBATR (SUB) Battery switch VBI BIAS PDRH PDRHL 60k - 2k 10k S1, S2 closed: ACTR, ROT, ROR, HIT, HIR, HIRT VCMS C1 Logic C2 C3 AGND VDD(+5V) ezm21002.emf Figure 11 Block Diagram SLIC-P (PEB 4266) Data Sheet 38 2000-07-14 DuSLIC Preliminary Functional Description Figure 12 shows the internal block structure of all SLICOFI-2x codec versions available. The Enhanced Digital Signal Processor (EDSP) realizing the add-on funtions1) is only integrated in the SLICOFI-2 (PEB 3265) device. PEB 3265 / PEB 3264 / PEB 3264-2 CDCNA CDCPA CDCNB CDCPB VCM VCMS IO1A IO2A IO3A IO4A IO1B IO2B IO3B IO4B ILA ITA ITACA VCMITA ACNA ACPA DCNA DCPA C1A C2A ILB ITB Supervision Prefi IMa + Channel A PEB 3265 only ADC HW-Fi EDSP Pofi HV Interf. Supervision Prefi DAC HW-Fi COMPAND IOM-2 IOM-2 Interface Channel B or CRAM PCM ADC HW-Fi CONTR C PCM / C Interface ITACB VCMITB ACNB ACPB DCNB DCPB C1B C2B IMa DSP + Pofi HV Interf. DAC HW-Fi DBUS GNDA GNDD GNDR GNDPLL VDDA VDDD VDDR VDDPLL CREF RESET PCM/IOM-2 ezm22021.emf Figure 12 Block Diagram SLICOFI-2/-2S/-2S2 (PEB 3265, PEB 3264/-2) 1) The add-on functions are DTMF detection, Caller ID generation, Message Waiting lamp support, Three Party Conferencing, Universal Tone Detection (UTD), Line Echo Cancellation (LEC) and Sleep Mode. Data Sheet 39 2000-07-14 DuSLIC Preliminary Functional Description 3.3 DC Feeding DC feeding with the DuSLIC is fully programmable by using the software coefficients depicted in Table 5 on Page 45. Figure 13 shows the signal paths for DC feeding between the SLIC and SLICOFI-2x: Transmit path IL IT C ITA RIT1A ILA ITACA ITA TIP SLIC Channel A DCP DCN ACP ACN R ILA R IT2A CVCMITA VCMITA VCM DCPA DCNA ACPA ACNA PCM out (data upstream) Transmit RING SLICOFI-2x IL IT C ITB R IT1B ILB ITACB ITB PCM or IOM-2 Interface PCM in (data downstream) Receive TIP SLIC RING Channel B DCP DCN ACP ACN R ILB R IT2B CVCMITB VCM VCMITB DCPB DCNB ACPB ACNB Receive path ezm140374.emf Figure 13 Signal Paths - DC Feeding Data Sheet 40 2000-07-14 DuSLIC Preliminary Functional Description 3.3.1 DC Characteristic Feeding Zones The DuSLIC DC feeding characteristic has three different zones: the constant current zone, the resistive zone and the constant voltage zone. A voltage reserve VRES (see Chapter 3.3.7) can be selected to avoid clipping the high level AC signals (e.g. TTX) and to take into account the voltage drop of the SLIC. The DC feeding characteristic is shown in Figure 14. ITIP/RING Constant current zone I0 Resistive zone Constant voltage zone Necessary voltage reserve VRES |VBAT| VTIP/RING ezm14017.emf Figure 14 DC Feeding Characteristic The simplified diagram shows the constant current zone as an ideal current source with an infinite internal resistance, while the constant voltage zone is shown as an ideal voltage source with an internal resistance of 0 . For the specification of the internal resistances see Chapter 3.3.5. Data Sheet 41 2000-07-14 DuSLIC Preliminary Functional Description 3.3.2 Constant Current Zone In the off-hook state, the feed current must usually be kept at a constant value independent of load (see Figure 15). The SLIC senses the DC current and supplies this information to SLICOFI-2x via the IT pin (input pin for DC control). SLICOFI-2x compares the actual current with the programmed value and adjusts the SLIC drivers as necessary. ITIP/RING in the constant current zone is programmable from 0 to 32 mA or 0 to 50 mA depending on the used SLIC version. ITIP/RING RLOAD RI I0 RK12 VRES |VBAT| Figure 15 Constant Current Zone VTIP/RING ezm14016.emf Depending on the load, the operating point is determined by the voltage VTIP/RING between the Tip and Ring pins. The operating point is calculated from: VTIP/RING = RLOAD x ITIP/RING where RLOAD = RPRE + RLINE + RPHONE,OFF-HOOK RPRE = RPROT + RSTAB (see Figure 99 on Page 370). The lower the load resistance RLOAD, the lower the voltage between the Tip and Ring pins. A typical value for the programmable feeding resistance in the constant current zone is about RI = 10 k (see Table 5). Data Sheet 42 2000-07-14 DuSLIC Preliminary Functional Description 3.3.3 Resistive Zone The programmable resistive zone RK12 of DuSLIC provides extra flexibility over a wide range of applications. The resistive zone is used for very long lines where the battery is incapable of feeding a constant current into the line. The operating point in this case crosses from the constant current zone for low and medium impedance loops to the resistive zone for high impedance loops (see Figure 16). The resistance of the zone RK12 is programmable from RV to 1000 . ITIP/RING RI I0 RLOAD RK12 VRES |VBAT| VTIP/RING ezm14035.emf Figure 16 Resistive Zone Data Sheet 43 2000-07-14 DuSLIC Preliminary Functional Description 3.3.4 Constant Voltage Zone The constant voltage zone (see Figure 17) is used in some applications to supply a constant voltage to the line. In this case VTIP/RING is constant and the current depends on the load between the Tip and Ring pin. In the constant voltage zone the external resistors RPRE = RStab + RProt necessary for stability and protection define the resistance RV seen at the RING and TIP wires of the application. The programmable range of the parameters RI, I0, IK1, VK1, RK12 and VLIM is given in Table 5. ITIP/RING I0 RK12 VRES RLOAD VLIM |VBAT| VTIP/RING ezm14036.emf Figure 17 Constant Voltage Zone Data Sheet 44 2000-07-14 DuSLIC Preliminary Functional Description 3.3.5 Programmable Voltage and Current Range of DC Characteristic The DC characteristic and all symbols are shown in Figure 18. ITIP/RING I0 IK1 IK2 RI 1 RK12 2 RV = RPRE = RPROT + RSTAB VK1 VK2 VLIM Figure 18 Table 5 DC Characteristic DC Characteristic Condition - 1.8 k ... 40 k 0 ... 32 mA 0 ... 50 mA 0 ... 32 mA 0 ... 50 mA 0 ... 50 V VTIP/RING ezm22009.wmf Symbol Programmable Range RI I0 IK1 VK1 only for DuSLIC-S, DuSLIC-E, DuSLIC-P only for DuSLIC-S2, DuSLIC-E2 only for DuSLIC-S, DuSLIC-E, DuSLIC-P only for DuSLIC-S2, DuSLIC-E2 - RK12 VLIM VK1 < VLIM - IK1 x RK12 only (VK1, IK1) VK1 < VLIM - IK1 x RV (VK1, IK1) and (VK2, IK2) VK1 > VLIM - IK1 x RK12 RV ... 1000 - 0 ... 50 V - VLIM > VK1 + IK1 x RK12 only (VK1, IK1) Data Sheet 45 2000-07-14 DuSLIC Preliminary Functional Description 3.3.6 SLIC Power Dissipation The major portion of the power dissipation in the SLIC can be estimated by the power dissipation in the output stages. The power dissipation can be calculated from: PSLIC (VBAT - VTIP/RING) x ITIP/RING ITIP/RING SLIC output stage power dissipation constant current zone I0 SLIC output stage power dissipation constant voltage zone |VBAT| VTIP/RING ezm14021.emf Figure 19 Power Dissipation For further information see Chapter 4.7.3 on Page 95. Data Sheet 46 2000-07-14 DuSLIC Preliminary Functional Description 3.3.7 Necessary Voltage Reserve To avoid clipping AC speech signals as well as AC metering pulses, a voltage reserve VRES (see Figure 14) has to be provided. VRES = |VBAT| - VLIM VBAT is the selected battery voltage, which can be depending on the mode either VBATH, VBATL, (VHR - VBATH) for SLIC-S/-S2/-E/-E2 or VBATH, VBATL, - VBATR for SLIC-P. VRES consists of: * Voltage reserve of the SLIC output buffers: this voltage drop depends on the output current through the Tip and Ring pins. For a standard output current of 25 mA, this voltage reserve is a few volts (see Table 17 on Page 95). * Voltage reserve for AC speech signals: max. signal amplitude (example 2 V) * Voltage reserve for AC metering pulses: The TTX signal amplitude VTTX depends on local specifications and varies from 0.1 Vrms to several Vrms at a load of 200 . To obtain VTTX = 2 Vrms at a load of 200 and RPRE = 50 =(RPRE = RPROT + RSTAB, see Figure 99 on Page 370), 3 Vrms = 4.24 Vpeak are needed at the SLIC output. Therefore a VRES value of 10.24 V must be selected (= 4 V (SLIC drop for peak current of DC and speech and TTX) + 2 V (AC speech signals) + 4.24 V (TTX-signal)). RPRE SLIC RPRE 200 VTTX ezm14032.wmf Figure 20 TTX Voltage Reserve Schematic Data Sheet 47 2000-07-14 DuSLIC Preliminary Functional Description 3.3.8 Extended Battery Feeding If the battery voltage is not sufficient to supply the minimum required current through the line even in the resistive zone, the auxiliary positive battery voltage can be used to expand the voltage swing between Tip and Ring. With this extended supply voltage VHR (DuSLIC-S/E) respectively VBATR (DuSLIC-P), it is possible to supply the constant current for long lines. Figure 21 shows the DC feeding impedances RMAX,ACTH in ACTH mode and RMAX,ACTR in ACTR mode (for ACTH and ACTR modes see Chapter 4.1). ACTH Normal Mode ACTR Extended Battery Feeding Mode RMAX IK1 RK12 RMAX, ACTR RK12, ACTR ITIP/RING VK1 VLIM |VBATH| VK1, ACTR VLIM, ACTR |VHR - VBATH|1) |VBATR|2) 1) VTIP/RING DuSLIC-S/-E, 2) DuSLIC-P ezm23019.emf Figure 21 DC Feeding Characteristics (ACTH, ACTR) The extended feeding characteristic is determined by the feeding characteristic in normal mode (ACTH) and an additional gain factor KB (DuSLICOS DC Control Parameter 1/3: Additional Gain in active Ring): VLIM,ACTR = VLIM x KB VK1,ACTR = VK1 x KB + RV x IK1 x (KB - 1) = VK1 x KB RK12,ACTR = KB x (RK12 - RV) + RV RK12 x=KB RI,ACTR = RI x KB/2 IK2,ACTR = IK2 x KB x (RK12 - RV)/(KB x RK12 - RV) VK2,ACTR = VLIM,ACTR - IK2,ACTR x RV Data Sheet 48 2000-07-14 DuSLIC Preliminary Functional Description 3.4 AC Transmission Characteristics SLICOFI-2x uses either an IOM-2 or a PCM digital interface. In receive direction, SLICOFI-2x converts PCM data from the network and outputs a differential analog signal (ACP and ACN) to the SLIC, that amplifies the signal and applies it to the subscriber line. In transmit direction, the transversal (IT) and longitudinal (IL) currents on the line are sensed by the SLIC and fed to the SLICOFI-2x. A capacitor separates the transversal line current into DC (IT) and AC (ITAC) components. As ITAC is the sensed transversal (also called metallic) current on the line, it includes both the receive and transmit components. SLICOFI-2x separates the receive and transmit components digitally, via a transhybrid circuit. Figure 22 shows the signal paths for AC transmission between the SLICs and SLICOFI-2x: Transmit path IL IT C ITA RIT1A ILA ITACA ITA TIP SLIC Channel A DCP DCN ACP ACN R ILA R IT2A CVCMITA VCMITA VCM DCPA DCNA ACPA ACNA PCM out (data upstream) Transmit RING SLICOFI-2x IL IT C ITB R IT1B ILB ITACB ITB PCM or IOM-2 Interface PCM in (data downstream) Receive TIP SLIC RING Channel B DCP DCN ACP ACN R ILB R IT2B CVCMITB VCM VCMITB DCPB DCNB ACPB ACNB Receive path ezm140373.emf Figure 22 Signal Paths - AC Transmission The signal flow within the SLICOFI-2x for one voice channel is shown in Figure 23 by the following schematic circuitry. With the exception of a few analog filter functions, signal processing is performed digitally in the SLICOFI-2x. Data Sheet 49 2000-07-14 DuSLIC Preliminary Functional Description SLICOFI-2x Channel B Channel A ITAC TTX filter Prefilter A/D Amplify transmit + Transmit DTMF detection Frequency response transmit CMP PCM out Impedance matching ACP Impedance matching Transhybrid filter TG 1 TG 2 + Postfilter D/A + Amplify receive Frequency response receive + PCM in EXP CID generation ACN Teletax generator Receive ezm14026.emf Figure 23 Signal Flow in Voice Channel (A) 3.4.1 Transmit Path The current sense signal (ITAC) is converted to a voltage by an external resistor. This voltage is first filtered by an anti-aliasing filter (pre-filter), that stops producing noise in the voiceband from signals near the A/D sampling frequency. A/D conversion is done by a 1-bit sigma-delta converter. The digital signal is down-sampled further and routed through programmable gain and filter stages. The coefficients for the filter and gain stages can be programmed to meet specific requirements. The processed digital signal goes through a compander (CMP) that converts the voice data into A-law or -law codes. A time slot assignment unit outputs the voice data to the programmed time slot. SLICOFI-2x can also operate in 16-bit linear mode for processing uncompressed voice data. In this case, two time slots are used for one voice channel. 3.4.2 Receive Path The digital input signal is received via the IOM-2 or PCM interface. Expansion (EXP), PCM low-pass filtering, frequency response correction and gain correction are performed by the DSP. The digital data stream is up-sampled and converted to a corresponding analog signal. After smoothing by post-filters in the SLICOFI-2x, the AC signal is fed to the SLIC, where it is superimposed on the DC signal. The DC signal has been processed in a separate DC path. A TTX signal, generated digitally within SLICOFI-2x, can also be added. Data Sheet 50 2000-07-14 DuSLIC Preliminary Functional Description 3.4.3 Impedance Matching The SLIC outputs the voice signal to the line (receive direction) and also senses the voice signal coming from the subscriber. The AC impedance of the SLIC and the load impedance need to be matched in order to maximize power transfer and minimize twowire return loss. The two-wire return loss is a measure of the impedance matching between a transmission line and the AC termination of DuSLIC. Impedance matching is done digitally within SLICOFI-2x by providing three impedance matching feedback loops. The loops feed the transmit signal back to the receive signal simulating the programmed impedance through the SLIC. When calculating the feedback filter coefficients, the external resistors between the protection network and SLIC (RPRE = RPROT + RSTAB, see Figure 100, Page 372) have to be taken into account. The impedance can be programmed to any appropriate real and complex values shown in the Nyquist diagram Figure 24. This means that the device can be adapted to requirements anywhere in the world without requiring the hardware changes that are necessary with conventional line card designs. Re ZL 0 200 400 600 800 1000 1200 1400 -200 Im ZL -400 Possible Values for Line Impedance -600 ezm22019.emf Figure 24 Nyquist Diagram Data Sheet 51 2000-07-14 DuSLIC Preliminary Functional Description 3.5 Ringing With the 170 V technology used for the SLIC, a ringing voltage of up to 85 Vrms can be generated on-chip without the need for an external ringing generator. The SLICOFI-2x generates a sinusoidal ringing signal that causes less noise and cross-talk in neighboring lines than a trapezoidal ringing signal. The ringing frequency is programmable from 3 to 300 Hz. SLIC-E/-E2, SLIC-S/-S2 and SLIC-P support different ringing methods (see Chapter 3.5.3). 3.5.1 Ringer Load A typical ringer load can be thought of as a resistor in series with a capacitor. Ringer loads are usually described as a REN (Ringer Equivalence Number) value. REN is used to describe the on-hook impedance of the terminal equipment, and is actually a dimensionless ratio that reflects a certain load. REN definitions vary from country to country. A commonly used REN is described in FCC part 68 that defines a single REN as either 5 k, 7 k or 8 k of AC impedance at 20 Hz. The impedance of an n-multiple REN is equivalent to parallel connection of n single RENs. In this manual, all references to REN assume the 7 k model. For example, a 1 REN and 5 REN load would be: 6930 8 F 1386 40 F 1 REN Figure 25 5 REN ezm14024.wmf Typical Ringer Loads of 1 and 5 REN Used in US 3.5.2 Ring Trip Once the subscriber has gone off-hook, the ringing signal must be removed within a specified time, and power must start feeding to the subscriber's phone. There are two ring trip methods: DC Ring Trip Detection Most applications with DuSLIC are using DC ring trip detection. By applying a DC offset together with the ringing signal, a transversal DC loop current starts to flow when the subscriber goes off-hook. This DC current is sensed by the SLIC and in this way used as an off-hook criterion. The SLIC supplies this information to the SLICOFI-2x at the IT pin. The SLICOFI-2x continuously integrates the sensed line current ITRANS over one Data Sheet 52 2000-07-14 DuSLIC Preliminary Functional Description ringer period. This causes the integration result to represent the DC component of the ring current. If the DC current exceeds the programmed ring trip threshold, SLICOFI-2x generates an interrupt. Ring trip is reliably detected and reported within two ring signal periods. The ringing signal is switched off automatically at zero crossing by the SLICOFI-2x. The threshold for the ring trip DC current is set internally in SLICOFI-2x, programmed via the digital interface. The DC offset for ring trip detection can be generated by the DuSLIC chip set and the internal ring trip function can be used, even if an external ringing generator is used. AC Ring Trip Detection For short lines (< 1 k loop length) and for low-power applications, the DC offset can be avoided to reduce the battery voltage for a given ring amplitude. Ring trip detection is done by rectifying the ring current ITRANS, integrating it over one ringer period and comparing it to a programmable AC ring trip threshold. If the ring current exceeds the programmed threshold the HOOK bit in register INTREG1 is set accordingly. Most applications with DuSLIC are using DC ring trip detection, which is more reliable than AC ring trip detection. 3.5.3 Ringing Methods There are two methods of ringing: * Balanced ringing (bridged ringing) * Unbalanced ringing (divided ringing) Internal balanced ringing generally offers more benefits compared to unbalanced ringing: * Balanced ringing produces much less longitudinal voltage, which results in a lower amount of noise coupled into adjacent cable pairs * By using a differential ringing signal, lower supply voltages become possible The phone itself cannot distinguish between balanced and unbalanced ringing. Where unbalanced ringing is still used, it is often simply a historical leftover. For a comparison between balanced and unbalanced ringing see also ANSI document T1.401-1993. Additionally, integrated ringing with the DuSLIC offers the following advantages: * Internal ringing (no need for external ringing generator and relays) * Reduction of board space because of much higher integration and fewer external components * Programmable ringing amplitude, frequency and ringing DC offset without hardware changes * Programmable ring trip thresholds * Switching off the ringing signal at zero-crossing Data Sheet 53 2000-07-14 DuSLIC Preliminary Functional Description 3.5.4 DuSLIC Ringing Options Application requirements differ with regard to ringing amplitudes, power requirements, loop length and loads. The DuSLIC options include three different SLICs to select the most appropriate ringing methods (see Table 6): Table 6 Ringing Options with SLIC-S, SLIC-E/-E2 and SLIC-P SLIC-S PEB 4264 SLIC-E/-E2 PEB 4265 PEB 4265-2 85 Vrms SLIC-P PEB 4266 85 Vrms SLIC Version/ Ringing Facility, Battery Voltages 45 Vrms Internal balanced ringing max. voltage in Vrms (sinusoidal) with 20 VDC used for ring trip detection DC voltage for balanced ringing1) programmable typ. 0 ... 50 V Internal unbalanced ringing NO max. voltage in Vrms (sinusoidal) DC voltage for unbalanced ringing Required SLIC supply voltages for maximum ringing amplitude (typically) Number of battery voltages for power saving NO programmable typ. 0 ... 50 V NO NO programmable typ. 0 ... 50 V 50 Vrms VBATR/2 VDD = 5 V, VDD = 5 V, VDD = 5 V or VBATH = - 54 V, VBATH = - 70 V, 3.3 V, VHR = 36 V VHR = 80 V VBATH = - 70 V, VBATR = - 150 V 2 (VBATL & VBATH) 2 (VBATL & VBATH) 2 (when internal ringing is used) 3 (when external ringing is used) 1) In most applications 20 VDC are sufficient for reliable ring trip detection. A higher DC voltage will reduce the achievable maximum ringing voltage. For short loops 10 VDC may be sufficient. SLIC-S allows balanced ringing up to 45 Vrms and is dedicated for short loop or PBX applications. For SLIC-S2 only external ringing is provided. SLIC-E/-E2 allows balanced ringing up to 85 Vrms and can therefore be used in systems with higher loop impedance. Data Sheet 54 2000-07-14 DuSLIC Preliminary Functional Description The low-power SLIC-P is optimized for power-critical applications (e.g. intelligent ISDN network termination). Internal ringing can be used up to 85 Vrms balanced or 50 Vrms unbalanced. For lowest power applications where external ringing is preferred, three different battery voltages (VBATR, VBATH, VBATL) can be used for optimizing the power consumption of the application.1) SLIC-E/-E2 and SLIC-P differ in supply voltage configuration and the ring voltages at Tip and Ring VT and VR. External ringing is supported by both SLIC's. Both internal and external ringing is activated by switching the DuSLIC to ringing mode by setting the CIDD/CIOP bits M2, M1, M0 to 101. External Ringing Support by DuSLIC The following settings have to be made: * Enabling the use of an external ring signal generator by setting bit REXT-EN in Register BCR2 to 1. * A TTL compatible zero crossing signal has to be applied to the RSYNC pin of the SLICOFI-2x (see Figure 26). * Activating the ringing mode by setting the CIDD/CIOP bits M2, M1, M0 to 101. * Setting the DuSLIC internal ring frequency to a value according a factor of about 0.75 of the external ring frequency. The ring relay is controlled by the IO1 pin (see Figure 100). Due to the high current drive capability of the IO1 ouput, no additional relay driver is necessary. The relay is switched: * Synchronous to the zero crossing of the external ringing frequency (bit ASYNCH-R in register XCR set to 0) A ring generator delay TRING,DELAY (see DuSLICOS control parameters 2/3) can be programmed to consider the ring relay delay TRING-RELAY,DELAY as shown in Figure 26. * Asynchronous (bit ASYNCH-R in register XCR set to 1) The ring relay is switched immediately with the ring command. 1) In this case VBATR is typically used for the on-hook state, while VBATH and VBATL are used for optimized feeding of different loop length in the off-hook state. Data Sheet 55 2000-07-14 DuSLIC Preliminary Functional Description E xte rn a l R in g in g V o lta g e t V RSYN C t V IO 1 T R IN G ,D E L A Y T R IN G -R E L A Y ,D E L A Y t V R IN G t duslic_0015_zero_crossing.emf Figure 26 External Ringing Zero Crossing Synchronization Data Sheet 56 2000-07-14 DuSLIC Preliminary Functional Description 3.5.5 Internal Balanced Ringing via SLICs SLIC-E/-E2 and SLIC-P support internal balanced ringing up toVRING,RMS = 85 Vrms, SLIC-S support balanced ringing up to VRING,RMS = 45 Vrms1). The ringing signal is generated digitally within SLICOFI-2x2). VHR VDROP,T vT VTp VRING,pp= VTp - VRp BGND VDC,RING VRp vR VDROP,R VBATH VBATR SLIC-E SLIC-E2 SLIC-P SLIC-S ezm140315.emf Figure 27 Balanced Ringing via SLIC-E/-E2, SLIC-S and SLIC-P In ringing mode, the DC feeding regulation loop is not active. A programmable DC ring offset voltage is applied to the line instead. During ring bursts, the ringing DC offset and the ringing signal are summed digitally within SLICOFI-2x in accordance with the programmed values. This signal is then converted to an analog signal and applied to the SLIC. The SLIC amplifies the signal and supplies the line with ringing voltages up to 85 Vrms. In balanced ringing mode, the SLIC uses an additional supply voltage VHR for SLIC-E/-E2/-S and VBATR for SLIC-P. The total supply span is now VHR - VBATH for SLIC-E/-E2/-S and VBATR for SLIC-P. The maximum ringing voltage that can be achieved is: for SLIC-E/-E2/-S: for SLIC-P: where: 1) VRING,RMS = (VHR - VBATH - VDROP, RT - VDC,RING)/1.41 VRING,RMS = (- VBATR - VDROP,RT - VDC,RING)/1.41 VDROP,RT = VDROP,T + VDROP,R In this case VRING,RMS = VRT,RMS = VRT0,RMS because of the low impedance of the SLIC output (< 1 ). VRT,RMS is the open-circuit rms voltage measured directly at pins RING and TIP at the SLIC output with ringer load. VRT0,RMS is the rms voltage measured directly at pins RING and TIP at the SLIC output without any ringer load. For calculation of the ringing voltage at the ringer load see the Voltage and Power Application Note and the accompanying MS Excel Sheet for calculation. 2) SLICOFI-2S2 supports only external ringing Data Sheet 57 2000-07-14 DuSLIC Preliminary Functional Description With the DuSLIC ringing voltages up to 85 Vrms sinusoidal can be applied, but also trapezoidal ringing can be programmed. For a detailed application diagram of internal balanced ringing refer to the chapter on "Application Circuits" (see Figure 97, Page 368). 3.5.6 Internal Unbalanced Ringing with SLIC-P The internal unbalanced ringing together with SLIC-P can be used for ringing voltages up to 50 Vrms. The SLICOFI-2 integrated ringing generator is used and the ringing signal is applied to either the Tip or Ring line. Ringing signal generation is the same as described above for balanced ringing. Since only one line is used for ringing, technology limits the ringing amplitude to about half the value of balanced ringing, to maximum 50 Vrms. VDROP,R,BGND =VDROP,T VDROP,T VDC,RING BGND VT VBATR / 2 VRING,p vR VDROP,R,VBATR vRING = vR VBATR ezm140316.wmf Figure 28 Unbalanced Ringing Signal The above diagram shows an example with the ring line used for ringing and the Tip line fixed at - VDROP,T which is the drop in the output buffer of the Tip line of SLIC-P (typ. < 1 V). The ring line has a fixed DC voltage of VBATR/2 used for ring trip detection. The maximum ringing voltage is: VRING,RMS = (- VBATR - VDROP,R,VBATR - VDROP,T)/2.82 When the called subscriber goes off-hook, a DC path is established from the Ring to the Tip line. The DC current is recognized by the SLICOFI-2 because it monitors the IT pin. An interrupt indicates ring trip if the line current exceeds the programmed threshold. The same hardware can be used for integrated balanced or unbalanced ringing. The balanced or unbalanced modes are configured by software. The maximum achievable amplitudes depend on the values selected for VBATR. Data Sheet 58 2000-07-14 DuSLIC Preliminary Functional Description In both balanced and unbalanced ringing modes, SLICOFI-2 automatically applies and removes the ringing signal during zero-crossing. This reduces noise and cross-talk to adjacent lines. 3.5.7 External Unbalanced Ringing SLICOFI-2x supports external ringing for higher unbalanced ringing voltage requirements above 85 Vrms with all SLICs. For a detailed application diagram of unbalanced ringing see Figure 100 and Figure 101 on Page 372 and Page 373. Since high voltages are involved, an external relay should be used to switch the RING line off and to switch the external ringing signal together with a DC voltage to the line. The DC voltage has to be applied for the internal ring trip detection mechanism which operates for external ringing in the same way as for internal ringing. The SLICOFI-2x has to be set to the external ringing mode by the REXT-EN bit in register BCR2. A synchronization signal of the external ringer is applied to the SLICOFI-2x via the RSYNC pin. The external relay is switched on or off synchronously to this signal via the IO1 pin of the SLICOFI-2x according to the actual mode of the DuSLIC. An interrupt is generated if the DC current exceeds the programmed ring trip threshold. 3.6 Signaling (Supervision) Signaling in the subscriber loop is monitored internally by the DuSLIC chip set. Supervision is performed by sensing the longitudinal and transversal line currents on the Ring and Tip wires. The scaled values of these currents are generated in the SLIC and fed to the SLICOFI-2x via the IT and IL pins. Transversal line current: ITRANS = (IR + IT)/2 Longitudinal line current: ILONG = (IR - IT)/2 where IR, IT are the loop currents on the Ring and Tip wires. Off-hook Detection Loop start signaling is the most common type of signaling. The subscriber loop is closed by the hook switch inside the subscriber equipment. * In Active mode, the resulting transversal loop current is sensed by the internal current sensor in the SLIC. The IT pin of the SLIC indicates the subscriber loop current to the SLICOFI-2x. External resistors (RIT1, RIT2, see Figure 97, Page 368) convert the current information to a voltage on the ITA (or ITB) pin. The analog information is first converted to a digital value. It is then filtered and processed further which effectively suppresses line disturbances. If the result exceeds a programmable threshold, an interrupt is generated to indicate off-hook detection. Data Sheet 59 2000-07-14 DuSLIC Preliminary Functional Description * In Sleep/Power Down mode (PDRx) a similar mechanism is used. In this mode, the internal current sensor of the SLIC is switched off to minimize power consumption. The loop current is therefore fed and sensed through 5 k resistors integrated in the SLIC (see Figure 9, Figure 10, Figure 11). The information is made available on the IT pin and interpreted by the SLICOFI-2x. - In Sleep mode, the analog information is fed to an analog comparator integrated in the SLICOFI-2x who directly indicates off-hook. - In Power Down mode, the SLICOFI-2x converts the analog information to a digital value. It is then filtered and processed further which effectively suppresses line disturbances. If the result exceeds a programmable threshold, an interrupt is generated to indicate off-hook detection. In applications using ground start signaling, DuSLIC can be set in the ground start mode. In this mode, the Tip wire is switched to high impedance mode. Ring ground detection is performed by the internal current sensor in the SLIC and transferred to the SLICOFI-2x via the IT pin. Ground Key Detection The scaled longitudinal current information is transferred from the SLIC via the IL pin and the external resistor RIL to SLICOFI-2x. This voltage is compared with a fixed threshold value. For the specified RIL (1.6 k, see application circuit Figure 97, Page 368) this threshold corresponds to 17 mA (positive and negative). After further post-processing, this information generates an interrupt (GNDK bit in the INTREG1 register) and ground key detection is indicated. The polarity of the longitudinal current is indicated by the GNKP bit in the INTREG1 register. Each change of the GNKP bit generates an interrupt. Both bits (GNDK, GNKP) can be masked in the MASK register. The post-processing is performed to guarantee ground key detection, even if longitudinal AC currents with frequencies of 162/3, 50 or 60 Hz are superimposed. The time delay between triggering the ground key function and registering the ground key interrupt will in most cases (f = 50 Hz, 60 Hz) be less than 40 ms. For longitudinal DC signals, the blocking period can be programmed by the DUP value in register IOCTL3. DC signals with less duration will not be detected. The DUP time is equivalent to the half of the cycle time for the lowest frequency for AC suppression (for values see Page 189). In Power Down mode, the SLIC's internal current sensors are switched off and ground key detection is disabled. Data Sheet 60 2000-07-14 DuSLIC Preliminary Functional Description 3.7 Metering There are two different metering methods: * Metering by sinusoidal bursts with either 12 or 16 kHz or * Polarity reversal of Tip and Ring. 3.7.1 Metering by 12/16 kHz Sinusoidal Bursts To satisfy worldwide application requirements, SLICOFI-2/-2S1) offers integrated metering injection of either 12 or 16 kHz signals with programmable amplitudes. SLICOFI-2/-2S also has an integrated adaptive TTX notch filter and can switch the TTX signal to the line in a smooth way. When switching the signal to the line, the switching noise is less than 1 mV. Figure 29 shows TTX bursts at certain points of the signal flow within SLICOFI-2/-2S. ZL/2 y + - A/D Transmit Path TTX Adaptive Filter x1 TTX Gen. SLIC-E/-E2 SLIC-S SLIC-P D/A IM Filter ZL/2 D/A SLICOFI-2/-2S + + Receive Path ezm14027.emf Figure 29 Teletax Injection and Metering The integrated, adaptive TTX notch filter guarantees an attenuation of > 40 dB. No external components for filtering TTX bursts are required. 1) Metering is not available with SLICOFI-2S2 Data Sheet 61 2000-07-14 DuSLIC Preliminary Functional Description 3.7.2 Metering by Polarity Reversal SLICOFI-2/-2S also supports metering by polarity reversal by changing the actual polarity of the voltages on the TIP/RING lines. Polarity reversal is activated by switching the REVPOL bit in register BCR1 to one or switching to the "Active with Metering" mode by the CIDD or CIOP command (see "Operating Modes for the DuSLIC Chip Set" on Page 78). 3.7.2.1 Soft Reversal Some applications require a smooth polarity reversal (soft reversal), as shown in Figure 30. Soft reversal helps to prevent negative effects like non-required ringing. Soft reversal is deactivated by the SOFT-DIS bit in register BCR2. SOFT-DIS = 1 SOFT-DIS = 0 Immediate reversal is performed (hard reversal) Soft reversal is performed. Transition time (time from START to SREND1, see Figure 30) is programmable by CRAM coefficients, default value 80 ms. VTIP/RING [V] 25 20 15 10 5 0 -5 -10 -15 -20 -25 START U SR-END1 U/8 SR-END2 = 1/16*SR-END1 t [ms] 0 50 1 00 150 2 00 250 ezm14038.wmf Figure 30 Soft Reversal (Example for Open Loop) START: The soft ramp starts by setting the REVPOL bit in register BCR1 to 1. The DC characteristic is switched off. SR-END1: At the soft reversal end one point, the DC characteristic is switched on again. Programmable by the DuSLICOS software, e.g. U/8. SR-END2: At the soft reversal end two point, the soft ramp is switched off. Programmable by the DuSLICOS software, e.g. 1/16 x SR-END1. From START to SR-END2 the READY bit in register INTREG2 is set to 0 (see register description in Chapter 6.3.1.2 for further information). Data Sheet 62 2000-07-14 DuSLIC Preliminary Functional Description 3.8 DuSLIC Enhanced Signal Processing Capabilities The signal processing capabilities described in this chapter are realized by an Enhanced Digital Signal Processor (EDSP) except for DTMF generation. Each function can be individually enabled or disabled for each DuSLIC channel. Therefore power consumption can be reduced according to the needs of the application. For the MIPS requirements of the different EDSP algorithms see Chapter 3.8.5. Figure 31 shows the AC signal path for DuSLIC with the ADCs and DACs, impedance matching loop, trans-hybrid filter, gain stages and the connection to the EDSP. VIN + ADC AX2 HPX2 LPX FRX AX1 HPX1 CMP XOUT IM1 IM2 UTD DAC TTXA IM3 TTXG TH LEC Switch DTMF UTD CID EDSP VOUT + DAC + + AR2 HPR2 LPR FRR AR1 HPR1 + EXP RIN TG DuSLIC_0005_ACsignal_path.emf Figure 31 DuSLIC AC Signal Path Figure 32 shows a closeup on the EDSP signal path shown in Figure 31 outlining signal names and SOP commands. Sx LPX FRX AX1 HPX1 LE C -O U T CMP XO U T LEC -EN U TD X-S UM UT DX -SR C UT DX -EN UTDX S L E C ,T IN S L E C ,T O U T G TH G L E C -X I LEC S S L E C ,R G G LE C -X 0 DT M F -S RC LE C-EN G G DTM F DT M F -E N DTMF G G L E C -R I + S SUM UT DR -SUM UT DR -EN UTDR CID LPR FRR SR R IN AR1 + EXP Switch position shown for control bit set to 0 TG DuSLIC_0006_EDSPsignal_path.emf Figure 32 Data Sheet DuSLIC EDSP Signal Path 63 2000-07-14 DuSLIC Preliminary Functional Description The enhanced Signal Processing Capabilities are available only for the DuSLIC-E/-E2/ -P versions, with an exception of DTMF generation. The DTMF generation is available for all DuSLIC versions. The functions of the EDSP are configured and controlled by POP register settings (see Chapter 6.2.3). 3.8.1 DTMF Generation and Detection1) Dual Tone Multi-Frequency (DTMF) is a signaling scheme using voice frequency tones to signal dialing information. A DTMF signal is the sum of two tones, one from a low group (697 - 941 Hz) and one from a high group (1209 - 1633 Hz), with each group containing four individual tones. This scheme allows 16 unique combinations. Ten of these codes represent the numbers from zero through nine on the telephone keypad, the remaining six codes (*, #, A, B, C, D) are reserved for special signaling. The buttons are arranged in a matrix, with the rows determining the low group tones, and the columns determining the high group tone for each button. In all SLICOFI-2x codec versions the 16 standard DTMF tone pairs can be generated independently in each channel via two integrated tone generators. Alternatively the frequency and the amplitude of the tone generators can be programmed individually via the digital interface. Each tone generator can be switched on and off. The generated DTMF tone signals meet the frequency variation tolerances specified in the ITU-T Q.23 recommendation. Both channels (A and B) of SLICOFI-21) have a powerful built-in DTMF decoder that will meet most national requirements. The receiver algorithm performance meets the quality criteria for central office/exchange applications. It complies with the requirements of ITUT Q.24, Bellcore GR-30-CORE (TR-NWT-000506) and Deutsche Telekom network (BAPT 223 ZV 5, Approval Specification of the Federal Office for Post and Telecommunications, Germany). The performance of the algorithm can be adapted according to the needs of the application via the digital interface (detection level, twist, bandwidth and center frequency of the notch filter). 1) DTMF Detection only available for DuSLIC-E/-E2/-P Data Sheet 64 2000-07-14 DuSLIC Preliminary Functional Description Table 7 shows the performance characteristics of the DTMF decoder algorithm: Table 7 1 2 3 4 5 6 7 Performance Characteristics of the DTMF Decoder Algorithm Value - 48 to 0 dBm0 - 5 dB of valid signal detection level < 8 dB < 8 dB < (1.5% + 4 Hz) and < 1.8% > 3% - 12 dB Notes Programmable - Programmable Programmable Related to center frequency Related to center frequency dB referenced to lowest amplitude tone - - - - - dB referenced to lowest amplitude tone - Characteristic Valid input signal detection level Input signal rejection level Positive twist accept Negative twist accept Frequency deviation accept Frequency deviation reject DTMF noise tolerance (could be the same as 14) Minimum tone accept duration Maximum tone reject duration Signaling velocity Maximum tone drop-out duration Interference rejection 30 Hz to 480 Hz for valid DTMF recognition Gaussian noise influence Signal level - 22 dBm0, SNR = 23 dB Pulse noise influence Impulse noise tape 201 according to Bellcore TR-TSY-000762 8 9 10 11 12 13 40 ms 25 ms 93 ms/digit 20 ms Level in frequency range 30 Hz ... 480 Hz level of DTMF frequency + 22 dB Error rate better than 1 in 10000 Error rate better than 14 in 10000 Minimum inter-digit pause duration 40 ms 14 15 measured with DTMF level - 22 dBm0 Impulse Noise - 10 dBm0 and - 12 dBm0 Data Sheet 65 2000-07-14 DuSLIC Preliminary In the event of pauses < 20 ms: * If the pause is followed by a tone pair with the same frequencies as before, this is interpreted as drop-out. * If the pause is followed by a tone pair with different frequencies and if all other conditions are valid, this is interpreted as two different numbers. DTMF decoders can be switched on or off individually to reduce power consumption. In normal operation, the decoder monitors the Tip and Ring wires via the ITAC pins (transmit path). Alternatively the decoder can be switched also in the receive path. On detecting a valid DTMF tone pair, SLICOFI-2 generates an interrupt via the appropriate INT pin and indicates a change of status. The DTMF code information is provided by a register which is read via the digital interface. The DTMF decoder also has excellent speech-rejection capabilities and complies with Bellcore TR-TSY-000763. The algorithm has been fully tested with the speech sample sequences in the Series-1 Digit Simulation Test Tapes for DTMF decoders from Bellcore. The characteristics of DTMF detection can be controlled by POP registers 30h to 39h. Functional Description 3.8.2 Caller ID Generation (only DuSLIC-E/-E2/-P) A generator to send calling line identification (Caller ID, CID) is integrated in the DuSLIC chip set. Caller ID is a generic name for the service provided by telephone utilities that supply information like the telephone number or the name of the calling party to the called subscriber at the start of a call. In call waiting, the Caller ID service supplies information about a second incoming caller to a subscriber already busy with a phone call. In typical Caller ID (CID) systems, the coded calling number information is sent from the central exchange to the called phone. This information can be shown on a display on the subscriber telephone set. In this case, the Caller ID information is usually displayed before the subscriber decides to answer the incoming call. If the line is connected to a computer, caller information can be used to search in databases and additional services can be offered. There are two methods used for sending CID information depending on the application and country-specific requirements: * Caller ID generation using DTMF signaling (see Chapter 3.8.1) * Caller ID generation using FSK DuSLIC contains DTMF generation units and FSK generation units which can be used for both channels simultaneously. The characteristics of the Caller ID generation circuitry can be controlled by POP registers 00h, 43h to 4Ah. Data Sheet 66 2000-07-14 DuSLIC Preliminary DuSLIC FSK Generation Different countries use different standards to send Caller ID information. The DuSLIC chip set is compatible with the widely used standards Bellcore GR-30-CORE, British Telecom (BT) SIN227, SIN242 or the UK Cable Communications Association (CCA) specification TW/P&E/312. Continuous phase binary frequency shift keying (FSK) modulation is used for coding which is compatible with BELL 202 (see Table 8) and ITU-T V.23, the most common standards. SLICOFI-2 can be easily adapted to these requirements by programming via the microcontroller interface. Coefficient sets are provided for the most common standards. Table 8 FSK Modulation Characteristics ITU-T V.23 1300 3 Hz 2100 3 Hz Bell 202 1200 3 Hz 2200 3 Hz FSK 1200 6 baud Serial binary asynchronous Functional Description Characteristic Mark (Logic 1) Space (Logic 0) Modulation Transmission rate Data format The Caller ID data of the calling party can be transferred via the microcontroller interface into a SLICOFI-2 buffer register. The SLICOFI-2 will start sending the FSK signal when the CIS-EN bit is set and the CID-data buffer is filled up to CIS-BRS plus 1 byte. The data transfer into the buffer register is handled by a SLICOFI-2 interrupt signal. Caller data is transferred from the buffer via the interface pins to the SLIC-E/-E2/-P and fed to the Tip and Ring wires. The Caller ID data bytes from CID-data buffer are sent LSB first. DuSLIC offers two different levels of framing: * A basic low-level framing mode All the data necessary to implement the FSK data stream - including channel seizure, mark sequence and framing for the data packet or checksum - has to be configured by firmware. SLICOFI-2 transmits the data stream in the same order in which the data is written to the buffer register. * A high level framing mode The number of channel seizure and mark bits can be programmed and are automatically sent by the DuSLIC. Only the data packet information has to be written into the CID buffer. Start and Stop bits are automatically inserted by the SLICOFI-2. The example below shows signaling of CID on-hook data transmission in accordance with Bellcore specifications. The Caller ID information applied on Tip and Ring is sent during the period between the first and second ring burst. Data Sheet 67 2000-07-14 DuSLIC Preliminary Functional Description Bellcore On-hook Caller ID Physical Layer Transmission First Ring Burst Channel Seizure Mark Data Packet A B C D E F Second Ring Burst G Parameter Message Parameter Header Parameter Body Message Type Message Length1 Parameter Type Parameter Length Parameter Byte More Parameter Bytes More Parameter Messages Checksum Message Header Message Message Body 1 Message length equals the number of bytes to follow in the message body, excluding the checksum. A: 0.2 - 3 second ring burst B: 0.5 - 1.5 seconds between first ring burst and start of data transmission C: 300 alternating mark and space bits D: 180 mark bits C + D + E = 2.9 to 3.7 seconds F: 200ms G: 1.8 - 3 second ring burst ezm14014.wmf Figure 33 Bellcore On-hook Caller ID Physical Layer Transmission Data Sheet 68 2000-07-14 DuSLIC Preliminary Functional Description 3.8.3 Line Echo Cancelling (LEC) (only DuSLIC-E/-E2/-P) The DuSLIC contains an adaptive line echo cancellation unit for the cancellation of near end echoes. With the adaptive balancing of the LEC unit the Transhybrid Loss can be improved up to a value of about 50 dB. The maximum echo cancellation time selectable is 8 ms. The line echo cancellation unit is especially useful in combination with the DTMF detection unit. In critical situations the performance of the DTMF detection can be improved. If 8 ms line echo cancellation length (LEC Length) is used, please take care about the MIPS requirements described in Chapter 3.8.5. The DuSLIC line echo canceller is compatible with applicable standards ITU-T G.165 and G.168. An echo cancellation delay time of up to 8 ms can be programmed. The LEC unit consists basically of an FIR filter, a shadow FIR filter, and a coefficient adaption mechanism between these two filters as shown in Figure 34. SLEC, TIN Adapt Coeff. SLEC, TOUT Shadow FIR Filter Copy Coeff. FIR Filter SLEC,R DuSLIC_0004_LECunit.emf Figure 34 Line Echo Cancelling Unit - Block Diagram The adaption process is controlled by the three parameters PowLECR (Power Detection Level Receive), DeltaPLEC (Delta Power) and DeltaQ (Delta Quality) ("POP Command" on Page 228). Adaptation takes place only if both of the following conditions hold: 1. SLEC,R > PowLECR 2. SLEC,R - SLEC,TIN > DeltaPLEC With the first condition, adaptation to small signals can be avoided. The second condition avoids adaptation during double talk. The parameter DeltaPLEC represents the echo loss provided by external circuitry. Data Sheet 69 2000-07-14 DuSLIC Preliminary Functional Description If the adaptation of the shadow filter is performed better than the adaption of the actual filter by a value of more than DeltaQ then the shadow filter coefficients will be copied to the actual filter. At the start of an adaption process the coefficients of the LEC unit can be reset to default initial values or set to the old coefficient values. The coefficients may also be frozen. 3.8.4 Universal Tone Detection (UTD) (only DuSLIC-E/-E2/-P) Each channel of the DuSLIC has two Universal Tone Detection units which can be used to detect special tones in the receive and transmit paths, especially fax or modem tones (e.g., see the modem startup sequence described in recommendation ITU-T V.8). This allows the use of modem-optimized filter for V.34 and V.90 connections. If the DuSLIC UTD detects that a modem connection is about to be established, the optimized filter coefficients for the modem connection can be downloaded before the modem connection is set up. With this mechanism implemented in the DuSLIC chip set, the optimum modem transmission rate can always be achieved. Figure 35 shows the functional block diagram of the UTD unit: P rogram m able B and -pa ss |x| Lim it + + Lim it LP S UTD |x| LP E v alu ation Log ic E Z M 140 61 Figure 35 UTD Functional Block Diagram Initially, the input signal is filtered by a programmable band-pass (center frequency fC and bandwidth fBW). Both the in-band signal (upper path) and the out-of-band signal (lower path) are determined, and the absolute value is calculated. Both signals are furthermore filtered by a limiter and a low-pass. All signal samples (absolute values) below a programmable limit LevN (Noise Level) are set to zero and all other signal samples are diminished by LevN. The purpose of this limiter is to increase noise robustness. After the limiter stages both signals are filtered by a fixed low-pass. The evaluation logic block determines whether a tone interval or silence interval is detected and an interrupt is generated for the receive or transmit path. Data Sheet 70 2000-07-14 DuSLIC Preliminary Functional Description The UTDR-OK respectively UTDX-OK bit (register INTREG3) will be set if both of the following conditions hold for a time span of at least RTIME without breaks longer than RBRKTime occurring: 1. The in-band signal exceeds a programmable level LevS. 2. The difference of the in-band and the out-of-band signal levels exceeds DeltaUTD. The UTDR-OK respectively UTDX-OK bit will be reset if at least one of these conditions is violated for a timespan of at least ETime during which the violation does not cease for at least EBRKTime. The times ETIME and EBRKTime help to reduce the effects of sporadic dropouts. If the bandwidth parameter is programmed to a negative value, the UTD unit can be used for the detection of silence intervals in the whole frequency range. The DuSLIC UTD unit is compatible with ITU-T G.164. The UTD is resistant to a modulation with 15 Hz sinusoidal signals and a phase reversal but is not able to detect the 15 Hz modulation and the phase reversal. 3.8.5 MIPS Requirements for EDSP Capabilities Table 9 shows the MIPS requirements for each algorithm using the EDSP: Table 9 MIPS Requirements Used MIPS 1.736*nCIS 1.208*nUTD 6.296*nDTMF (3.448 + 0.032*LEN)*nLEC 1.432 Conditions nCIS = 0...2 nUTD= 0...4, transmit and receive for two channels nDTMF= 0...2 nLEC= 0...2 LEN - see Page 239 - Algorithm / Device Caller ID Sender (CIS) Universal Tone Detection (UTD) DTMF Receiver Line Echo Canceller (LEC) Operating System The maximum capability of the EDSP is 32 MIPS. Example: * All devices enabled and LEC Length = 8 ms (LEN = 64): 33.32 MIPS total computing load exceeding the 32 MIPS limit! * All devices enabled and LEC Length = 4 ms (LEN = 32): 31.272 MIPS total computing load within the 32 MIPS limit. * 4 x UTD, 2 x DTMF Receiver and 2 x LEC (8 ms) enabled: 29.85 MIPS total computing load within the 32 MIPS limit. Data Sheet 71 2000-07-14 DuSLIC Preliminary Functional Description 3.9 Message Waiting Indication (only DuSLIC-E/-E2/-P) Message Waiting Indication (MWI) is usually performed using a glow lamp at the subscriber phone. Current does not flow through a glow lamp until the voltage reaches a threshold value above approximately 80 V. At this threshold, the neon gas in the lamp will start to glow. When the voltage is reduced, the current falls under a certain threshold and the lamp glow is extinguished. DuSLIC has high-voltage SLIC technology (170 V) which is able to activate the glow lamp without any external components. The hardware circuitry is shown in Figure 36 below. The figure shows a typical telephone circuit with the hook switch in the on-hook mode, together with the impedances for the on-hook (ZR) and off-hook (ZL) modes. RMW ZL ZR MW Lamp ZL ZR RMW AC Impedance Ringer Impedance Pre Resistor Message Waiting ezm14066.wmf Figure 36 MWI Circuitry with Glow Lamp The glow lamp circuit also requires a resistor (RMW) and a lamp (MW Lamp) built into the phone. When activated, the lamp must be able to either blink or remain on constantly. In non-DuSLIC solutions the telephone ringer may respond briefly if the signal slope is too steep, which is not desirable. DuSLIC's integrated ramp generator can be programmed to increase the voltage slowly, to ensure activating the lamp and not the ringer. Data Sheet 72 2000-07-14 DuSLIC Preliminary Functional Description To activate the Message Waiting function of DuSLIC the following steps should be performed: * * * * Activating Ring Pause mode by setting the M0-M2 bits Select Ring Offset RO2 by setting the bits in register LMCR3 Enable the ramp generator by setting bit RAMP-EN in register LMCR2 Switching between the Ring Offsets RO3 and RO2 in register LMCR3 will flash the lamp on and off (see Figure 37). The values for RO2 and RO3 have to be programmed in the CRAM to the according values before so that the lamp will flash on and off. VTR VHIGH RO 3 Lamp On Lamp Off VLOW Power Down State Ring Pause State t RO 2 RNG-OFFSET Bits 11 10 t ezm14067.emf Figure 37 Timing Diagram Data Sheet 73 2000-07-14 DuSLIC Preliminary Functional Description 3.10 Three-party Conferencing (only DuSLIC-E/-E2/-P) Each DuSLIC channel has a three-party conferencing facility implemented which consist of four PCM registers, adders and gain stages in the microprogram and the corresponding control registers (see Figure 38). This facility is available in PCM/C mode only. The PCM control registers PCMR1 through PCMR4 and PCMX1 through PCMX4 control the timeslot assignment and PCM highway selection, while the bits PCMX-EN, CONF-EN and CONFX-EN in the BCR3 register control the behavior of the conferencing facility and the PCM line drivers (see Figure 38). A programmable gain stage G is able to adjust the gain of the conferencing voice data (B, C, D, S) in a range of - 6 dB to + 3 dB to prevent an overload of the sum signals. PCM Highways Subscribers PCM channel X4 X1 X3 X2 D R4 B R2 C R3 A R1 G X2 = (R3 - R4)*G X3 = (R2 - R4)*G X4 = (R2 - R3)*G G + + G + 1 0 0 CONF_EN = 0 CONF_EN = 0 1 Subscriber S ezm14069.emf Figure 38 Conference Block for One DuSLIC Channel Note: G ... Gain Stage (Gain Factor) set in CRAM coefficients, X1 - X4 ... PCM transmit channels, R1 - R4 ... PCM receive channels, A, B, C, D, S ... examples for voice data on PCM channels X1 - X4, R1 - R4 Data Sheet 74 2000-07-14 DuSLIC Preliminary Functional Description 3.10.1 Table 10 Conferencing Modes Conference Modes Configuration Registers Receive Channels Transmit Channels R2 - - B B R3 - - C C R4 - - D D X1 X2 off off S off X3 off off X4 off off Subscriber S off A Mode PCM Off PCM Active External Conference External Conference + PCM Active Internal Conference PCMX CONF CONFX R1 -EN -EN -EN 0 1 0 1 0 0 0 0 0 0 1 1 - A - A off G (C+D) G (B+D) G (B+C) off S G (C+D) G (B+D) G (B+C) A 0 1 0 - B C - off G (C+S) G (B+S) off G (B+C) (see also "Control of the Active PCM Channels" on Page 142) * PCM Off After a reset, or in power down there is no communication via the PCM highways. Also when selecting new timeslots it is recommended to switch off the PCM line drivers by setting the control bits to zero. * PCM Active This is the normal operating mode without conferencing. Only the channels R1 and X1 are in use, and voice data are transferred from subscriber A to analog subscriber S and vice versa. * External Conference In this mode the SLICOFI-2 acts as a server for a three-party conference of subscribers B, C and D which may be controlled by any device connected to the PCM highways. The SLICOFI-2 channel itself can remain in power down mode to lower power consumption. * External Conference + PCM Active Like in External Conference mode any external three-party conference is supported. At the same time an internal phone call is active using the channels R1 and X1. * Internal Conference If the analog subscriber S is one of the conference partners, the internal conference mode will be selected. The partners (B, C) do not need any conference facility, since the SLICOFI-2 performs all required functions for them as well. Data Sheet 75 2000-07-14 DuSLIC Preliminary Functional Description 3.11 16 kHz Mode on PCM Highway In addition to the standard 8 kHz transmission PCM interface modes, there are also two 16 kHz modes for high data transmission performance. Table 11 shows the configuration of PCM channels for the different PCM interface modes. Table 11 Config. Bits PCM16K LIN PCM Mode 0 LIN Mode 0 1 A-HB A-LB B C D S-HB S-LB depends on conference mode DS1 - - DS2 - 0 A 4) Possible Modes in PCM/C Interface Mode1) Receive PCM Channels R1 R1L2) B R2 R3 C R4 D S X1 Transmit PCM Channels X1L3) - X2 X3 X4 depends on conference mode PCM16 Mode 1 1 1) 2) 3) 4) 0 1 DS1 - - DS2 - LIN16 Mode DS1- - HB DS1- DS2- DS2- DS1- - LB HB LB HB DS1- DS2- DS2LB HB LB see "Control of the Active PCM Channels" on Page 142 Time slot R1 + 1 Time slot X1 + 1 Empty cells in the table mark unused data in the PCM receive channels and switched-off line drivers in the PCM transmit channels The configuration bits PCM16K and LIN (in the BCR3 register) are used to select the following PCM interface modes: * PCM Mode Normal mode used for voice transmission via channels R1 and X1 (receive and transmit). The PCM input channels R2, R3 and R4 are always available for use in different conference configurations. The status of the PCM output channels depends on the conference mode configuration. Data Sheet 76 2000-07-14 DuSLIC Preliminary * LIN Mode Similar to the PCM mode, but for 16 bit linear data at 8 kHz sample rate via the PCM channels R1, R1L (receive) and X1, X1L (transmit). * PCM16 Mode Mode for higher data transmission rate of PCM encoded data using a 16 kHz sample rate (only in PCM/C Interface mode with the PCMX-EN bit in the BCR3 register set to one). In this mode the channels R1, R3 (X1, X3) are used to receive (transmit) two samples of data (DS1, DS2) in each 8 kHz frame. * LIN16 Mode Like the PCM16 mode for 16 kHz sample rate but for linear data. Channels R1 to R4 (X1 to X4) are used for receiving (transmitting) the high and low bytes of the two linear data samples DS1 and DS2. Functional Description Data Sheet 77 2000-07-14 DuSLIC Preliminary Operational Description 4 4.1 Table 12 Operational Description Operating Modes for the DuSLIC Chip Set Overview of DuSLIC Operating Modes SLIC Type CIDD/ CIOP1) Additional Bits used (Note 2)) SLICOFI-2x Mode SLIC-S/ SLIC-E/ SLIC-P M2 M1 M0 SLIC-S2 SLIC-E2 Sleep (SL) - PDRH PDRH PDH PDRH PDRR PDRH PDRR PDH 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 SLEEP-EN = 1 SLEEP-EN = 1, ACTR = 1 SLEEP-EN = 0 SLEEP-EN = 0, ACTR = 1 - Power Down PDRH Resistive (PDR) Power Down PDH High Impedance (PDH) Active High (ACTH) Active Low (ACTL) Active Ring (ACTR) Ringing (Ring) ACTH ACTL ACTR ACTH ACTL ACTR ACTH ACTL ACTR ACTR ROT ROR HIT 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 - ACTL = 1 ACTR = 1 - HIT = 1 HIR = 1 HIT = 1 HIT = 1, ACTR = 0 HIR = 0 HIR = 0, ACTR = 0 HIT = 1, ACTR = 1 HIR = 1, ACTR = 1 HIR = 1, HIT = 1 TTX-DIS to select Reverse Polarity or TTX Metering 2000-07-14 ACTR3) ACTR - - - - HIT HIR Active with HIT HIT Active with HIR HIR Active with Ring to Ground Active with Tip to Ground HIRT Active with Metering Data Sheet HIR ROT ROR - ACTx 4) 3) HIRT ACTx 4) HIRT ACTx 4) 1 78 DuSLIC Preliminary Table 12 SLICOFI-2x Mode Operational Description Overview of DuSLIC Operating Modes (cont'd) SLIC Type CIDD/ CIOP1) Additional Bits used (Note 2)) SLIC-S/ SLIC-E/ SLIC-P M2 M1 M0 SLIC-S2 SLIC-E2 Ground Start Ring Pause HIT ACTR 3) HIT HIT ACTR ACTR ROR ROT 1 1 0 0 0 0 0 0 1 - ACTR = 0 HIR = 1 HIT = 1 1) CIDD = Data Downstream Command/Indication Channel Byte (IOM-2 interface) CIOP = Command/Indication Operation For further information see "SLICOFI-2x Command Structure and Programming" on Page 163. if not otherwise stated in the table, the bits ACTL, ACTR, HIT, HIR have to be set to 0. only for SLIC-S ACTx means ACTH, ACTL or ACTR. 2) 3) 4) Sleep (SL) (only available with DuSLIC-E/-E2/-P) The SLICOFI-2 is able to go into a sleep mode with minimal power dissipation. In this mode off-hook detection is performed without any checks on spikes or glitches. The sleep mode can be used for either channel, but for the most effective power saving, both channels should be set to this mode. Note that this requires the following: * Due to the lack of persistence checking only non-noisy lines should use this feature. * If both channels are set to the sleep mode, waking up takes about 1.25 ms, since the on-chip PLL is also switched off. Therefore it is also possible to switch off all external clocks. In this time no programming or other functionality is available. The off-hook event is indicated either by setting the interrupt pin to active mode if the PCM/C interface mode is selected or by pulling down the DU pin if IOM-2 interface is used. * If only one channel is set to sleep mode, persistence checking and off-hook indication is performed as in any other mode, but the off-hook level is fixed to 2 mA at the subscriber line. No special wake-up is needed if only one channel is in sleep mode. A simple mode change ends the sleep mode. * A sleeping SLICOFI-2 is woken up if the CS pin is drawn to low level when the PCM/ C interface is used or the MX bit is set to zero when the IOM-2 interface is used. Note that no programming is possible until the SLICOFI-2 wakes up. In IOM-2 mode the identification request can be used as a wake-up signal since this command is independent of the internal clock. In the PCM/C mode it is recommended to set the CS to 0 for only one clock cycle. * After a wake up from Sleep mode the SLICOFI-2 enters the PDRH or PDRR mode. To re-enter the Sleep mode it is necessary to perform a mode change to any Active mode at least at one channel first. Data Sheet 79 2000-07-14 DuSLIC Preliminary Operational Description Power Down Resistive (PDRH for SLIC-E/-E2/-S/-S2 and PDRR for SLIC-P) The Power Down Resistive mode is the standard mode for none-active lines. Off-hook is detected by a current value fed to the DSP, compared with a programmable threshold, and filtered by a data upstream persistence checker. The power management SLIC-P can be switched to a Power Down Resistive High or a Power Down Resistive Ring mode. HIRT The line drivers in the SLIC-E/-E2/-P are shut down and no resistors are switched to the line. Off-hook detection is not possible. In HIRT mode the SLICOFI-2 is able to measure the input offset of the current sensors. Power Down High Impedance (PDH) In Power Down High Impedance mode, the SLIC is totally powered down. No off-hook sensing can be performed. This mode can be used for emergency shutdown of a line. Active High (ACTH) A regular call can be performed, voice and metering pulses can be transferred via the telephone line and the DC loop is operational in the Active High mode. Active Low (ACTL) The Active Low mode is similar to the Active High mode. The only difference is that the SLIC uses a lower battery voltage, VBATL (bit ACTL = 1). Active Ring (ACTR) The Active Ring mode is different for the SLIC-E/-E2 and the SLIC-P. The SLIC-E/-E2 uses the additional positive voltage VHR for extended feeding and the SLIC-P will switch to the negative battery voltage VBATR. Ringing If the SLICOFI-2x is switched to Ringing mode, the SLIC is switched to ACTR mode. With the SLIC-P connected to the SLICOFI-2, the Ring on Ring (ROR) mode allows unbalanced internal ringing on the Ring wire. The Tip wire is set to battery ground. The Ring signal will be superimposed by VBATR/2. The Ring on Tip (ROT) mode is the equivalent to the ROR mode. Active with HIT This is a testing mode where the Tip wire is set to a high impedance mode. It is used for special line testing. It is only available in an active mode of the SLICOFI-2x to enable all necessary test features. Data Sheet 80 2000-07-14 DuSLIC Preliminary Active with HIR HIR is similar to HIT but with the Ring wire set to high impedance. Active with Metering Any available active mode can be used for metering either with Reverse Polarity or with TTX Signals. Ground Start The Tip wire is set to high impedance in Ground Start mode. Any current drawn on the Ring wire leads to a signal on IT, indicating off-hook. Ring Pause The Ring burst is switched off in Ring Pause, but the SLIC remains in the specified mode and the off-hook recognition behaves like in ringing mode (Ring Trip). Operational Description Data Sheet 81 2000-07-14 DuSLIC Preliminary Operational Description 4.2 Table 13 Operating Modes for the DuSLIC-S/-S2 Chip Set DuSLIC-S/-S2 Operating Modes Tip/Ring Output Voltage SLICOFI-2S / SLIC-S / SLIC-S/-S2 System Active SLICOFI-2S2 SLIC-S2 Internal Functionality Circuits Mode Mode Supply Voltages (+/-) [VHI/VBI] PDH PDH Open/VBATH Open/VBATH None Off-hook detect as in active mode (DSP) Off-hook detect as in active mode (DSP) Voice and/or TTX transmission None Off-hook, DC transmit path Off-hook, DC transmit path Buffer, Sensor, DC + AC loop, TTX generator (optional) Buffer, Sensor, DC + AC loop, TTX generator (optional) Buffer, Sensor, DC + AC loop, TTXgenerator (optional) Buffer, Sensor, DC loop, Ring generator High Impedance Power Down PDRH Resistive VBGND/VBATH (via 5 k) - 1) PDRHL Open/VBATH VBGND/VBATH (via 5 k) Active Low (ACTL) ACTL VBGND/VBATL Tip: (VBATL + VAC + VDC)/2 Ring: (VBATL - VAC - VDC)/2 Active High (ACTH) ACTH VBGND/VBATH Voice and/or TTX transmission Tip: (VBATH + VAC + VDC)/2 Ring: (VBATH - VAC - VDC)/2 Active Ring (ACTR) ACTR VHR/VBATH Voice and/or TTX transmission Tip: (+ VBATH + VHR + VAC + VDC)/2 Ring: (+ VBATH + VHR - VAC - VDC)/2 Tip: (VBATH + Ringing (Ring) ACTR VHR/VBATH Balanced ring signal feed (incl. DC offset) 82 VHR + VDC)/2 Ring: (VBATH + VHR - VDC)/2 2000-07-14 Data Sheet DuSLIC Preliminary Table 13 DuSLIC-S/-S2 Operating Modes (cont'd) Tip/Ring Output Voltage Operational Description SLICOFI-2S / SLIC-S / SLIC-S/-S2 System Active SLICOFI-2S2 SLIC-S2 Internal Functionality Circuits Mode Mode Supply Voltages (+/-) [VHI/VBI] Ring Pause ACTR VHR/VBATH DC offset feed Buffer, Sensor, DC loop, Ramp generator Tip: (VBATH + VHR + VDC)/2 Ring: (VBATH + VHR - VDC)/2 Active with HIR HIR VHR/VBATH E.g. line test (Tip) Tip Buffer, Tip: (VBATH + VHR + VAC + Sensor, DC + AC loop VDC)/2 Ring: High impedance Ring Buffer, Ring: (VBATH + VHR - VAC - Sensor, DC + AC loop VDC)/2 Tip: High impedance Active with HIT HIT VHR/VBATH E.g. line test (Ring) 1) load ext. C for switching from PDRH to ACTH in on-hook mode VAC ... Tip/Ring AC Voltage VDC ... Tip/Ring DC Voltage Data Sheet 83 2000-07-14 DuSLIC Preliminary Operational Description 4.3 Table 14 Operating Modes for the DuSLIC-E/-E2 Chip Set DuSLIC-E/-E2 Operating Modes Tip/Ring Output Voltage SLICOFI-2 SLIC-E / SLIC-E/-E2 System Active Mode SLIC-E2 Internal Functionality Circuits Mode Supply Voltages (+/-) [VHI/VBI] PDH Sleep PDH PDRH Open/VBATH Open/VBATH None None High Impedance Off-hook Off-hook, detect via off- Analog hook comparator comparator Off-hook detect as in active mode (DSP) Off-hook detect as in active mode (DSP) Voice and/or TTX transmission Voice and/or TTX transmission Voice and/or TTX transmission Off-hook, DC transmit path VBGND/VBATH (via 5 k) Power Down Resistive - PDRH Open/VBATH VBGND/VBATH (via 5 k) PDRHL1) Open/VBATH Off-hook, DC transmit path VBGND/VBATH (via 5 k) Active Low ACTL (ACTL) VBGND/VBATL Buffer, Sensor, DC + AC loop, TTX generator (optional) Buffer, Sensor, DC + AC loop, TTX generator (optional) Buffer, Sensor, DC + AC loop, TTX generator (optional) Tip: (VBATL + VAC + VDC)/2 Ring: (VBATL - VAC - VDC)/2 Tip: (VBATH + VAC + VDC)/2 Ring: (VBATH - VAC - VDC)/2 Tip: (+ VBATH + VHR + VAC + VDC)/2 Ring: (+ VBATH + VHR - VAC - VDC)/2 Active High (ACTH) Active Ring (ACTR) ACTH VBGND/VBATH ACTR VHR/VBATH Data Sheet 84 2000-07-14 DuSLIC Preliminary Table 14 DuSLIC-E/-E2 Operating Modes (cont'd) Tip/Ring Output Voltage Operational Description SLICOFI-2 SLIC-E / SLIC-E/-E2 System Active Mode SLIC-E2 Internal Functionality Circuits Mode Supply Voltages (+/-) [VHI/VBI] Ringing (Ring) ACTR VHR/VBATH Balanced Buffer, Sensor, Ring signal DC loop, Ring feed (incl. DC generator offset) Tip: (VBATH + VHR + VDC)/2 Ring: (VBATH + VHR - VDC)/2 Ring Pause ACTR VHR/VBATH DC offset feed Buffer, Sensor, Tip: (VBATH + DC loop, ramp VHR + VDC)/2 Ring: (VBATH + generator VHR - VDC)/2 E.g. sensor offset calibration E.g. line test (Tip) Sensor, DC transmit path Tip-Buffer, Sensor, DC + AC loop High Impedance Tip: (VBATH + VHR + VAC + VDC)/2 Ring: High impedance Ring: (VBATH + VHR - VAC - VDC)/2 Tip: High impedance HIRT HIRT VHR/VBATH Active with HIR HIR VHR/VBATH Active with HIT HIT VHR/VBATH E.g. line test (Ring) Ring-Buffer, Sensor, DC + AC loop 1) load ext. C for switching from PDRH to ACTH in on-hook mode VAC ... Tip/Ring AC Voltage VDC ... Tip/Ring DC Voltage Data Sheet 85 2000-07-14 DuSLIC Preliminary Operational Description 4.4 Table 15 Operating Modes for the DuSLIC-P Chip Set DuSLIC P Operating Modes SLIC-P Internal Supply Voltages [VBI] System Functionality Active Circuits Tip/Ring Output Voltage SLICOFI-2 SLIC-P Mode Mode PDH Sleep PDH PDRH VBATR VBATH None None High impedance Off-hook detect Off-hook, via off-hook Analog comparator comparator Off-hook detect Off-hook, via off-hook Analog comparator comparator Off-hook detect Off-hook, DC as in active transmit path mode (DSP) Off-hook detect Off-hook, DC as in active transmit path mode (DSP) Off-hook detect Off-hook, as in active Analog mode (DSP) comparator Off-hook detect Off-hook, DC as in active transmit path mode (DSP) Voice and/or TTX transmission Voice and/or TTX transmission Buffer, Sensor, DC + AC loop, TTX generator (optional) Buffer, Sensor, DC + AC loop, TTX generator (optional) VBGND/VBATH (via 5 k) Sleep PDRR VBATR VBGND/VBATR (via 5 k) Power Down Resistive - PDRH VBATH VBGND/VBATH (via 5 k) PDRHL1) VBATH VBGND/VBATH (via 5 k) - PDRR VBATR VBGND/VBATR (via 5 k) - PDRRL2) VBATR VBGND/VBATR (via 5 k) Tip: (VBATL + VAC + VDC)/2 Ring: (VBATL - VAC - VDC)/2 Tip: (VBATH + VAC + VDC)/2 Ring: (VBATH - VAC - VDC)/2 Active Low ACTL (ACTL) VBATL Active High (ACTH) ACTH VBATH Data Sheet 86 2000-07-14 DuSLIC Preliminary Table 15 DuSLIC P Operating Modes (cont'd) SLIC-P Internal Supply Voltages [VBI] System Functionality Active Circuits Tip/Ring Output Voltage Operational Description SLICOFI-2 SLIC-P Mode Mode Active Ring (ACTR) Ringing (Ring) ACTR VBATR Voice and/or TTX transmission Balanced ring signal feed (incl. DC offset) Buffer, Sensor, DC + AC loop, TTX generator (optional) Buffer, Sensor, DC loop, ring generator Tip: (VBATR + VAC + VDC)/2 Ring: (VBATR - VAC - VDC)/2 Tip: (VBATR + VDC)/2 Ring: (VBATR - VDC)/2 Ring: (VBATR - VDC)/2 Tip: 0 V Tip: (VBATR + VDC)/2 Ring: 0 V Tip: (VBATR + VDC)/2 Ring: (VBATR - VDC)/2 High impedance Tip: (VBATR + VAC + VDC)/2 Ring: High impedance Ring: (VBATR - VAC - VDC)/2 Tip: High impedance ACTR VBATR Ringing (Ring) Ringing (Ring) Ring Pause ROR VBATR Ring signal on Buffer, Sensor, ring, Tip on DC loop, ring BGND generator Ring signal on Buffer, Sensor, ring, Tip on DC loop, ring BGND generator DC offset feed Buffer, Sensor, DC loop, ramp generator E.g. sensor offset calibration E.g. line test (Tip) Sensor, DC transmit path Tip-Buffer, Sensor, DC + AC loop Ring-Buffer, Sensor, DC + AC loop ROT VBATR ACTR, ROR, ROT HIRT VBATR HIRT VBATR Active with HIR HIR VBATR Active with HIT HIT VBATR E.g. line test (Ring) 1) 2) load ext. C for switching from PDRH to ACTH in on-hook mode load ext. C for switching from PDRR to ACTR in on-hook mode Data Sheet 87 2000-07-14 DuSLIC Preliminary Operational Description 4.5 4.5.1 Reset Mode and Reset Behavior Hardware and Power On Reset A reset of the DuSLIC is initiated by a power-on reset or a hardware reset by setting the signal at RESET input pin to low level for at least 4 s1). The reset input pin has a spike rejection which will safely suppress spikes with an duration of less than 1 s2). By setting the reset signal to low, the chip will be reset (see Figure 39): * * * * * all I/O pins deactivated all outputs inactive (e.g. DXA/DXB) internal PLL stopped internal clocks deactivated chip in power down high impedance (PDH) With the high going reset signal, the following actions take place: * Clock detection * PLL synchronization * Running the reset routine The internal reset routine will then initialize the whole chip to default condition as described in the SOP default register setting (see Chapter 6). To run through the internal reset routine it is necessary that all external clocks are supplied: * C/PCM mode: FSC, MCLK, PCLK * IOM-2 mode: FSC and DCL. Without valid and stable external clock signals, the DuSLIC will not finish the reset sequence properly. The internal reset routine requires 12 frames (125 s) to be finished (including PLL start up and clock synchronization) and is setting the default values given in Table 16. The first register access to the SLICOFI-2x may be done after the internal reset routine is finished. 1) 2) Maximum spike rejection time trej, max Minimum spike rejection time trej,min Data Sheet 88 2000-07-14 DuSLIC Preliminary Operational Description R E S E T sig na l t t re j (1 to 4 s) S L IC O F I-2 x in te rn a l re se t ro u tin e m in . 1 2 *1 25 s = 1.5 m s C h ip re se t: - all I/O p in s d e a ctiva te d - all o u tp u ts in ac tive (e .g . D X A /D X B ) - intern a l P LL sto p pe d - intern a l clo cks d e activa te d - ch ip in po w e r d o w n h igh im pe d a nc e (P D H ) F irs t a cc es s to S L IC O FI-2 x p os sible duslic_0016_reset_sequence.emf Figure 39 DuSLIC Reset Sequence Data Sheet 89 2000-07-14 DuSLIC Preliminary Operational Description 4.5.2 Software Reset When performing a software reset, the DuSLIC is running the reset routine and sets the default settings of the configuration registers. The software reset can be performed individually for each channel. Table 16 Default Values DC 20 34 1 10 100 25.4 62 23 0 50 75 2 8 mA V - k Limit for Constant Current Voltage of limit between Constant Current and Resistive Zone Additional gain with extended battery feeding Output Resistance in constant current zone Programmable resistance in resistive zone Ring frequency Ring amplitude at Ring/Tip wire Ring offset voltage RO1 Ring offset voltage RO2 Ring offset voltage RO3 Corner frequency of Ring low-pass filter Current threshold for Off-hook Detection in Power Down mode Off-hook Detection in Active with 2 mA hysteresis DC-Current threshold for Off-hook Detection in Ringing mode DC-Current threshold for Off-hook Detection in Message Waiting Current threshold Line-Supervision for ground start Voltage threshold at Ring/Tip wire for VRTLIM bit DC low-pass set to 1.2 and 20 Hz respectively Slope of the ramp generator Delay of Ring burst Soft-reversal threshold 1 (referred to the input of the ramp generator) IK1 VK1 KB RI RK12 fRING ARING RO1 RO2 RO3 Hz Vrms V V V Hz mA mA mA mA fRINGLP Off-hookPD Off-hookAct Off-hookRing 5 Off-hookMW Off-hookAC LineSup Ring/Tip ConstRamp delayRING SRend1 5 22 5 30 300 0 1/128 mArms Current threshold for AC Ring-Trip detection mA V Hz V/s ms - DC-Lowpass 1.2/20 Data Sheet 90 2000-07-14 DuSLIC Preliminary Table 16 SRend2 DUP DUP-IO Default Values (cont'd) 1/512 10 16.5 - ms ms Soft-reversal threshold 2 (referred to the input of the ramp generator) Data Upstream Persistence Counter is set to 10 ms Data Upstream Persistence Counter for I/O pins, VRTLIM and ICON bits (register INTREG1) is set to 16.5 ms Time for soft-reversal AC IM-Filter TH-Filter LX LR ATTX 900 0 7 2.5 16 940 1633 1004 Approximately 900 real input impedance Approximately BRD impedance for balanced network Relative level in transmit Relative level in receive Teletax generator amplitude at the resistance of 200 Teletax generator frequency Tone generator 1 (- 12 dBm) Tone generator 2 (- 10 dBm) AC level meter band pass Operational Description SR-Time 80 ms dB dB Vrms kHz Hz Hz Hz THBRD - fTTX TG1 TG2 AC-LM-BP Data Sheet 91 2000-07-14 DuSLIC Preliminary Operational Description 4.6 Interrupt Handling SLICOFI-2x provides much interrupt data for the host system. Interrupt handling is performed by the on chip microprogram which handles the interrupts in a fixed 2 kHz (500 s) frame. Therefore, some delays up to 500 s can occur in the reactions of SLICOFI-2x depending on when the host reads the interrupt registers. Independent of the selected interface mode (PCM/C or IOM-2), the general behavior of the interrupt is as follows: * Any change (at some bits only transitions from 0 to 1) in one of the four interrupt registers leads to an interrupt. The interrupt channel bit INT-CH in INTREG1 is set to one and all interrupt registers of one DuSLIC channel are locked at the end of the interrupt procedure (500 s period). Therefore all changes within one 2 kHz frame are stored in the interrupt registers. The lock remains until the interrupt channel bit is cleared (Release Interrupt by reading all four interrupt registers INTREG1 to INTREG4 with one command). * In IOM-2 interface mode, the interrupt channel bits are fed to the CIDU channel (see IOM-CIDU). In PCM mode, the INT pin is set to active (low). * The interrupt is released (INT-CH bit reset to zero) by reading all four interrupt registers by one command. Reading the interrupt registers one by one using a series of commands does not release the interrupt even if all four registers are read. * A hardware or power-on reset of the chip clears all pending interrupts and resets the INT line to inactive (PCM/C mode) or resets the INT-CH bit in CIDU (IOM-2 mode). The behavior after a software reset of both channels is similar, the interrupt signal switches to non-active within 500 s. A software reset of one DuSLIC channel deactivates the interrupt signal if there is no active interrupt on the other DuSLIC channel. If the reset line is deactivated, a reset interrupt is generated for each channel (bit RSTAT in register INTREG2). Data Sheet 92 2000-07-14 DuSLIC Preliminary Operational Description 4.7 Operating Modes and Power Management In many applications, the power dissipated on the line card is a critical parameter. In larger systems, the mean power value (taking into account traffic statistics and line length distribution) determines cooling requirements. Particularly in remotely fed systems, the maximum power for a line must not exceed a given limit. 4.7.1 Introduction Generally, system power dissipation is determined mainly by the high-voltage part. The most effective power-saving method is to limit SLIC functionality and reduce supply voltage in line with requirements. This is achieved using different operating modes. The three main modes - Power Down, Active and Ringing - correspond to the main system states: on-hook, signal transmission (voice and/or TTX) and ring signal feed. For power critical applications the Sleep mode can be used for even lower power consumption than in Power Down mode. - Power Down Off-hook detection is the only function available. It is realized by 5 k resistors applied by the SLIC from Tip to VBGND and Ring to VBAT, respectively. A simple sensing circuit supervises the DC current through these resistors (zero in on-hook and non-zero in offhook state). This scaled transversal line current is transferred to the IT pin and compared with a programmable current threshold in the SLICOFI-2x. Only the DC loop in the SLICOFI-2x is active. In Sleep mode, all functions of the SLICOFI-2x are switched off except for off-hook detection which is still available via an analog comparator. Both AC and DC loops are inactive. To achieve the lowest power consumption of the DuSLIC chip set, the clock cycles fed to the MCLK and PCLK pins have to be shut off. For changing into another state the DuSLIC has to be woken up according to the procedure described in Chapter 4.1. - Active Both AC and DC loops are operative. The SLIC provides low-impedance voltage feed to the line. The SLIC senses, scales and separates transversal (metallic) and longitudinal line currents. The voltages at Tip and Ring are always symmetrical with reference to half the battery voltage (no ground reference!). An integrated switch makes it possible to choose between two (SLIC-S/-S2, SLIC-E/-E2) or even three (SLIC-P) different battery voltages. With these voltages selected according to certain loop lengths, power optimized solutions can be achieved. Data Sheet 93 2000-07-14 DuSLIC Preliminary - Ringing For SLIC-E/-E2 and SLIC-S, an auxiliary positive supply voltage VHR is used to give a total supply range of up to 150 V. For SLIC-P the whole supply range is provided by VBATR. The low-impedance line feed (RSTAB (2x30 )=+ RFUSE (2x20 )= + appr. 1 101 output impedance) with a balanced sinusoidal Ring signal of up to 85 Vrms, plus a DC offset of 20 V, is sufficient to supply very long lines at any kind of ringer load and to reliable detect Ring trip. Unbalanced ringing is supported by applying the Ring signal to only one line, while Ground is applied to the other line. For an overview of all DuSLIC operating modes see Table 13 for PEB 4264/-2, Table 14 for PEB 4265/-2 and Table 15 for PEB 4266. Operational Description 4.7.2 Power Dissipation of the SLICOFI-2x For an optimized power consumption unused EDSP functions have to be switched off. Typical power dissipation values for different operating modes of the SLICOFI-2x are shown in Chapter 7.4.3 and Chapter 7.4.4. Data Sheet 94 2000-07-14 DuSLIC Preliminary Operational Description 4.7.3 Power Dissipation of the SLIC The SLIC power dissipation mainly comes from internal bias currents and the buffers output stage (to a lesser extent from the sensor) where additional power is dissipated whenever current is fed to the line. 4.7.3.1 Power Down Modes In Power Down modes, the internal bias currents are reduced to a minimum and no current is fed to the line (see Table 19, Table 21 and Table 23). Even with active offhook detection, the power dissipation of 5 mW (6 mW for SLIC-P) is negligible. Note that this is the dominant factor for a low mean power value in large systems, as a large percentage of lines are always inactive. 4.7.3.2 Active Mode In Active mode, the selected battery voltage VBATx1) has the strongest influence on power dissipation. The power dissipation in the output stage PO (see Chapter 7.1.5 and Chapter 7.2.5) is determined by the difference between VBATx and the Tip-Ring voltage VTIP/RING. At constant DC line current ITrans, the shortest lines (lowest RL) cause lowest VTIP/RING, and accordingly exhibit the highest on-chip power dissipation. However, the minimum battery voltage required is determined by the longest line and therefore the maximum line resistance RL,MAX and in addition RPROT and RSTAB. VBATx,min = ITrans x (RL,MAX + RPROT + RSTAB) + VAC,P + VDROP VAC,P ..................... Peak value of AC signal VDROP ................... Sum of voltage drop in the SLIC buffers (Table 17) Table 17 Mode ACTL ACTH ACTR ROR, ROT HIR, HIT Typical Buffer Voltage Drops (Sum) for ITRANS (IT or IR) Total Voltage drop VDROP [V] SLIC-E/-E2/-S/-S2 SLIC-P ITRANS x 96 ITRANS x 100 (ITRANS x 100 ) + 1 V - (IT or R x 48 ) + 1 V ITRANS x 88 ITRANS x 100 ITRANS x 92 ITRANS x 92 IT or R x 52 1) VBATx = VBATL, VBATH or VBATR 95 2000-07-14 Data Sheet DuSLIC Preliminary Operational Description The most efficient way to reduce short-loop power dissipation is to use a lower battery supply voltage (VBATL) whenever line resistance is small enough. This method is supported on the SLIC-E/-E2 by integrating a battery switch. With a standard battery voltage of - 48 V, long lines up to 2 k=can be driven at 20 mA line current. The SLIC-P PEB 4266 "low-power" version even allows three battery voltages (typically the most negative one, e.g. - 48 V, is used in Active mode (On-hook) and Power Down mode). DuSLIC contains two mechanism which can be used as indication for the battery switching: 1. A threshold for the voltage at Tip/Ring can be set for generating an interrupt 2. The change between constant current and resistive feeding will generate an interrupt 4.7.3.3 SLIC Power Consumption Calculation in Active Mode A scheme for a typical calculation is shown in Figure 40. Circuit Diagram ILINE RPHONE VSUBSCRIBER VPHONE VTR SLIC RLINE RPROT + RSTAB OFF-HOOK ezm14049.emf Figure 40 Circuit Diagram for Power Consumption RPROT = 40 , RSTAB = 60 , RPHONE = 150 , VPHONE = 7 V, ILINE = 20 mA Conditions: VVoice peak = 2 V, IVoice peak = 2 mA, VTTX,rms (see example below) Typical Power Consumption Calculation with SLIC-E/-E2 Assuming a typical application where the following battery voltages are used: VDD = 5 V, VBATL = - 43 V, VBATH = - 62 V, VHR = 80 V and line feeding is guaranteed up to RL = 1900 . For longer lines (RL > 1900 ) the extended battery feeding option can be used (Mode ACTR). Requirement for TTX: VTTX = 2.5 Vrms at a load of 200 . Data Sheet 96 2000-07-14 DuSLIC Preliminary Operational Description Table 18 shows line currents and output voltages for different operating modes. Table 18 Line Feed Conditions for Power Calculation of SLIC-E/-E2 Line Currents Output Voltages - Operating Mode PDRH, PDRHL ACTL ACTH ACTR extended battery feeding at higher loop length (RL > 1900 ) ITRANS = 0 mA ITRANS = 20 mA ITRANS = 20 mA ITRANS = 20 mA VTIP/RING = 32 V VTIP/RING = 50 V VTIP/RING = 130 V With the line feed conditions given in the above table the total power consumption PTOT and its shares at different operating modes are shown in Table 19. The output voltage at Tip and Ring is calculated for the longest line (RL = 1900 in ACTH, RL = 996 in ACTL). Table 19 Operating Mode PDH PDRH ACTL ACTH ACTR 1) SLIC-E/-E2 Typical Total Power Dissipation PQ1) [mW] 4.6 5.6 127 222 379 PI [mW] 0 0 51.3 72.2 96.2 PG [mW] 0 0 27.1 32.8 412 PO [mW] 0 0 220 240 240 PTOT [mW] 4.6 5.6 425.4 567 1127.3 The formulas for the calculation of the power shares PQ, PI, PG and PO can be found in Chapter 7.2.5. Figure 41 shows the total power dissipation PTOT of the SLIC-E/-E2 in Active Mode (ACTH and ACTL) with switched battery voltage (VBATH, VBATL) as a function of RLine. The power dissipation in the SLIC is strongly reduced for short lines. Data Sheet 97 2000-07-14 DuSLIC Preliminary Operational Description 1000 900 800 700 PTOT [mW] 600 500 400 300 200 100 0 10 0 19 0 27 9 36 9 45 8 54 8 63 8 72 7 81 7 90 6 99 6 10 86 11 77 12 67 13 58 14 48 15 38 16 29 17 19 18 10 19 00 RLine [ ] duslic_0002_powerdiss.emf Figure 41 SLIC-E/-E2 Power Dissipation with Switched Battery Voltage Typical Power Consumption Calculation with SLIC-P (Internal Ringing) Assuming a typical application where the following battery voltages are used: VDD = 5 V, VBATL = - 36 V, VBATH = - 48 V, VBATR = - 108 V and line feeding is guaranteed up to RL = 1200 . Requirement for TTX: VTTX = 2.5 Vrms at a load of 200 . Table 20 shows line currents and output voltages for different operating modes. Table 20 Line Feed Conditions for Power Calculation for SLIC-P Line Currents Output Voltages - Operating Mode PDRH, PDRHL ACTL ACTH ACTR ITRANS = 0 mA ITRANS = 20 mA ITRANS = 20 mA ITRANS = 20 mA VTIP/RING = 25.2 V VTIP/RING = 36 V VTIP/RING = 96 V With the line feed conditions given in the above table, the total power consumption PTOT and its shares at different operating modes are shown in Table 21. The output voltage at Tip and Ring is calculated for the longest line (RL = 1200 in ACTH, RL = 662 in ACTL). . Data Sheet 98 2000-07-14 DuSLIC Preliminary Table 21 SLIC-P PEB 4266 Power Dissipation Operational Description PQ Operating Mode PDH PDRH PDRR ACTL ACTH [mW] 8.8 7.7 10.4 81.7 135 PI [mW] 0 0 0 43.6 56.8 123 0 PG [mW] 0 0 0 15.3 0 112 102 PO [mW] 0 0 0 216 240 240 0 PTOT [mW] 8.8 7.7 10.4 357 432 857 365 ACTR (Extended 383 Battery Feeding) ROR, ROT (Ring Pause) 263 Figure 43 shows the total power dissipation PTOT of the SLIC-P in Active mode (ACTH and ACTL) with switched battery voltage (VBATH, VBATL) as a function of RLine. 700 600 500 P TOT [mW] 400 300 200 100 0 10 0 15 6 21 2 26 9 32 5 38 1 43 7 49 3 55 0 60 6 66 2 71 6 77 0 82 3 87 7 93 1 98 5 10 39 10 92 11 46 12 00 RLine [ ] duslic_0001_powerdiss.emf Figure 42 SLIC-P Power Dissipation (Switched Battery Voltage, Long Loops) Data Sheet 99 2000-07-14 DuSLIC Preliminary Operational Description Typical Power Consumption Calculation with SLIC-P (External Ringing) Assuming a typical application where the following battery voltages are used: VDD = 5 V, VBATL = - 25 V, VBATH = - 31 V, VBATR = - 48 V and line feeding is guaranteed up to RL = 600 . Requirement for TTX: VTTX,rms = 0.7 V. This is a typical lowest-power application, where VBATR is used just in the On-hook state and VBATH and VBATL is used in the active modes with battery switching. Table 22 shows line currents and output voltages for different operating modes. Table 22 Line Feed Conditions for Power Calculation for SLIC-P Line Currents Output Voltages - Operating Mode PDRH, PDRHL ACTL ACTH ACTR ITRANS = 0 mA ITRANS = 20 mA ITRANS = 20 mA ITRANS = 20 mA VTIP/RING = 19.2 V VTIP/RING = 24 V VTIP/RING = 41 V With the line feed conditions given in the above table, the total power consumption PTOT and its shares at different operating modes are shown in Table 23. The output voltage at Tip and Ring is calculated for the longest line (RL = 600 in ACTH, RL = 358 in ACTL). Table 23 Operating Mode PDH PDRH PDRR ACTL ACTH ACTR SLIC-P PEB 4266 Power Dissipation PQ [mW] 4.3 4.5 5.0 57.8 88.7 172.5 PI [mW] 0 0 0 31.5 38.1 56.8 PG [mW] 0 0 0 1.0 -28.6 -87.2 PO [mW] 0 0 0 116 140 140 PTOT [mW] 4.3 4.5 5.0 206 238 282 Figure 43 shows the total power dissipation PTOT of the SLIC-P in Active mode (ACTH and ACTL) with switched battery voltage (VBATH, VBATL) as a function of RLine (Lowest Power Applications). Data Sheet 100 2000-07-14 DuSLIC Preliminary 350 300 250 P TOT [mW] 200 150 100 50 0 Operational Description 0 6 2 7 3 9 5 1 6 2 8 2 5 6 1 9 3 7 2 6 57 10 12 15 17 20 22 25 28 30 33 35 38 45 40 43 47 50 52 55 RLine [ ] duslic_0003_powerdiss.emf Figure 43 SLIC-P Power Dissipation (Switched Battery Voltage, Short Loops) 4.7.3.4 Ringing Modes Internal Balanced Ringing (SLIC-E/-E2 and SLIC-P) The SLIC-E/-E2/-P internal balanced ringing facility requires a higher supply voltage (auxiliary voltage VHR). The highest share of the total power is dissipated in the output stage of the SLIC-E/-E2/-P. The output stage power dissipation PO (see Table 24, Table 25) depends on the ring amplitude (VRNG,PEAK), the equivalent ringer load (RRNG and CRNG), the ring frequency (via cosL) and the line length (RL). The minimum auxiliary voltage VHR necessary for a required ring amplitude can be calculated using: VHR - VBATH = VRNG,PEAK + VRNG,DC + VDROP = VRNG,RMS x crest factor + VRNG,DC + VDROP The crest factor is defined as peak value divided by RMS value (here always 1.41 because sinusoidal ringing is assumed). VRNG,DC Superimposed DC voltage for Ring trip detection (10 to 20 V) VDROP Sum of voltage drops in SLIC buffers (Table 17) VRNG,PEAK Peak ring voltage at Tip/Ring Data Sheet 101 2000-07-14 60 0 DuSLIC Preliminary Operational Description The strong influence of the ringer load impedance ZLD and the number of ringers is demonstrated by the formula for the current sensor power dissipation (PI + PO) in Table 24 and Table 25. The ringer load impedance ZLD can be calculated as follows: ZLD = |ZLD| x e jLD = RL + RRNG + 1/jCRNG with ZLD Load impedance RRNG Ringer resistance CRNG Ringer capacitance RL Line resistance Internal Unbalanced Ringing with SLIC-P The ring signal is present just on one line (modes ROR, ROT), while the other line is connected to a potential of GND. The minimum battery voltage VBATR necessary for a required ring amplitude can be calculated using: - VBATR - VDROP = 2 x VRNG, PEAK = 2 x VRNG,RMS x crest factor External Ringing (SLIC-E/-E2 and SLIC-P) When an external ring generator and ring relays are used, the SLIC can be switched to Power Down mode. The "low-power" SLIC-P is optimized for extremely power-sensitive applications (see Table 23). SLIC-P has three different battery voltages. VBATR can be used for on-hook, while VBATH and VBATL are normally used for off-hook mode. Data Sheet 102 2000-07-14 DuSLIC Preliminary Operational Description 4.7.3.5 SLIC Power Consumption Calculation in Ringing Mode The average power consumption for a ringing cadence of 1 second on and 4 seconds off is given by PTOT, average = k x PTOT, Ringing + (1 - k) x PTOT, RingPause with k = 0.20 The typical circuit for ringing is shown in Figure 44. Circuit Diagram for Ringing i RRNG RLINE RPROT + RSTAB ZRNG SLIC CRNG vRNG vTR ON HOOK ezm35004.emf Figure 44 Circuit Diagram for Ringing Data Sheet 103 2000-07-14 DuSLIC Preliminary Operational Description - Power Consumption Calculation for SLIC-E/-E2 in Balanced Ringing Mode With the example of the above calculation for SLIC-E/-E2 (see Chapter 4.7.3.3) and a typical ringer load. RRNG = 450 ,= CRNG = 3.4 F, required ringing voltage VRNG = 58 Vrms and ringing frequency fRNG = 20 Hz. DC Offset Voltage for ring trip detection VDC = 20 V. Table 24 shows the power calculation for the total power dissipation PTOT of the SLIC-E/ -E2 in balanced ringing mode consisting of the quiescent power dissipation PQ, the current sensor power dissipation PI, the gain stage power dissipation PG and the output stage power dissipation PO. Table 24 SLIC-E/-E2 Balanced Ringing Power Dissipation (typical) 710 mW 2481 mW1) 390 mW 118 mW 320 mW PTOT, RingPause = PQ + PI + PG + PO (ITrans = 0 mA) PTOT, Ringing = PQ + PI + PG + PO PQ = VDD x IDD + IVBATHI x IBATH + IVBATLI x IBATL + VHR x IHR PI = 0.015 x ITrans,rms x VHR + 0.055 x ITrans,rms x |VBATH| + 0.04 x ITrans,rms x VDD with ITrans,rms = VTIP/RING, rms/|ZLD| PG = (VHR + |VBATH|) x (SQRT((VHR + VBATH + VDC-offset)2 + (VTIP/ 2 2 2 RING )/2) -IVHR + VBATHI)/60k + (VHR2 - 322 + VBATH - 48 ) x (1/60k + 1/216k) PO = (VHR + IVBATHI) x ITrans,rms x 2 x SQRT(2)/ - VTIP/RING, rms x ITrans,rms x cos(Load) 1) 1653 mW Values for VDD = 5 V, VBATL = - 43 V, VBATH = - 62 V, VHR = 80 V, TJ = 25 C Data Sheet 104 2000-07-14 DuSLIC Preliminary Operational Description - Power Consumption Calculation for SLIC-P in Balanced Ringing Mode With the example of the above calculation with RL = 1200 line length for SLIC-P (see Chapter 4.7.3.3) when the internal ringing feature will be used. Typical ringer load: RRNG = 1000 ,= CRNG = 3.7 F. Required ringing voltage VRNGr = 45 Vrms and ringing frequency fRNG = 20 Hz. DC Offset voltage for ring trip detection VDC = 20 V. Table 25 shows the power calculation for the total power dissipation PTOT of the SLIC-P in balanced ringing mode consisting of the quiescent power dissipation PQ, the current sensor power dissipation PI, the gain stage power dissipation PG and the output stage power dissipation PO. Table 25 SLIC-P Balanced Ringing Power Dissipation (typical) 482 mW 1618 mW1) 370 mW 117 mW 112 mW 1019 mW PTOT, RingPause = PQ + PI + PG + PO (ITrans = 0 mA) PTOT, Ringing = PQ + PI + PG + PO PQ = VDD x IDD + IVBATRI x IBATR + IVBATHI x IBATH + IVBATLI x IBATL PI = 0.055 x ITrans,rms x IVBATRI + 0.04 x ITrans,rms x VDD with ITrans,rms = VTIP/RING, rms/IZLDI PG = (VBATR2 - 802) x (1/60k + 1/216k) PO = IVBATRI x ITrans,rms x 2 x SQRT(2)/ - VTIP/RING, rms x ITrans,rms x cos(Load) 1) Values for VDD = 5 V, VBATL = - 36 V, VBATH = - 48 V, VBATR = - 108 V, TJ = 25 C Data Sheet 105 2000-07-14 DuSLIC Preliminary Operational Description - Power Consumption Calculation for SLIC-P in Unbalanced Ringing Mode A similar power calculation is valid for internal unbalanced ringing mode, which is only available for the SLIC-P. With the following example: VDD = 5 V, VBATL = - 30 V, VBATH = - 36 V, VBATR = - 150 V and line feeding is guaran-teed up to 600 . Typical ringer load RRNG = 1000 ,= CRNG = 3.7 F, required ringing voltage VRNG = 45 Vrms and ringing frequency fRNG = 20 Hz. Table 26 shows the power calculation for the total power dissipation PTOT of the SLIC-P in unbalanced ringing mode. Table 26 SLIC-P Unbalanced Ringing Power Dissipation (typical) 644 mW 2756 mW1) 349 mW 160 mW 295 mW 1952 mW PTOT, RingPause = PQ + PI + PG + PO (ITrans = 0 mA) PTOT, Ringing = PQ + PI + PG + PO PQ = VDD x IDD + IVBATRI x IBATR + IVBATHI x IBATH + IVBATLI x IBATL PI = 0.055 x ITrans,rms x IVBATRI + 0.04 x ITrans,rms x VDD with ITrans,rms = VTIP/RING, rms/IZLDI PG = (0.5 x VTIP/RING2 - (VBATR/2)2)/60k + (VBATR2 - 802) x (1/60k + 1/216k) PO = IVBATRI x ITrans,rms x 2 x SQRT(2)/ - VTIP/RING, rms x ITrans,rms x cos(Load) 1) Values for VDD = 5 V, VBATL = - 30 V, VBATH = - 36 V, VBATR = - 150 V, TJ = 25 C Data Sheet 106 2000-07-14 DuSLIC Preliminary Operational Description 4.8 4.8.1 Integrated Test and Diagnosis Functions (ITDF)1) Introduction Subscriber loops are affected by a variety of failures which have to be monitored. Monitoring the loop supposes the access to the subscriber loop and to have test equipment in place which are capable to perform certain measurements. The measurements or tests involve resistance, capacitance, leakage, and measurements of interfering currents and voltages. 4.8.1.1 Conventional Line Testing Conventional linecards in Central Office (CO) applications usually need two test relays per channel to access the subscriber loop with the appropriate test equipment. One relay (test-out) connects the actual test unit to the local loop. All required line tests can be accomplished that way. The second relay (test-in) separates the local loop from the SLIC-E/-E2/-P and connects a termination impedance to it. Hence, by sending a tone signal the entire loop can be checked, including the SLICOFI-2 and SLIC-E/-E2/-P. 4.8.1.2 DuSLIC Line Testing The DuSLIC with its Integrated Test and Diagnosis Functions (ITDF) is capable to perform all tests necessary to monitor the local loop without an external test unit and test relays. The fact, that measurements can be accomplished much faster as with conventional test capabilities makes it even more a compelling argument for the DuSLIC. With the DuSLIC both channels are able to perform line tests concurrently, which also has a tremendous impact on the test time. All in all, the DuSLIC increases the quality of service and reduces the costs in various applications. 1) only available with DuSLIC-E/-E2/-P Data Sheet 107 2000-07-14 DuSLIC Preliminary Operational Description 4.8.2 Diagnostics The two-channel chip set has a set of signal generators and features implemented to accomplish a variety of diagnostic functions. The SLICOFI-2 device generates all test signals, processes the information that comes back from the SLIC-E/-E2/-P and provides the data to a higher level master device, e.g. a microprocessor. All the tests can be initiated by the micropocessor and the results can be read back very easily. The Integrated Test and Diagnosis Functions (ITDF) might prevent any problem which affects service caused by the subscriber line or line equipment before the customer complains. IDTF has been integrated to facilitate the monitoring of the subscriber loop. 4.8.2.1 * * * * * * * * * * * * * * * Line Test Capabilities The line test comprises the following functions: Loop resistance Leakage current Tip/Ring Leakage current Tip/GND Leakage current Ring/GND Ringer capacitance Line capacitance Line capacitance Tip/GND Line capacitance Ring/GND Foreign voltage measurement Tip/GND Foreign voltage measurement Ring/GND Foreign voltage measurement Tip/Ring Measurement of ringing voltage Measurement of line feed current Measurement of supply voltage VDD of the SLICOFI-2 Measurement of transversal- and longitudinal current Two main transfer paths (levelmeter) are implemented to accomplish all the different line measurement functions (refer to Figure 45). 4.8.2.2 Integrated Signal Sources The signal sources available on the DuSLIC chip set are: * Constant DC voltage (three programmable ringing DC offset voltages) Please refer to the CRAM coefficient set and register LMCR3 (bits RNGOFFSET[1:0]) on Page 206. * 2 independent tone generators TG1 and TG2: Please refer to the CRAM coefficient set and register DSCR (bits PTG, TG2-EN, TG1EN) on Page 200. Data Sheet 108 2000-07-14 DuSLIC Preliminary Operational Description * TTX metering signal generator (12/16 kHz) Please refer to the CRAM coefficient set and register BCR2 (bits TTX-DIS, TTX-12k) on Page 192. * Ramp generator (used for capacitance measurements) Please refer to the CRAM coefficient set and register LMCR2 (bit RAMP-EN) on Page 204. * Ring generator (5 Hz - 300 Hz) Please refer to the CRAM coefficient Table 51 "CRAM Coefficients" on Page 226. Figure 45 shows the entire levelmeter block for AC and DC: ITAC AC PREFI A/D SIGMA DELTA 4 MHz VOICE PATH DECIMATION a AC LEVELMETER BANDPASS NOTCH FILTER CRAM LMCR2: LM-NOTCH LM-FILT RECTIFIER SHIFT FACTOR KINTAC CRAM INTEGRATOR 1x16ms ... 16x16ms + PCM IN: Receive Data from PCM or IOM-2 Interface MUX b LMCR2: LM-SEL[3:0] LMCR3: LM-ITIME[3:0] OFR1/2 IT IL IO3 IO4 IO4 - IO3 Offset VDD OFFSET REGISTER A/D MUX DC PREFI 1 Bit SIGMA DELTA 1 MHz DECIMATION 2 kHz +/- 19 Bit + c LMCR2: LM-SEL[3:0] LMCR2: LM-SEL[3:0] DC Output Voltage VDC on DCN - DCP A-B a VOICE PATH A-B b DC LEVELMETER MUX PCM OUT: Transmit Data to PCM or IOM-2 Interface LMCR1: LM2PCM RECTIFIER c 16 / 1 ON / OFF PROGR GAIN STAGE LMCR1: DC-AD16 LMCR2: LM-RECT SHIFT FACTOR KINTDC CRAM INTEGRATOR (Ring Period) LMCR1: LM-EN MUX CRAM RESULT REG LMRES1/2 TTX ADAPTIVE FILTER TTX REAL TTX IMG. Programmable Not Programmable LMCR2: LM-SEL[3:0] duslic_0010_level_meter_block.emf Figure 45 Data Sheet Blockdiagram Levelmeter 109 2000-07-14 DuSLIC Preliminary Operational Description 4.8.2.3 Result Register Data Format The result of any measurement can be read via the result registers LMRES1/2. This gives a 16 bit value with LMRES1 being the high and LMRES2 being the low byte. The result is coded in 16 bit twos complement: Table 27 - Fullscale 0x8000 - 32768 0xFFFF -1 0 0 Levelmeter Result Value Range Positive Value Range + Fullscale 0x7FFF + 32767 Negative Value Range 4.8.2.4 Using the Levelmeter Integrator Both AC and DC levelmeter allow to use a programmable integrator. The integrator may be configured to run continuously or single. Single Measurement Sequence (AC & DC Levelmeter) LM C R 1: LM -O N C E = 1 S tart N ew M e asurem ent LM C R 1: LM -E N In t. P e rio d In t. P e rio d IN TR E G 2: LM -O K Read Result LMRES1/2 duslic_0019_LM_single.emf Figure 46 Single Measurement Sequence (AC&DC Levelmeter) Data Sheet 110 2000-07-14 DuSLIC Preliminary Continuous Measurement Sequence (DC Levelmeter) Operational Description LM C R 1: LM -O N C E = 0 LM C R 1: LM -E N In t. P e rio d In t. P e rio d In t. P e rio d In t. P e rio d 500 s 500 s 500 s IN TR E G 2: LM -O K Read Result LMRES1/2 Read Result LMRES1/2 Read Result LMRES1/2 duslic_0020_LM_contDC.emf Figure 47 Continuous Measurement Sequence (DC Levelmeter) Continuous Measurement Sequence (AC Levelmeter) LM C R 1: LM -O N C E = 0 LM C R 1: LM -E N 1 ms In t. P e rio d In t. P e rio d 1 ms In t. Pe rio d 500 s 500 s 500 s IN TR E G 2: LM -O K Read Result LMRES1/2 Read Result LMRES1/2 Read Result LMRES1/2 duslic_0021_LM_contAC.emf Figure 48 Continuous Measurement Sequence (AC Levelmeter) Data Sheet 111 2000-07-14 DuSLIC Preliminary Operational Description 4.8.2.5 DC Levelmeter The path of the DC levelmeter is shown in Figure 45. Hereby, the DC levelmeter results will be determined and prepared depending on certain configuration settings. The selected input signal becomes digitized after pre-filtering and analog-to-digital conversion. The DC levelmeter is selected and enabled as shown in Table 28: Table 28 Selecting DC Levelmeter Path DC Levelmeter Path DC out voltage on DCP-DCN DC current on IT DC current on IL Voltage on IO3 Voltage on IO4 VDD Offset of DC-pre-filter (short circuit on DC-pre-filter input) Voltage on IO4 - IO3 LM-SEL[3:0] in register LMCR2 0100 0101 1001 1010 1011 1101 1110 1111 The effective sampling rate after the decimation stages is 2 kHz. The decimated value has a resolution of 19 bits. The offset compensation value (see Chapter 4.8.2.8) within the offset registers OFR1 (bits OFFSET-H[7:0]) and OFR2 (bits OFFSET-L[7:0]) can be set to eliminate the offset caused by the SLIC-E/-E2/-P current sensor, pre-filter, and analog-to-digital converter. After the summation point the signal passes a programmable digital gain filter. The additional gain factor is either 1 or 16 depending on register LMCR1 (bit DC-AD16): - LMCR1 (bit DC-AD16) = 0: No additional gain factor - LMCR1 (bit DC-AD16) = 1: Additional gain factor of 16 The rectifier after the gain filter can be turned on/off with: - LMCR2 (bit LM-RECT) = 0: Rectifier disabled - LMCR2 (bit LM-RECT) = 1: Rectifier enabled A shift-factor KINTDC in front of the integrator prevents the levelmeter during an integration operation to create an overflow. If an overflow in the levelmeter occurs, the output result will be fullscale (see Table 27). If the shift factor KINTDC is set to e.g. 1/8, the content of the levelmeter result register is the integration result divided by 8. The shift factor KINTDC is set in the CRAM (offset address 0x76): Data Sheet 112 2000-07-14 DuSLIC Preliminary CRAM: Address Address 0x76: LMDC2/LMDC1 0x77: 0/LMDC3 Operational Description LMDC1, LMDC2 and LMDC3 are 4 bit nibbles which contain KINTDC. Table 29 LMDC1 8 8 8 8 8 KINTDC Setting Table LMDC2 8 8 8 8 8 LMDC3 0 1 : 6 7 KINTDC 1 1/2 : 1/64 1/128 DuSLICOS allows to automatically calculate the coefficients for KINTDC for ITRANS measurement. The expected "Current for Ring Off-hook Detection" (see DuSLICOS DC Control Parameter 2/3) of e.g. 20 mA is entered in to the program and then KINTDC is automatically calculated to achieve 50 % full scale if the current of 20 mA is integrated over the set ringer period. The integration function accumulates and sums up the levelmeter values over a set time period. The time period is determined by the programmed ring frequency. A ring frequency fRING of 20 Hz results in 100 samples (NSamples), because of the 2 kHz effective DC sampling rate fS,DC. f S, DC 2000Hz N Samples = ------------- = -------------------f RING f RING The number of integration samples NSamples may also be programmed directly by accessing dedicated bytes in the Coefficient RAM (CRAM). CRAM: Address Address 0x73: RGF2/RGF1 0x74: RGA1/RGF3 RGF1, RGF2 and RGF3 are 4 bit nibbles which control the ring frequency fRING. RGA1 is a 4 bit nibble which is calculated by DuSLICOS and controls the ringer amplitude (see DuSLICOS byte file). To ensure that RGA1 is not changed please perform a read/modify/write operation. Data Sheet 113 2000-07-14 DuSLIC Preliminary Table 30 RGF1 8 8 8 8 8 8 8 8 8 8 NSamples Setting Table RGF2 RGF3 0 1 : 6 7 fRING 500 250 : 7.81 3.91 NSamples 4 8 : 256 512 Operational Description The integration function can be turned on and off by bit LM-EN in register LMCR1. The levelmeter result of the selected signal source will be stored in the result registers LMRES1 (bits LM-VAL-H[7:0]) and LMRES2 (bits LM-VAL-L[7:0]) depending on the LM-SEL[3:0] bits in register LMCR2. The result registers get frequently updated every 500 s if bit LM-EN in register LMCR1 = 0, or after an integration period, if bit LM-EN in register LMCR1 = 1. If the bit LM-ONCE in register LMCR1 is set to 1 then the integration is executed only once. To start again bit LM-EN has to be set from 0 to 1. The levelmeter source/result can be transferred to the PCM/IOM-2 interface, depending on the bit LM2PCM in register LMCR1. Table 31 shows the levelmeter results without and with integrator function. The integrator is enabled if bit LM-EN in register LMCR1 = 1. The levelmeter result LMValue is a 16 bit twos complement value of LM-VAL-H[7:0] and LM-VAL-L[7:0]. The factor LMResult used in Table 31 is defined: LM Value LM Result = --------------------32768 * Example for positive value of LMResult: LM-VAL-H = "0010 0100" = 0x24 LM-VAL-L = "1010 0101" = 0xA5 LMValue = 0x24A5 = 9381 LMResult = 0.2863 * Example for negative value of LMResult: LM-VAL-H = "1001 1001" = 0x99 LM-VAL-L = "0110 0010" = 0x62 LMValue = 0x9962 = - 26270 LMResult = - 0.8017 Data Sheet 114 2000-07-14 DuSLIC Preliminary Operational Description Table 31 ITRANS1): Power Down Resistive ITRANS1): any other mode Levelmeter Results with and without Integrator Function LM-EN = 0 (without Integrator) I TRANS TRANS = LM Result Result K IT, PDR x ------------------------- x V AD R IT2 LM-EN = 1 (with Integrator) K xV IT, PDR AD I TRANS = LM Result x --------------------------------------------------------------------------------R xN xK IT2 Samples INTDC I = LM x 7.966 mA K I TRANS = LM Result 7.966 mA x -----------------------------------------------------------N xK Samples INTDC I I TRANS TRANS = LM = LM IT x ----------- x V AD Result R IT2 K xV IT AD I TRANS = LM Result x --------------------------------------------------------------------------------R xN xK IT2 Samples INTDC Result x 79.66 mA K I TRANS = LM Result 79.66 mA x ----------------------------------------------------------N xK Samples INTDC ILONG2) I LONG = I LONG IL - LMResult x --------- x V AD Result I = - LM x IL 67.7 mA R LONG = - LM K xV IL AD x ----------------------------------------------------------------------------Result R x N xK IL Samples INTDC I LONG = - LM Result 67.7 mA x ----------------------------------------------------------N xK Samples V INTDC Voltage: IO33), IO44), IO4-IO35) V INPUT = - LM Result x V AD V INPUT = - LM x ----------------------------------------------------------Result N xK Samples INTDC AD VDD VDC6) with ACTL, ACTH V DD = - LM Result x 3.9 V 3.9 V V DD = - LM Result x ----------------------------------------------------------N xK Samples INTDC V = - LM 76.35 V x ----------------------------------------------------------N Samples x K INTDC V DC = - LM Result x 76.35 V DC Result VDC6) with ACTR, ringing mode 1) 2) 3) 4) 5) 6) V DC = - LM Result x 152.7 V V DC = - LM Result 152.7 V x ----------------------------------------------------------N xK Samples INTDC DC current on pin IT (bits LM-SEL[3:0] = 0101) DC current on pin IL (bits LM-SEL[3:0] = 1001) Voltage on IO3 referenced to VVCM (typical 1.5 V) (bits LM-SEL[3:0] = 1010) Voltage on IO4 referenced to VVCM (typical 1.5 V) (bits LM-SEL[3:0] = 1011) Voltage on IO4 - IO3 referenced to VVCM (typical 1.5 V) (bits LM-SEL[3:0] = 1111) DC output voltage at SLIC measured via DCN - DCP (bits LM-SEL[3:0] = 0100) Data Sheet 115 2000-07-14 DuSLIC Preliminary KINTDC KIT,PDR KIT KIL RIT2 RIL Shift Factor (see Table 29) Value of the current divider in power down resistive mode Value of the current divider for transversal current Value of the current divider for longitudinal current Sense resistor for transversal current Sense resistor for longitudinal current Voltage at A/D converter refered to digital fullscale DC output voltage at SLIC measured via DCN - DCP 5 50 100 680 1600 1.0834 Operational Description VAD VDC Note: Measurement of pins IL, IO3, IO4, IO4-IO3 and VDD can cause problems in the DC loop. The measured value is always interpreted as ITRANS current. This can disturb the DC regulation and the off-hook indication. In active mode you can freeze the output of the DC loop by setting the bit LM-HOLD to '1'. In ringburst mode it is possible that DuSLIC automatically switches back to ringpause mode because the measurement result was interpreted as off-hook. This can be avoided by programming the off-hook current to the maximum value (79.66 mA). Measurement of AC signals via DC levelmeter This method is applicable for a single frequency sinusoidal AC signal which is superimposed on a DC signal. 1. Set the ring frequency fRING to the frequency of the signal to be measured. Multiples of the expected signal period may also be used. 2. Set the offset registers OFR1 and OFR2 to 0x00. 3. Measure the DC content with disabled rectifier (bit LM-RECT = 0). The DC content can be calculated as described in Table 31. Note: If there was an overflow inside the integrator during the integration period, the result will be fullscale. Reduce the shift factor KINTDC or the number of samples NSamples and start the measurement again. 4. The offset registers OFR1 and OFR2 have to be programmed to the value LM Value OFFSET = - ----------------------------------------------------------N Samples x K INTDC where OFR1 is the high byte and OFR2 is the low byte of the 16 bit word OFFSET. 5. Repeating the measurement of the DC content should result in a LMValue of zero. 6. Perform a new measurement with the rectifier enabled (bit LM-RECT = 1). The result is the rectified mean value of the measured signal an can be calculated with the formulas of Table 31. 7. From this result the peak value and the RMS value can be calculated: Data Sheet 116 2000-07-14 DuSLIC Preliminary V Mean x V Peak = ---------------------------2 V Peak V RMS = --------------2 Operational Description 4.8.2.6 AC Levelmeter The AC levelmeter is selected and enabled as shown in Table 32: Table 32 Selecting AC Levelmeter Path AC Levelmeter Path AC levelmeter in transmit AC levelmeter in receive AC levelmeter receive + transmit LM-SEL[3:0] in register LMCR2 0000 0110 0111 Figure 45 on Page 109 shows the path of the AC/TTX levelmeter functions. The AC levelmeter allows access to the voice signal while the active voice signal is being processed. The input signal for the AC levelmeter might get processed with a programmable filter characteristic, i.e. bandpass- or notch filter. Depending on the following settings, the bandpass or notch filter is turned on or off: - - - - Register LMCR2 bit LM-FILT = 0: No filter enabled (normal operation) Register LMCR2 bit LM-FILT = 1: Bandpass/notch filter characteristics enabled Register LMCR2 bit LM-NOTCH = 0: Notch filter enabled, bandpass filter disabled Register LMCR2 bit LM-NOTCH = 1: Bandpass filter enabled, notch filter disabled The rectifier cannot be turned off, it is always active in the AC path. A shift-factor in front of the integrator prevents the levelmeter during an integration operation to create an overflow. The shift-factor can be set by the coefficient LM-AC gain (see CRAM coefficient set Table 51 "CRAM Coefficients" on Page 226). KINTAC can be set via coefficient LM-AC: CRAM: Address 0x34: CG1/LM-AC LM-AC is a 4 bit nibble which contains KINTAC. CG1 is a 4 bit nibble which is calculated by DuSLICOS and controls the conference gain (see DuSLICOS byte file). To ensure that CG1 is not changed please perform a read/ modify/write operation. Data Sheet 117 2000-07-14 DuSLIC Preliminary Table 33 LM-AC 0 1 : 6 7 KINTAC Setting Table KINTAC 1 1/2 : 1/64 1/128 Operational Description The integration function accumulates and sums up the levelmeter values over a set time period. The time period from 1*16 ms to 16*16 ms is set by the bits LM-ITIME[3:0] in register LMCR3. The integration function can be turned on and off by bit LM-EN in register LMCR1. The number of samples NSamples for the integrator is defined by: NSamples = LM-ITIME * 8000 The level can be calculated by: U dBm0 = 20 x log ae LM Result x ------------------------------------------------------------ o + 3.14 e 2 x K INT x N Samples The result registers get frequently updated after an integration period, if bit LM-EN in register LMCR1 = 1. If the bit LM-ONCE in register LMCR1 is set to 1 then the integration is executed only once. To start again bit LM-EN has to be set from 0 to 1. The levelmeter result can be transferred to the PCM/IOM-2 interface, depending on bit LM2PCM in register LMCR1. Measurement of currents via ITAC In order to do current measurements via pin ITAC, all feedback loops (IM-filters and THfilters) should be disabled. To simplify the formulas, the programmable receive and transmit gain is disabled. This is done by setting the following bits: Register BCR4: Register TSTR4: AR-DIS = 1, AX-DIS = 1, TH-DIS = 1, IM-DIS = 1, FRR-DIS = 1, FRX-DIS = 1 OPIM-AN = 1, OPIM-4M = 1 Register LMCR1: TEST-EN = 1 Data Sheet 118 2000-07-14 DuSLIC Preliminary Operational Description This setting results in a receive gain of 11.88 dB caused by the internal filters. Based on this a factor KAD (analog to digital) can be defined: 10 10 -1 K AD = --------------------- = ---------------------- = 3.272 V 1.2 V ADC Transversal current IRMS measured at SLIC: LM LM x K IT x Result Result I RMS = ----------------------------------------------------------------------------------------------------------------- = -------------------------------------------------- x 14.76 mA K INTAC x N Samples K AD x R ITAC x K INTAC x N Samples x 2 x 2 filterAD ------------------20 11.88 V ------------------20 RITAC KAD VADC KIT Sense resistor for AC transversal current (RIT1 + RIT2) Constant factor from Analog to Digital Voltage at A/D converter refered to digital fullscale Value of the current divider for transversal current 1150 3.272 V-1 1.2 V 50 In order not to overload the analog input, the maximum AC transversal current may not be higher than 9 mA rms. Usage of Tone Generator as Signal Source To simplify the formulas, the programmable receive and transmit gain is disabled. This is done by setting the following bits: Register BCR4: Register TSTR4: AR-DIS = 1, AX-DIS = 1, TH-DIS = 1, IM-DIS = 1, FRR-DIS = 1, FRX-DIS = 1 OPIM-AN = 1, OPIM-4M = 1 Register LMCR1: TEST-EN = 1 The tone generator level is influenced by a factor KTG which is set in the tone generator coefficients. The internal filter attenuation is 2.87 dB. K DA = V DAC x 10 - 2.87 --------------20 Trapez x ------------------- x K AC ,SLIC = 1.2 x 10 2 - 2.87 --------------20 x --------- x 6 2 1.05 Data Sheet 119 2000-07-14 DuSLIC Preliminary KDA KAC,SLIC VDAC Trapez Constant factor from Digital to Analog Amplification factor of the SLIC Voltage at D/A converter refered to digital fullscale Crestfactor of the trapazoidal signal Operational Description 3.84 Vrms 6 1.2 V 1.05 Output voltage between Tip and Ring: VOUT = KDA * KTG The bytes below are valid for tone generator TG1 an a frequency of 1000 Hz. CRAM: Address Address Address Address Address Address 0x38: 0x08 0x39: T11G/0 0x40: T13G/T12G 0x41: 0x05 0x42: 0xB3 0x43: 0x01 T11G, T12G and T13G are 4 bit nibbles which control the amplitude of the tone generator TG1. Table 34 T11G 8 8 8 8 8 8 8 KTG Setting Table T12G 9 0 1 : 5 6 7 T13G 1 8 8 8 8 8 8 KTG 7/8 1/2 1/4 : 1/64 1/128 1/256 Data Sheet 120 2000-07-14 DuSLIC Preliminary Operational Description 4.8.2.7 Levelmeter Threshold For the levelmeter result a threshold can be set. When the result exceeds the threshold then bit LM-THRES in register INTREG 2 is set to '1'. It is also possible to activate an interrupt when the LM-THRES bit changes by setting the bit LM-THM (levelmeter threshold mask bit) in register LMCR2 to '0'. The levelmeter threshold can be calculated with DuSLICOS or taken from Table 35. CRAM: Address Address 0x32: LMTH2/LMTH1 0x33: 0/LMTH3 (LMTH1, LMTH2 and LMTH3 are 4 bit nibbles) Table 35 LMTH1 1 0 8 8 9 8 8 Threshold Setting Table LMTH2 0 1 8 9 0 1 0 LMTH3 0 0 0 0 0 0 0 Threshold 75.0 % 62.5 % 50.0 % 37.5 % 25.0 % 12.5 % 0.0 % Data Sheet 121 2000-07-14 DuSLIC Preliminary Operational Description 4.8.2.8 Current Offset Error Compensation The current offset error caused by the current sensor inside the SLIC-E/-E2/-P can be compensated by programming the compensation registers OFR1 and OFR2 accordingly. The current offset error can be measured with the DC levelmeter. The following settings are necessary to accomplish this: * The DuSLIC has to be set into the HIRT mode by setting the bits HIR and HIT in register BCR1 to 1. In HIRT mode the line-drivers of the SLIC-E/-E2/-P are shut down and no resistors are switched to the line. As a matter of fact, no current is present in that mode, but the current sensor wrongly indicates a current flowing (current offset error). * The DC path for ITRANS current levelmeter must be selected by setting the LMSEL[3:0] bits in register LMCR2 to 0101 (see Table 28). * The offset registers OFR1 and OFR2 must be set to 0000h. * IOff-Err can be calculated like shown for "ITRANS: any other mode" in Table 31 (see also example below). The current offset error can be eliminated by programming the offset registers OFR1 and OFR2 according to the inverse value of the measured current offset error. Example: KINTDC = 1, NSamples = 256, LMValue = 0x0605 = 1541 LM Value 1541 LM Result = --------------------- = --------------- = 0.047 32768 32768 79.66 mA 79.66 mA I off - Err = LM Result x ----------------------------------------------------------- = 0.047 x ------------------------ = 0.0146 mA 256 x 1 N Samples x K INTDC I Off - Err 0.0146 mA OFFSET = - ------------------------ x 32768 = - ---------------------------- x 32768 - 6 = 0xFFFA 79.66 mA 79.66 mA Short form: LM Value OFFSET = - ----------------------------------------------------------N Samples x K INTDC OFR1 = OFFSET-H = 0xFF OFR2 = OFFSET-L = 0xFA Data Sheet 122 2000-07-14 DuSLIC Preliminary Operational Description 4.8.2.9 Loop Resistance Measurements The DC loop resistance can be determined by supplying a constant DC voltage VTR,DC to the Ring- and Tip line and measuring the DC loop current via IT pin. The following steps are necessary to accomplish this: * Program a certain ring offset voltage RO1, RO2, RO3 (see DuSLICOS DC Control Parameter 2/3). * Select ring offset voltage RNG-OFFSET[1:0] in register LMCR3 either to 01, 10 or 11. If 00 is selected, the DC regulation would be still active and would not allow resistance measurement. * Choose an operation mode, either Active High (ACTH) or Ring Pause. * Select the DC path for levelmeter by setting the bits LM-SEL[3:0] in register LMCR2 to 0101 (DC current on IT). * The transversal current can be determined by reading the levelmeter result registers LMRES1, LMRES2. * Based on the known constant output voltage VTR,DC (DC voltage according to RNG-OFFSET[1:0]) and the measured ITRANS current, the resistance can be calculated. It should be noted, that the calculated resistance includes also the onboard resistors RPROT and RSTAB. In order to increase the accuracy of the result, either the current offset can be compensated or the measurement can be done differentially. The latter one eliminates the current- and voltage offsets. Figure 49 shows an example circuit for resistance measurement: LINECARD line current sense signal to be measured IT IL ILINE RPROT + RSTAB RLINE VTR,DC* SLIC-E/-E2/-P DCP SLICOFI-2 RPROT + RSTAB DCN * DC Offset Voltage according to RNG-OFFSET[1:0] duslic_0011_measurement_tip_ring.emf Figure 49 Data Sheet Example Resistance Measurement 123 2000-07-14 DuSLIC Preliminary Assumption: * Loop resistance Rloop = 1000 ; Rloop = RLINE + 2*RPROT + 2*RSTAB * Ring offset RO2 = 60 V (CRAM coefficient set accordingly). Ring offset RO2 is selected by setting bits RNG-OFFSET[1:0] in register LMCR3 to 10. The exact value for the Ring offset voltage can be determined from the *.res result file generated by DuSLICOS during the calculation of the appropriate coefficients. * Select Active High (ACTH) mode by setting the line mode command CIDD/CIOP bits M2, M1, M0 to 010. In ACTH mode half of the ring offset voltage RO2 of e.g. 60 V will be present and applied to Ring and Tip. Sequence to determine the loop resistance Rloop differentially: * * * * Select DC levelmeter by setting bits LM-SEL[3:0] in register LMCR2 to 0101. Read levelmeter result registers LMRES1, LMRES2. Switch into reverse polarity mode by setting bit REVPOL in register BCR1 to 1. Read levelmeter result registers LMRES1, LMRES2. Operational Description If the loop resistor connected between Ring and Tip is 1000 (RLINE + RPROT + RSTAB), the expected current will be 30 mA, because the actual voltage applied to Ring and Tip is 30 V. Considering the fact, that the current measurement in reverse polarity mode will also become inverted, the read results have to be added. The sum of both levelmeter results (normal- and reverse polarity) should therefore be 60 mA current difference. Figure 50 shows the differential measurement method and the elimination of the offsets. Normal Polarity ITIP/RING expected values measured values dI VTIP/RING Offsets Ioffset Uoffset dU Reverse Polarity duslic_0008_differentially.emf Figure 50 Differential Resistance Measurement The following calculation shows the elimination of the voltage and current offset caused by output stage and current sensor. This differential measurement method both Data Sheet 124 2000-07-14 DuSLIC Preliminary Operational Description eliminates the offsets caused by the SLIC-E/-E2/-P current sensor and the offset caused by the DC voltage output (Ring offset voltage). Differential Resistance Calculation: V TR, prog + V offset I measure ( normal ) = ---------------------------------------------- + I offset R - V TR, prog + V offset I measure ( reverse ) = ------------------------------------------------- + I offset R 2 x V TR, prog I measure ( normal ) - I measure ( reverse ) = -------------------------------R 2 x V TR, prog R = ------------------------------------------------------------------------------------------- = R LINE + R PROT + R STAB I measure ( normal ) - I measure ( reverse ) 4.8.2.10 Line Resistance Tip/GND and Ring/GND The DuSLIC offers the modes of setting either the Tip- or the Ring line to high impedance or even both by setting the bits HIR and HIT in register BCR1 accordingly. While one of both lines is set to high impedance, the other line is still active and able to supply a known voltage. The transversal and/or longitudinal current can be measured and the line impedance can be calculated. Because of one line (Tip or Ring) being high impedance, there is only current flowing in either Tip or Ring line. This causes the calculated current (according Table 31) to be half the actual value. Therefore in either HIR or HIT mode the calculated current has to be multiplied by a factor of 2. Data Sheet 125 2000-07-14 DuSLIC Preliminary Operational Description 4.8.2.11 Capacitance Measurements Capacitance measurements with the DuSLIC are accomplished by using the integrated ramp generator function. The ramp generator is capable of applying a voltage ramp to the Ring- and Tip line with the flexibility of: - Programmable slopes from 30 V/s to 2000 V/s - Programmable start- and stop DC voltage offsets via ring offsets - Programmable start time of the voltage ramp after enabling the levelmeter function Figure 51 shows the voltage ramp and the voltage levels at the Ring and Tip line. The slope of the ramp can be programmed (refer to CRAM coefficients). The ring offset voltages RO1, RO2 and RO3 might be used as start and stop voltages. The ramp starts for instance at RO1 and stops at RO2. The current can be calculated as i(t) = CMeasure*dU/dt, where dU/dt is the slope and i(t) is the current which will be measured by the levelmeter. In order to measure accurate values, the integration has to start after the current has settled to a constant value. This can be calculated by the time constant of the ringer load. It is recommended to set the programmable ring generator delay higher than 3 times the time constant of the ringer load. When there is a resistor in parallel to the capacitor (e.g. leakage), it is recommended to measure symmetrically around the voltage zero crossing. This can be achieved by programming the ring generator delay appropriately (see DuSLICOS DC Control Parameter 2/3). The integration time for the current measurement is determinded by the ring frequency (refer to CRAM coefficients, see Table 30). After the integration time the measurement automatically stops only when the bit LM-ONCE in register LMCR1 is set. Otherwise the levelmeter would continuously measure the current even if the ramp is finished and turned into its constant voltage position, i.e., that because of the constant voltage no current will flow. Data Sheet 126 2000-07-14 DuSLIC Preliminary Operational Description S LIC -E /-E 2 S LIC -P GND V HR T IP GND R IN G (V H R + V B A T H )/2 V D C ,S to p V D C ,S tart T IP R IN G P rogram m able V oltage S lope V B A TR /2 V BATH S e ttlin g of lin e cu rre nt i: S e t ring er de lay T R IN G ,D E LA Y h ig h en o ug h to do th e a ctu al curre n t m e asu rem e nt in the settled cu rre n t ra ng e . V B A TR Line C urrent i LM C R 1: LM -E N T RIN G ,D E LA Y IN T R E G 2: LM -O K In t. P e rio d IN T R E G 2: R E A D Y ezm14053.emf Figure 51 Capacitance Measurement f Data Sheet 127 2000-07-14 DuSLIC Preliminary Example: * Assumptions: - Capacitance as object to be determined: CMeasure = 9.8 F - Resistor RMeasure in series to CMeasure: RMeasure = 6930 - = RMeasure*CMeasure = 67.9 ms * Calculating parameter values: - Choose Ring Offset voltage 1: RO1 = 70 V (Start voltage on Ring/Tip where the ramp should start; programmed by ring offset voltage RO1) - Choose Ring Offset voltage 2: RO2 = - 30 V (End voltage on Ring/Tip where the ramp should stop; programmed by ring offset voltage RO2) - Choose slope of ramp while testing: dU/dt = 200 V/s - Time from start to stop of the ramp from RO1 to RO2 is 100 V/200 V/s = 500 ms - Time from start to zero cross is 70 V/200 V/s = 350 ms - Choose Integration time: TI = 1/fRING = 1/100 Hz = 10 ms - Measure around zero cross =from 345 ms to 355 ms - TRING,DELAY is programmed to 345 ms - Check ring generator delay: TRING,DELAY > 3* = 204 ms =OK! - Expected current i = CMeasure*dU/dt = 1.96 mA - Choose current for LM off-hook threshold ILM,DC = 2 mA Note: A current of 2 mA will result in LMResult = 0.5 (half of the fullscale value) Operational Description Program Sequence: * Set the following parameter values: Parameter Slope of ramp while testing Ring frequency Ring generator delay Ring offset voltage 1 Ring offset voltage 2 Current for LM off-hook threshold * * * * Symbol & Value dU/dt = 200 V/s fRING = 100 Hz TRING,DELAY = 345 ms RO1 = 70 V RO2 = - 30 V ILM,DC = 2 mA DuSLICOS DC Control Parameter 3/3 DC Control Parameter 2/3 DC Control Parameter 2/3 DC Control Parameter 2/3 DC Control Parameter 2/3 DC Control Parameter 2/3 Integration time TI = 1/fRING = 1/100 Hz = 10 ms Select the DC levelmeter by setting bits LM-SEL[3:0] in register LMCR2 to 0101 Execute the levelmeter only once by setting bit LM-ONCE in register LMCR1 to 1. Apply Ring Offset voltage RO1 to Ring and Tip line by setting bits RNG-OFFSET[1:0] in register LMCR3 to 01. * Enable the ramp generator by setting bit RAMP-EN in register LMCR2 to 1. Data Sheet 128 2000-07-14 DuSLIC Preliminary Operational Description * Apply Ring Offset voltage RO2 to Ring and Tip line by setting bits RNG-OFFSET[1:0] in register LMCR3 to 10. * Enable the levelmeter by setting bit LM-EN in register LMCR1 to 1. - Comment: The voltage ramp starts at RO1 and ramps up/down until RO2 is achieved. After the integration time, the result will be stored within LMRES1 and LMRES2 registers. * Read the result registers LMRES1 and LMRES2 The actual current ICMeasure amounts to: I CMeasure = 2 x I LM, DC x LM Result The capacitance CMeasure calculates as: I CMeasure C Measure = ------------------------dU ------dt Example: LMValue = 0x3AF2 = 15090 LMResult = 0.4605 ICMeasure = 2*2 mA*0.4605 = 1.842 mA CMeasure = 1,842 mA/200 V/s = 9.21 F 4.8.2.12 Line Capacitance Measurements Ring and Tip to GND The voltage ramp can be applied to either line, whereas the other line is set to high impedance by setting bits HIR and HIT in register BCR1 accordingly. That way capacitance measurements from Ring and Tip to GND may be accomplished. Because of one line being high impedance, the actual line current will be twice the calculated one (multiplication by a factor of 2 necessary). 4.8.2.13 Foreign- and Ring Voltage Measurements The DuSLIC supports two user-programmable input/output pins (IO3, IO4) which can be used for measuring external voltages. If the pins IO3 and/or IO4 are led properly over a voltage divider to the Ring- and Tip wire, foreign voltages from external voltage sources supplied to the lines can be measured on either pin, even a differential measurement will be supported (IO4-IO3). The selection of which input information shall be taken for the measurement is done via bits LM-SEL[3:0] in configuration register LMCR2 (Table 36). Data Sheet 129 2000-07-14 DuSLIC Preliminary Table 36 Measurement Input Selection Measurement Input Voltage on IO3 Voltage on IO4 Voltage IO4 - IO3 Operational Description LM-SEL[3:0] in register LMCR2 1010 1011 1111 The measurement is accomplished by the DC levelmeter function. VCM R2 R1 IT IO4 FOREIGN VOLTAGE SOURCE AC LINECARD DC IL RPROT + RSTAB SLIC-E/-E2/-P RPROT + RSTAB ACN / P SLICOFI-2 DCN / P R3 IO3 R4 VCM duslic_0009_foreign_voltage.emf Figure 52 Foreign Voltage Measurement Principle Figure 52 shows the connection and external resistors used for supporting foreign voltage measurements at the Ring and Tip lines. Since the pins IO3 and IO4 support analog input functionality and are limited to a certain voltage range of VVCM 1.0 V (typ. 1.5 V 1.0 V), the values for the voltage divider has to be determined according to following conditions: * Maximum level of the expected foreign voltages * Voltage range of IO3 and IO4 = VVCM 1.0 V The voltage on IO3 or IO4 is measured with a reference to VCM. Hence an input voltage of VVCM on either input pin would result into zero output value. Whereas a voltage of VVCM + 1 V would result into the negative full scale value, VVCM - 1 V would result into the positive full scale value respectively. For that reason the voltage divider has to be referenced to VCM. The unknown foreign voltage VFOREIGN can be calculated as: Data Sheet 130 2000-07-14 DuSLIC Preliminary R1 + R2 V FOREIGN = V INPUT x --------------------- + V VCM R2 VINPUT = VIOx - VVCM (refer to Table 31) VIOx = Voltage on pins IOx (e.g. pins IO3, IO4) The resistor directly connected to either Ring or Tip (R1, R3) should be high enough so that the loop impedance will not be affected by them. Several M s, e.g. 10 M would be a reasonable value. The following example illustrates the potential voltage range that can be measured by chosing the values as: * R1 = R3 = 10 M * R2 = R4 = 47 k The values given for the maximum and minimum voltage levels are: * VVCM = 1.5 V * VINPUT,max = 1 V =VIOX,max = 2.5 V * VINPUT,min = - 1 V =VIOX,min = 0.5 V R1 + R2 V FOREIGN, max = V INPUT, max x --------------------- + V VCM = 215 V R2 R1 + R2 V FOREIGN, min = V INPUT, min x --------------------- + V VCM = - 212 V R2 The voltage range would span from 215 V to - 212 V. In order to measure small input voltages on IO3/IO4 more accurately the user might consider to enable the integration function (see Figure 45) by setting bit LM-EN in register LMCR1 to 1. In case of measuring the ring voltage supplied to either Ring or Tip or even both (balanced ringing) pins via IO3 and IO4, the rectifier can be enabled by setting bit LM-RECT in register LMCR2 to 1. Operational Description Data Sheet 131 2000-07-14 DuSLIC Preliminary Operational Description 4.9 Signal Path and Test Loops The following figures show the main AC and DC signal path and the integrated analog and digital loops of DuSLIC-E/-E2/-P, DuSLIC-S and DuSLIC-S2. Please note the interconnections between the AC and DC pictures of the respective chip set. 4.9.1 Test Loops DuSLIC-E/-E2/-P L M -D C LM -N O T C H LM -F IL T L M -E N 16K COX16 AX2 HPX2 LPX FRX AX1 HPX1 LM-AC LM-VAL* d AC-DLB-32K a LM -S E L[3 :0] LM 2PCM M U-LAW LIN CMP PCM OUT: Transmit Data to PCM or IOM-2 Interface AX-DIS HPX-DIS LPRX-CR PCM16K FRX-DIS AX-DIS HPX-DIS AC-DLB-8K *LM -V A L-H [7 :0] LM -V A L-L[7 :0] TH PCM16K AR-DIS b AR2 P C M 2D C FRR-DIS FRR c LPX-CR LPR HPR-DIS HPR AR-DIS COR8 AR1 + EXP PCM IN: COR-64 TH-DIS PTG , TG 1-EN, TG 2-EN TG TG M U-LAW Receive Data from PCM or LIN IOM-2 Interface ITAC PD-AC-GN PD-AC-PR PD-AC-AD AC-XGAIN AC-DLB-4M + PREFI ADC AC-DLB-128K a TTX Adapt. Programmable via CRAM IM1 HIM-AN OPIM_4M OPIM_AN PD-AC-PO PD-AC-DA IM2 Not Programmable TTX -12K TTX -DIS P D -T T X -A TTX -12K TTX -DIS TTX Gen. IM3 SWITCH SWITCH Always available Available only when bit TEST-EN = 1 Figure 53 AC Test Loops DuSLIC-E/-E2/-P Data Sheet + ACN/ACP POFI DAC + + b IM-DIS duslic_0022_intstru_slicofi2_a.wmf 132 2000-07-14 DuSLIC Preliminary Operational Description LM-SEL[3:0] IT IL IO3 IO4 IO4 - IO3 VDD Offset PD-DC-PR PD-DC-AD DC DC ADC PREFI *O F F S E T -H [7 :0] O F F S E T -L[7 :0] OFFSET* LM-EN LM-RECT LM-DC d RTR-SEL + LP Hook RNG -O FFSET[1:0] DC Char. RG RO1 RO1 RO1 PD-DCBUF PC-POFI-HI PD-DC-DA DCN/DCP DC BUF DC POFI DC DAC DC-HOLD RAMP-EN RAMP + + c PCM 2DC Programmable via CRAM PD-OFHK IT OFFHOOK COMP PD-OVTC OVERT. COMP Not Programmable PD-GNKC SWITCH SWITCH Always available Available only when bit TEST-EN = 1 IL GNK COMP C1 C2 HV-INT. PD-HVI duslic_0022_intstru_slicofi2_b.wmf Figure 54 DC Test Loops DuSLIC-E/-E2/-P Data Sheet 133 2000-07-14 DuSLIC Preliminary Operational Description 4.9.2 Test Loops DuSLIC-S/-S2 The AC test loops for DuSLIC-S (Figure 55) and DuSLIC-S2 (Figure 56) are different since Teletax (TTX) is not available with SLICOFI-2S2. The DC test loops are identical. AC-DLB-32K a AX2 16K COX16 HPX2 LPX FRX AX1 HPX1 M U-LAW LIN CMP PCM OUT: Transmit Data to PCM or IOM-2 Interface AX-DIS HPX-DIS LPRX-CR FRX-DIS AX-DIS HPX-DIS AC-DLB-8K TH P C M 2D C AR-DIS b AR2 c LP X-CR LPR FRR-DIS FRR HPR-DIS HPR AR-DIS COR8 AR1 + EXP PCM IN: COR-64 TH-DIS PTG , TG 1-EN, TG 2-EN TG TG M U-LAW Receive Data from PCM LIN or IOM-2 Interface ITAC PD-AC-GN PD-AC-PR PD-AC-AD AC-XGAIN AC-DLB-4M + PREFI ADC AC-DLB-128K a TTX Adapt. Programmable via CRAM IM1 HIM-AN OPIM_4M OPIM_AN IM2 Not Programmable TTX-12K TTX-DIS P D -T T X -A TTX-12K TTX-DIS TTX Gen. IM3 SWITCH SWITCH Always available Available only when bit TEST-EN = 1 Figure 55 AC Test Loops DuSLIC-S Data Sheet + ACN/ACP PD-AC-PO PD-AC-DA POFI DAC + + b IM-DIS duslic_0023_intstru_slicofi2S_c.wmf 134 2000-07-14 DuSLIC Preliminary Operational Description AC-DLB-32K a AX2 16K COX16 HPX2 LPX FRX AX1 HPX1 M U-LAW LIN CMP PCM OUT: Transmit Data to PCM or IOM-2 Interface AX-DIS HPX-DIS LPRX-CR FRX-DIS AX-DIS HPX-DIS AC-DLB-8K TH P C M 2D C AR-DIS b AR2 c LPX-CR LPR FRR-DIS FRR HPR-DIS HPR AR-DIS COR8 AR1 + EXP PCM IN: COR-64 TH-DIS PTG , TG 1-EN, TG 2-EN TG TG M U-LAW Receive Data from PCM LIN or IOM-2 Interface PD-AC-GN ITAC PD-AC-PR AC-XGAIN PD-AC-AD AC-DLB-4M PREFI ADC AC-DLB-128K a IM1 HIM-AN OPIM_4M OPIM_AN IM2 IM3 Programmable via CRAM Not Programmable SWITCH Available only when bit TEST-EN = 1 Figure 56 AC Test Loops DuSLIC-S2 Data Sheet + SWITCH Always available ACN/ACP PD-AC-PO PD-AC-DA POFI DAC + b IM-DIS duslic_0023_intstru_slicofi2S_a.wmf 135 2000-07-14 DuSLIC Preliminary Operational Description *O F F S E T -H [7 :0 ] O F F S E T -L [7 :0 ] OFFSET* IT PD-DC-PR DC PREFI PD-DC-AD DC ADC + LP RTR-SEL Hook R N G -O FFSET [1:0] DC Char. RG RO1 RO1 RO1 PD-DCBUF DCN/DCP DC BUF PC-POFI-HI DC POFI PD-DC-DA DC DAC + + c PC M 2D C Programmable via CRAM PD-OFHK IT OFFHOOK COMP PD-OVTC OVERT. COMP Not Programmable PD-GNKC SWITCH SWITCH Always available Available only when bit TEST-EN = 1 IL GNK COMP C1 C2 HV-INT. PD-HVI duslic_0023_intstru_slicofi2S_b.wmf Figure 57 DC Test Loops DuSLIC-S/-S2 Data Sheet 136 2000-07-14 DuSLIC Preliminary Operational Description 4.10 Caller ID Buffer Handling of SLICOFI-2 This chapter intends to describe the handling of the caller ID buffer and the corresponding handshake bits in the interrupt registers. Programming Sequence In order to send a caller ID information over the telephone line the following sequence should be programmed between the first and the second ring burst. The initialization part of the coefficients in the POP registers 43h to 4Ah must be done prior to that sequence. 1. Enable the extended feature DSP in register XCR (EDSP-EN = 1) 2. Enable the caller ID sender feature in register BCR5 (CIS-EN = 1) 3. Wait for an interrupt. 4. Read out all 4 interrupt registers to serve the interrupt and check the CIS-REQ bit. 5. If this bit is set, send at least BRS + 2 bytes (see POP register CIS-BRS) of caller ID data but not more than 48 bytes to the caller ID sender buffer register CIS-DAT. 6. Wait for the next interrupt and check again the CIS-REQ bit. 7. If this bit is set, send the next data to the caller ID-data buffer but not more than (48 - BRS) bytes. CIS-REQ bit gets reset to zero, if the data buffer is filled again above the Caller ID sender buffer request size (BRS). 8. Repeat steps 6 and 7 as long as there is data to be sent. 9. Right after sending the last data byte to the caller ID sender buffer, set the bit CISAUTO to 1 and the bit CIS-EN to 0. After processing the last bit the caller ID sender will stop automatically and set the CIS-ACT bit in INTREG4 to zero. No more CIS interrupt will be generated until the caller ID sender will be enabled again (interrupt bits: CIS-BOF, CIS-BUF and CIS-REQ). The end of the CID transmission can also be controlled by not setting CIS-AUTO and leaving CIS-EN at one. If the caller ID buffer gets empty, an interrupt is generated to indicate buffer underflow (CIS-BUF). If CIS-BUF is set, set CIS-EN to zero with at least 1 ms delay, in order to allow to send the last bit of caller ID data. In case of errors in the handling of the CID data buffer CIS-BUF (buffer underflow) and CIS-BOF (buffer overflow) indicate these errors. Please stop CID transmission in any of these cases since unpredictable results may occur. Note: CID data will be sent out LSB first If CIS-FRM is set to one: seizure and mark bits are generated automatically (according to the settings of CIS-SEIZ-H/L and CIS-MARK-H/L) as well as start and stop bits for every byte Data Sheet 137 2000-07-14 DuSLIC Preliminary Interfaces 5 Interfaces The DuSLIC connects the analog subscriber to the digital switching network by two different types of digital interfaces to allow for the highest degree of flexibility in different applications: * PCM interface combined with a serial microcontroller interface * IOM-2 interface. The PCM/IOM-2 pin selects the interface mode. PCM/IOM-2 = 0: The IOM-2 interface is selected. PCM/IOM-2 = 1: The PCM/C interface is selected. The analog TIP/RING interface connects the DuSLIC to the subscriber. 5.1 PCM Interface with a Serial Microcontroller Interface In PCM/C interface mode, voice and control data are separated and handled by different pins of the SLICOFI-2x. Voice data are transferred via the PCM highways while control data are using the microcontroller interface. 5.1.1 PCM Interface The serial PCM interface is used to transfer A-law or -law-compressed voice data. In test mode, the PCM interface can also transfer linear data. The eight pins of the PCM interface are used as follows (two PCM highways): PCLK: FSC: DRA: DRB: DXA: DXB: TCA: TCB: PCM Clock, 128 kHz to 8192 kHz Frame Synchronization Clock, 8 kHz Receive Data Input for PCM Highway A Receive Data Input for PCM Highway B Transmit Data Output for PCM Highway A Transmit Data Output for PCM Highway B Transmit Control Output for PCM Highway A, Active low during transmission Transmit Control Output for PCM Highway B, Active low during transmission The FSC pulse identifies the beginning of a receive and transmit frame for both channels. The PCLK clock signal synchronizes the data transfer on the DXA (DXB) and DRA (DRB) lines. On all channels, bytes are serialized with MSB first. As a default setting, the rising edge indicates the start of the bit, while the falling edge is used to buffer the contents of the received data on DRA (DRB). If double clock rate is selected (PCLK Data Sheet 138 2000-07-14 DuSLIC Preliminary Interfaces clock rate is twice the data rate), the first rising edge indicates the start of a bit, while, by default, the second falling edge is used to buffer the contents of the data line DRA (DRB). 125 s FSC PCLK DRA Time Slot 0123 High 'Z' Time Slot High 'Z' 31 DXA TCA Detail A DETAIL A: FSC Clock 01234567 PCLK DRA Bit High 'Z' Voice Data 76543210 Voice Data High 'Z' DXA TCA ezm14046.wmf Figure 58 General PCM Interface Timing The data rate of the interface can vary from 2*128 kbit/s to 2*8192 kbit/s (two highways). A frame may consist of up to 128 time slots of 8 bits each. The time slot and PCM Data Sheet 139 2000-07-14 DuSLIC Preliminary Interfaces highway assignment for each DuSLIC channel can be programmed. Receive and transmit time slots can also be programmed individually. When DuSLIC is transmitting data on DXA (DXB), pin TCA (TCB) is activated to control an external driving device. The DRA/B and DXA/B pins may be connected to form a bidirectional data pin for special purposes, e.g., for the Serial Interface Port (SIP) with the Subscriber Line Data (SLD) bus. The SLD approach provides a common interface for analog or digital per-line components. For more details, please see the "ICs for Communications"1) User's Manual available from Infineon Technologies on request. Table 37 shows PCM interface examples; other frequencies (e.g., 1536 kHz) are also possible. Table 37 SLICOFI-2x PCM Interface Configuration Single/Double Clock [1/2] 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 Time Slots [per highway] 2 2 4 4 8 6 12 8 16 16 32 32 64 64 128 f/64 f/128 Data Rate [kbit/s per highway] 128 128 256 256 512 384 768 512 1024 1024 2048 2048 4096 4096 8192 f f/2 Clock Rate PCLK [kHz] 128 256 256 512 512 768 768 1024 1024 2048 2048 4096 4096 8192 8192 f f Valid PCLK clock rates are: f = n x 64 kHz (2 n 128) 1) Ordering No. B115-H6377-X-X-7600, published by Infineon Technologies. Data Sheet 140 2000-07-14 DuSLIC Preliminary Interfaces FSC transmit slope receive slope Single Clock Mode PCLK PCMC1: DBLCLK XSLOPE RSLOPE NODRIVE SHIFT PCMO[2:0] 0 DBLCLK 0 XSLOPE 0 RSLOPE 0 NODRIVE 0 SHIFT 0 0 PCMO[2:0] 0 0 DBLCLK 0 XSLOPE 1 RSLOPE 0 NODRIVE 0 SHIFT 0 0 PCMO[2:0] 0 0 DBLCLK 1 XSLOPE 0 RSLOPE 0 NODRIVE 0 SHIFT 0 0 PCMO[2:0] 0 0 Bit 7 Time-Slot 0 1 1 0 0 0 0 0 Double Clock Mode PCMC1: DBLCLK XSLOPE RSLOPE NODRIVE SHIFT PCMO[2:0] PCLK 1 DBLCLK 0 XSLOPE 0 RSLOPE 0 NODRIVE 0 SHIFT 0 0 PCMO[2:0] 0 1 DBLCLK 0 XSLOPE 1 RSLOPE 0 NODRIVE 0 SHIFT 0 0 PCMO[2:0] 0 1 DBLCLK 1 XSLOPE 0 RSLOPE 0 NODRIVE 0 SHIFT 0 0 PCMO[2:0] 0 1 1 1 0 0 0 0 0 ezm22011.wmf Figure 59 Setting of Slopes in Register PCMC1 Data Sheet 141 2000-07-14 DuSLIC Preliminary Interfaces 5.1.2 Control of the Active PCM Channels The SLICOFI-2x offers additional functionality on the PCM interface including threeparty conferencing and a 16 kHz sample rate. Five configuration bits control, together with the PCM configuration registers, the activation of the PCM transmit channels. For details of the different functions see Chapter 6.2. Table 38 gives an overview of the data transmission configuration of the PCM channels. X1L is used only when linear data are transmitted. In this case the time slot for X1 is defined by the number X1-TS from the PCMX1 register. The time slot for X1L is defined by the number X1-TS + 1. Table 38 PCMXEN 0 1 1 0 1 1 0 1 1 0 1 1 1 1 Active PCM Channel Configuration Bits Control Bits CONF- CONFX- PCM16K LIN EN EN 0 0 0 1 1 1 0 0 0 1 1 1 - - 0 0 0 0 0 0 1 1 1 1 1 1 - - - 0 0 - 0 0 - 0 0 - 0 0 1 1 - 0 1 - 0 1 - 0 1 - 0 1 0 1 X1 - PCM HB - PCM HB - PCM HB - PCM HB DS1 HB1 Transmit PCM Channel X1L - - LB - - LB - - LB - - LB - - X2 - - - PCM PCM PCM PCM PCM PCM PCM PCM PCM - LB1 X3 - - - PCM PCM PCM PCM PCM PCM PCM PCM PCM DS2 HB2 X4 - - - - - - PCM PCM PCM PCM PCM PCM - LB2 Note: PCM means PCM-coded data (A-law / -law) HB1, HB2, LB1, LB2 indicate the high byte, low byte of linearly transmitted data for an 8 kHz (16 kHz) sample rate. Modes in rows with gray background are for testing purposes only. Data Sheet 142 2000-07-14 DuSLIC Preliminary Interfaces 5.1.3 Serial Microcontroller Interface The microcontroller interface consists of four lines: CS, DCLK, DIN and DOUT. CS DCLK DIN DOUT A synchronization signal starting a read or write access to SLICOFI-2x. A clock signal (up to 8.192 MHz) supplied to SLICOFI-2x. Data input carries data from the master device to the SLICOFI-2x. Data output carries data from SLICOFI-2x to a master device. There are two different command types. Reset commands have just one byte. Read/ write commands have two command bytes with the address offset information located in the second byte. A write command consists of two command bytes and the following data bytes. The first command byte determines whether the command is read or write, how the command field is to be used, and which DuSLIC channel (A or B) is written. The second command byte contains the address offset. A read command consists of two command bytes written to DIN. After the second command byte is applied to DIN, a dump-byte consisting of `1's is written to DOUT. Data transfer starts with the first byte following the `dump-byte'. CS n Data Bytes write command DIN Comm 1st Comm 2nd Data Data Data Data Byte n Data Byte 1 DCLK CS Single Byte write command DIN Comm 1st ezm14057.emf Figure 60 1) Serial Microcontroller Interface Write Access1) for n data bytes and single byte command Data Sheet 143 2000-07-14 DuSLIC Preliminary Interfaces CS DIN Comm 1st Comm 2nd DCLK DOUT * 'Dump Byte' Data Data Byte 1 Data Data Data Byte n * * high impedance ezm14058.wmf Figure 61 Serial Microcontroller Interface Read Access Programming the Microcontroller Interface Without Clocks at FSC, MCLK, PCLK The SLICOFI-2x can also be programmed via the C interface without any clocks connected to the FSC, MCLK, PCLK pins. This can be useful in Power Down modes when further power saving on system level is necessary. In this case a data clock of up to 1.024 MHz can be used on pin DCLK. Since the SLICOFI-2x will leave the basic reset routine only if clocks at the FSC, MCLK and PCLK pins are applied, it is not possible to program the SLICOFI-2x without any clocks at these pins directly after the hardware reset or power on reset. Data Sheet 144 2000-07-14 DuSLIC Preliminary Interfaces 5.2 The IOM-2 Interface IOM-2 defines an industry-standard serial bus for interconnecting telecommunication ICs for a broad range of applications - typically ISDN-based applications. The IOM-2 bus provides a symmetrical full-duplex communication link containing data, control/programming and status channels. Providing data, control and status information via a serial channel reduces pin count and cost by simplifying the line card layout. The IOM-2 Interface consists of two data lines and two clock lines as follows: DU: DD: FSC: DCL: Data Upstream carries data from the SLICOFI-2x to a master device. Data Downstream carries data from the master device to the SLICOFI-2x. A Frame Synchronization Signal (8 kHz) supplied to SLICOFI-2x. A Data Clock Signal (2048 kHz or 4096 kHz) supplied to SLICOFI-2x. SLICOFI-2x handles data as described in the IOM-2 specification1) for analog devices. 125 s FSC DCL DD DU TS0 TS0 TS1 TS1 TS2 TS2 TS3 TS3 TS4 TS4 TS5 TS5 TS6 TS6 TS7 TS7 Detail A Detail A DD DU Voice Channel A Voice Channel B Voice Channel A Voice Channel B Monitor Channel C/I Channel Monitor Channel C/I Channel MR MX MR MX ezm04104.emf Figure 62 IOM-2 Int. Timing for up to 16 Voice Channels (Per 8-kHz Frame) 1) Available on request from Infineon Technologies. Data Sheet 145 2000-07-14 DuSLIC Preliminary Interfaces The information is multiplexed into frames, which are transmitted at an 8-kHz rate. The frames are subdivided into 8 sub-frames, with one sub-frame dedicated to each transceiver or pair of codecs (in this case, two SLICOFI-2x channels). The sub-frames provide channels for data, programming and status information for a single transceiver or codec pair. 125 s FSC DCL 4096 kHz DD DU TS0 TS0 Detail B TS1 TS1 TS2 TS2 TS3 TS3 TS4 TS4 TS5 TS5 TS6 TS6 TS7 TS7 Detail B FSC DCL DD/DU Bit N Bit 0 Bit 1 ezm04105.emf Figure 63 IOM-2 Interface Timing (DCL = 4096 kHz, Per 8-kHz Frame) Data Sheet 146 2000-07-14 DuSLIC Preliminary Interfaces 125 s FSC DCL 2048 kHz DD DU TS0 TS0 Detail C TS1 TS1 TS2 TS2 TS3 TS3 TS4 TS4 TS5 TS5 TS6 TS6 TS7 TS7 Detail C FSC DCL DD/DU Bit N Bit 0 Bit 1 ezm04106.emf Figure 64 IOM-2 Interface Timing (DCL = 2048 kHz, Per 8-kHz Frame) Both DuSLIC channels (see Figure 62) can be assigned to one of the eight time slots. Set the IOM-2 time slot selection as shown in Table 39 below by pin-strapping. In this way, up to 16 channels can be handled with one IOM-2 interface on the line card. Table 39 TS2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 IOM-2 Time Slot Assignment TS1 TS0 0 1 0 1 0 1 0 1 IOM-2 Operating Mode Time slot 0; DCL = 2048, 4096 kHz Time slot 1; DCL = 2048, 4096 kHz Time slot 2; DCL = 2048, 4096 kHz Time slot 3; DCL = 2048, 4096 kHz Time slot 4; DCL = 2048, 4096 kHz Time slot 5; DCL = 2048, 4096 kHz Time slot 6; DCL = 2048, 4096 kHz Time slot 7; DCL = 2048, 4096 kHz 2 MHz or 4 MHz DCL is selected by the SEL24 pin: SEL24 = 0: DCL = 2048 kHz SEL24 = 1: DCL = 4096 kHz Data Sheet 147 2000-07-14 DuSLIC Preliminary Interfaces 5.2.1 IOM-2 Interface Monitor Transfer Protocol Monitor Channel Operation The monitor channel is used for the transfer of maintenance information between two functional blocks. Using two monitor control bits (MR and MX) per direction, the data are transferred in a complete handshake procedure. The MR and MX bits in the fourth byte (C/I channel) of the IOM-2 frame are used for the handshake procedure of the monitor channel. The monitor channel transmission operates on a pseudo-asynchronous basis: Data transfer (bits) on the bus is synchronized to Frame Sync FSC. Data flow (bytes) is asynchronously controlled by the handshake procedure. For example: Data is placed onto the DD-Monitor-Channel by the monitor transmitter of the master device (DD-MX-Bit is activated, i.e., set to zero). This data transfer will be repeated within each frame (125 s rate) until it is acknowledged by the SLICOFI-2x monitor receiver by setting the DU-MR-bit to zero, which is checked by the monitor transmitter of the master device. The data rate on IOM-2 monitor channels is 4 kb/s. MX Monitor Transmitter MR DD MX Monitor Receiver MR DU MR Monitor Receiver MX MX MR Monitor Transmitter Master Device SLICOFI-2x ezm04125.emf Figure 65 IOM-2 Interface Monitor Transfer Protocol Data Sheet 148 2000-07-14 DuSLIC Preliminary Monitor Handshake Procedure The monitor channel works in three states - idle state: - sending state: - acknowledging: A pair of inactive (set to `1') MR and MX bits during two or more consecutive frames: End of Message (EOM) MX bit is activated (set to zero) by the monitor transmitter, together with data bytes (can be changed) on the monitor channel MR bit is set to active (set to zero) by the monitor receiver, together with a data byte remaining in the monitor channel. Interfaces A start of a transmission is initiated by a monitor transmitter in sending out an active MX bit together with the first byte of data (the address of the receiver) to be transmitted in the monitor channel. The monitor channel remains in this state until the addressed monitor receiver acknowledges the received data by sending out an active MR bit, which means that the data transmission is repeated each 125 s frame (minimum is one repetition). During this time the monitor transmitter evaluates the MR bit. Flow control can only take place when the transmitter's MX and the receiver's MR bit are in active state. Since the receiver is capable to receive the monitor data at least twice (in two consecutive frames), it is able to check for data errors. If two different bytes are received, the receiver will wait for the receipt of two identical successive bytes (last look function). A collision resolution mechanism (checking whether another device is trying to send data during the same time) is implemented in the transmitter. This is done by looking for the inactive (`1') phase of the MX bit and making a per-bit collision check on the transmitted monitor data (check if transmitted `1's are on DU/DD line; DU/DD line are open-drain lines). Any abort leads to a reset of the SLICOFI-2x command stack, the device is ready to receive new commands. To maximum speed during data transfers the transmitter anticipates the falling edge of the receivers acknowledgment. Due to the programming structure, duplex operation is not possible. It is not allowed to send any data to the SLICOFI-2x, while transmission is active. Data transfer to the SLICOFI-2x starts with a SLICOFI-2x-specific address byte (81H). Attention: Each byte on the monitor channel has to be sent twice at least according to the IOM-2 Monitor handshake procedure. Data Sheet 149 2000-07-14 DuSLIC Preliminary Interfaces MR + MXR MXR Idle MX = 1 MR MXR wait MX = 1 MR MXR abort MX = 1 initial state MR RQT MR 1st byte MX = 0 MR RQT EOM MX = 1 MR MR RQT nth byte ack MX = 1 MR MR MR RQT wait for ack MX = 0 MR RQT CLS/ABT any state ezm04126.emf Figure 66 MR ... MX ... MXR ... CLS ... RQT ... ABT ... Data Sheet State Diagram of the SLICOFI-2x Monitor Transmitter MR bit received on DD line MX bit calculated and expected on DU line MX bit sampled on DU line Collision within the monitor data byte on DU line Request for transmission form internal source Abort request/indication 150 2000-07-14 DuSLIC Preliminary Interfaces Idle MR = 1 MX LL MX 1st byte MX rec. MR = 0 abort MR = 1 initial state MX ABT any state MX MX byte valid MR = 0 MX LL wait for LL MR = 0 MX LL MX MX LL MX new byte MR = 1 nth byte rec. MR = 1 MX LL MX LL wait for LL MR = 0 MX MX ezm04127.emf Figure 67 MR ... MX ... LL ... ABT ... State Diagram of the SLICOFI-2x Monitor Receiver MR bit calculated and transmitted on DU line MX bit received data downstream (DD line) Last lock of monitor byte received on DD line Abort indication to internal source Data Sheet 151 2000-07-14 DuSLIC Preliminary Address Byte Messages to and from the SLICOFI-2x start with the following byte: Bit 7 1 6 0 5 0 4 0 3 0 2 0 1 0 0 1 Interfaces 5.2.2 SLICOFI-2x Identification Command (only IOM-2 Interface) In order to unambiguously identify different devices by software, a two-byte identification command is defined for analog line IOM-2 devices. A device requesting the identification of the SLICOFI-2x will send the following two byte code: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Each device will then respond with its specific identification code. For the SLICOFI-2x this two byte identification code is: 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 5.3 TIP/RING Interface The TIP/RING interface is the interface that connects the subscriber to the DuSLIC. It meets the ITU-T recommendation Q.552 for a Z interface and applicable LSSGR. For the performance of the TIP/RING interface see Chapter 7.5 and Chapter 7.6, for application circuits see Chapter 8. Data Sheet 152 2000-07-14 DuSLIC Preliminary Interfaces 5.4 SLICOFI-2S/-2S2 and SLIC-S/-S2 Interface The SLIC-S/-S2 PEB 4264/-2 operates in the following modes controlled by a ternary logic signal at the C1 and C2 input: Table 40 SLIC-S/-S2 Interface Code C2 (Pin 17) L C1 (Pin 18) L1) M H 1) M PDRHL ACTH HIT H PDRH ACTR HIR PDH ACTL unused no "Overtemp" signaling possible via pin C1 if C1 is low. Table 41 SLIC Mode PDH PDRH PDRHL ACTL ACTH ACTR HIT HIR SLIC-S/-S2 Modes Mode Description Power Down High Impedance Used SLIC-S/-S2 Battery Voltage VBATH Power Down Resistive High VBATH Power Down Resistive High Load VBATH Active Low VBATL Active High VBATH Active Ring VBATH, VHR High Impedance on TIP VBATH, VHR High Impedance on RING VBATH, VHR Data Sheet 153 2000-07-14 DuSLIC Preliminary Interfaces Active (ACTL, ACTH): These are the regular transmit and receive modes for voice band. The line driving section is operated between VBATL, VBATH and VBGND. Active Ring (ACTR): In order to provide a balanced ring signal of up to 45 Vrms or to drive longer telephone lines, an auxiliary positive battery voltage VHR is used, making possible a higher voltage across the line. Transmission performance remains unchanged compared with Active modes. The Power Down mode PDRH is intended to reduce the power consumption of the linecard to a minimum: the SLIC-S/-S2 is switched off completely, no operation is available except off-hook detection. With respect to the output impedance of TIP and RING, two Power Down modes have to be distinguished: PDRH provides a connection of 5 k each from TIP to VBGND and RING to VBATH, respectively, while the outputs of the buffers show high impedance. The current through these resistors is sensed and transferred to the IT pin to allow off-hook supervision. PDRHL is used as a transition state at a mode change from PDRH or PDH to ACTH mode (automatically initiated by SLICOFI-2S/-2S2 at a mode change). High Impedance (HIR/HIT): In this mode each of the line outputs can be programmed to show high impedance. HIT switches off the TIP buffer, while the current through the RING output still can be measured by IT or IL. Programming HIR switches off the RING buffer. Data Sheet 154 2000-07-14 DuSLIC Preliminary Interfaces PEB 4264/-2 Off-hook (IRO + ITO) / 10 (IR + IT) / 100 BGND PDRHL PDRH ITO 60k 5k TIP IT VBI SymFi 2k + + PEB 3264/-2 VHI VHR VH Switch BGND IT IL ILA CITA ITACA Current Sensor (IR - IT) / 200 RILA RIT1A RIT2A - CVCMITA VCMITA VCM ITA VHI 10k 2k 2k S1 S1 ACN ACNA DCN DCNA CEXT VHI RING IR 5k 60k IRO PDRHL PDRH 2k - S2 DCP DCPA 10k S1, S2 closed: ACTR, HIT, HIR ACP ACPA VCMS VCMS VBATL VBATH (Sub) VBAT Switch VBI BIAS Logik C1 C2 C1A C2A AGND VDD(3.3 V) VDD (+5 V) AGND ezm29204.emf Figure 68 Interface SLICOFI-2S/-2S2 and SLIC-S/-S2 Capacitor and resistor values are specified in Chapter 8. Data Sheet 155 2000-07-14 DuSLIC Preliminary Interfaces 5.5 SLICOFI-2 and SLIC-E/-E2 Interface The SLIC-E/-E2 PEB 4265/-2 operates in the following modes controlled by a ternary logic signal at the C1 and C2 input: Table 42 SLIC-E/-E2 Interface Code C2 L C1 L1) M H 1) M PDRHL ACTH HIT H PDRH ACTR HIR PDH ACTL HIRT no "Overtemp" signaling possible via pin C1 if C1 is low. Table 43 SLIC Mode PDH PDRH PDRHL ACTL ACTH ACTR HIRT HIT HIR SLIC-E/-E2 Modes Mode Description Power Down High Impedance Used SLIC-E/-E2 Battery Voltage VBATH Power Down Resistive High VBATH Power Down Resistive High Load VBATH Active Low VBATL Active High VBATH Active Ring VBATH, VHR High Impedance on RING and TIP VBATH, VHR High Impedance on TIP VBATH, VHR High Impedance on RING VBATH, VHR Data Sheet 156 2000-07-14 DuSLIC Preliminary Interfaces High Impedance (HIR/HIT/HIRT): In this mode each of the line outputs can be programmed to show high impedance. HIT switches off the TIP buffer, while the current through the RING output still can be measured by IT or IL. Programming HIR switches off the RING buffer. In the mode HIRT both buffers show high impedance. Active (ACTL, ACTH): These are the regular transmit and receive modes for voice band. The line driving section is operated between VBATL, VBATH and VBGND. Active Ring (ACTR): In order to provide a balanced ring signal of up to 85 Vrms or to drive longer telephone lines, an auxiliary positive battery voltage VHR is used, making possible a higher voltage across the line. Transmission performance remains unchanged compared with Active modes. The Power Down modes are intended to reduce the power consumption of the linecard to a minimum: the SLIC-E/-E2 is switched off completely, no operation is available. With respect to the output impedance of TIP and RING, three Power Down modes have to be distinguished: A resistive one (PDRH) provides a connection of 5 k each from TIP to VBGND and RING to VBATH, respectively, while the outputs of the buffers show high impedance. The current through these resistors is sensed and transferred to the IT pin to allow off-hook supervision. PDRHL is used as a transition mode at a mode change from PDRH mode to ACTH mode (automatically initiated by SLICOFI-2 at a mode change from PDRH to ACTH). The other mode (PDH) offers high impedance at TIP and RING. Data Sheet 157 2000-07-14 DuSLIC Preliminary Interfaces PEB 4265/-2 Off-hook (IRO + ITO) / 10 (IR + IT) / 100 BGND PDRHL PDRH ITO 60k 5k TIP IT VBI SymFi 2k + + PEB 3265 VHI VH Switch VHR BGND IT IL ILA CITA Current Sensor ITACA (IR - IT) / 200 RILA RIT1A RIT2A - CVCMITA VCMITA VCM ITA VHI 10k 2k 2k ACN S1 ACNA DCN DCNA CEXT VHI RING IR 5k 60k IRO PDRHL PDRH 2k - S2 DCP DCPA 10k S1, S2 closed: ACTR, HIT, HIR, HIRT ACP ACPA VCMS VCMS VBATL VBATH (Sub) VBAT Switch VBI BIAS Logik C1 C2 C1A C2A AGND VDD(3.3 V) VDD (+5 V) AGND ezm20204.emf Figure 69 Interface SLICOFI-2 and SLIC-E/-E2 Capacitor and resistor values are specified in Chapter 8. Data Sheet 158 2000-07-14 DuSLIC Preliminary Interfaces 5.6 SLICOFI-2 and SLIC-P Interface The SLIC-P PEB 4266 operates in the following modes controlled by a ternary logic signal at the C1, C2 inputs and a binary logic signal at C3 input: Table 44 SLIC-P Interface Code C2 L L1) C1 M H PDH ACTL HIRT M PDRR PDRHL ACTH HIT ROT C3 = H or L 1) 2) H PDRRL PDRH ACTR HIR ROR C3 = L2) C3 = H2) no "Overtemp" signaling possible via pin C1 if C1 is low. C3 pin of SLIC-P is typically connected to IO2 pin of SLICOFI-2. For extremely power-sensitive applications using external ringing the C3 pin can be connected to GND. In this case, SEL-SLIC[1:0] in register BCR1 has to be set to 10. Operating Modes for SLIC-P with Two Battery Voltages (VBATH, VBATL) for Voice and an Additional Voltage (VBATR) for Ringing: Table 45 SLIC Mode PDH PDRH PDRHL ACTL ACTH ACTR HIRT ROR ROT SLIC-P Modes Mode Description Power Down High Impedance Used SLIC-P Battery Voltage VBATR Power Down Resistive High VBATH Power Down Load Resistive High VBATH Load VBATL Active High VBATH Active Ring VBATR High Impedance on RING and TIP VBATR Ring on RING VBATR Ring on TIP VBATR Active Low Data Sheet 159 2000-07-14 DuSLIC Preliminary Interfaces Active (ACTL, ACTH): These are the regular transmit and receive modes for voice band. The line driving section is operated between VBATL, VBATH and VBGND. Ringing: Active Ring (ACTR): In order to provide a balanced ring signal of up to 85 Vrms or to drive longer telephone lines, an additional negative battery voltage VBATR is used, making possible a higher voltage across the line. Transmission performance remains unchanged compared with ACT mode. Ring on Tip (ROT): An unbalanced ring signal up to 50 Vrms can be fed to the Tip line. The Ring line is fixed to a potential near VBGND. Ring on Ring (ROR): An unbalanced ring signal up to 50 Vrms can be fed to the Ring line. The Tip line is fixed to a potential near VBGND. PDRH is a power down mode providing a connection of 5 k each from TIP to VBGND and RING to VBATH, respectively, while the outputs of the buffers show high impedance. The current through these resistors is sensed and transferred to the IT pin to allow offhook supervision. PDRHL is used as a transition mode at a mode change from PDRH mode to ACTH mode (automatically initiated by SLICOFI-2 at a mode change from PDRH to ACTH). Operating Modes for SLIC-P with Three Battery Voltages (VBATH, VBATL, VBATR) for voice and External Ringing Table 46 SLIC Mode PDH PDRR PDRRL ACTL ACTH ACTR HIRT HIT HIR SLIC-P Modes Mode Description Power Down High Impedance Used SLIC-P Battery Voltage VBATR Power Down Resistive Ring VBATR Power Down Load Resistive Ring VBATR Load VBATL Active High VBATH Active Ring VBATR High Impedance on RING and TIP VBATR High Impedance on TIP VBATR High Impedance on RING VBATR Active Low Data Sheet 160 2000-07-14 DuSLIC Preliminary Interfaces Active (ACTL, ACTH, ACTR): These are the regular transmit and receive modes for voice band. The line driving section is operated between VBATL, VBATH, VBATR and VBGND. PDRR is a power down mode providing a connection of 5 k each from TIP to VBGND and RING to VBATR, respectively, while the outputs of the buffers show high impedance. The current through these resistors is sensed and transferred to the IT pin to allow offhook supervision. PDRRL is used as a transition mode at a mode change from PDRR mode to ACTR mode (automatically initiated by SLICOFI-2 at a mode change from PDRR to ACTR). High Impedance (HIR/HIT): In this mode each of the line outputs can be programmed to show high impedance. HIT switches off the TIP buffer, while the current through the RING output still can be measured by IT or IL. Programming HIR switches off the RING buffer. For Both Operating Modes of SLIC-P (Ringing and Non Ringing): The Power Down modes are intended to reduce the power consumption of the linecard to a minimum: the PEB 4266 is switched off completely, no operation is available. With respect to the output impedance of TIP and RING, the following Power Down modes have to be distinguished: The PDH mode offers high impedance at TIP and RING. High Impedance (HIRT): The output buffers of the Tip and Ring line show high impedance. Data Sheet 161 2000-07-14 DuSLIC Preliminary Interfaces PEB 4266 Off-hook (IR0 + IT0) / 10 (IR + IT) / 100 BGND PDRR PDRRL PDRH PDRHL 5k TIP IT VBI SymFi DCP 2k + + PEB3265 BGND IT CITA Current sensor ITACA ILA (IR - IT) / 200 IL RILA RIT1A IT0 BGND 60k - CVCMITA VCMITA VCM RIT2A 10k 2k 2k ACN S1 DCN ITA ACNA DCNA CEXT DCPA S2 ACP ACPA RING IR 5k 60k IR0 PDRR PDRRL VBATL VBATH VBATR (SUB) Battery switch VBI BIAS PDRH PDRHL - 2k 10k S1, S2 closed: ACTR, ROT, ROR, HIT, HIR, HIRT VCMS VCMS C1 C2 C3 Logic C1A C2A IO2A AGND VDD(+3.3 V) AGND VDD(+5 V) ezm14041.emf Figure 70 Interface SLICOFI-2 and SLIC-P Capacitor and resistor values are specified in Chapter 8. Data Sheet 162 2000-07-14 DuSLIC Preliminary SLICOFI-2x Command Structure and Programming 6 SLICOFI-2x Command Structure and Programming With the commands described in this chapter, the SLICOFI-2x can be programmed, configured and tested very flexibly via the microcontroller interface or via the IOM-2 interface monitor channel. The command structure uses one and two-byte commands in order to ensure a high flexible and quick programming procedure for the most common commands. Structure of the First Command Byte The first command byte includes the R/W bit, the addresses of the different channels and the command type. Bit 7 RD 6 OP 5 4 ADR[2:0] 3 2 1 CMD[2:0] 0 RD Read Data RD = 0 Write data to chip. RD = 1 Read data from chip. OP Selects the usage of the CMD field OP = 0 The CMD field works as a CIOP (Command/Indication Operation) command and acts like the M[2:0] bits located in the CIDD byte of the IOM Interface (C interface mode only). See Table 47. . Bit 7 0 6 0 5 4 ADR[2:0] 3 2 M2 1 M1 0 M0 OP = 1 The CMD field acts as the SOP, COP or POP command described below. Data Sheet 163 2000-07-14 DuSLIC Preliminary Table 47 SLICOFI-2x Command Structure and Programming M2, M1, M0: General Operating Mode SLICOFI-2x Operating Mode (for details see "Operating Modes for the DuSLIC Chip Set" on Page 78) Sleep, Power Down (PDRx) Power Down High Impedance (PDH) Any Active mode Ringing (ACTR Burst On) Active with Metering Ground Start Ring Pause Command/Indication Operation (CIOP) M2 1 0 0 1 1 1 0 ADR[2:0] M1 1 0 1 0 1 0 0 M0 1 0 0 1 0 0 1 Channel address for the subsequent data ADR[2:0] = 0 0 0 ADR[2:0] = 0 0 1 Channel A Channel B (other codes reserved for future use) CMD[2:0] Command for programming the SLICOFI-2x (OP = 1) or command equivalent to the CIDD channel bits M[2:0] in microcontroller interface mode (OP = 0) The first four commands have no second command byte following. All necessary information is present in the first command byte. CMD[2:0] = 0 0 0 Soft reset of the chip (Reset routine for all channels will reset all configuration registers, CRAM data is not affected). Soft reset for the specified channel A or B in ADR field Resychronization of the PCM interface (only available when pin PCM/IOM-2 = 1) reserved for future use CMD[2:0] = 0 0 1 CMD[2:0] = 0 1 0 CMD[2:0] = 0 1 1 The second four commands are followed by a second command byte which defines additional information, e.g., specifying sub-adresses of the CRAM. CMD[2:0] = 1 0 0 CMD[2:0] = 1 0 1 SOP command (status operation, programming and monitoring of all status-relevant data). COP command (coefficient operation, programming and monitoring of all coefficients in the CRAM). Data Sheet 164 2000-07-14 DuSLIC Preliminary CMD[2:0] = 1 1 0 CMD[2:0] = 1 1 1 SLICOFI-2x Command Structure and Programming POP command (PINE access operation programming the EDSP). reserved for production tests Structure of the Second Command Byte The second command byte specifies a particular SOP, COP or POP command, depending on the CMD[2:0] bits of the first command byte. In the following sections, the content of this register is described for each command group. The second command byte specifies the initial offset for the subsequent data bytes. After each data byte transferred the internal offset is incremented automatically. Therefore it is possible to send a various number of data bytes with one SOP, COP or POP command. Writing over read-only registers will not destroy their contents. Register Description Example At the beginning of each register description a single line gives information about * * * * Offset: Offset of register address (hex) Name: Short name of the register Detailed name: Detailed name of the register Reset value: Value of the register after reset (hex) "hw" - value depends on specific hardware fuses * Test status: "T" - the register has no effect unless the TEST-EN bit in register LMCR1 is set to 1 * Channel selection: "N" - the register effects both SLICOFI-2x channels, "Y" - the register effects a specific SLICOFI-2x channel The line is organized as follows (with example): Offset 27H Name TSTR1 Detailed Name Test Register 1 Reset Value 00H Test T Per Channel Y Data Sheet 165 2000-07-14 DuSLIC Preliminary SLICOFI-2x Command Structure and Programming 6.1 SOP Bit Byte 1 Byte 2 Overview of Commands STATUS OPERATION 7 RD 6 1 5 4 ADR[2:0] OFFSET[7:0] 3 2 1 1 0 0 0 COP Bit Byte 1 Byte 2 COEFFICIENT OPERATION 7 RD 6 1 5 4 ADR[2:0] OFFSET[7:0] 3 2 1 1 0 0 1 POP Bit Byte 1 Byte 2 POP OPERATION (only SLICOFI-2 PEB 3265 used for DuSLIC-E/-E2/-P) 7 RD 6 1 5 4 ADR[2:0] OFFSET[7:0] 3 2 1 1 1 0 0 Data Sheet 166 2000-07-14 DuSLIC-E/-E2/-P Preliminary SLICOFI-2x Command Structure and Programming 6.2 SLICOFI-2 Command Structure and Programming This chapter comprises only the SLICOFI-2 PEB 3265 and therefore the DuSLIC-E, DuSLIC-E2 and DuSLIC-P chip sets. 6.2.1 SOP Command The SOP "Status Operation" command provides access to the configuration and status registers of the SLICOFI-2. Common registers change the mode of the entire SLICOFI-2 chip, all other registers are channel-specific. It is possible to access single or multiple registers. Multiple register access is realized by an automatic offset increment. Write access to read-only registers is ignored and does not abort the command sequence. Offsets may change in newer versions of the SLICOFI-2. (All empty register bits have to be filled with zeros.) 6.2.1.1 00H SOP Register Overview REVISION Revision Number (read-only) REV[7:0] 01H CHIPID 1 Chip Identification 1 (read-only) for internal use only 02H CHIPID 2 Chip Identification 2 (read-only) for internal use only 03H CHIPID 3 Chip Identification 3 (read-only) for internal use only 04H FUSE1 Fuse Register 1 for internal use only 05H PCMC1 DBL-CLK X-SLOPE PCM Configuration Register 1 R-SLOPE NO-DRIVE-0 SHIFT PCMO[2:0] 06H XCR EDSP-EN ASYNCH-R Extended Configuration Register 0 0 0 0 Data Sheet 167 2000-07-14 DuSLIC-E/-E2/-P Preliminary SLICOFI-2x Command Structure and Programming 07H INTREG1 INT-CH HOOK Interrupt Register 1 (read-only) GNDK GNKP ICON VRTLIM OTEMP SYNC-FAIL 08H INTREG2 LM-THRES READY Interrupt Register 2 (read-only) RSTAT LM-OK IO[4:1]-DU 09H INTREG3 DTMF-OK Interrupt Register 3 (read-only) DTMF-KEY[4:0] UTDR-OK UTDX-OK 0AH INTREG4 EDSP-FAIL 0 Interrupt Register 4 (read-only) 0 0 CIS-BOF CIS-BUF CIS-REQ CIS-ACT 0BH CHKR1 SUM-OK Checksum Register 1 (High Byte) (read-only) CHKSUM-H[6:0] 0CH CHKR2 Checksum Register 2 (Low Byte) (read-only) CHKSUM-L[7:0] 0DH LMRES1 Level Metering Result 1 (High Byte) (read-only) LM-VAL-H[7:0] 0EH LMRES2 Level Metering Result 2 (Low Byte) (read-only) LM-VAL-L[7:0] 0FH FUSE2 Fuse Register 2 for internal use only 10H FUSE3 Fuse Register 3 for internal use only 11H MASK READY-M HOOK-M Mask Register GNDK-M GNKP-M ICON-M VRTLIM-M OTEMP-M SYNC-M Data Sheet 168 2000-07-14 DuSLIC-E/-E2/-P Preliminary SLICOFI-2x Command Structure and Programming 12H IOCTL1 IO Control Register 1 IO[4:1]-INEN IO[4:1]-M 13H IOCTL2 IO Control Register 2 IO[4:1]-OEN IO[4:1]-DD 14H IOCTL3 IO Control Register 3 DUP[3:0] DUP-IO[3:0] 15H BCR1 HIR HIT Basic Configuration Register 1 SLEEP-EN REVPOL ACTR ACTL SEL-SLIC[1:0] 16H BCR2 REXT-EN SOFT-DIS Basic Configuration Register 2 TTX-DIS TTX-12K HIM-AN AC-XGAIN UTDX-SRC PDOT-DIS 17H BCR3 MU-LAW LIN Basic Configuration Register 3 PCM16K PCMX-EN CONFX-EN CONF-EN LPRX-CR CRAM-EN 18H BCR4 TH-DIS IM-DIS Basic Configuration Register 4 AX-DIS AR-DIS FRX-DIS FRR-DIS HPX-DIS HPR-DIS 19H BCR5 UTDR-EN UTDX-EN Basic Configuration Register 5 CIS-AUTO CIS-EN LEC-OUT LEC-EN DTMF-SRC DTMF-EN 1AH DSCR DTMF Sender Configuration Register DG-KEY[3:0] COR8 PTG TG2-EN TG1-EN 1BH reserved 0 0 0 0 0 0 0 0 Data Sheet 169 2000-07-14 DuSLIC-E/-E2/-P Preliminary SLICOFI-2x Command Structure and Programming 1CH LMCR1 TEST-EN LM-EN Level Metering Configuration Register 1 LM-THM PCM2DC LM2 PCM LM-ONCE LM-MASK DC-AD16 1DH LMCR2 LM-NOTCH LM-FILT Level Metering Configuration Register 2 LM-RECT RAMP-EN LM-SEL[3:0] 1EH LMCR3 AC-SHORTEN RTR-SEL Level Metering Configuration Register 3 LM-ITIME[3:0] RNG-OFFSET[1:0] 1FH OFR1 Offset Register 1 (High Byte) OFFSET-H[7:0] 20H OFR2 Offset Register 2 (Low Byte) OFFSET-L[7:0] 21H PCMR1 R1-HW PCM Receive Register 1 R1-TS[6:0] 22H PCMR2 R2-HW PCM Receive Register 2 R2-TS[6:0] 23H PCMR3 R3-HW PCM Receive Register 3 R3-TS[6:0] 24H PCMR4 R4-HW PCM Receive Register 4 R4-TS[6:0] 25H PCMX1 X1-HW PCM Transmit Register 1 X1-TS[6:0] Data Sheet 170 2000-07-14 DuSLIC-E/-E2/-P Preliminary SLICOFI-2x Command Structure and Programming 26H PCMX2 X2-HW PCM Transmit Register 2 X2-TS[6:0] 27H PCMX3 X3-HW PCM Transmit Register 3 X3-TS[6:0] 28H PCMX4 X4-HW PCM Transmit Register 4 X4-TS[6:0] 29H TSTR1 PD-AC-PR PD-AC-PO Test Register 1 PD-AC-AD PD-AC-DA PD-AC-GN PD-GNKC PD-OFHC PD-OVTC 2AH TSTR2 PD-DC-PR 0 Test Register 2 PD-DC-AD PD-DC-DA PD-DCBUF 0 PD-TTX-A PD-HVI 2BH TSTR3 0 0 Test Register 3 AC-DLB-4M AC-DLB128K AC-DLB32K AC-DLB8K 0 0 2CH TSTR4 OPIM-AN OPIM-4M Test Register 4 COR-64 COX-16 0 0 0 0 2DH TSTR5 0 0 Test Register 5 0 DC-POFIHI DC-HOLD 0 0 0 Data Sheet 171 2000-07-14 DuSLIC-E/-E2/-P Preliminary SLICOFI-2x Command Structure and Programming 6.2.1.2 00H SOP Register Description REVISION Revision Number (read-only) curr. rev. N Bit 7 6 5 4 3 2 1 0 REV[7:0] REV[7:0] Current revision number of the SLICOFI-2. 01H Bit CHIPID 1 Chip Identification 1 (read-only) hw N 7 6 5 4 for internal use only 3 2 1 0 02H Bit CHIPID 2 Chip Identification 2 (read-only) hw N 7 6 5 4 for internal use only 3 2 1 0 03H Bit CHIPID 3 Chip Identification 3 (read-only) hw N 7 6 5 4 for internal use only 3 2 1 0 04H Bit FUSE1 Fuse Register 1 hw N 7 6 5 4 for internal use only 3 2 1 0 Data Sheet 172 2000-07-14 DuSLIC-E/-E2/-P Preliminary 05H Bit PCMC1 7 SLICOFI-2x Command Structure and Programming PCM Configuration Register 1 6 5 4 3 SHIFT 00H 2 1 PCMO[2:0] N 0 DBL-CLK X-SLOPE R-SLOPE NO-DRIVE-0 DBL-CLK Clock mode for the PCM interface (see Figure 59 on Page 141) DBL-CLK = 0 DBL-CLK = 1 Single-clocking is used. Double-clocking is used. X-SLOPE Transmit slope (see Figure 59 on Page 141) X-SLOPE = 0 X-SLOPE = 1 Transmission starts with rising edge of the clock. Transmission starts with falling edge of the clock. R-SLOPE Receive slope (see Figure 59 on Page 141) R-SLOPE = 0 R-SLOPE = 1 Data is sampled with falling edge of the clock. Data is sampled with rising edge of the clock. NODRIVE-0 Driving mode for bit 0 (only available in single-clocking mode). NO-DRIVE = 0 NO-DRIVE = 1 Bit 0 is driven the entire clock period. Bit 0 is driven during the first half of the clock period only. SHIFT Shifts the access edges by one clock cycle in double-clocking mode. SHIFT = 0 SHIFT = 1 No shift takes place. Shift takes place. PCMO[2:0] The whole PCM timing is moved by PCMO data periods against the FSC signal. PCMO[2:0] = 0 0 0 PCMO[2:0] = 0 0 1 No offset is added. One data period is added. Seven data periods are added. ... PCMO[2:0] = 1 1 1 Data Sheet 173 2000-07-14 DuSLIC-E/-E2/-P Preliminary 06H Bit XCR 7 EDSPEN 6 ASYNC H-R SLICOFI-2x Command Structure and Programming Extended Configuration Register 5 0 4 0 3 0 2 00H 1 0 0 N EDSP-EN Enables the Enhanced Digital Signal Processor EDSP. EDSP-EN = 0 EDSP-EN = 1 Enhanced Digital Signal Processor is switched off. Enhanced Digital Signal Processor is switched on. ASYNCH-R Enables asynchronous ringing in case of external ringing. ASYNCH-R = 0 ASYNCH-R = 1 External ringing with zero crossing selected. Asynchronous ringing selected. Data Sheet 174 2000-07-14 DuSLIC-E/-E2/-P Preliminary 07H Bit INTREG1 7 INT-CH SLICOFI-2x Command Structure and Programming Interrupt Register 1 (read-only) 6 HOOK 5 GNDK 4 GNKP 3 ICON 2 80H 1 Y 0 SYNCFAIL VRTLIM OTEMP INT-CH Interrupt channel bit. This bit indicates that the corresponding channel caused the last interrupt. Will be automatically set to zero after all interrupt registers were read. INT-CH = 0 INT-CH = 1 No interrupt in corresponding channel. Interrupt caused by corresponding channel. HOOK On/off-hook information for the loop in all operating modes, filtered by the DUP (Data Upstream Persistence) counter and interrupt generation masked by the HOOK-M bit. A change of this bit generates an interrupt. HOOK = 0 HOOK = 1 On-hook. Off-hook. GNDK Ground-Key or Ground Start information via the IL pin in all active modes, filtered for AC suppression by the DUP counter and interrupt generation masked by the GNDK-M bit. A change of this bit generates an interrupt. GNDK = 0 GNDK = 1 No longitudinal current detected. Longitudinal current detected (Ground Key or Ground Start). GNKP Ground Key polarity. Indicating the active Ground Key level (positive/ negative) interrupt generation masked by the GNKP-M bit. A change of this bit generates an interrupt. This bit can be used to get information about interference voltage influence. GNKP = 0 GNKP = 1 Negative Ground Key threshold level active. Positive Ground Key threshold level active. Data Sheet 175 2000-07-14 DuSLIC-E/-E2/-P Preliminary ICON SLICOFI-2x Command Structure and Programming Constant current information. Filtered by DUP-IO counter and interrupt generation masked by the ICON-M bit. A change of this bit generates an interrupt. ICON = 0 ICON = 1 VRTLIM Resistive or constant voltage feeding. Constant current feeding. Exceeding of a programmed voltage threshold for the TIP/RING voltage, filtered by the DUP-IO counter and interrupt generation masked by the VRTLIM-M bit. A change of this bit causes an interrupt. The voltage threshold for the TIP/RING voltage is set in CRAM (calculated with DuSLICOS DC Control Parameter 2/3: Tip-Ring Threshold). VRTLIM = 0 VRTLIM = 1 Voltage at Ring/Tip is below the limit. Voltage at Ring/Tip is above the limit. OTEMP Thermal overload warning from the SLIC-E/-E2/-P line drivers masked by the OTEMP-M bit. An interrupt is only generated if the OTEMP bit changes from 0 to1. OTEMP = 0 OTEMP = 1 Temperature at SLIC-E/-E2/-P is below the limit. Temperature at SLIC-E/-E2/-P is above the limit. In case of bit PDOT-DIS = 0 (register BCR2) the DuSLIC is switched automatically into PDH mode and OTEMP is hold at 1 until the SLICOFI-2 is set to PDH by a CIOP/CIDD command. SYNC-FAIL Failure of the Synchronization of the IOM-2/PCM interface. An interrupt is only generated if the SYNC-FAIL bit changes from 0 to1. Resynchronization of the PCM interface can be done with the Resynchronization command (see Chapter 6) SYNC-FAIL = 0 SYNC-FAIL = 1 Synchronization OK. Synchronization failure. Data Sheet 176 2000-07-14 DuSLIC-E/-E2/-P Preliminary 08H Bit INTREG2 7 SLICOFI-2x Command Structure and Programming Interrupt Register 2 (read-only) 6 5 4 LM-OK 3 2 20H 1 Y 0 LMREADY RSTAT THRES IO[4:1]-DU After a hardware reset the RSTAT bit is set and generates an interrupt. Therefore the default value of INTREG2 is 20h. After reading all four interrupt registers, the INTREG2 value changes to 4Fh. LM-THRES Indication whether the level metering result is above or below the threshold set by the CRAM coefficients LM-THRES = 0 Level metering result is below threshold. LM-THRES = 1 Level metering result is above threshold. READY Indication whether the ramp generator has finished. An interrupt is only generated if the READY bit changes from 0 to 1. Upon a new start of the ramp generator, the bit is set to 0. For further information regarding soft reversal see Chapter 3.7.2.1. READY = 0 READY = 1 RSTAT Ramp generator active. Ramp generator not active. Reset status since last interrupt. RSTAT = 0 RSTAT = 1 No reset has occurred since the last interrupt. Reset has occurred since the last interrupt. LM-OK Level metering sequence has finished. An interrupt is only generated if the LM-OK bit changes from 0 to 1. LM-OK = 0 LM-OK = 1 Level metering result not ready. Level metering result ready. IO[4:1]-DU Data on IO pins 1 to 4 filtered by DUP-IO counter and interrupt generation masked by the IO[4:1]-DU-M bits. A change of any of this bits generates an interrupt. Data Sheet 177 2000-07-14 DuSLIC-E/-E2/-P Preliminary 09H Bit INTREG3 7 DTMFOK SLICOFI-2x Command Structure and Programming Interrupt Register 3 (read-only) 6 5 4 DTMF-KEY[4:0] 3 2 00H 1 UTDROK Y 0 UTDXOK DTMF-OK Indication of a valid DTMF Key by the DTMF receiver. A change of this bit generates an interrupt. DTMF-OK = 0 DTMF-OK = 1 No valid DTMF Key was encountered by the DTMF receiver. A valid DTMF Key was encountered by the DTMF receiver. DTMF-KEY[4:0] Valid DTMF keys decoded by the DTMF receiver. Table 48 Valid DTMF Keys (Bit DTMF-KEY4 = 1) DIGIT 1 2 3 4 5 6 7 8 9 0 * # A B [Hz] 697 697 697 770 770 770 852 852 852 941 941 941 697 770 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 DTMFKEY4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DTMFKEY3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 DTMFKEY2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 DTMFKEY1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 DTMFKEY0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 fLOW [Hz] fHIGH Data Sheet 178 2000-07-14 DuSLIC-E/-E2/-P Preliminary Table 48 SLICOFI-2x Command Structure and Programming Valid DTMF Keys (Bit DTMF-KEY4 = 1) (cont'd) DIGIT C D [Hz] 852 941 1633 1633 DTMFKEY4 1 1 DTMFKEY3 1 0 DTMFKEY2 1 0 DTMFKEY1 1 0 DTMFKEY0 1 0 fLOW [Hz] fHIGH UTDR-OK Universal Tone Detection Receive (e.g., Fax/Modem tones) UTDR-OK = 0 UTDR-OK = 1 No specific tone signal was detected. A specific tone signal was detected. UTDX-OK Universal Tone Detection Transmit (e.g., Fax/Modem tones) UTDX-OK = 0 UTDX-OK = 1 No specific tone signal was detected. A specific tone signal was detected. Data Sheet 179 2000-07-14 DuSLIC-E/-E2/-P Preliminary 0AH INTREG4 SLICOFI-2x Command Structure and Programming Interrupt Register 4 (read-only) 00H Y Bit 7 EDSPFAIL 6 0 5 0 4 0 3 CISBOF 2 CISBUF 1 CISREQ 0 CISACT EDSP-FAIL Indication of a malfunction of the Enhanced Digital Signal Processor EDSP. EDSP-FAIL = 0 Enhanced Digital Signal Processor EDSP normal operation. EDSP-FAIL = 1 Enhanced Digital Signal Processor EDSP failure. It is necessary to restart this DSP with bit EDSP-EN in the XCR register set. CIS-BOF Caller ID buffer overflow. An interrupt is only generated if the CIS-BOF bit changes from 0 to 1. CIS-BOF = 0 CIS-BOF = 1 Not data buffer overflow has occurred. Too many bytes have been written to the data buffer for Caller ID generation. Caller ID generation is aborted and the buffer is cleared. CIS-BUF Caller ID buffer underflow. An interrupt is only generated if the CIS-BUF bit changes from 0 to 1. CIS-BUF = 0 CIS-BUF = 1 Data buffer for Caller ID generation is filled. Data buffer for Caller ID generation is empty (underflow). Data Sheet 180 2000-07-14 DuSLIC-E/-E2/-P Preliminary CIS-REQ SLICOFI-2x Command Structure and Programming Caller ID data request. An interrupt is only generated if the CIS-REQ bit changes from 0 to 1. CIS-REQ = 0 CIS-REQ = 1 Caller ID data buffer requests no data. Caller ID data buffer requests more data to transmit, when the amount of data stored in the buffer is less than the buffer request size. CIS-ACT Caller ID generator active. This is a status bit only. No interrupt will be generated. CIS-ACT = 0 CIS-ACT = 1 Caller ID generator is not active. Caller ID generator is active. Data Sheet 181 2000-07-14 DuSLIC-E/-E2/-P Preliminary 0BH CHKR1 SLICOFI-2x Command Structure and Programming Checksum Register 1 (High Byte) (read-only) 00H Y Bit 7 SUMOK 6 5 4 3 CHKSUM-H[6:0] 2 1 0 SUM-OK Information about the validity of the checksum. The checksum is valid if the internal checksum calculation is finished. Checksum calculation: For (cram_adr = 0 to 159) do cram_dat = cram[cram_adr] csum[14:0] = (csum[13:0] &1) `0') xor (`0000000' & cram_dat[7:0]) xor (`0000000000000' & csum[14] & csum[14]) End SUM-OK = 0 SUM-OK = 1 1) CRAM checksum is not valid. CRAM checksum is valid. "&" means a concatenation, not the logic operation CHKSUM-H[6:0] CRAM checksum high byte 0CH CHKR2 Checksum Register 2 (Low Byte) (read-only) 00H Y Bit 7 6 5 4 3 2 1 0 CHKSUM-L[7:0] CHKSUM-L[7:0] CRAM checksum low byte Data Sheet 182 2000-07-14 DuSLIC-E/-E2/-P Preliminary 0DH LMRES1 SLICOFI-2x Command Structure and Programming Level Metering Result 1 (High Byte) (read-only) 6 5 4 3 LM-VAL-H[7:0] LM-VAL-H[7:0] LM result high byte (selected by the LM-SEL bits in the LMCR2 register) 2 00H Y Bit 7 1 0 0EH LMRES2 Level Metering Result 2 (Low Byte) (read-only) 00H Y Bit 7 6 5 4 3 2 1 0 LM-VAL-L[7:0] LM-VAL-L[7:0] LM result low byte (selected by the LM-SEL bits in the LMCR2 register) 0FH Bit FUSE2 7 Fuse Register 2 6 5 4 3 2 hw 1 Y 0 for internal use only 10H Bit FUSE3 7 Fuse Register 3 6 5 4 3 2 hw 1 Y 0 for internal use only Data Sheet 183 2000-07-14 DuSLIC-E/-E2/-P Preliminary 11H Bit MASK 7 READY -M SLICOFI-2x Command Structure and Programming Mask Register 6 HOOK -M 5 GNDK -M 4 GNKP -M 3 ICON -M 2 FFH 1 Y 0 SYNC -M VRTLIM OTEMP -M -M The mask bits in the mask register only influence the generation of an interrupt. Even if the mask bit is set to 1, the corresponding status bit in the INTREGx registers gets updated to show the current status of the corresponding event. READY-M Mask bit for Ramp Generator READY bit READY-M = 0 READY-M = 1 HOOK-M An interrupt is generated if the READY bit changes from 0 to 1. Changes of the READY bit don't generate interrupts. Mask bit for Off-hook Detection HOOK bit HOOK-M = 0 HOOK-M = 1 Each change of the HOOK bit generates an interrupt. Changes of the HOOK bit don't generate interrupts. GNDK-M Mask bit for Ground Key Detection GNDK bit GNDK-M = 0 GNDK-M = 1 Each change of the GNDK bit generates an interrupt. Changes of the GNDK bit don't generate interrupts. GNKP-M Mask bit for Ground Key Level GNKP bit GNKP-M = 0 GNKP-M = 1 Each change of the GNKP bit generates an interrupt. Changes of the GNKP bit don't generate interrupts. ICON-M Mask bit for Constant Current Information ICON bit ICON-M = 0 ICON_M = 1 Each change of the ICON bit generates an interrupt. Changes of the ICON bit don't generate interrupts. VRTLIM-M Mask bit for Programmed Voltage Limit VRTLIM bit VRTLIM-M = 0 VRTLIM-M = 1 Each change of the VRTLIM bit generates an interrupt. Changes of the VRTLIM bit don't generate interrupts. Data Sheet 184 2000-07-14 DuSLIC-E/-E2/-P Preliminary SLICOFI-2x Command Structure and Programming OTEMP-M Mask bit for Thermal Overload Warning OTEMP bit OTEMP-M = 0 OTEMP-M = 1 A change of the OTEMP bit from 0 to 1 generates an interrupt. A change of the OTEMP bit from 0 to 1 doesn't generate interrupts. SYNC-M Mask bit for Synchronization Failure SYNC-FAIL bit SYNC-M = 0 SYNC-M = 1 A change of the SYNC-FAIL bit from 0 to 1 generates an interrupt. A change of the SYNC-FAIL bit from 0 to 1 doesn't generate interrupts. Data Sheet 185 2000-07-14 DuSLIC-E/-E2/-P Preliminary 12H Bit IOCTL1 7 SLICOFI-2x Command Structure and Programming IO Control Register 1 6 5 4 3 2 0FH 1 Y 0 IO[4:1]-INEN IO[4:1]-M The mask bits IO[4:1]-M only influence the generation of an interrupt. Even if the mask bit is set to 1, the corresponding status bit in the INTREGx registers gets updated to show the current status of the corresponding event. IO4-INEN Input enable for programmable IO pin IO4 IO4-INEN = 0 Input Schmitt trigger of pin IO4 is disabled. IO4-INEN = 1 Input Schmitt trigger of pin IO4 is enabled. IO3-INEN Input enable for programmable IO pin IO3 IO3-INEN = 0 Input Schmitt trigger of pin IO3 is disabled. IO3-INEN = 1 Input Schmitt trigger of pin IO3 is enabled. IO2-INEN Input enable for programmable IO pin IO2 IO2-INEN = 0 Input Schmitt trigger of pin IO2 is disabled. IO2-INEN = 1 Input Schmitt trigger of pin IO2 is enabled. IO1-INEN Input enable for programmable IO pin IO1 IO1-INEN = 0 Input Schmitt trigger of pin IO1 is disabled. IO1-INEN = 1 Input Schmitt trigger of pin IO1 is enabled. IO4-M Mask bit for IO4-DU bit IO4-M = 0 IO4-M = 1 IO3-M Each change of the IO4 bit generates an interrupt. Changes of the IO4 bit don't generate interrupts. Mask bit for IO3-DU bit IO3-M = 0 IO3-M = 1 Each change of the IO3 bit generates an interrupt. Changes of the IO3 bit don't generate interrupts. Data Sheet 186 2000-07-14 DuSLIC-E/-E2/-P Preliminary IO2-M SLICOFI-2x Command Structure and Programming Mask bit for IO2-DU bit IO2-M = 0 IO2-M = 1 IO1-M Each change of the IO2 bit generates an interrupt. Changes of the IO2 bit don't generate interrupts. Mask bit for IO1-DU bit IO1-M = 0 IO1-M = 1 Each change of the IO1 bit generates an interrupt. Changes of the IO1 bit don't generate interrupts. Data Sheet 187 2000-07-14 DuSLIC-E/-E2/-P Preliminary 13H Bit IOCTL2 7 SLICOFI-2x Command Structure and Programming IO Control Register 2 6 5 4 3 2 00H 1 Y 0 IO[4:1]-OEN IO[4:1]-DD IO4-OEN Enabling output driver of the IO4 pin IO4-OEN = 0 IO4-OEN = 1 The output driver of the IO4 pin is disabled. The output driver of the IO4 pin is enabled. IO3-OEN Enabling output driver of the IO3 pin IO3-OEN = 0 IO3-OEN = 1 The output driver of the IO3 pin is disabled. The output driver of the IO3 pin is enabled. IO2-OEN Enabling output driver of the IO2 pin. If SLIC-P is selected (bits SEL-SLIC [1:0] in register BCR1 set to 01), pin IO2 cannot be controlled by the user but is utilized by the SLICOFI-2 to control the C3 input of SLIC-P. IO2-OEN = 0 IO2-OEN = 1 The output driver of the IO2 pin is disabled. The output driver of the IO2 pin is enabled. IO1-OEN Enabling output driver of the IO1 pin. If external ringing is selected (bit REXT-EN in register BCR2 set to 1), pin IO1 cannot be controlled by the user but is utilized by the SLICOFI-2 to control the ring relay. IO1-OEN = 0 IO1-OEN = 1 The output driver of the IO1 pin is disabled. The output driver of the IO1 pin is enabled. IO4-DD Value for the programmable IO pin IO4 if programmed as an output pin. IO4-DD = 0 IO4-DD = 1 The corresponding pin is driving a logic 0. The corresponding pin is driving a logic 1. IO3-DD Value for the programmable IO pin IO3 if programmed as an output pin. IO3-DD = 0 IO3-DD = 1 The corresponding pin is driving a logic 0. The corresponding pin is driving a logic 1. Data Sheet 188 2000-07-14 DuSLIC-E/-E2/-P Preliminary IO2-DD SLICOFI-2x Command Structure and Programming Value for the programmable IO pin IO2 if programmed as an output pin. IO2-DD = 0 IO2-DD = 1 IO1-DD The corresponding pin is driving a logic 0. The corresponding pin is driving a logic 1. Value for the programmable IO pin IO1 if programmed as an output pin. IO1-DD = 0 IO1-DD = 1 The corresponding pin is driving a logic 0. The corresponding pin as driving a logic 1. 14H Bit IOCTL3 7 IO Control Register 3 6 5 4 3 2 94H 1 Y 0 DUP[3:0] DUP-IO[3:0] DUP[3:0] Data Upstream Persistence Counter end value. Restricts the rate of interrupts generated by the HOOK bit in the interrupt register INTREG1. The interval is programmable from 1 to 16 ms in steps of 1 ms (reset value is 10 ms). The DUP[3:0] value affects the blocking period for ground key detection (see Chapter 3.6). DUP[3:0] HOOK Active, Ringing 0000 0001 ... 1111 1) HOOK Power Down 2 ms 4 ms 32 ms GNDK GNDK fmin,ACsup1) 125 Hz 62.5 Hz 7.8125 Hz 1 2 16 4 ms 8 ms 64 ms Minimum frequency for AC suppression. DUP-IO[3:0] Data Upstream Persistence Counter end value for * the IO pins when used as digital input pins. * the bits ICON and VRTLIM in register INTREG1. The interval is programmable from 0.5 to 60.5 ms in steps of 4 ms (reset value is 16.5 ms). Data Sheet 189 2000-07-14 DuSLIC-E/-E2/-P Preliminary 15H BCR1 SLICOFI-2x Command Structure and Programming Basic Configuration Register 1 00H Y Bit 7 HIR 6 HIT 5 4 3 2 ACTL 1 0 SLEEP- REVPOL ACTR EN SEL-SLIC[1:0] HIR This bit modifies different basic modes. In ringing mode an unbalanced ringing on the RING wire (ROR) is enabled. In active mode, high impedance on the RING wire is activated (HIR). If the HIT bit is set in addition to the HIR bit, the HIRT mode is activated. HIR = 0 HIR = 1 Normal operation (ringing mode). Controls SLIC-E/-E2/-P interface and sets the RING wire to high impedance (active mode). HIT This bit modifies different basic modes. In ringing mode an unbalanced ringing on the TIP wire (ROT) is enabled. In active mode, high impedance on the TIP wire is performed (HIT).If the HIR bit is set in addition to the HIT bit, the HIRT mode is activated. HIT = 0 HIT = 1 Normal operation (ringing mode). Controls SLIC-E/-E2/-P interface and sets the TIP wire to high impedance (active mode). SLEEP-EN Enables Sleep mode of the DuSLIC channel. Valid only in the Power Down mode of the SLICOFI-2. SLEEP-EN = 0 SLEEP-EN = 1 Sleep mode is disabled. Sleep mode is enabled. REVPOL Reverses the polarity of DC feeding REVPOL = 0 REVPOL = 1 Normal polarity. Reverse polarity. Data Sheet 190 2000-07-14 DuSLIC-E/-E2/-P Preliminary ACTR SLICOFI-2x Command Structure and Programming Selection of extended battery feeding in Active mode. Changes also the voltage in Power Down Resistive mode for SLIC-P. In this case VBATR for SLIC-P and VHR - VBATH for SLIC-E/-E2 is used. ACTR = 0 ACTR = 1 No extended battery feeding selected. Extended battery feeding selected. ACTL Selection of the low battery supply voltage VBATL on SLIC-E/-E2/-P if available. Valid only in the Active mode of the SLICOFI-2. ACTL = 0 ACTL = 1 Low battery supply voltage on SLIC-E/-E2/-P is not selected. Low battery supply voltage on SLIC-E/-E2/-P is selected. SEL-SLIC[1:0] Selection of the current SLIC type used. For SLIC-E/-E2 and SLIC-P, the appropriate predefined mode table has to be selected. SEL-SLIC[1:0] = 0 0 SEL-SLIC[1:0] = 0 1 SEL-SLIC[1:0] = 1 0 SEL-SLIC[1:0] = 1 1 SLIC-E/-E2 selected. SLIC-P selected. SLIC-P selected for extremely power sensitive applications using external ringing. Reserved for future use. For SLIC-P two selections are possible. * The standard SLIC-P selection automatically uses the IO2 pin of the SLICOFI-2 to control the C3 pin of the SLIC-P. By using pin C3 additionaly to the pins C1 and C2 all possible operating modes of the SLIC-P can be selected. * For extremely power sensitive applications using external ringing with SLIC-P SEL-SLIC[1:0] = 10 should be chosen. In this case internal unbalanced ringing in not needed and therefore there is no need to switch the C3 pin of the SLIC-P to 'High'. The C3 pin of the SLIC-P has be connected to GND and the IO2 pin of the SLICOFI-2 is free programmable for the user. There is no need for a high battery voltage for ringing either. This mode uses VBATR for the on-hook voltage (e.g. - 48 V) in Power Down Resistive (PDR) mode and the other battery supply voltages (e.g. VBATH = - 24 V and VBATL = - 18 V) can be used for the off-hook state. This will help to save power because the lowest possible battery voltage can be selected (see DuSLIC Voltage and Power Application Note). Data Sheet 191 2000-07-14 DuSLIC-E/-E2/-P Preliminary 16H Bit BCR2 7 REXTEN SLICOFI-2x Command Structure and Programming Basic Configuration Register 2 6 SOFTDIS 5 TTXDIS 4 TTX12K 3 HIM-AN 2 ACXGAIN 00H 1 UTDXSRC Y 0 PDOTDIS REXT-EN Enables the use of an external ring signal generator. The synchronization is done via the RSYNC pin and the Ring Burst Enable signal is transferred via the IO1 pin. REXT-EN = 0 REXT-EN = 1 External ringing is disabled. External ringing enabled. SOFT-DIS Polarity soft reversal (to minimize noise on DC feeding) SOFT-DIS = 0 SOFT-DIS = 1 Polarity soft reversal active. Polarity hard reversal. TTX-DIS Disables the generation of TTX bursts for metering signals. If TTX bursts are disabled, reverse polarity will be used instead. TTX-DIS = 0 TTX-DIS = 1 TTX bursts are enabled. TTX bursts are disabled, reverse polarity used. TTX-12K Selection of TTX frequencies TTX-12K = 0 TTX-12K = 1 Selects 16 kHz TTX signals instead of 12 kHz signals. 12 kHz TTX signals. HIM-AN Higher impedance in analog impedance matching loop. HIM-AN corresponds to the coefficients calculated with DuSLICOS. If the coefficients are calculated with standard impedance in analog impedance matching loop, HIM-AN must be set to 0; if the coefficients are calculated with high impedance in analog impedance matching loop, HIM-AN must be set to 1. HIM-AN = 0 HIM-AN = 1 Standard impedance in analog impedance matching loop (300 ). High impedance in analog impedance matching loop (600 ). 192 2000-07-14 Data Sheet DuSLIC-E/-E2/-P Preliminary SLICOFI-2x Command Structure and Programming AC-XGAIN Analog gain in transmit direction (should be set to zero). AC-XGAIN = 0 AC-XGAIN = 1 No additional analog gain in transmit direction. Additional 6 dB analog amplification in transmit direction. UTDX-SRC Universal Tone Detector transmit source UTDX-SRC = 0 The Universal Tone Detection unit uses the data from the transmit path directly (UTDX-SUM = 0) or uses the data from the sum signal of receive path and LEC (if LEC is enabled) (UTDX-SUM = 1). The Universal Tone Detection unit uses the data from the LEC output, if the LEC is enabled (LEC-EN = 1), otherwise the UTD unit uses automatically the transmit signal. UTDX-SRC = 1 (see Figure 32 on Page 63) PDOT-DIS Power Down Overtemperature Disable PDOT-DIS = 0 When overtemperature is detected, the SLIC is automatically switched into Power Down High Impedance mode (PDH). This is the safe operation mode for the SLIC-E/-E2/-P in case of overtemperature. To leave the automatically activated PDH mode, DuSLIC has to be switched manually to PDH mode and then in the mode as desired. When over temperature is detected, the SLIC-E/-E2/ -P doesn't automatically switch into Power Down High Impedance mode. In this case the output current of the SLIC-E/-E2/-P buffers is limited to a value which keeps the SLIC-E/-E2/-P temperature below the upper temperature limit. PDOT-DIS = 1 Data Sheet 193 2000-07-14 DuSLIC-E/-E2/-P Preliminary 17H Bit BCR3 7 MULAW SLICOFI-2x Command Structure and Programming Basic Configuration Register 3 6 LIN 5 PCM16K 4 3 2 CONFEN 00H 1 LPRXCR Y 0 CRAMEN PCMX- CONFX EN -EN MU-LAW Selects the PCM Law MU-LAW = 0 MU-LAW = 1 A-Law enabled. -Law enabled. LIN Voice transmission in a 16-bit linear representation for test purposes. Note: Voice transmission on the other channel is inhibited if one channel is set to linear mode and IOM-2-interface is used. In the PCM/ C interface mode both channels can be in linear mode using two consecutive PCM timeslots on the highways. A proper timeslot selection must be specified. LIN = 0 LIN = 1 PCM mode enabled (8 bit, A-law or -law). Linear mode enabled (16 bit). PCM16K Selects 16-kHz sample rate for the PCM interface. PCM16K = 0 PCM16K = 1 16-kHz mode disabled (8 kHz sampling rate). 16-kHz mode enabled. PCMX-EN Enables writing of subscriber voice data to the PCM highway. PCMX-EN = 0 PCMX-EN = 1 Writing of subscriber voice data to PCM highway is disabled. Writing of subscriber voice data to PCM highway is enabled. CONFX-EN Enables an external three-party conference. CONFX-EN = 0 External conference is disabled. CONFX-EN = 1 External conference is enabled. Data Sheet 194 2000-07-14 DuSLIC-E/-E2/-P Preliminary CONF-EN SLICOFI-2x Command Structure and Programming Selection of three-party conferencing for this channel. The voice data of this channel and the voice data from the corresponding conferencing channels (see Chapter 5.1.1) are added and fed to analog output (see Chapter 3.10). CONF-EN = 0 CONF-EN = 1 LPRX-CR Three-party conferencing is not selected. Three-party conferencing is selected. Select CRAM coefficients for the filter characteristic of the LPR/LPX filters. These coefficients my be enabled in case of a modem transmission to improve modem performance. LPRX-CR = 0 LPRX-CR = 1 Coefficients from ROM are used. Coefficients from CRAM are used. CRAM-EN Coefficients from CRAM are used for programmable filters and DC loop behavior. CRAM-EN = 0 CRAM-EN = 1 Coefficients from ROM are used. Coefficients from CRAM are used. Data Sheet 195 2000-07-14 DuSLIC-E/-E2/-P Preliminary 18H Bit BCR4 7 TH-DIS SLICOFI-2x Command Structure and Programming Basic Configuration Register 4 6 IM-DIS 5 AX-DIS 4 AR-DIS 3 FRXDIS 2 FRRDIS 00H 1 HPXDIS Y 0 HPRDIS TH-DIS Disables the TH filter. TH-DIS = 0 TH-DIS = 1 TH filter is enabled. TH filter is disabled (HTH = 0). IM-DIS Disables the IM filter. IM-DIS = 0 IM-DIS = 1 IM filter is enabled. IM filter is disabled (HIM = 0). AX-DIS Disables the AX filter. AX-DIS = 0 AX-DIS = 1 AX filter is enabled. AX filter is disabled (HAX = 1). AR-DIS Disables the AR filter. AX-DIS = 0 AX-DIS = 1 AR filter is enabled. AR filter is disabled (HAR = 1). FRX-DIS Disables the FRX filter. FRX-DIS = 0 FRX-DIS = 1 FRX filter is enabled. FRX filter is disabled (HFRX = 1). FRR-DIS Disables the FRR filter. FRR-DIS = 0 FRR-DIS = 1 FRR filter is enabled. FRR filter is disabled (HFRR = 1). HPX-DIS Disables the high-pass filter in transmit direction. HPX-DIS = 0 HPX-DIS = 1 High-pass filter is enabled. High-pass filter is disabled (HHPX = 1). Data Sheet 196 2000-07-14 DuSLIC-E/-E2/-P Preliminary HPR-DIS SLICOFI-2x Command Structure and Programming Disables the high-pass filter in receive direction. HPR-DIS = 0 HPR-DIS = 1 High-pass filter is enabled. High-pass filter is disabled (HHPR = 1). Data Sheet 197 2000-07-14 DuSLIC-E/-E2/-P Preliminary 19H Bit BCR5 7 UTDREN SLICOFI-2x Command Structure and Programming Basic Configuration Register 5 6 UTDXEN 5 CISAUTO 4 CIS-EN 3 LECOUT 2 LEC-EN 00H 1 DTMFSRC Y 0 DTMFEN UTDR-EN Enables the Universal Tone detection in receive direction. UTDR-EN = 0 Universal Tone detection is disabled. UTDR-EN = 1 Universal Tone detection is enabled. UTDX-EN Enables the Universal Tone detection in transmit direction. UTDX-EN = 0 Universal Tone detection is disabled. UTDX-EN = 1 Universal Tone detection is enabled. CIS-AUTO Controls the turn-off behavior of the Caller ID sender. CIS-AUTO = 0 The Caller ID sender stops when CIS-EN is switched to 0. CIS-AUTO = 1 The Caller ID sender continues sending data until the data buffer is empty. CIS-EN Enables the Caller ID sender in the SLICOFI-2. Note: The Caller ID sender is configured directly by programming the according POP registers. Caller ID data are written to a 48 byte RAM buffer. According to the buffer request size this influences the CIS-REQ and CIS-BUF bits. CIS-EN = 0 CIS-EN = 1 Caller ID sender is disabled and Caller ID data buffer is cleared after all data are sent or if CIS-AUTO = 0. Caller ID sender is enabled and Caller ID data can be written to the data buffer. After the last data bit is sent, stop bits are sent to the subscriber. Caller ID data are sent to the subscriber when the number of bytes written to the buffer exceeds CIS-BRS + 2. Data Sheet 198 2000-07-14 DuSLIC-E/-E2/-P Preliminary LEC-OUT SLICOFI-2x Command Structure and Programming Line Echo Canceller result for transmit path. LEC-OUT = 0 LEC-OUT = 1 LEC-EN Line Echo Canceller result used for DTMF only. Line Echo Canceller result fed to transmit path. Line Echo Canceller LEC-EN = 0 LEC-EN = 1 Line Echo Canceller for DTMF disabled. Line Echo Canceller for DTMF enabled. DTMF-SRC Selects data source for DTMF receiver. DTMF-SRC = 0 The Transmit path data (with or without LEC) is used for the DTMF detection. DTMF-SRC = 1 The Receive path data is used for the DTMF detection. DTMF-EN Enables the DTMF receiver of the SLICOFI-2. The DTMF receiver will be configured in a proper way by programming registers in the EDSP. DTMF-EN = 0 DTMF receiver is disabled. DTMF-EN = 1 DTMF receiver is enabled. Data Sheet 199 2000-07-14 DuSLIC-E/-E2/-P Preliminary 1AH Bit DSCR 7 SLICOFI-2x Command Structure and Programming DTMF Sender Configuration Register 6 5 4 3 COR8 2 PTG 00H 1 Y 0 DG-KEY[3:0] TG2-EN TG1-EN DG-KEY[3:0] Selects one of sixteen DTMF keys generated by the two tone generators. The key will be generated if TG1-EN and TG2-EN are `1'. Table 49 DTMF Keys fLOW [Hz] 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 COR8 fHIGH [Hz] DIGIT 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633 1 2 3 4 5 6 7 8 9 0 * # A B C D DG-KEY3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 DG-KEY2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 DG-KEY1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 DG-KEY0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Cuts off receive path at 8 kHz before the tone generator summation point. Allows sending of tone generator signals with no overlaid voice. COR8 = 0 COR8 = 1 Cut off receive path disabled. Cut off receive path enabled. Data Sheet 200 2000-07-14 DuSLIC-E/-E2/-P Preliminary PTG SLICOFI-2x Command Structure and Programming Programmable coefficients for tone generators will be used. PTG = 0 PTG = 1 TG2-EN Frequencies set by DG-KEY are used for both tone generators. CRAM coefficients used for both tone generators. Enables tone generator two TG2-EN = 0 TG2-EN = 1 Tone generator is disabled. Tone generator is enabled. TG1-EN Enables tone generator one TG1-EN = 0 TG1-EN = 1 Tone generator is disabled. Tone generator is enabled. 1BH Bit 7 0 reserved 6 0 5 0 4 0 3 0 2 0 00H 1 0 Y 0 0 Data Sheet 201 2000-07-14 DuSLIC-E/-E2/-P Preliminary 1CH Bit LMCR1 7 TESTEN SLICOFI-2x Command Structure and Programming Level Metering Configuration Register 1 6 LM-EN 5 LMTHM 4 PCM2DC 3 LM2 PCM 2 LMONCE 22H 1 LMMASK Y 0 DCAD16 TEST-EN Activates the SLICOFI-2 test features controlled by test registers TSTR1 to TSTR5. TEST-EN = 0 TEST-EN = 1 SLICOFI-2 test features are disabled. SLICOFI-2 test features are enabled. (The Test Register bits can be programmed before the TEST-EN bit is set to 1.) LM-EN Enables level metering. A positive transition of this bit starts level metering (AC and DC). LM-EN = 0 LM-EN = 1 LM-THM Level metering stops. Level metering enabled. Level metering threshold mask bit LM-THM = 0 LM-THM = 1 A change of the LM-THRES bit (register INTREG2) generates an interrupt. No interrupt is generated. PCM2DC PCM voice channel data added to the DC-output. PCM2DC = 0 PCM2DC = 1 Normal operation. PCM voice channel data is added to DC output. LM2PCM Level metering source/result (depending on LM-EN bit) feeding to PCM or IOM-2 interface. LM2PCM = 0 LM2PCM = 1 Normal operation. Level metering source/result is fed to the PCM or IOM-2 interface. Data Sheet 202 2000-07-14 DuSLIC-E/-E2/-P Preliminary LM-ONCE SLICOFI-2x Command Structure and Programming Level metering execution mode. LM-ONCE = 0 LM-ONCE = 1 Level metering is executed continuously. Level metering is executed only once. To start the levelmeter again, the LM-EN bit must again be set from 0 to 1. LM-MASK Interrupt masking for level metering. LM-MASK = 0 LM-MASK = 1 An interrupt is generated after level metering. No interrupt is generated. DC-AD16 Additional digital amplification in the DC AD path for level metering. DC-AD16 = 0 DC-AD16 = 1 Additional gain factor 16 disabled. Additional gain factor 16 enabled. Data Sheet 203 2000-07-14 DuSLIC-E/-E2/-P Preliminary 1DH Bit LMCR2 7 LMNOTCH SLICOFI-2x Command Structure and Programming Level Metering Configuration Register 2 6 LMFILT 5 LMRECT 4 RAMPEN 3 2 00H 1 Y 0 LM-SEL[3:0] LM-NOTCH Selection of a notch filter instead of the band-pass filter for level metering. LM-NOTCH = 0 LM-NOTCH = 1 Notch filter selected. Band-pass filter selected. LM-FILT Enabling of a programmable band-pass or notch filter for level metering. LM-FILT = 0 LM-FILT = 1 Normal operation. Band-pass/notch filter enabled. LM-RECT Rectifier in DC level meter LM-RECT = 0 LM-RECT = 1 Rectifier disabled. Rectifier enabled. RAMP-EN The ramp generator works together with the RNG-OFFSET bits in LMCR3 and the LM-EN bit to create different voltage slopes in the DCPath. RAMP-EN = 0 RAMP-EN = 1 Ramp generator disabled. Ramp generator enabled. LM-SEL[3:0] Selection of the source for the level metering. LM-SEL[3:0] = 0 0 0 0 AC level metering in transmit LM-SEL[3:0] = 0 0 0 1 Real part of TTX (TTXREAL) LM-SEL[3:0] = 0 0 1 0 Imaginary part of TTX (TTXIMG) LM-SEL[3:0] = 0 0 1 1 Not used LM-SEL[3:0] = 0 1 0 0 DC out voltage on DCN-DCP LM-SEL[3:0] = 0 1 0 1 DC current on IT LM-SEL[3:0] = 0 1 1 0 AC level metering in receive Data Sheet 204 2000-07-14 DuSLIC-E/-E2/-P Preliminary SLICOFI-2x Command Structure and Programming LM-SEL[3:0] = 0 1 1 1 AC level metering in receive and transmit LM-SEL[3:0] = 1 0 0 0 Not used LM-SEL[3:0] = 1 0 0 1 DC current on IL LM-SEL[3:0] = 1 0 1 0 Voltage on IO3 LM-SEL[3:0] = 1 0 1 1 Voltage on IO4 LM-SEL[3:0] = 1 1 0 0 Not used LM-SEL[3:0] = 1 1 0 1 VDD LM-SEL[3:0] = 1 1 1 0 Offset of DC-Prefi (short circuit on DC-Prefi input) LM-SEL[3:0] = 1 1 1 1 Voltage on IO4 - IO3 Data Sheet 205 2000-07-14 DuSLIC-E/-E2/-P Preliminary 1EH Bit LMCR3 7 ACSHORT -EN SLICOFI-2x Command Structure and Programming Level Metering Configuration Register 3 6 RTRSEL 5 4 3 2 00H 1 Y 0 LM-ITIME[3:0] RNGOFFSET[1:0] AC-SHORT-EN The input pin ITAC will be set to a lower input impedance so that the capacitor CITAC can be recharged faster during a soft reversal which makes it more silent during conversation. AC-SHORT-EN = 0 Input impedance of the ITAC pin is standard. AC-SHORT-EN = 1 Input impedance of the ITAC pin is lowered. RTR-SEL Ring Trip method selection. RTR-SEL = 0 RTR-SEL = 1 Ring Trip with a DC offset is selected. AC Ring Trip is selected. Recommended for short lines only. LM-ITIME[3:0] Integration Time for AC Level Metering. LM-ITIME[3:0] = 0 0 0 0 LM-ITIME[3:0] = 0 0 0 1 LM-ITIME[3:0] = 0 0 1 0 ... LM-ITIME[3:0] = 1 1 1 1 RNGOFFSET[1:0] 16 x 16 ms 16 ms 2 x 16 ms 3 x 16 ms Selection of the Ring Offset source. Data Sheet 206 2000-07-14 DuSLIC-E/-E2/-P Preliminary RNGOFFSET[1:0] SLICOFI-2x Command Structure and Programming Ring Offset Voltage in Given Mode Active ACTH ACTL 00 01 10 11 Active Ring ACTR Ring Pause Ringing Voltage given by DC Voltage given by DC Ring Offset RO1 regulation regulation Hook Threshold Ring Ring Offset RO1/2 (no DC regulation) Ring Offset RO2/2 (no DC regulation) Ring Offset RO3/2 (no DC regulation) Ring Offset RO1 (no DC regulation) Ring Offset RO2 (no DC regulation) Ring Offset RO3 (no DC regulation) Ring Offset RO1 Hook Threshold Ring Ring Offset RO2 Hook Message Waiting Ring Offset RO3 Hook Message Waiting By setting the RAMP_EN bit to 1, the ramp generator is started by setting LM_EN from 0 to 1 (see Figure 71). Exception: Transition of RNG-OFFSET from 10 to 11 or 11 to 10 where the ramp generator is started automatically (see Figure 71). For Ring Offset RO1 the usual "Hook Threshold Ring" is used. Using Ring Offset RO2 or RO3 in any ringing mode (Ringing and Ring Pause) also changes the hook thresholds. In this case the "Hook Message Waiting" threshold is used automatically. When using the Ring Offsets RO2 and RO3 for Message Waiting an additional lamp current is expected. In this case the Hook Message Waiting threshold should be programmed higher than the Hook Threshold Ring. Data Sheet 207 2000-07-14 DuSLIC-E/-E2/-P Preliminary SLICOFI-2x Command Structure and Programming RNG-OFFSET[1:0] RAMP-EN (register LMCR2) LM-EN (register LMCR1) Generated Ring Offset (RO) Voltage RO3 = 120 V 01 10 11 01 RO2 = 40 V RO1 = 20 V t ezm35002.emf Figure 71 Example for Switching Between Different Ring Offset Voltages The three programmable Ring Offsets are typically used for the following purposes: Table 50 Typical Usage for the three Ring Offsets Application Ringing Low voltage for message waiting lamp High voltage for message waiting lamp Ring Offset Voltage Ring Offset RO1 Ring Offset RO2 Ring Offset RO3 Besides the typical usage described in Table 50 the Ring Offsets RO1, RO2 and RO3 can also be used for the generation of different custom waveforms (see Figure 71). Data Sheet 208 2000-07-14 DuSLIC-E/-E2/-P Preliminary 1FH Bit OFR1 7 SLICOFI-2x Command Structure and Programming Offset Register 1 (High Byte) 6 5 4 3 2 00H 1 Y 0 OFFSET-H[7:0] OFFSET-H[7:0] Offset register high byte. 20H OFR2 Offset Register 2 (Low Byte) 00H Y Bit 7 6 5 4 3 OFFSET-L[7:0] 2 1 0 OFFSET-L[7:0] Offset register low byte. The value of this register together with OFFSET-H is added to the input of the DC loop to compensate a given offset of the current sensors in the SLIC-E/-E2/-P. Data Sheet 209 2000-07-14 DuSLIC-E/-E2/-P Preliminary 21H Bit PCMR1 7 R1HW SLICOFI-2x Command Structure and Programming PCM Receive Register 1 6 5 4 3 R1-TS[6:0] 2 00H 1 Y 0 This register is not applicable and not used in IOM-2 mode. Only enabled in PCM/C mode. R1-HW Selection of the PCM highway for receiving PCM data or the higher byte of the first data sample if a linear 16-kHz PCM mode is selected. R1-HW = 0 R1-HW = 1 R1-TS[6:0] PCM highway A is selected. PCM highway B is selected. Selection of the PCM time slot used for data reception. Note: The programmed PCM time slot must correspond to the available slots defined by the PCLK frequency. No reception will occur if a slot outside the actual numbers of slots is programmed. In linear mode (bit LIN = 1 in register BCR3) R1-TS defines the first of two consecutive slots used for reception. Data Sheet 210 2000-07-14 DuSLIC-E/-E2/-P Preliminary 22H Bit PCMR2 7 R2HW SLICOFI-2x Command Structure and Programming PCM Receive Register 2 6 5 4 3 R2-TS[6:0] 2 00H 1 Y 0 This register is not applicable and not used in IOM-2 mode. Only enabled in PCM/C mode. R2-HW Selection of the PCM highway for receiving conferencing data for conference channel B or the lower byte of the first data sample if a linear 16-kHz PCM mode is selected. R2-HW = 0 R2-HW = 1 R2-TS[6:0] PCM highway A is selected. PCM highway B is selected. Selection of the PCM time slot used for receiving data (see description of PCMR1 register). Data Sheet 211 2000-07-14 DuSLIC-E/-E2/-P Preliminary 23H Bit PCMR3 7 R3HW SLICOFI-2x Command Structure and Programming PCM Receive Register 3 6 5 4 3 R3-TS[6:0] 2 00H 1 Y 0 This register is not applicable and not used in IOM-2 mode. Only enabled in PCM/C mode. R3-HW Selection of the PCM highway for receiving conferencing data for conference channel C or the higher byte of the second data sample if a linear 16-kHz PCM mode is selected. R3-HW = 0 R3-HW = 1 R3-TS[6:0] PCM highway A is selected. PCM highway B is selected. Selection of the PCM time slot used for receiving data (see description of PCMR1 register). Data Sheet 212 2000-07-14 DuSLIC-E/-E2/-P Preliminary 24H Bit PCMR4 7 R4HW SLICOFI-2x Command Structure and Programming PCM Receive Register 4 6 5 4 3 R4-TS[6:0] 2 00H 1 Y 0 This register is not applicable and not used in IOM-2 mode. Only enabled in PCM/C mode. R4-HW Selection of the PCM highway for receiving conferencing data for conference channel D or the lower byte of the second data sample if alinear 16-kHz PCM mode is selected. R4-HW = 0 R4-HW = 1 R4-TS[6:0] PCM highway A is selected. PCM highway B is selected. Selection of the PCM time slot used for receiving data (see description of PCMR1 register). Data Sheet 213 2000-07-14 DuSLIC-E/-E2/-P Preliminary 25H Bit PCMX1 7 X1HW SLICOFI-2x Command Structure and Programming PCM Transmit Register 1 6 5 4 3 X1-TS[6:0] 2 00H 1 Y 0 This register is not applicable and not used in IOM-2 mode. Only enabled in PCM/C mode. X1-HW Selection of the PCM highway for transmitting PCM data or the higher byte of the first data sample if a linear 16-kHz PCM mode is selected. X1-HW = 0 X1-HW = 1 X1-TS[6:0] PCM highway A is selected. PCM highway B is selected. Selection of the PCM time slot used for data transmission. Note: The programmed PCM time slot must correspond to the available slots defined by the PCLK frequency. No transmission will occur if a slot outside the actual numbers of slots is programmed. In linear mode X1-TS defines the first of two consecutive slots used for transmission. PCM data transmission is controlled by the bits 6 through 2 in register BCR3. Data Sheet 214 2000-07-14 DuSLIC-E/-E2/-P Preliminary 26H Bit PCMX2 7 X2HW SLICOFI-2x Command Structure and Programming PCM Transmit Register 2 6 5 4 3 X2-TS[6:0] 2 00H 1 Y 0 This register is not applicable and not used in IOM-2 mode. Only enabled in PCM/C mode. X2-HW Selection of the PCM highway for transmitting conferencing data for conference channel C + S or C + D or the lower byte of the first data sample if a linear 16-kHz PCM mode is selected. X2-HW = 0 X2-HW = 1 X2-TS[6:0] PCM highway A is selected. PCM highway B is selected. Selection of the PCM time slot used for transmitting data (see description of PCMX1 register). Data Sheet 215 2000-07-14 DuSLIC-E/-E2/-P Preliminary 27H Bit PCMX3 7 X3HW SLICOFI-2x Command Structure and Programming PCM Transmit Register 3 6 5 4 3 X3-TS[6:0] 2 00H 1 Y 0 This register is not applicable and not used in IOM-2 mode. Only enabled in PCM/C mode. X3-HW Selection of the PCM highway for transmitting conferencing data for conference channel B + S or B + D or the lower byte of the first data sample if a linear 16-kHz PCM mode is selected. X3-HW = 0 X3-HW = 1 X3-TS[6:0] PCM highway A is selected. PCM highway B is selected. Selection of the PCM time slot used for transmitting data (see description of PCMX1 register). Data Sheet 216 2000-07-14 DuSLIC-E/-E2/-P Preliminary 28H Bit PCMX4 7 X4HW SLICOFI-2x Command Structure and Programming PCM Transmit Register 4 6 5 4 3 X4-TS[6:0] 2 00H 1 Y 0 This register is not applicable and not used in IOM-2 mode. Only enabled in PCM/C mode. X4-HW Selection of the PCM highway for transmitting conferencing data for conference channel B + C or the lower byte of the first data sample if a linear 16-kHz PCM mode is selected. X4-HW = 0 X4-HW = 1 X4-TS[6:0] PCM highway A is selected. PCM highway B is selected. Selection of the PCM time slot used for transmitting data (see description of PCMX1 register). Data Sheet 217 2000-07-14 DuSLIC-E/-E2/-P Preliminary 29H Bit TSTR1 7 SLICOFI-2x Command Structure and Programming Test Register 1 6 5 4 3 2 PDGNKC 00H 1 PDOFHC T Y 0 PDOVTC PD-AC- PD-AC- PD-AC- PD-AC- PD-ACPR PO AD DA GN Register setting is only active if bit TEST-EN in register LMCR1 is set to 1. PD-AC-PR AC-PREFI power down PD-AC-PR = 0 PD-AC-PR = 1 PD-AC-PO Normal operation. Power Down mode. AC-POFI power down PD-AC-PO = 0 PD-AC-PO = 1 Normal operation. Power Down mode. PD-AC-AD AC-ADC power down PD-AC-AD = 0 PD-AC-AD = 1 Normal operation. Power Down mode, transmit path is inactive. PD-AC-DA AC-DAC power down PD-AC-DA = 0 PD-AC-DA = 1 Normal operation. Power Down mode, receive path is inactive. PD-AC-GN AC-Gain power down PD-AC-GN = 0 PD-AC-GN = 1 Normal operation. Power Down mode. PD-GNKC Groundkey comparator (GNKC) is set to power down PD-GNKC = 0 PD-GNKC = 1 Normal operation. Power Down mode. Data Sheet 218 2000-07-14 DuSLIC-E/-E2/-P Preliminary PD-OFHC SLICOFI-2x Command Structure and Programming Off-hook comparator (OFHC) power down PD-OFHC = 0 PD-OFHC = 1 PD-OVTC Normal operation. Power Down mode. Overtemperature comparator (OVTC) power down PD-OVTC = 0 PD-OVTC = 1 Normal operation. Power Down mode. Data Sheet 219 2000-07-14 DuSLIC-E/-E2/-P Preliminary 2AH Bit TSTR2 7 PD-DCPR SLICOFI-2x Command Structure and Programming Test Register 2 6 0 5 4 3 2 0 00H 1 PDTTX-A T Y 0 PD-HVI PD-DC- PD-DCPDAD DA DCBUF Register setting is only active if bit TEST-EN in register LMCR1 is set to 1. PD-DC-PR DC-PREFI power down PD-DC-PR = 0 PD-DC-PR = 1 PD-DC-AD Normal operation. Power Down mode. DC-ADC power down PD-DC-AD = 0 PD-DC-AD = 1 Normal operation. Power Down mode, transmit path is inactive. PD-DC-DA DC-DAC power down PD-DC-DA = 0 PD-DC-DA = 1 Normal operation. Power Down mode, receive path is inactive. PD-DCBUF DC-BUFFER power down PD-DCBUF = 0 PD-DCBUF = 1 Normal operation. Power Down mode. PD-TTX-A TTX Adaptation DAC and POFI power down PD-TTX-A = 0 PD-TTX-A = 1 Normal operation. Power Down mode. PD-HVI HV interface (to SLIC-E/-E2/-P) power down PD-HVI = 0 PD-HVI = 1 Normal operation. Power Down mode. Data Sheet 220 2000-07-14 DuSLIC-E/-E2/-P Preliminary 2BH Bit TSTR3 7 0 SLICOFI-2x Command Structure and Programming Test Register 3 6 0 5 ACDLB4M 4 ACDLB128K 3 ACDLB32K 2 ACDLB8K 00H 1 0 T Y 0 0 Register setting is only active if bit TEST-EN in register LMCR1 is set to 1. AC-DLB-4M AC digital loop via a 4-MHz bitstream. (Loop encloses all digital hardware in the AC path. Together with DLB-DC, a pure digital test is possible because there is no influence from the analog hardware.) AC-DLB-4M = 0 AC-DLB-4M = 1 Normal operation. Digital loop closed. AC-DLB-128K AC digital loop via 128 kHz AC-DLB-128K = 0 Normal operation. AC-DLB-128K = 1 Digital loop closed. AC-DLB-32K AC digital loop via 32 kHz AC-DLB-32K = 0 AC-DLB-32K = 1 AC-DLB-8K Normal operation. Digital loop closed. AC digital loop via 8 kHz AC-DLB-8K = 0 AC-DLB-8K = 1 Normal operation. Digital loop closed. Data Sheet 221 2000-07-14 DuSLIC-E/-E2/-P Preliminary 2CH Bit TSTR4 7 OPIMAN SLICOFI-2x Command Structure and Programming Test Register 4 6 OPIM4M 5 4 3 0 2 0 00H 1 0 T Y 0 0 COR-64 COX-16 Register setting is only active if bit TEST-EN in register LMCR1 is set to 1. OPIM-AN Open Impedance Matching Loop in the analog part. OPIM-AN = 0 OPIM-AN = 1 OPIM-4M Normal operation. Loop opened. Open fast digital Impedance Matching Loop in the hardware filters. OPIM-4M = 0 OPIM-4M = 1 Normal operation. Loop opened. COR-64 Cut off the AC receive path at 64 kHz (just before the IM filter). COR-64 = 0 COR-64 = 1 Normal operation. Receive path is cut off. COX-16 Cut off the AC transmit path at 16 kHz. (The TH filter can be tested without influencing the analog part.) COX-16 = 0 COX-16 = 1 Normal operation. Transmit path is cut off. Data Sheet 222 2000-07-14 DuSLIC-E/-E2/-P Preliminary 2DH Bit TSTR5 7 0 SLICOFI-2x Command Structure and Programming Test Register 5 6 0 5 0 4 DCPOFIHI 3 DCHOLD 2 0 00H 1 0 T Y 0 0 Register setting is only active if bit TEST-EN in register LMCR1 is set to 1. DC-POFI-HI Higher value for DC post filter limit DC-POFI-HI = 0 DC-POFI-HI = 1 DC-HOLD Limit frequency is set to 100 Hz (normal operation). Limit frequency is set to 300 Hz. Actual DC output value hold (value of the last DSP filter stage will be kept) DC-HOLD = 0 DC-HOLD = 1 Normal operation. DC output value hold. Data Sheet 223 2000-07-14 DuSLIC-E/-E2/-P Preliminary SLICOFI-2x Command Structure and Programming 6.2.2 COP Command The COP command gives access to the CRAM data of the DSPs. It is organized in the same way as the SOP command. The offset value allows a direct as well as a block access to the CRAM. Writing beyond the allowed offset will be ignored, reading beyond it will give unpredictable results. The value of a specific CRAM coefficient is calculated by the DuSLICOS software. Bit Byte 1 Byte 2 RD Read Data RD = 0 Write data to chip. RD = 1 Read data from chip. ADR[2:0] Channel address for the subsequent data 7 RD 6 1 5 4 ADR[2:0] OFFSET[7:0] 3 2 1 1 0 0 1 ADR[2:0] = 0 0 0 ADR[2:0] = 0 0 1 Channel A Channel B (other codes reserved for future use) Data Sheet 224 2000-07-14 DuSLIC-E/-E2/-P Preliminary Offset [7:0] 00H 08H 10H 18H 20H 28H 30H 38H 40H 48H 50H 58H 60H 68H 70H 78H 80H 88H 90H 98H Short Name TH1 TH2 TH3 FRR FRX AR AX PTG1 PTG2 LPR LPX TTX IM1 IM2 RINGF RAMPF DCF HF TPF SLICOFI-2x Command Structure and Programming Long Name Transhybrid Filter Coefficients Part 1 Transhybrid Filter Coefficients Part 2 Transhybrid Filter Coefficients Part 3 Frequency-response Filter Coefficients Receive Direction Frequency-response Filter Coefficients Transmit Direction Amplification/Attenuation Stage Coefficients Receive Amplification/Attenuation Stage Coefficients Transmit Tone Generator 1 Coefficients Tone Generator 2 Coefficients Low Pass Filter Coefficients Receive Low Pass Filter Coefficients Transmit Teletax Coefficients Impedance Matching Filter Coefficients Part 1 Impedance Matching Filter Coefficients Part 2 Ringer Frequency and Amplitude Coefficients (DC loop) Ramp Generator Coefficients (DC loop) DC Characteristics Coefficients (DC loop) Hook Threshold Coefficients (DC loop) Low-pass Filter Coefficients (DC loop) Reserved Data Sheet 225 2000-07-14 DuSLIC-E/-E2/-P Preliminary Table 51 Byte 7 SLICOFI-2x Command Structure and Programming CRAM Coefficients Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 Offset [7:0] 00H 08H 10H 18H 20H 1st Gain Stage Receive 1st Gain Stage Transmit TG1 Gain TG2 Gain TG1 Frequency TG2 Frequency 28H 30H 38H 40H 48H 50H TTX Slope IM FIR Filter IM WDF Filter Ring Generator Frequency Constant Ramp CR Ring Generator Low-pass Soft Ramp SS Ring Offset RO1 Ring Delay RD TTX Level 58H 60H 68H 70H 78H TH1 TH2 TH3 FRR FRX AR AX PTG1 1) PTG2 1) LPR 2) LPX 2) TTX IM1_F IM2_F RINGF RAMPF Transhybrid Coefficient Part 1 Transhybrid Coefficient Part 2 Transhybrid Coefficient Part 3 FIR Filter in Receive Direction FIR Filter in Transmit Direction LM Threshold Bandpass for AC LM Conference Gain LMAC 2nd Gain Stage Receive 2nd Gain Stage Transmit TG1 Bandpass TG2 Bandpass LPR LPX FIR Filter for TTX IM K Factor IM 4 MHz Filter LM DC Gain Extended Battery Feeding Gain Res. in Resistive Zone RK12 Ring Generator Amplitude Soft Reversal End Res. in Constant Current Zone RI Constant Current IK1 Hook Threshold Ring Knee Voltage VK1 Hook Threshold Active Open Circuit Volt. 80H 88H 90H 98H DCF HF TPF VLIM Hook Threshold Power Down DC Low-pass Filter TP1 Hook Message Waiting Ring Offset RO3 Hook Threshold AC Ringtrip Ring Offset RO2 Voltage Level VRT Reserved DC Low-pass Filter TP2 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Note: CRAM coefficients are enabled by setting bit CRAM-EN in register BCR3 to 1, except coefficients marked 1) and 2): Coefficients market 1) are enabled by setting bit PTG in register DSCR to 1. Coefficients market 2) are enabled by setting bit LPRX-CR in register BCR3 to 1. Data Sheet 226 2000-07-14 DuSLIC-E/-E2/-P Preliminary SLICOFI-2x Command Structure and Programming 6.2.2.1 Table 52 Parameter CRAM Programming Ranges CRAM Programming Ranges Programming Range 0...50 mA, < 0.5 mA 0..25 mA, < 0.7 mA 25...50 mA, < 1.3 mA 3..40 Hz, < 1 Hz 40..80 Hz, < 2 Hz > 80 Hz, < 4 Hz 0..20 V, < 1.7 V 20..85 V, < 0.9 V 0..25 V, < 0.6 V 25..50 V, < 1.2 V 50..100 V, < 2.4 V, max. 150 V 0..25 V, < 0.6 V 25..50 V, < 1.2 V > 50 V, < 2.4 V 0..1000 , < 30 1.8 k..4.8 k, < 120 4.8 k..9.6 k, < 240 9.6 k..19 k, < 480 19 k..38 k, < 960 , max. 40 k Constant Current IK1 Hook Message Waiting, Hook Thresholds Ring Generator Frequency fRING Ring Generator Amplitude Ring Offset RO1, RO2, RO3 Knee Voltage VK1, Open Circuit Voltge VLIM Resistance in Resistive Zone RK12 Resistance in Constant Current Zone RI Data Sheet 227 2000-07-14 DuSLIC-E/-E2/-P Preliminary SLICOFI-2x Command Structure and Programming 6.2.3 POP Command The POP command provides access to the EDSP registers of the SLICOFI-2. Before using an EDSP function the according POP registers have to be programmed. Any change in any of the POP registers (except registers CIS-DAT and CIS/LEC-MODE) is only updated with enabling the corresponding device. For example a change of the center frequency fC of the UTD is handled by changing the registers UTD-CF-H and UTD-CF-L, switching off the UTD and switching it on again. The POP registers do no have default values after any kind of reset. 6.2.3.1 00H POP Register Overview CIS-DAT Caller ID Sender Data Buffer (write-only) 30H DTMF-LEV 0 DTMF Receiver Level Byte b e 31H DTMF-TWI DTMF Receiver Twist Byte TWI 32H DTMF-NCF-H DTMF Receiver Notch Filter Center Frequency High Byte NCF-H 33H DTMF-NCF-L DTMF Receiver Notch Filter Center Frequency Low Byte NCF-L 34H DTMF-NBW-H DTMF Receiver Notch Filter Bandwidth High Byte NBW-H 35H DTMF-NBW-L DTMF Receiver Notch Filter Bandwidth Low Byte NBW-L 36H DTMF-GAIN e Gain Stage Control for DTMF Input Signal m Data Sheet 228 2000-07-14 DuSLIC-E/-E2/-P Preliminary SLICOFI-2x Command Structure and Programming 37H DTMF-RES1 DTMF Receiver Reserved Byte 1 38H DTMF-RES2 DTMF Receiver Reserved Byte 2 39H DTMF-RES3 DTMF Receiver Reserved Byte 3 3AH LEC-LEN Line Echo Canceller Length LEN 3BH LEC-POWR Line Echo Canceller Power Detection Level POWR 3CH LEC-DELP Line Echo Canceller Delta Power DELP 3DH LEC-DELQ Line Echo Canceller Delta Quality DELQ 3EH LEC-GAIN-XI e Line Echo Canceller Input Gain Transmit m 3FH LEC-GAIN-RI e Line Echo Canceller Input Gain Receive m 40H LEC-GAIN-XO e Line Echo Canceller Output Gain Transmit m 41H LEC-RES1 Line Echo Canceller Reserved Byte 1 Data Sheet 229 2000-07-14 DuSLIC-E/-E2/-P Preliminary SLICOFI-2x Command Structure and Programming 42H LEC-RES2 Line Echo Canceller Reserved Byte 2 43H CIS-LEV-H Caller ID Sender Level High Byte LEV-H 44H CIS-LEV-L Caller ID Sender Level Low Byte LEV-L 45H CIS-BRS Caller ID Sender Buffer Request Size BRS 46H CIS-SEIZ-H Caller ID Sender Number of Seizure Bits High Byte SEIZ-H 47H CIS-SEIZ-L Caller ID Sender Number of Seizure Bits Low Byte SEIZ-L 48H CIS-MARK-H Caller ID Sender Number of Mark Bits High Byte MARK-H 49H CIS-MARK-L Caller ID Sender Number of Mark Bits Low Byte MARK-L 4AH CIS/LEC-MODE LEC-ADAPT LEC-FREZE CIS/LEC Mode Setting UTDX-SUM UTDR-SUM 0 0 CIS-FRM CIS-V23 4BH UTD-CF-H Universal Tone Detection Center Frequency High Byte CF-H 4CH UTD-CF-L Universal Tone Detection Center Frequency Low Byte CF-L Data Sheet 230 2000-07-14 DuSLIC-E/-E2/-P Preliminary SLICOFI-2x Command Structure and Programming 4DH UTD-BW-H Universal Tone Detection Bandwidth High Byte BW-H 4EH UTD-BW-L Universal Tone Detection Bandwidth Low Byte BW-L 4FH UTD-NLEV Universal Tone Detection Noise Level NLEV 50H UTD-SLEV-H Universal Tone Detection Signal Level High Byte SLEV-H 51H UTD-SLEV-L Universal Tone Detection Signal Level Low Byte SLEV-L 52H UTD-DELT Universal Tone Detection Delta DELT-H 53H UTD-RBRK Universal Tone Detection Recognition Break Time RBRK 54H UTD-RTIME Universal Tone Detection Recognition Time RTIME 55H UTD-EBRK UTD Allowed Tone End Detection Break Time EBRK 56H UTD-ETIME UTD Tone End Detection Time ETIME Data Sheet 231 2000-07-14 DuSLIC-E/-E2/-P Preliminary SLICOFI-2x Command Structure and Programming 6.2.4 00H POP Register Description CIS-DAT Caller ID Sender Data Buffer (write-only) Y Bit 7 6 5 4 Byte 0 3 2 1 0 Byte 1 Byte 2 Byte 47 Data Sheet 232 2000-07-14 DuSLIC-E/-E2/-P Preliminary 30H Bit DTMF-LEV 7 6 0 SLICOFI-2x Command Structure and Programming DTMF Receiver Level Byte 5 4 b 3 2 1 e Y 0 Minimum DTMF Signal Detection Level LevelDTMFdet * for DTMF detection in transmit: LevelDTMFdet[dB] = LevelDTMFdet[dBm0] - 3.14 + GDTMF[dB] LevelDTMFdet[dB] = LevelDTMFdet[dBm] - Lx[dBr] - 3.14 + GDTMF[dB] * for DTMF detection in receive: LevelDTMFdet[dB] = LevelDTMFdet[dBm0] - 3.14 + AR1[dB] + GDTMF[dB] LevelDTMFdet[dB] = LevelDTMFdet[dBm] - LR[dBr] - 3.14 + AR1[dB] + GDTMF[dB] AR1[dB]: The exact value for AR1 is shown in the DuSLICOS result file; approximate value AR1 LR for LR - 2 dBr, AR1 - 2 dB for LR > - 2 dBr. LevelDTMFdet[dB] = - 30 - b - 3 x e[dB] - 54 dB LevelDTMFdet - 30 dB with 0e7 0b3 Alternative representation b = MOD[(- LevelDTMFdet[dB] - 30),3] e = INT[(- LevelDTMFdet[dB] - 30)/3] Note: MOD = Modulo function, INT = Integer function Data Sheet 233 2000-07-14 DuSLIC-E/-E2/-P Preliminary 31H Bit DTMF-TWI 7 6 SLICOFI-2x Command Structure and Programming DTMF Receiver Twist Byte 5 4 TWI 3 2 1 Y 0 DTMF Receiver Twist is the maximum allowed difference between the signal levels of the two tones for DTMF detection: TWI[dB] = 2 x Twistacc[dB] 0 dB Twistacc 12 dB Data Sheet 234 2000-07-14 DuSLIC-E/-E2/-P Preliminary 32H SLICOFI-2x Command Structure and Programming Y DTMF-NCF-H DTMF Receiver Notch Filter Center Frequency High Byte 7 6 5 4 NCF-H 3 2 1 Bit 0 33H DTMF-NCF-L DTMF Receiver Notch Filter Center Frequency Low Byte 7 6 5 4 NCF-L 3 2 1 Y Bit 0 DTMF Receiver Notch Filter Center Frequency: f NCF [ Hz ] NCF = 32768 x cos ae 2 --------------------- o = NCF-L + 256 x NCF-H - e 8000 0 Hz fNCF 2000 Hz The bytes are calculated as follows: NCF-L = MOD (NCF,256) = NCF & 0x00FF NCF-H = INT (NCF/256) = NCF >> 8 The echo of the dial tone can activate the double talk detection which means that the DTMF tone will not be detected. Therefore a notchfilter can be programmed to filter out the echo of the dialtone, because the frequency of the dialtone is known. The center frequency and the bandwith of the notch filter can be programmed. Data Sheet 235 2000-07-14 DuSLIC-E/-E2/-P Preliminary 34H SLICOFI-2x Command Structure and Programming Y DTMF-NBW-H DTMF Receiver Notch Filter Bandwidth High Byte 7 6 5 4 NBW-H 3 2 1 Bit 0 35H DTMF-NBW-L DTMF Receiver Notch Filter Bandwidth Low Byte 5 4 NBW-L 3 2 1 Y Bit 7 6 0 DTMF Receiver Notch Filter Bandwidth: a NBW = 65536 x ------------ = NBW-L + 256 x NBW-H 1+a with F NBW [ Hz ] a = tan ae --------------------------- o e 8000 0 Hz FNBW 2000 Hz NBWL = MOD (NBW,256) NBWH = INT (NBW/256) Data Sheet 236 2000-07-14 DuSLIC-E/-E2/-P Preliminary 36H Bit SLICOFI-2x Command Structure and Programming Y 1 0 DTMF-GAIN Gain Stage Control for DTMF Input Signal 7 6 e 5 4 3 2 m DTMF Input Signal Gain: GDTMF[dB] = 20 x log1016 + 20 x log10[g/32768] 24.08 + 20 x log10[g/32768] - 24.08 dB GDTMF 23.95 dB with g = 2(9 - e) (32 + m) and 0 m 31, 0 e 7 Table 53 e 0 1 7 Ranges of GDTMF[dB] dependent on "e" DTMF Input Signal Gain GDTMF [dB] Range 23.95 dB GDTMF 18.06 dB 17.93 dB GDTMF 12.04 dB - 18.20 dB GDTMF - 24.08 dB Alternative representation: Choose "e" as the next integer number which is bigger than or equal to: log 10GDTMF G DTMF [ dB ] e 3 - log 2GDTMF = 3 - ------------------------------- 3 - ------------------------------log 102 6.02 m = G DTMF x 2 Table 54 GDTMF[dB] 0 - 6.02 6.02 2+e - 32 = 10 G DTMF [ dB ] -----------------------------20 x2 2+e - 32 Example for DTMF-GAIN Calculation GDTMF 1 0.5 2 e 3 4 2 m 0 0 0 DTMF-GAIN 0x60 0x80 0x40 Data Sheet 237 2000-07-14 DuSLIC-E/-E2/-P Preliminary 37H Bit SLICOFI-2x Command Structure and Programming DTMF-RES1 DTMF Receiver Reserved Byte 1 7 6 5 4 3 2 1 Y 0 38H Bit DTMF-RES2 DTMF Receiver Reserved Byte 2 7 6 5 4 3 2 1 Y 0 39H Bit DTMF-RES3 DTMF Receiver Reserved Byte 3 7 6 5 4 3 2 1 Y 0 Data Sheet 238 2000-07-14 DuSLIC-E/-E2/-P Preliminary 3AH Bit LEC-LEN 7 SLICOFI-2x Command Structure and Programming Line Echo Canceller Length 6 5 4 LEN 3 2 1 Y 0 Line Echo Canceller Length: LEN = LEC Length[ms] / 0.125 LEC Length has to be entered in multiples of 0.125 ms. The selected LEC Length has to be higher than the maximum line echo length but not higher than 8 ms. Table 6-1 LEN 1 ... 64 8 ms LEC Length LEC Length 0.125 ms Data Sheet 239 2000-07-14 DuSLIC-E/-E2/-P Preliminary 3BH LEC-POWR SLICOFI-2x Command Structure and Programming Line Echo Canceller Power Detection Level 6 5 4 POWR Minimum Power Detection Level for Line Echo Canceller: PowLECR[dB] = SR,LEC-POWR[dBm0] - 3.14 + AR1[dB] + GLEC-RI[dB] - 20*log10(/2) SR,LEC-POWR[dBm0]: Minimum Power Detection Level for Line Echo Canceller at digital input AR1[dB]: The exact value for AR1 is shown in the DuSLICOS result file; approximate value AR1 LR for LR - 2 dBr, AR1 - 2 dB for LR > - 2 dBr. POWR = (6.02 x 16 + PowLECR[dB]) x 2 / (5 x log102) = (96.32 + PowLECR[dB]) x 1.329 - 96 dB PowLECR 0 dB Table 55 POWR 0x00 ... 0x7F Example: AR1 = - 3 dB SR,LEC-POWR = - 40 dBm0 PowLECR = - 46.14 dB POWR = 66.69 67 = 0x43 0 Characteristic Values PowLECR[dB] - 96 3 2 1 Y Bit 7 0 Data Sheet 240 2000-07-14 DuSLIC-E/-E2/-P Preliminary 3CH Bit LEC-DELP 7 6 SLICOFI-2x Command Structure and Programming Line Echo Canceller Delta Power 5 4 DELP Line Echo Canceller Delta Power for Double Talk Detection (DTD): DeltaPLEC[dB] = (SR - SX)DTDThr[dB] + AR1[dB] + GLEC-RI[dB] - GLEC-XI[dB] (SR - SX)DTDThr[dB]: Double Talk Detection threshold AR1[dB]: The exact value for AR1 is shown in the DuSLICOS result file; approximate value AR1 LR for LR - 2 dBr, AR1 - 2 dB for LR > - 2 dBr. DELP = DeltaPLEC[dB] x 2/5 x log102 = DeltaPLEC[dB] x 1.329 - 96 dB DeltaPLEC 96 dB Table 56 DELP 0x81 ... 0x7F Example: AR1 = - 3 dB expected echo signal < - 15 dB (SR - SX)DTDThr = - 15 dB DeltaPLEC = 12 dB DELP = 16 = 0x10 96 Characteristic Values DeltaPLEC[dB] - 96 3 2 1 Y 0 Data Sheet 241 2000-07-14 DuSLIC-E/-E2/-P Preliminary 3DH Bit LEC-DELQ 7 6 SLICOFI-2x Command Structure and Programming Line Echo Canceller Delta Quality 5 4 DELQ Line Echo Canceller Delta Quality Between Shadow Filter and Main Filter: The higher DeltaQ is, the less copying between shadow filter and main filter takes place and the higher is the quality. DELQ[dB] = DeltaQ[dB] x 2/5 x log102 = DeltaQ[dB] x 1.329 0 dB DeltaQ 10 dB Table 57 DELQ 8 4 3 2 Characteristic Values DeltaQ[dB] 6.02 dB 3.01 dB (typical) 2.26 dB 1.505 dB 3 2 1 Y 0 Data Sheet 242 2000-07-14 DuSLIC-E/-E2/-P Preliminary 3EH Bit SLICOFI-2x Command Structure and Programming Y 1 0 LEC-GAIN-XI Line Echo Canceller Input Gain Transmit 7 6 e 5 4 3 2 m Line Echo Canceller Input Gain Transmit: It is important, that GLEC-XI[dB] will not be changed, so GLEC-XI[dB] = - GLEC-X0[dB] GLEC-XI[dB] = 20 x log1016 + 20 x log10[g/32768] 24.08 + 20 x log10[g/32768] - 24.08 dB GLEC-XI 23.95 dB with g = 29-e (32 + m) and 0 m 31, 0 e 7 Table 58 e 0 1 7 Ranges of GLEC-XI[dB] Dependent on "e" Input Gain GLEC-XI[dB] Range 23.95 dB GLEC-XI 18.06 dB 17.93 dB GLEC-XI 12.04 dB - 18.20 dB GLEC-XI - 24.08 dB Alternative representation: Choose "e" as the next integer number which is bigger than or equal to: log 10GLEC - XI G LEC - XI [ dB ] e 3 - log 2GLEC - XI = 3 - ------------------------------------ 3 - -----------------------------------log 102 6.02 m = G LEC - XI x 2 Table 59 GLEC-XI[dB] 0 - 6.02 6.02 2+e - 32 = 10 G LEC - XI [ dB ] ---------------------------------20 x2 2+e - 32 Example for LEC-GAIN-XI Calculation GLEC-XI 1 0.5 2 e 3 4 2 m 0 0 0 LEC-GAIN-XI 0x60 0x80 0x40 Data Sheet 243 2000-07-14 DuSLIC-E/-E2/-P Preliminary 3FH Bit SLICOFI-2x Command Structure and Programming Y 1 0 LEC-GAIN-RI Line Echo Canceller Input Gain Receive 7 6 e 5 4 3 2 m Line Echo Canceller Input Gain Receive: GLEC-RI[dB] = 20 x log1016 + 20 x log10[g/32768] 24.08 + 20 x log10[g/32768] - 24.08 dB GLEC-RI 23.95 dB with g = 29-e (32 + m) and 0 m 31, 0 e 7 Table 60 e 0 1 7 Ranges of GLEC-RI[dB] Dependent on "e" Input Gain GLEC-RI[dB] Range 23.95 dB GLEC-RI 18.06 dB 17.93 dB GLEC-RI 12.04 dB - 18.20 dB GLEC-RI - 24.08 dB Alternative representation: Choose "e" as the next integer number which is bigger than or equal to: log 10GLEC - RI G LEC - RI [ dB ] e 3 - log 2GLEC - RI = 3 - ------------------------------------- 3 - -----------------------------------log 102 6.02 m = G LEC - RI x 2 Table 61 GLEC-RI[dB] 0 - 6.02 6.02 2+e - 32 = 10 G LEC - RI [ dB ] ----------------------------------20 x2 2+e - 32 Example for LEC-GAIN-RI Calculation GLEC-RI 1 0.5 2 e 3 4 2 m 0 0 0 LEC-GAIN-RI 0x60 0x80 0x40 Data Sheet 244 2000-07-14 DuSLIC-E/-E2/-P Preliminary 40H Bit SLICOFI-2x Command Structure and Programming Y 1 0 LEC-GAIN-XO Line Echo Canceller Output Gain Transmit 7 6 e 5 4 3 2 m Line Echo Canceller Output Gain Transmit: It is important, that GLEC-X0[dB] will not be changed, so GLEC-X0[dB] = - GLEC-XI[dB] GLEC-X0[dB] = 20 x log1016 + 20 x log10[g/32768] 24.08 + 20 x log10[g/32768] - 24.08 dB GLEC-X0 23.95 dB with g = 29-e (32 + m) and 0 m 31, 0 e 7 Table 62 e 0 1 7 Ranges of GLEC-X0[dB] Dependent on "e" Output Gain GLEC-X0[dB] Range 23.95 dB GLEC-X0 18.06 dB 17.93 dB GLEC-X0 12.04 dB - 18.20 dB GLEC-X0 - 24.08 dB Alternative representation: Choose "e" as the next integer number which is bigger than or equal to: log 10GLEC - X0 G LEC - X0 [ dB ] e 3 - log 2GLEC - X0 = 3 - -------------------------------------- 3 - ------------------------------------log 102 6.02 m = G LEC - X0 x 2 Table 63 GLEC-X0[dB] 0 - 6.02 6.02 2+e - 32 = 10 G LEC - X0 [ dB ] -----------------------------------20 x2 2+e - 32 Example for LEC-GAIN-X0 Calculation GLEC-X0 1 0.5 2 e 3 4 2 m 0 0 0 LEC-GAIN-X0 0x60 0x80 0x40 Data Sheet 245 2000-07-14 DuSLIC-E/-E2/-P Preliminary 41H Bit LEC-RES1 7 SLICOFI-2x Command Structure and Programming Line Echo Canceller Reserved Byte 1 6 5 4 3 2 1 Y 0 42H Bit LEC-RES2 7 Line Echo Canceller Reserved Byte 2 6 5 4 3 2 1 Y 0 Data Sheet 246 2000-07-14 DuSLIC-E/-E2/-P Preliminary 43H Bit CIS-LEV-H 7 SLICOFI-2x Command Structure and Programming Caller ID Sender Level High Byte 6 5 4 LEV-H 3 2 1 Y 0 44H Bit CIS-LEV-L 7 Caller ID Sender Level Low Byte 6 5 4 LEV-L 3 2 1 Y 0 Caller ID Sender Level: LevCIS[dB] = LevCIS[dBm0] - 3.14 - 3.37 LevCIS[dB] = LevCIS[dBm] -LR[dBr] - 3.14 - 3.37 LEV = 32767 x 10 (LevCIS[dB]/20) - 90.31 dB LevCIS 0 dB LEV-L = MOD (LEV,256) LEV-H = INT (LEV/256) Table 64 LEV 0 1 32767 Examples Level [dB] - (signal off) - 90.31 0 Data Sheet 247 2000-07-14 DuSLIC-E/-E2/-P Preliminary 45H Bit CIS-BRS 7 SLICOFI-2x Command Structure and Programming Caller ID Sender Buffer Request Size 6 5 4 BRS 3 2 1 Y 0 Caller ID Sender Buffer Request Size: 0 BRS 46 CIS-BRS is a threshold to be set within the Caller ID sender buffer (CIS-DAT, 48 bytes). If the number of bytes in the CID sender buffer falls below the buffer request size an interrupt is generated. This is the indication to fill up the buffer again. The first bit will be sent if the number of bytes in the CID sender buffer exceeds the buffer request size (start sending with BRS + 1 number of bytes). The buffer request size BRS must always be smaller than the number of bytes to be sent: BRS < Number of bytes to be sent Typical values: 10 - 30. Data Sheet 248 2000-07-14 DuSLIC-E/-E2/-P Preliminary 46H CIS-SEIZ-H SLICOFI-2x Command Structure and Programming Caller ID Sender Number of Seizure Bits High Byte 6 5 4 SEIZ-H 3 2 1 Y Bit 7 0 47H CIS-SEIZ-L Caller ID Sender Number of Seizure Bits Low Byte 6 5 4 SEIZ-L 3 2 1 Y Bit 7 0 Caller ID Sender Number of Seizure Bits: (only if High Level Framing is selected in the CIS/LEC-MODE register (see Page 251)) 0 SEIZ 32767 SEIZ-L = MOD (SEIZ,256) SEIZ-H = INT (SEIZ/256) Data Sheet 249 2000-07-14 DuSLIC-E/-E2/-P Preliminary 48H CIS-MARK-H SLICOFI-2x Command Structure and Programming Caller ID Sender Number of Mark Bits High Byte 5 4 3 2 1 Y Bit 7 6 0 MARK-H 49H CIS-MARK-L Caller ID Sender Number of Mark Bits Low Byte 5 4 3 2 1 Y Bit 7 6 0 MARK-L Caller ID Sender Number of Mark Bits: (only if High Level Framing is selected in the CIS/LEC-MODE register) 0 MARK 32767 MARK-L = MOD (MARK,256) MARK-H = INT (MARK/256) Data Sheet 250 2000-07-14 DuSLIC-E/-E2/-P Preliminary 4AH CIS/LECMODE 7 SLICOFI-2x Command Structure and Programming CIS/LEC Mode Setting Y Bit 6 5 4 UTDRSUM 3 0 2 0 1 CISFRM 0 CISV23 LECLECUTDXADAPT FREEZE SUM LEC-ADAPT Line Echo Canceller Adaptation Start. The LEC-ADAPT bit is only evaluated if the LEC-EN is changed from 0 to 1. To initialize the LEC coefficients to 0 requires the LEC-ADAPT bit set to 0 followed by the LEC-EN bit changed from 0 to 1. It is not possible to reset the LEC coefficients to 0 while the LEC is running. The LEC has to be disabled first by setting bit LEC-EN to 0 and then it is necessary to enable the LEC again (LEC-EN = 1, LEC-ADAPT = 0). If valid coefficients from a former LEC adaptation are present in the RAM, it is possible to activate the LEC with this coefficents by setting bit LEC-ADAPT to 1. It is also possible to read out adapted coefficients from the LEC for external storage and to reuse these coefficients as a start up value for the next connection (see the available Apllication Notes). LEC-ADAPT = 0 LEC-ADAPT = 1 Line Echo Canceller coefficients initialized with zero Line Echo Canceller coefficients initialized with old coefficients LEC-FREEZE Line Echo Canceller Adaptation Freeze LEC-FREEZE = 0 No freezing of coefficients LEC-FREEZE = 1 Freezing of coefficients UTDX-SUM Sum signal for Universal Tone Detection unit in transmit direction UTDX-SUM = 0 UTDX-SUM = 1 The transmit signal is fed through The sum signal SSUM (receive signal + LEC signal, if LEC is enabled) is fed through (see bit UTDX-SRC in BCR2 and Figure 32) Data Sheet 251 2000-07-14 DuSLIC-E/-E2/-P Preliminary UTDR-SUM SLICOFI-2x Command Structure and Programming Sum signal for Universal Tone Detection unit in receive direction UTDR-SUM = 0 UTDR-SUM = 1 The receive signal is fed to the UDT unit The sum signal SSUM (receive signal + LEC signal, if LEC is enabled) is fed to the UTD unit CIS-FRM Caller ID Sender Framing CIS-FRM = 0 Low-level framing: all data for CID transmissions have to be written to the CID Buffer including channel seizure and mark sequence, start and stop bits. High-level framing: channel seizure and mark sequence as well as start and stop bits are automatically inserted by the SLICOFI-2x. Only transmission bytes from the Data Packet (see Figure 33) have to be written to the CIS buffer. CIS-FRM = 1 CIS-V23 Caller ID Sender Mode CIS-V23 = 0 CIS-V23 = 1 Bell 202 selected V.23 selected Data Sheet 252 2000-07-14 DuSLIC-E/-E2/-P Preliminary 4BH UTD-CF-H SLICOFI-2x Command Structure and Programming Universal Tone Detection Center Frequency High Byte 6 5 4 CF-H 3 2 1 Y Bit 7 0 4CH UTD-CF-L Universal Tone Detection Center Frequency Low Byte 6 5 4 CF-L 3 2 1 Y Bit 7 0 Universal Tone Detection Center Frequency: *** ] ae 2 f c [ Hz -o CF = 32768 x cos ----------------------e 8000 0 < fC < 4000 Hz CF-L = MOD (CF,256) CF-H = INT (CF/256) Data Sheet 253 2000-07-14 DuSLIC-E/-E2/-P Preliminary 4DH UTD-BW-H SLICOFI-2x Command Structure and Programming Universal Tone Detection Bandwidth High Byte 6 5 4 BW-H 3 2 1 Y Bit 7 0 4EH UTD-BW-L Universal Tone Detection Bandwidth Low Byte 6 5 4 BW-L 3 2 1 Y Bit 7 0 Universal Tone Detection Bandwidth: a BW = 65536 x -----------1+a with f BW [ Hz ] x a = tan ae ------------------------------- o e 8000 0 < fBW < 2000 Hz BW-L = MOD (BW,256) BW-H = INT (BW/256) Data Sheet 254 2000-07-14 DuSLIC-E/-E2/-P Preliminary 4FH Bit UTD-NLEV 7 6 SLICOFI-2x Command Structure and Programming Universal Tone Detection Noise Level 5 4 NLEV 3 2 1 Y 0 Universal Tone Detection Noise Level: NLEV = 32768 x 10(LevN[dB])/20 - 96 dB LevN - 42.18 dB Data Sheet 255 2000-07-14 DuSLIC-E/-E2/-P Preliminary 50H SLICOFI-2x Command Structure and Programming Y UTD-SLEV-H Universal Tone Detection Signal Level High Byte 7 6 5 4 SLEV-H 3 2 1 Bit 0 51H UTD-SLEV-L Universal Tone Detection Signal Level Low Byte 7 6 5 4 SLEV-L 3 2 1 Y Bit 0 Universal Tone Detection Signal Level: Calculation for Transmit: LevS[dB] = LevS[dBm0] - 3.14 - 20*log10(/2) LevS[dB] = LevS[dBm] - Lx[dBr] - 3.14 - 20*log10(/2) Calculation for Receive: LevS[dB] = LevS[dBm0] - 3.14 + AR1[dB] - 20*log10(/2) LevS[dB] = LevS[dBm] - LR[dBr] - 3.14 + AR1[dB] - 20*log10(/2) AR1[dB]: The exact value for AR1 is shown in the DuSLICOS result file; approximate value AR1 LR for LR - 2 dBr, AR1 - 2 dB for LR > - 2 dBr. SLEV = 32768 x 10(LevS[dB])/20 - NLEV - 96 dB LevS 0 dB Signal Level: SLEV-L = MOD (SLEV,256) SLEV-H = INT (SLEV/256) UTD for Receive and Transmit: By enabling the UTD the coefficients in the UTD registers are copied to the main memory. Therefore different coefficients can be set for receive and transmit direction. Data Sheet 256 2000-07-14 DuSLIC-E/-E2/-P Preliminary 52H Bit UTD-DELT 7 6 SLICOFI-2x Command Structure and Programming Universal Tone Detection Delta 5 4 DELT 3 2 1 Y 0 Universal Tone Detection Delta Inband/Outband: DELT = Sign(DeltaUTD) x 128 x 10-|DeltaUTD[dB]|/20 - 42 dB DeltaUTD 42 dB Example: Detection of a tone that is between 1975 Hz and 2025 Hz =fC = 2000 Hz * fBW = 50 Hz Tone at 2025 Hz: Outband = - 3 dB, Inband = - 3 dB (see Table 65) DeltaUTD = 0 dB DELT = 128 = 0x80 * fBW = 500 Hz Tone at 2025 Hz: Outband = - 20 dB, Inband = - 0.04 dB (see Table 65) DeltaUTD 20 dB DELT = 13 = 0x0D Table 65 f UTD Inband/Outband Attenuation Outband Inband - 20 dB - 3 dB - 0.04 dB - 0 dB - 0.04 dB - 3 dB - 20 dB - 40 dB fC fC fC fC fBW/0.2 fBW/2 fBW/20 fBW/200 Data Sheet 257 2000-07-14 DuSLIC-E/-E2/-P Preliminary 53H UTD-RBRK SLICOFI-2x Command Structure and Programming Universal Tone Detection Recognition Break Time 6 5 4 RBRK 3 2 1 Y Bit 7 0 Allowed Recognition Break Time for Universal Tone Detection: RBRK = RBRKTime[ms]/4 RBRKTime has to be entered in multiples of 4 ms. 0 ms RBRKTime 1000 ms For an example see Figure 72. Data Sheet 258 2000-07-14 DuSLIC-E/-E2/-P Preliminary 54H UTD-RTIME SLICOFI-2x Command Structure and Programming Universal Tone Detection Recognition Time 6 5 4 RTIME Universal Tone Detection Recognition Time: RTIME = RTime[ms]/16 RTime has to be entered in multiples of 16 ms. 0 ms RTime 4000 ms 3 2 1 Y Bit 7 0 T o ne 1 0 U T D i-O K b it (IN T R E G 3) t R B R K T im e 1 R T im e 0 U T D i-O K b it (IN T R E G 3) t R B R K T im e 1 R T im e 0 t duslic_0013_RBRK_timing.emf Figure 72 Example for UTD Recognition Timing Data Sheet 259 2000-07-14 DuSLIC-E/-E2/-P Preliminary 55H UTD-EBRK SLICOFI-2x Command Structure and Programming UTD Allowed Tone End Detection Break Time 6 5 4 EBRK Allowed tone end detection break time for Universal Tone Detection: EBRK = EBRKTime [ms] 0 ms EBRKTime 255 ms For an example see Figure 73. 3 2 1 Y Bit 7 0 Data Sheet 260 2000-07-14 DuSLIC-E/-E2/-P Preliminary 56H Bit UTD-ETIME 7 6 SLICOFI-2x Command Structure and Programming UTD Tone End Detection Time 5 4 ETIME 3 2 1 Y 0 Tone End Detection Time for Universal Tone Detection: ETIME = ETime[ms]/4 ETime has to be entered in multiples of 4 ms. 0 ms ETime 1000 ms Tone 1 0 U T D i-O K b it (IN T R E G 3 ) t E B R K T im e 1 E T im e 0 U T D i-O K b it (IN T R E G 3 ) E B R K T im e t 1 E T im e 0 t duslic_0014_EBRK_timing.emf Figure 73 Example for UTD Tone End Detection Timing Data Sheet 261 2000-07-14 DuSLIC-E/-E2/-P Preliminary SLICOFI-2x Command Structure and Programming 6.2.5 IOM-2 Interface Command/Indication Byte The Command/Indication (C/I) channel is used to communicate real-time status information and for fast controlling of the DuSLIC. Data on the C/I channel are continuously transmitted in each frame until new data are sent. Data Downstream C/I - Channel Byte (Receive) - IOM-CIDD The first six CIDD data bits control the general operating modes for both DuSLIC channels. According to the IOM-2 specifications, new data have to be present for at least two frames to be accepted. Table 66 CIDD M2 1 0 0 1 1 1 0 M2, M1, M0: General Operating Mode M1 1 0 1 0 1 0 0 M0 1 0 0 1 0 0 1 SLICOFI-2 Operating Mode (for details see "Operating Modes for the DuSLIC Chip Set" on Page 78) Sleep, Power Down (PDRx) Power Down High Impedance (PDH) Any Active mode Ringing (ACTR Burst On) Active with Metering Ground Start Ring Pause CIDD Bit 7 M2A ) Data Downstream C/I - Channel Byte 6 M1A 5 M0A 4 M2B 3 M1B 2 M0B 1 MR N 0 MX M2A, M1A, M0A M2B, M1B, M0B MR, MX Select operating mode for DuSLIC channel A Select operating mode for DuSLIC channel B Handshake bits Monitor Receive and Transmit (see "IOM-2 Interface Monitor Transfer Protocol" on Page 148) Data Sheet 262 2000-07-14 DuSLIC-E/-E2/-P Preliminary SLICOFI-2x Command Structure and Programming Data Upstream C/I - Channel Byte (Transmit) - IOM-CIDU This byte is used to quickly transfer the most important and time-critical information from the DuSLIC. Each transfer from the DuSLIC lasts for at least 2 consecutive frames. CIDU Bit 7 Data Upstream C/I - Channel Byte 6 5 4 3 2 00H 1 MR N 0 MX INT-CHA HOOKA GNDKA INT-CHB HOOKB GNDKB INT-CHA Interrupt information channel A INT-CHA = 0 No interrupt in channel A INT-CHA = 1 Interrupt in channel A Hook information channel A HOOKA = 0 On-hook channel A HOOKA = 1 Off-hook channel A Ground key information channel A GNDKA = 0 No longitudinal current detected GNDKA = 1 Longitudinal current detected in channel A Interrupt information channel B INT-CHB = 0 No interrupt in channel B INT-CHB = 1 Interrupt in channel B Hook information channel B HOOKB = 0 On-hook Channel B HOOKB = 1 Off-hook Channel B Ground key information channel B GNDKB = 0 No longitudinal current detected GNDKB = 1 Longitudinal current detected in channel B HOOKA GNDKA INT-CHB HOOKB GNDKB MR, MX Handshake bits Monitor Receive and Transmit (see "IOM-2 Interface Monitor Transfer Protocol" on Page 148) Data Sheet 263 2000-07-14 DuSLIC-E/-E2/-P Preliminary SLICOFI-2x Command Structure and Programming 6.2.6 6.2.6.1 Programming Examples of the SLICOFI-2 Microcontroller Interface SOP Write to Channel 0 Starting After the Channel Specific Read-only Registers 01000100 00010101 00000000 00000000 00010001 00000000 00000000 First command byte (SOP write for channel 0) Second command byte (Offset to BCR1 register) Contents of BCR1 register Contents of BCR2 register Contents of BCR3 register Contents of BCR4 register Contents of BCR5 register Command DIN DCLK CS ezm220121.wmf Offset BCR1 BCR2 BCR3 BCR4 BCR5 Figure 74 Waveform of Programming Example SOP-Write to Channel 0 SOP Read from Channel 1 Reading Out the Interrupt Registers 11001100 00000111 First command byte (SOP read for channel 1). Second command byte (Offset to Interrupt register 1). The SLICOFI-2 will send data when it has completely received the second command byte. 11111111 11000000 00000010 00000000 00000000 Dump byte (This byte is always FFH). Interrupt register INTREG1 (An interrupt has occurred, Off-hook was detected). Interrupt register INTREG2 (IO pin 2 is `1'). Interrupt register INTREG3 Interrupt register INTREG4 Command DIN DOUT DCLK CS Offset Dump Intreg 1 Intreg 2 Intreg 3 Intreg 4 ezm220122.emf Figure 75 Data Sheet Waveform of Programming Example SOP Read from Channel 0 264 2000-07-14 DuSLIC-E/-E2/-P Preliminary SLICOFI-2x Command Structure and Programming 6.2.6.2 IOM-2 Interface An example with the same programming sequence as before, using the IOM-2 interface is presented here to show the differences between the microcontroller interface and the IOM-2 interface. SOP Write to Channel 0 Starting After the Channel-Specific Read-only Registers Monitor MR/MX Monitor data down data up 10000001 10000001 01000100 01000100 00010101 00010101 00000000 00000000 00000000 00000000 00010001 00010001 00000000 00000000 11111111 11111111 10 10 11 10 11 10 11 10 11 10 11 10 11 10 11 11 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 MR/MX Comment 11 01 01 11 01 11 01 11 01 11 01 11 01 11 01 11 IOM-2 address first byte IOM-2 address second byte First command byte (SOP write for channel 0) First command byte second time Second command byte (Offset to BCR1 register) Second command byte second time Contents of BCR1 register Contents of BCR1 register second time Contents of BCR2 register Contents of BCR2 register second time Contents of BCR3 register Contents of BCR3 register second time Contents of BCR4 register Contents of BCR4 register second time No more information (dummy byte) Signaling EOM (end of message) by holding MX bit at `1'. Since the SLICOFI-2 has an open command structure there is no fixed command length. The IOM-2 handshake protocol allows for an infinite length of a data stream, therefore the host has to terminate the data transfer by sending an end-of-message signal (EOM) to the SLICOFI-2. The SLICOFI-2 will abort the transfer only if the host tries to write or read beyond the allowed maximum offset given by the different types of commands. Each transfer has to start with the SLICOFI-2-specific IOM-2 address (81H) and must end with an EOM of the handshake bits. Appending a command immediately to its predecessor without an EOM in between is not allowed. When reading interrupt registers, SLICOFI-2 stops the transfer after the fourth register in IOM-2 mode. This is to prevent some host chips reading 16 bytes because they can't terminate the transfer after n bytes. Data Sheet 265 2000-07-14 DuSLIC-E/-E2/-P Preliminary SLICOFI-2x Command Structure and Programming SOP-Read from Channel 1 Reading Out the Interrupt Registers Monitor MR/MX Monitor data down data up 10000001 10000001 11001100 11001100 00001000 00001000 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 10 10 11 10 11 10 11 11 01 01 11 01 11 01 11 01 11 11 11 11111111 11111111 11111111 11111111 11111111 11111111 11111111 10000001 10000001 11000000 11000000 00000010 00000010 00000000 00000000 00000000 00000000 01001101 11111111 MR/MX Comment 11 01 01 11 01 11 01 10 10 11 10 11 10 11 10 11 10 11 11 IOM-2 address first byte IOM-2 address second byte First command byte (SOP read for channel 1) First command byte second time Second command byte (offset to interrupt register 1) Second command byte second time Acknowledgement for the second command byte IOM-2 Address first byte (answer) IOM-2 Address second byte Interrupt register INTREG1 Interrupt register INTREG1 second time Interrupt register INTREG2 Interrupt register INTREG2 second time Interrupt register INTREG3 Interrupt register INTREG3 second time Interrupt register INTREG4 Interrupt register INTREG4 second time SLICOFI-2 sends the next register SLICOFI-2 aborts transmission Data Sheet 266 2000-07-14 DuSLIC-S/-S2 Preliminary SLICOFI-2x Command Structure and Programming 6.3 SLICOFI-2S/-2S2 Command Structure and Programming This chapter comprises only the SLICOFI-2S/-2S2 PEB 3264/-2 and therefore the DuSLIC-S and DuSLIC-S2 chip sets. 6.3.1 SOP Command The SOP "Status Operation" command provides access to the configuration and status registers of the SLICOFI-2S/-2S2. Common registers change the mode of the entire SLICOFI-2S/-2S2 chip, all other registers are channel-specific. It is possible to access single or multiple registers. Multiple register access is realized by an automatic offset increment. Write access to read-only registers is ignored and does not abort the command sequence. Offsets may change in newer versions of the SLICOFI-2S/-2S2. (All empty register bits have to be filled with zeros.) 6.3.1.1 00H SOP Register Overview REVISION Revision Number (read-only) REV[7:0] 01H CHIPID 1 Chip Identification 1 (read-only) for internal use only 02H CHIPID 2 Chip Identification 2 (read-only) for internal use only 03H CHIPID 3 Chip Identification 3 (read-only) for internal use only 04H FUSE1 Fuse Register 1 for internal use only 05H PCMC1 DBL-CLK X-SLOPE PCM Configuration Register 1 R-SLOPE NO-DRIVE-0 SHIFT PCMO[2:0] 06H XCR 0 ASYNCH-R Extended Configuration Register 0 0 0 0 0 0 Data Sheet 267 2000-07-14 DuSLIC-S/-S2 Preliminary SLICOFI-2x Command Structure and Programming 07H INTREG1 INT-CH HOOK Interrupt Register 1 (read-only) GNDK GNKP ICON VRTLIM OTEMP SYNC-FAIL 08H INTREG2 0 READY Interrupt Register 2 (read-only) RSTAT 0 IO[4:1]-DU 09H INTREG3 0 0 Interrupt Register 3 (read-only) 0 0 0 0 0 0 0AH INTREG4 0 0 Interrupt Register 4 (read-only) 0 0 0 0 0 0 0BH CHKR1 SUM-OK Checksum Register 1 (High Byte) (read-only) CHKSUM-H[6:0] 0CH CHKR2 Checksum Register 2 (Low Byte) (read-only) CHKSUM-L[7:0] 0DH reserved 0 0 0 0 0 0 0 0 0EH reserved 0 0 0 0 0 0 0 0 0FH FUSE2 Fuse Register 2 for internal use only 10H FUSE3 Fuse Register 3 for internal use only 11H MASK READY-M HOOK-M Mask Register GNDK-M GNKP-M ICON-M VRTLIM-M OTEMP-M SYNC-M Data Sheet 268 2000-07-14 DuSLIC-S/-S2 Preliminary SLICOFI-2x Command Structure and Programming 12H IOCTL1 IO Control Register 1 IO[4:1]-INEN IO[4:1]-M 13H IOCTL2 IO Control Register 2 IO[4:1]-OEN IO[4:1]-DD 14H IOCTL3 IO Control Register 3 DUP[3:0] DUP-IO[3:0] 15H BCR1 HIR HIT Basic Configuration Register 1 0 REVPOL ACTR ACTL 0 0 16H BCR2 REXT-EN SOFT-DIS Basic Configuration Register 2 TTX-DIS1) TTX-12K2) HIM-AN AC-XGAIN 0 PDOT-DIS 17H BCR3 MU-LAW LIN Basic Configuration Register 3 0 PCMX-EN 0 0 0 CRAM-EN 18H BCR4 TH-DIS IM-DIS Basic Configuration Register 4 AX-DIS AR-DIS FRX-DIS FRR-DIS HPX-DIS HPR-DIS 19H reserved 0 0 0 0 0 0 0 0 1AH DSCR DTMF Sender Configuration Register DG-KEY[3:0] COR8 PTG TG2-EN TG1-EN 1BH reserved 0 0 0 0 0 0 0 0 1CH LMCR1 TEST-EN 0 Level Metering Configuration Register 1 1 PCM2DC 0 0 1 0 Data Sheet 269 2000-07-14 DuSLIC-S/-S2 Preliminary SLICOFI-2x Command Structure and Programming 1DH LMCR2 0 0 Level Metering Configuration Register 2 0 0 0 0 0 0 1EH LMCR3 AC-SHORTEN RTR-SEL Level Metering Configuration Register 3 0 0 0 0 0 0 1FH OFR1 Offset Register 1 (High Byte) OFFSET-H[7:0] 20H OFR2 Offset Register 2 (Low Byte) OFFSET-L[7:0] 21H PCMR1 R1-HW PCM Receive Register 1 R1-TS[6:0] 22H reserved 23H reserved 24H reserved 25H PCMX1 X1-HW PCM Transmit Register 1 X1-TS[6:0] 26H reserved Data Sheet 270 2000-07-14 DuSLIC-S/-S2 Preliminary SLICOFI-2x Command Structure and Programming 27H reserved 28H reserved 29H TSTR1 PD-AC-PR PD-AC-PO Test Register 1 PD-AC-AD PD-AC-DA PD-AC-GN PD-GNKC PD-OFHC PD-OVTC 2AH TSTR2 PD-DC-PR 0 Test Register 2 PD-DC-AD PD-DC-DA PD-DCBUF 0 PD-TTX-A2) PD-HVI 2BH TSTR3 0 0 Test Register 3 AC-DLB-4M AC-DLB128K AC-DLB32K AC-DLB8K 0 0 2CH TSTR4 OPIM-AN OPIM-4M Test Register 4 COR-64 COX-16 0 0 0 0 2DH TSTR5 0 0 Test Register 5 0 DC-POFIHI DC-HOLD 0 0 0 1) 2) Only for DuSLIC-S, is set to 1 for DuSLIC-S2 Only for DuSLIC-S, is set to 0 for DuSLIC-S2 Data Sheet 271 2000-07-14 DuSLIC-S/-S2 Preliminary SLICOFI-2x Command Structure and Programming 6.3.1.2 00H SOP Register Description REVISION Revision Number (read-only) curr. rev. N Bit 7 6 5 4 3 2 1 0 REV[7:0] REV[7:0] Current revision number of the SLICOFI-2S/-2S2. 01H CHIPID 1 Chip Identification 1 (read-only) hw N Bit 7 6 5 4 3 2 1 0 for internal use only 02H CHIPID 2 Chip Identification 2 (read-only) hw N Bit 7 6 5 4 3 2 1 0 for internal use only 03H CHIPID 3 Chip Identification 3 (read-only) hw N Bit 7 6 5 4 3 2 1 0 for internal use only 04H FUSE1 Fuse Register 1 hw N Bit 7 6 5 4 3 2 1 0 for internal use only Data Sheet 272 2000-07-14 DuSLIC-S/-S2 Preliminary 05H Bit PCMC1 7 SLICOFI-2x Command Structure and Programming PCM Configuration Register 1 6 5 4 3 SHIFT 00H 2 1 PCMO[2:0] N 0 DBL-CLK X-SLOPE R-SLOPE NO-DRIVE-0 DBL-CLK Clock mode for the PCM interface (see Figure 59 on Page 141). DBL-CLK = 0 DBL-CLK = 1 Single clocking is used. Double clocking is used. X-SLOPE Transmit Slope (see Figure 59 on Page 141). X-SLOPE = 0 X-SLOPE = 1 Transmission starts with rising edge of the clock. Transmission starts with falling edge of the clock. R-SLOPE Receive Slope (see Figure 59 on Page 141). R-SLOPE = 0 R-SLOPE = 1 Data is sampled with falling edge of the clock. Data is sampled with rising edge of the clock. NODRIVE-0 Driving Mode for Bit 0 (only available in single-clocking mode). NO-DRIVE = 0 NO-DRIVE = 1 Bit 0 is driven the entire clock period. Bit 0 is driven during the first half of the clock period only. SHIFT Shifts the access edges by one clock cycle in double clocking mode. SHIFT = 0 SHIFT = 1 No shift takes place. Shift takes place. PCMO[2:0] The whole PCM timing is moved by PCMO data periods against the FSC signal. PCMO[2:0] = 0 0 0 PCMO[2:0] = 0 0 1 No offset is added. One data period is added. Seven data periods are added. ... PCMO[2:0] = 1 1 1 Data Sheet 273 2000-07-14 DuSLIC-S/-S2 Preliminary 06H Bit XCR 7 0 SLICOFI-2x Command Structure and Programming Extended Configuration Register 6 ASYNCH -R 5 0 4 0 3 0 2 0 00H 1 0 N 0 0 ASYNCH-R Enables asynchronous ringing in case of external ringing. ASYNCH-R = 0 ASYNCH-R = 1 External ringing with zero crossing selected Asynchronous ringing selected. Data Sheet 274 2000-07-14 DuSLIC-S/-S2 Preliminary 07H Bit INTREG1 7 INT-CH SLICOFI-2x Command Structure and Programming Interrupt Register 1 (read-only) 6 HOOK 5 GNDK 4 GNKP 3 ICON 2 80H 1 Y 0 SYNCFAIL VRTLIM OTEMP INT-CH Interrupt channel bit. This bit indicates that the corresponding channel caused the last interrupt. Will be set automatically to zero after all interrupt registers were read. INT-CH = 0 INT-CH = 1 No interrupt in corresponding channel. Interrupt caused by corresponding channel. HOOK On/Off-hook information for the loop in all operating modes, filtered by DUP (Data Upstream Persistence) counter and interrupt generation masked by the HOOK-M bit. A change of this bit generates an interrupt. HOOK = 0 HOOK = 1 On-hook. Off-hook. GNDK Ground Key or Ground Start information via the IL pin in all active modes, filtered for AC suppression by the DUP counter and interrupt generation masked by the GNDK-M bit. A change of this bit generates an interrupt. GNDK = 0 GNDK = 1 No longitudinal current detected. Longitudinal current detected (Ground Key or Ground Start). GNKP Ground key polarity. Indicating the active ground key level (positive/ negative) interrupt generation masked by the GNKP-M bit. A change of this bit generates an interrupt. This bit can be used to get information about interference voltage influence. GNKP = 0 GNKP = 1 Negative ground key threshold level active. Positive ground key threshold level active. Data Sheet 275 2000-07-14 DuSLIC-S/-S2 Preliminary ICON SLICOFI-2x Command Structure and Programming Constant current information. Filtered by DUP-IO counter and interrupt generation masked by the ICON-M bit. A change of this bit generates an interrupt. ICON = 0 ICON = 1 VRTLIM Resistive or constant voltage feeding. Constant current feeding. Exceeding of a programmed voltage threshold for the TIP/RING voltage, filtered by the DUP-IO counter and interrupt generation masked by the VRTLIM-M bit. A change of this bit causes an interrupt. The voltage threshold for the TIP/RING voltage is set in CRAM (calculated with DuSLICOS DC Control Parameter 2/3: Tip-Ring Threshold). VRTLIM = 0 VRTLIM = 1 Voltage at Ring/Tip is below the limit. Voltage at Ring/Tip is above the limit. OTEMP Thermal overload warning from the SLIC-S/-S2 line drivers masked by the OTEMP-M bit. An interrupt is only generated if the OTEMP bit changes from 0 to1. OTEMP = 0 OTEMP = 1 Temperature at SLIC-S/-S2 is below the limit. Temperature at SLIC-S/-S2 is above the limit. In case of bit PDOT-DIS = 0 (register BCR2) the DuSLIC is switched automatically into PDH mode and OTEMP is hold at 1 until the SLICOFI-2S/-2S2 is set to PDH by a CIOP/CIDD command. SYNC-FAIL Failure of the synchronization of the IOM-2/PCM Interface. An interrupt is only generated if the SYNC-FAIL bit changes from 0 to 1. Resynchronization of the PCM interface can be done with the Resynchronization command (see Chapter 6) SYNC-FAIL = 0 SYNC-FAIL = 1 Synchronization OK. Synchronization failure. Data Sheet 276 2000-07-14 DuSLIC-S/-S2 Preliminary 08H Bit INTREG2 7 0 SLICOFI-2x Command Structure and Programming Interrupt Register 2 (read-only) 6 5 4 0 3 2 20H 1 Y 0 READY RSTAT IO[4:1]-DU After a hardware reset the RSTAT bit is set and generates an interrupt. Therefore the default value of INTREG2 is 20h. After reading all four interrupt registers, the INTREG2 value changes to 4Fh. READY Indication whether ramp generator has finished. An interrupt is only generated if the READY bit changes from 0 to 1. At a new start of the ramp generator, the bit is set to 0. For further information regarding soft reversal see Chapter 3.7.2.1. READY = 0 READY = 1 RSTAT Ramp generator active. Ramp generator not active. Reset status since last interrupt. RSTAT = 0 RSTAT = 1 No reset has occurred since the last interrupt. Reset has occurred since the last interrupt. IO[4:1]-DU Data on IO pins 1 to 4 filtered by the DUP-IO counter and interrupt generation masked by the IO[4:1]-DU-M bits. A change of any of these bits generates an interrupt. 09H INTREG3 Interrupt Register 3 (read-only) 00H Y Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 0AH INTREG4 Interrupt Register 4 (read-only) 00H Y Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Data Sheet 277 2000-07-14 DuSLIC-S/-S2 Preliminary 0BH CHKR1 SLICOFI-2x Command Structure and Programming Checksum Register 1 (High Byte) (read-only) 00H Y Bit 7 SUMOK 6 5 4 3 CHKSUM-H[6:0] 2 1 0 SUM-OK Information about the validity of the checksum. The checksum is valid if the internal checksum calculation is finished. Checksum calculation: For (cram_adr = 0 to 159) do cram_dat = cram[cram_adr] csum[14:0] = (csum[13:0] &1) `0') xor (`0000000' & cram_dat[7:0]) xor (`0000000000000' & csum[14] & csum[14]) End SUM-OK = 0 SUM-OK = 1 1) CRAM checksum is not valid. CRAM checksum is valid. "&" means a concatenation, not the logic operation CHKSUM-H[6:0] CRAM checksum high byte Data Sheet 278 2000-07-14 DuSLIC-S/-S2 Preliminary 0CH CHKR2 SLICOFI-2x Command Structure and Programming Checksum Register 2 (Low Byte) (read-only) 00H Y Bit 7 6 5 4 3 2 1 0 CHKSUM-L[7:0] CHKSUM-L[7:0] CRAM-checksum low byte 0DH Bit 7 0 reserved 6 0 5 0 4 0 3 0 2 0 00H 1 0 Y 0 0 0EH reserved 00H Y Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 0FH Bit FUSE2 7 Fuse Register 2 6 5 4 3 2 hw 1 Y 0 for internal use only 10H Bit FUSE3 7 Fuse Register 3 6 5 4 3 2 hw 1 Y 0 for internal use only Data Sheet 279 2000-07-14 DuSLIC-S/-S2 Preliminary 11H Bit MASK 7 READY -M SLICOFI-2x Command Structure and Programming Mask Register 6 HOOK -M 5 GNDK -M 4 GNKP -M 3 ICON -M 2 FFH 1 Y 0 SYNC -M VRTLIM OTEMP -M -M The mask bits in the mask register only influence the generation of an interrupt. Even if the mask bit is set to 1, the corresponding status bit in the INTREGx registers gets updated to show the current status of the corresponding event. READY-M Mask bit for Ramp Generator READY bit READY-M = 0 READY-M = 1 HOOK-M An interrupt is generated if the READY bit changes from 0 to 1. Changes of the READY bit don't generate interrupts. Mask bit for Off-Hook Detection HOOK bit HOOK-M = 0 HOOK-M = 1 Each change of the HOOK bit generates an interrupt. Changes of the HOOK bit don't generate interrupts. GNDK-M Mask bit for Ground Key Detection GNDK bit GNDK-M = 0 GNDK-M = 1 Each change of the GNDK bit generates an interrupt. Changes of the GNDK bit don't generate interrupts. GNKP-M Mask bit for Ground Key Level GNKP bit GNKP-M = 0 GNKP-M = 1 Each change of the GNKP bit generates an interrupt. Changes of the GNKP bit don't generate interrupts. ICON-M Mask bit for Constant Current Information ICON bit ICON-M = 0 ICON_M = 1 Each change of the ICON bit generates an interrupt. Changes of the ICON bit don't generate interrupts. VRTLIM-M Mask bit for Programmed Voltage Limit VRTLIM bit VRTLIM-M = 0 VRTLIM-M = 1 Each change of the VRTLIM bit generates an interrupt. Changes of the VRTLIM bit don't generate interrupts. Data Sheet 280 2000-07-14 DuSLIC-S/-S2 Preliminary SLICOFI-2x Command Structure and Programming OTEMP-M Mask bit for Thermal Overload Warning OTEMP bit OTEMP-M = 0 OTEMP-M = 1 A change of the OTEMP bit from 0 to 1 generates an interrupt. A change of the OTEMP bit from 0 to 1 doesn't generate interrupts. SYNC-M Mask bit for Synchronization Failure SYNC-FAIL bit SYNC-M = 0 SYNC-M = 1 A change of the SYNC-FAIL bit from 0 to 1 generates an interrupt. A change of the SYNC-FAIL bit from 0 to 1 doesn't generate interrupts. Data Sheet 281 2000-07-14 DuSLIC-S/-S2 Preliminary 12H Bit IOCTL1 7 SLICOFI-2x Command Structure and Programming IO Control Register 1 6 5 4 3 2 0FH 1 Y 0 IO[4:1]-INEN IO[4:1]-M The mask bits IO[4:1]-M only influence the generation of an interrupt. Even if the mask bit is set to 1, the corresponding status bit in the INTREGx registers gets updated to show the current status of the corresponding event. IO4-INEN Input enable for programmable IO pin IO4 IO4-INEN = 0 Input Schmitt trigger of pin IO4 is disabled. IO4-INEN = 1 Input Schmitt trigger of pin IO4 is enabled. IO3-INEN Input enable for programmable IO pin IO3 IO3-INEN = 0 Input Schmitt trigger of pin IO3 is disabled. IO3-INEN = 1 Input Schmitt trigger of pin IO3 is enabled. IO2-INEN Input enable for programmable IO pin IO2 IO2-INEN = 0 Input Schmitt trigger of pin IO2 is disabled. IO2-INEN = 1 Input Schmitt trigger of pin IO2 is enabled. IO1-INEN Input enable for programmable IO pin IO1 IO1-INEN = 0 Input Schmitt trigger of pin IO1 is disabled. IO1-INEN = 1 Input Schmitt trigger of pin IO1 is enabled. IO4-M Mask bit for IO4-DU bit IO4-M = 0 IO4-M = 1 IO3-M Each change of the IO4 bit generates an interrupt. Changes of the IO4 bit don't generate interrupts. Mask bit for IO3-DU bit IO3-M = 0 IO3-M = 1 Each change of the IO3 bit generates an interrupt. Changes of the IO3 bit don't generate interrupts. Data Sheet 282 2000-07-14 DuSLIC-S/-S2 Preliminary IO2-M SLICOFI-2x Command Structure and Programming Mask bit for IO2-DU bit IO2-M = 0 IO2-M = 1 IO1-M Each change of the IO2 bit generates an interrupt. Changes of the IO2 bit don't generate interrupts. Mask bit for IO1-DU bit IO1-M = 0 IO1-M = 1 Each change of the IO1 bit generates an interrupt. Changes of the IO1 bit don't generate interrupts. Data Sheet 283 2000-07-14 DuSLIC-S/-S2 Preliminary 13H Bit IOCTL2 7 SLICOFI-2x Command Structure and Programming IO Control Register 2 6 5 4 3 2 00H 1 Y 0 IO[4:1]-OEN IO[4:1]-DD IO4-OEN Enabling the output driver of pin IO4 IO4-OEN = 0 IO4-OEN = 1 The output driver of pin IO4 is disabled. The output driver of pin IO4 is enabled. IO3-OEN Enabling the output driver of pin IO3 IO3-OEN = 0 IO3-OEN = 1 The output driver of pin IO3 is disabled. The output driver of pin IO3 is enabled. IO2-OEN Enabling the output driver of pin IO2 IO2-OEN = 0 IO2-OEN = 1 The output driver of pin IO2 is disabled. The output driver of pin IO2 is enabled. IO1-OEN Enabling the output driver of pin IO1 If external ringing is selected (bit REXT-EN in register BCR2 set to 1), pin IO1 cannot be controlled by the user but is utilized by the SLICOFI-2S/-2S2 to control the ring relay. IO1-OEN = 0 IO1-OEN = 1 The output driver of pin IO1 is disabled. The output driver of pin IO1 is enabled. IO4-DD Value for the programmable IO pin IO4 if programmed as an output pin. IO4-DD = 0 IO4-DD = 1 The corresponding pin is driving a logical 0. The corresponding pin is driving a logical 1. IO3-DD Value for the programmable IO pin IO3 if programmed as an output pin. IO3-DD = 0 IO3-DD = 1 The corresponding pin is driving a logical 0. The corresponding pin is driving a logical 1. Data Sheet 284 2000-07-14 DuSLIC-S/-S2 Preliminary IO2-DD SLICOFI-2x Command Structure and Programming Value for the programmable IO pin IO2 if programmed as an output pin. IO2-DD = 0 IO2-DD = 1 IO1-DD The corresponding pin is driving a logical 0. The corresponding pin is driving a logical 1. Value for the programmable IO pin IO1 if programmed as an output pin. IO1-DD = 0 IO1-DD = 1 The corresponding pin is driving a logical 0. The corresponding pin as driving a logical 1. Data Sheet 285 2000-07-14 DuSLIC-S/-S2 Preliminary 14H Bit IOCTL3 7 SLICOFI-2x Command Structure and Programming IO Control Register 3 6 5 4 3 2 94H 1 Y 0 DUP[3:0] DUP-IO[3:0] DUP[3:0] Data Upstream Persistence Counter end value. Restricts the rate of interrupts generated by the HOOK bit in the interrupt register INTREG1. The interval is programmable from 1 to 16 ms in steps of 1 ms (reset value is 10 ms). The DUP[3:0] value affects the blocking period for ground key detection (see Chapter 3.6). DUP[3:0] HOOK Active, Ringing 0000 0001 ... 1111 1) HOOK Power Down 2 ms 4 ms 32 ms GNDK GNDK fmin,ACsup1) 125 Hz 62.5 Hz 7.8125 Hz 1 2 16 4 ms 8 ms 64 ms Minimum frequency for AC suppression. DUP-IO[3:0] Data Upstream Persistence Counter end value for * the IO pins when used as digital input pins. * the bits ICON and VRTLIM in register INTREG1. The interval is programmable from 0.5 to 60.5 ms in steps of 4 ms (reset value is 16.5 ms). Data Sheet 286 2000-07-14 DuSLIC-S/-S2 Preliminary 15H BCR1 SLICOFI-2x Command Structure and Programming Basic Configuration Register 1 00H Y Bit 7 HIR 6 HIT 5 0 4 3 2 ACTL 1 0 0 0 REVPOL ACTR HIR This bit modifies different basic modes. In ringing mode an unbalanced ringing on the RING-wire (ROR) is enabled. In active mode, high impedance on the RING-wire is performed (HIR). It enables the HIRT-mode together with the HIT bit. HIR = 0 HIR = 1 Normal operation (ringing mode). Controls SLIC-S/-S2-interface and sets the RING wire to high impedance (active mode). HIT This bit modifies different basic modes. In ringing mode an unbalanced ringing on the TIP-wire (ROT) is enabled. In active mode, high impedance on the TIP-wire is performed (HIT). It enables the HIRT-mode together with the HIR bit. HIT = 0 HIT = 1 Normal operation (ringing mode). Controls SLIC-S/-S2-interface and sets the TIP-wire to high impedance (active mode). REVPOL Reverse polarity of DC feeding REVPOL = 0 REVPOL = 1 Normal polarity. Reverse polarity. ACTR Selection of extended battery feeding in Active mode. In this caseVHR - VBATH for SLIC-S/-S2 is used. ACTR = 0 ACTR = 1 No extended battery feeding selected. Extended battery feeding selected. Data Sheet 287 2000-07-14 DuSLIC-S/-S2 Preliminary ACTL SLICOFI-2x Command Structure and Programming Selection of the low battery supply voltage VBATL on SLIC-S/-S2 if available. Valid only in Active mode of the SLICOFI-2S/-2S2. ACTL = 0 ACTL = 1 Low battery supply voltage on SLIC-S/-S2 is not selected. Low battery supply voltage on SLIC-S/-S2 is selected. Data Sheet 288 2000-07-14 DuSLIC-S/-S2 Preliminary 16H Bit BCR2 7 REXTEN 1) 2) SLICOFI-2x Command Structure and Programming Basic Configuration Register 2 6 SOFTDIS 5 TTXDIS1) 4 TTX12K2) 3 HIM-AN 2 ACXGAIN 00H 1 0 Y 0 PDOTDIS Only for DuSLIC-S, is set to 1 for DuSLIC-S2 Only for DuSLIC-S, is set to 0 for DuSLIC-S2 REXT-EN Enables the use of an external ring-signal generator. The synchronization is done via the RSYNC pin and the ring-burst-enable signal is transferred via the IO1 pin. REXT-EN = 0 REXT-EN = 1 External ringing is disabled. External ringing enabled. SOFT-DIS Polarity soft reversal (to minimize noise on DC feeding) SOFT-DIS = 0 SOFT-DIS = 1 Polarity soft reversal active. Polarity hard reversal. TTX-DIS Disables the generation of TTX bursts for metering signals. If they are disabled, revese polarity is used instead. TTX-DIS = 0 TTX-DIS = 1 TTX bursts are enabled. TTX bursts are disabled, reverse polarity used. TTX-12K Selection of TTX frequencies TTX-12K = 0 TTX-12K = 1 Selects 16 kHz TTX signals instead of 12 kHz signals. 12 kHz TTX signals. Data Sheet 289 2000-07-14 DuSLIC-S/-S2 Preliminary HIM-AN SLICOFI-2x Command Structure and Programming Higher impedance in analog impedance matching loop. HIM-AN corresponds to the coefficients calculated with DuSLICOS. If the coefficients are calculated with standard impedance in analog impedance matching loop, HIM-AN must be set to 0; if the coefficients are calculated with high impedance in analog impedance matching loop, HIM-AN must be set to 1. HIM-AN = 0 HIM-AN = 1 Standard impedance in analog impedance matching loop (300 ). High impedance in analog impedance matching loop (600 ). AC-XGAIN Analog gain in transmit direction (should be set to zero). AC-XGAIN = 0 AC-XGAIN = 1 No additional analog gain in transmit direction. Additional 6 dB analog amplification in transmit direction. PDOT-DIS Power Down Overtemperature Disable PDOT-DIS = 0 When over temperature is detected, the SLIC-S/-S2 is automatically switched into Power Down High Impedance mode (PDH). This is the safe operation mode for the SLIC-S/-S2 in case of overtemperature. To leave the automatically activated PDH mode, DuSLIC has to be switched manually to PDH mode and then in the mode as desired. When over temperature is detected, the SLIC-S/-S2 doesn't automatically switch into Power Down High Impedance mode. In this case the output current of the SLIC-S/-S2 buffers is limited to a value which keeps the SLIC-S/-S2 temperature below the upper temperature limit. PDOT-DIS = 1 Data Sheet 290 2000-07-14 DuSLIC-S/-S2 Preliminary 17H Bit BCR3 7 MULAW SLICOFI-2x Command Structure and Programming Basic Configuration Register 3 6 LIN 5 0 4 PCMXEN 3 0 2 0 00H 1 0 Y 0 CRAMEN MU-LAW Selects the PCM Law MU-LAW = 0 MU-LAW = 1 A-Law enabled. -Law enabled. LIN Voice transmission in a 16 bit linear representation for test purposes. Note: Voice transmission on the other channel is inhibited if one channel is set to linear mode and the IOM-2 interface is used. In PCM/ C interface mode both channels can be in linear mode using two consecutive PCM timeslots on the highways. A proper timeslot selection must be specified. LIN = 0 LIN = 1 PCM mode enabled (8 bit, A-law or -law). Linear mode enabled (16 bit). PCMX-EN Enables writing of subscriber voice data to the PCM highway. PCMX-EN = 0 PCMX-EN = 1 Writing of subscriber voice data to PCM highway is disabled. Writing of subscriber voice data to PCM highway is enabled. CRAM-EN Coefficients from CRAM are used for programmable filters and DC loop behavior. CRAM-EN = 0 CRAM-EN = 1 Coefficients from ROM are used. Coefficients from CRAM are used. Data Sheet 291 2000-07-14 DuSLIC-S/-S2 Preliminary 18H Bit BCR4 7 TH-DIS SLICOFI-2x Command Structure and Programming Basic Configuration Register 4 6 IM-DIS 5 AX-DIS 4 AR-DIS 3 FRXDIS 2 FRRDIS 00H 1 HPXDIS Y 0 HPRDIS TH-DIS Disables the TH filter. TH-DIS = 0 TH-DIS = 1 TH filter is enabled. TH filter is disabled (HTH = 0). IM-DIS Disables the IM filter. IM-DIS = 0 IM-DIS = 1 IM filter is enabled. IM filter is disabled (HIM = 0). AX-DIS Disables the AX filter. AX-DIS = 0 AX-DIS = 1 AX filter is enabled. AX filter is disabled (HAX = 1). AR-DIS Disables the AR filter. AX-DIS = 0 AX-DIS = 1 AR filter is enabled. AR filter is disabled (HAR = 1). FRX-DIS Disables the FRX filter. FRX-DIS = 0 FRX-DIS = 1 FRX filter is enabled. FRX filter is disabled (HFRX = 1). FRR-DIS Disables the FRR filter. FRR-DIS = 0 FRR-DIS = 1 FRR filter is enabled. FRR filter is disabled (HFRR = 1). HPX-DIS Disables the high-pass filter in transmit direction. HPX-DIS = 0 HPX-DIS = 1 High-pass filter is enabled. High-pass filter is disabled (HHPX = 1). Data Sheet 292 2000-07-14 DuSLIC-S/-S2 Preliminary HPR-DIS SLICOFI-2x Command Structure and Programming Disables the high-pass filter in receive direction. HPR-DIS = 0 HPR-DIS = 1 High-pass filter is enabled. High-pass filter is disabled (HHPR = 1). 19H reserved 00H Y Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Data Sheet 293 2000-07-14 DuSLIC-S/-S2 Preliminary 1AH Bit DSCR 7 SLICOFI-2x Command Structure and Programming DTMF Sender Configuration Register 6 5 4 3 COR8 2 PTG 00H 1 Y 0 DG-KEY[3:0] TG2-EN TG1-EN DG-KEY[3:0] Selects one of sixteen DTMF keys generated by the two tone generators. The key will be generated if both TG1-EN and TG2-EN are `1'. Table 67 DTMF Keys fLOW [Hz] 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 COR8 fHIGH [Hz] DIGIT 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633 1 2 3 4 5 6 7 8 9 0 * # A B C D DG-KEY3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 DG-KEY2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 DG-KEY1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 DG-KEY0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Cuts off the receive path at 8 kHz before the tone generator summation point. Allows sending of tone generator signals without overlaid voice. COR8 = 0 COR8 = 1 Cut off receive path disabled. Cut off receive path enabled. Data Sheet 294 2000-07-14 DuSLIC-S/-S2 Preliminary PTG SLICOFI-2x Command Structure and Programming Programmable coefficients for tone generators will be used. PTG = 0 PTG = 1 TG2-EN Frequencies set by DG-KEY are used for both tone generators. CRAM coefficients used for both tone generators. Enables tone generator two TG2-EN = 0 TG2-EN = 1 Tone generator is disabled. Tone generator is enabled. TG1-EN Enables tone generator one TG1-EN = 0 TG1-EN = 1 Tone generator is disabled. Tone generator is enabled. Data Sheet 295 2000-07-14 DuSLIC-S/-S2 Preliminary 1BH Bit 7 0 reserved 6 0 5 0 4 0 3 0 2 0 SLICOFI-2x Command Structure and Programming 00H 1 0 Y 0 0 1CH Bit LMCR1 7 TESTEN Level Metering Configuration Register 1 6 0 5 1 4 PCM2DC 3 0 2 0 22H 1 1 Y 0 0 TEST-EN Activates the SLICOFI-2S/-2S2 test features controlled by test registers TSTR1 to TSTR5. TEST-EN = 0 TEST-EN = 1 SLICOFI-2S/-2S2 test features are disabled. SLICOFI-2S/-2S2 test features are enabled. (The Test Register bits can be programmed before the TEST-EN bit is set to 1.) PCM2DC PCM voice channel data added to the DC-output. PCM2DC = 0 PCM2DC = 1 Normal operation. PCM voice channel data is added to DC-output. 1DH Bit LMCR2 7 0 Level Metering Configuration Register 2 6 0 5 0 4 0 3 0 2 0 00H 1 0 Y 0 0 Data Sheet 296 2000-07-14 DuSLIC-S/-S2 Preliminary 1EH Bit LMCR3 7 ACSHORT -EN SLICOFI-2x Command Structure and Programming Level Metering Configuration Register 3 6 RTRSEL 5 0 4 0 3 0 2 0 00H 1 0 Y 0 0 ACThe input pin ITAC will be set to a lower input impedance so that the SHORT-EN capacitor CITAC can be recharged faster during soft reversal which makes it more silent during conversation. AC-SHORT-EN = 0 Input impedance of the ITAC pin is standard. AC-SHORT-EN = 1 Input impedance of the ITAC pin is lowered. RTR-SEL Ring Trip method selection. RTR-SEL = 0 RTR-SEL = 1 Ring Trip with a DC offset is selected. AC Ring Trip is selected. Recommended for short lines only. 1FH OFR1 Offset Register 1 (High Byte) 00H Y Bit 7 6 5 4 3 2 1 0 OFFSET-H[7:0] OFFSET-H[7:0] Offset register high byte. Data Sheet 297 2000-07-14 DuSLIC-S/-S2 Preliminary 20H OFR2 SLICOFI-2x Command Structure and Programming Offset Register 2 (Low Byte) 00H Y Bit 7 6 5 4 3 OFFSET-L[7:0] 2 1 0 OFFSET-L[7:0] Offset register low byte. The value of this register together with OFFSET-H is added to the input of the DC loop to compensate a given offset of the current sensors in the SLIC-S/-S2. 21H Bit PCMR1 7 R1HW PCM Receive Register 1 6 5 4 3 R1-TS[6:0] 2 00H 1 Y 0 R1-HW Selection of the PCM highway for receiving PCM data or the higher byte of the first data sample if linear 16 kHz PCM mode is selected. R1-HW = 0 R1-HW = 1 PCM highway A is selected. PCM highway B is selected. R1-TS[6:0] Selection of the PCM time slot used for data reception. Note: The programmed PCM time slot must correspond to the available slots defined by the PCLK frequency. No reception will occur if a slot outside the actual numbers of slots is programmed. In linear mode (bit LIN = 1 in register BCR3) R1-TS defines the first of two consecutive slots used for reception. Data Sheet 298 2000-07-14 DuSLIC-S/-S2 Preliminary 22H Bit 7 reserved 6 5 4 3 2 SLICOFI-2x Command Structure and Programming 00H 1 Y 0 23H Bit 7 reserved 6 5 4 3 2 00H 1 Y 0 24H Bit 7 reserved 6 5 4 3 2 00H 1 Y 0 Data Sheet 299 2000-07-14 DuSLIC-S/-S2 Preliminary 25H Bit PCMX1 7 X1-HW SLICOFI-2x Command Structure and Programming PCM Transmit Register 1 6 5 4 3 X1-TS[6:0] 2 00H 1 Y 0 X1-HW Selection of the PCM highway for transmitting PCM data or the higher byte of the first data sample if linear 16 kHz PCM mode is selected. X1-HW = 0 X1-HW = 1 PCM highway A is selected. PCM highway B is selected. X1-TS[6:0] Selection of the PCM time slot used for data transmission. Note: The programmed PCM time slot must correspond to the available slots defined by the PCLK frequency. No transmission will occur if a slot outside the actual numbers of slots is programmed. In linear mode X1-TS defines the first of two consecutive slots used for transmission. PCM data transmission is controlled by bits 6 to 2 in register BCR3. Data Sheet 300 2000-07-14 DuSLIC-S/-S2 Preliminary 26H Bit 7 reserved 6 5 4 3 2 SLICOFI-2x Command Structure and Programming 00H 1 Y 0 27H Bit 7 reserved 6 5 4 3 2 00H 1 Y 0 28H Bit 7 reserved 6 5 4 3 2 00H 1 Y 0 Data Sheet 301 2000-07-14 DuSLIC-S/-S2 Preliminary 29H Bit TSTR1 7 SLICOFI-2x Command Structure and Programming Test Register 1 6 5 4 3 2 PDGNKC 00H 1 PDOFHC T Y 0 PDOVTC PD-AC- PD-AC- PD-AC- PD-AC- PD-ACPR PO AD DA GN Register setting is only active if bit TEST-EN in register LMCR1 is set to 1. PD-AC-PR AC-PREFI power down PD-AC-PR = 0 PD-AC-PR = 1 PD-AC-PO Normal operation. Power down mode. AC-POFI power down PD-AC-PO = 0 PD-AC-PO = 1 Normal operation. Power down mode. PD-AC-AD AC-ADC power down PD-AC-AD = 0 PD-AC-AD = 1 Normal operation. Power down mode, transmit path is inactive. PD-AC-DA AC-DAC power down PD-AC-DA = 0 PD-AC-DA = 1 Normal operation. Power down mode, receive path is inactive. PD-AC-GN AC-Gain power down PD-AC-GN = 0 PD-AC-GN = 1 Normal operation. Power down mode. PD-GNKC Ground Key comparator (GNKC) is set to power down PD-GNKC = 0 PD-GNKC = 1 Normal operation. Power down mode. Data Sheet 302 2000-07-14 DuSLIC-S/-S2 Preliminary PD-OFHC SLICOFI-2x Command Structure and Programming Off-hook comparator (OFHC) power down PD-OFHC = 0 PD-OFHC = 1 PD-OVTC Normal operation. Power down mode. Overtemperature comparator (OVTC) power down PD-OVTC = 0 PD-OVTC = 1 Normal operation. Power down mode. Data Sheet 303 2000-07-14 DuSLIC-S/-S2 Preliminary 2AH Bit TSTR2 7 PD-DCPR 1) SLICOFI-2x Command Structure and Programming Test Register 2 6 0 5 4 3 2 0 00H 1 T Y 0 PD-DC- PD-DCPDAD DA DCBUF PDPD-HVI TTX-A1) Only for DuSLIC-S, is set to 0 for DuSLIC-S2 Register setting is only active if bit TEST-EN in register LMCR1 is set to 1. PD-DC-PR DC-PREFI power down PD-DC-PR = 0 PD-DC-PR = 1 PD-DC-AD Normal operation. Power down mode. DC-ADC power down PD-DC-AD = 0 PD-DC-AD = 1 Normal operation. Power down mode, transmit path is inactive. PD-DC-DA DC-DAC power down PD-DC-DA = 0 PD-DC-DA = 1 Normal operation. Power down mode, receive path is inactive. PD-DCBUF DC-BUFFER power down PD-DCBUF = 0 PD-DCBUF = 1 Normal operation. Power down mode. PD-TTX-A TTX adaptation DAC and POFI power down PD-TTX-A = 0 PD-TTX-A = 1 Normal operation. Power down mode. PD-HVI HV interface (to SLIC-S/-S2) power down PD-HVI = 0 PD-HVI = 1 Normal operation. Power down mode. Data Sheet 304 2000-07-14 DuSLIC-S/-S2 Preliminary 2BH Bit TSTR3 7 0 SLICOFI-2x Command Structure and Programming Test Register 3 6 0 5 ACDLB4M 4 ACDLB128K 3 ACDLB32K 2 ACDLB8K 00H 1 0 T Y 0 0 Register setting is only active if bit TEST-EN in register LMCR1 is set to 1. AC-DLB-4M AC digital loop via 4 MHz bitstream. (The loop encloses all digital hardware in the AC path. Together with DLB-DC a pure digital test is possible because there is no influence the analog hardware.) AC-DLB-4M = 0 AC-DLB-4M = 1 Normal operation. Digital loop closed. AC-DLB-128K AC digital loop via 128 kHz AC-DLB-128K = 0 Normal operation. AC-DLB-128K = 1 Digital loop closed. AC-DLB-32K AC digital loop via 32 kHz AC-DLB-32K = 0 AC-DLB-32K = 1 Normal operation. Digital loop closed. AC-DLB-8K AC digital loop via 8 kHz AC-DLB-8K = 0 AC-DLB-8K = 1 Normal operation. Digital loop closed. Data Sheet 305 2000-07-14 DuSLIC-S/-S2 Preliminary 2CH Bit TSTR4 7 OPIMAN SLICOFI-2x Command Structure and Programming Test Register 4 6 OPIM4M 5 4 3 0 2 0 00H 1 0 T Y 0 0 COR-64 COX-16 Register setting is only active if bit TEST-EN in register LMCR1 is set to 1. OPIM-AN Open Impedance Matching Loop in the analog part. OPIM-AN = 0 OPIM-AN = 1 Normal operation. Loop opened. OPIM-4M Open fast digital Impedance Matching Loop in the hardware filters. OPIM-4M = 0 OPIM-4M = 1 Normal operation. Loop opened. COR-64 Cut off the AC receive path at 64 kHz (just before the IM filter). COR-64 = 0 COR-64 = 1 Normal operation. Receive path is cut off. COX-16 Cut off the AC transmit path at 16 kHz. (The TH filter can be tested without influencing the analog part.) COX-16 = 0 COX-16 = 1 Normal operation. Transmit path is cut off. Data Sheet 306 2000-07-14 DuSLIC-S/-S2 Preliminary 2DH Bit TSTR5 7 0 SLICOFI-2x Command Structure and Programming Test Register 5 6 0 5 0 4 DCPOFIHI 3 DCHOLD 2 0 00H 1 0 T Y 0 0 Register setting is only active if bit TEST-EN in register LMCR1 is set to 1. DC-POFI-HI DC post filter limit frequency higher value DC-POFI-HI = 0 DC-POFI-HI = 1 DC-HOLD Limit frequency is set to 100 Hz (normal operation). Limit frequency is set to 300 Hz. Actual DC output value hold (value of the last DSP filter stage will be kept) DC-HOLD = 0 DC-HOLD = 1 Normal operation. DC output value hold. Data Sheet 307 2000-07-14 DuSLIC-S/-S2 Preliminary SLICOFI-2x Command Structure and Programming 6.3.2 COP Command The COP command gives access to the CRAM data of the DSPs. It is organized in the same way as the SOP command. The offset value allows a direct as well as a block access to the CRAM. Writing beyond the allowed offset will be ignored, reading beyond it will give unpredictable results. The value of a specific CRAM coefficient is calculated by the DuSLICOS software. Bit Byte 1 Byte 2 RD Read Data RD = 0 Write data to chip. RD = 1 Read data from chip. ADR[2:0] Channel address for the subsequent data 7 RD 6 1 5 4 ADR[2:0] OFFSET[7:0] 3 2 1 1 0 0 1 ADR[2:0] = 0 0 0 ADR[2:0] = 0 0 1 Channel A Channel B (other codes reserved for future use) Data Sheet 308 2000-07-14 DuSLIC-S/-S2 Preliminary Offset [7:0] 00H 08H 10H 18H 20H 28H 30H 38H 40H 48H 50H 58H 60H 68H 70H 78H 80H 88H 90H 98H Short Name TH1 TH2 TH3 FRR FRX AR AX PTG1 PTG2 LPR LPX TTX IM1 IM2 RINGF RAMPF DCF HF TPF SLICOFI-2x Command Structure and Programming Long Name Transhybrid Filter Coefficients Part 1 Transhybrid Filter Coefficients Part 2 Transhybrid Filter Coefficients Part 3 Frequency-response Filter Coefficients Receive Direction Frequency-response Filter Coefficients Transmit Direction Amplification/Attenuation Stage Coefficients Receive Amplification/Attenuation Stage Coefficients Transmit Tone Generator 1 Coefficients Tone Generator 2 Coefficients Low Pass Filter Coefficients Receive Low Pass Filter Coefficients Transmit Teletax Coefficients Impedance Matching Filter Coefficients Part 1 Impedance Matching Filter Coefficients Part 2 Ringer Frequency and Amplitude Coefficients (DC loop) Ramp Generator Coefficients (DC loop) DC-Characteristics Coefficients (DC loop) Hook Threshold Coefficients (DC loop) Low Pass Filter Coefficients (DC loop) Reserved Data Sheet 309 2000-07-14 DuSLIC-S/-S2 Preliminary Table 68 Byte 7 SLICOFI-2x Command Structure and Programming CRAM Coefficients Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 Offset [7:0] 00H 08H 10H 18H 20H 1st Gain Stage Receive 1st Gain Stage Transmit TG1 Gain TG2 Gain TG1 Frequency TG2 Frequency 28H 30H 38H 40H 48H 50H TTX Slope IM FIR Filter IM WDF Filter Ring Generator Frequency Constant Ramp CR Ring Generator Lowpass Soft Ramp SS Ring Offset RO1 Ring Delay RD TTX Level 58H 60H 68H 70H 78H TTX IM1_F IM2_F RINGF RAMPF TH1 TH2 TH3 FRR FRX AR AX PTG11) PTG21) Transhybrid Coefficient Part 1 Transhybrid Coefficient Part 2 Transhybrid Coefficient Part 3 FIR Filter in Receive Direction FIR Filter in Transmit Direction 2nd Gain Stage Receive 2nd Gain Stage Transmit TG1 Bandpass TG2 Bandpass Reserved Reserved FIR Filter for TTX IM K Factor IM 4 MHz Filter Ring Generator Amplitude Extended Battery Feeding Gain Res. in Resistive Zone RK12 Soft Reversal End Res. in Constant Current Zone RI Constant Current IK1 Hook Threshold Ring Knee Voltage VK1 Hook Threshold Active Open Circuit Volt. 80H 88H 90H 98H DCF HF TPF VLIM Hook Threshold Power Down DC Lowpass Filter TP1 Hook Message Waiting Hook Threshold AC Ring Trip Voltage Level VRT Reserved 16 15 14 13 12 11 10 9 8 DC Lowpass Filter TP2 7 6 5 4 3 2 1 Note: CRAM coefficients are enabled by setting bit CRAM-EN in register BCR3 to 1, except coefficients PTG1 and PTG21) which are enabled by setting bit PTG in register DSCR to 1. Data Sheet 310 2000-07-14 DuSLIC-S/-S2 Preliminary SLICOFI-2x Command Structure and Programming 6.3.2.1 Table 69 Parameter CRAM Programming Ranges CRAM Programming Ranges Programming Range 0...50 mA, < 0.5 mA 0..25 mA, < 0.7 mA 25...50 mA, < 1.3 mA 3..40 Hz, < 1 Hz 40..80 Hz, < 2 Hz > 80 Hz, < 4 Hz 0..20 V, < 1.7 V 20..85 V, < 0.9 V 0..25 V, < 0.6 V 25..50 V, < 1.2 V 50..100 V, < 2.4 V, max. 150 V 0..25 V, < 0.6 V 25..50 V, < 1.2 V > 50 V, < 2.4 V 0..1000 , < 30 1.8 k..4.8 k, < 120 4.8 k..9.6 k, < 240 9.6 k..19 k, < 480 19 k..38 k, < 960 , max. 40 k Constant Current IK1 Hook Message Waiting, Hook Thresholds Ring Generator Frequency fRING Ring Generator Amplitude Ring Offset RO1 Knee Voltage VK1, Open Circuit Voltge VLIM Resistance in Resistive Zone RK12 Resistance in Constant Current Zone RI Data Sheet 311 2000-07-14 DuSLIC-S/-S2 Preliminary SLICOFI-2x Command Structure and Programming 6.3.3 IOM-2 Interface Command/Indication Byte The Command/Indication (C/I) channel is used to communicate real time status information and for fast controlling of the DuSLIC. Data on the C/I channel are continuously transmitted in each frame until new data are sent. Data Downstream C/I - Channel Byte (Receive) - IOM-CIDD The first six CIDD data bits control the general operating modes for both DuSLIC channels. According to the IOM-2 specification, new data have to be present for at least two frames to be accepted. Table 70 CIDD M2 1 0 0 1 1 1 0 M2, M1, M0: General Operating Mode M1 1 0 1 0 1 0 0 M0 1 0 0 1 0 0 1 SLICOFI-2S/-2S2 Operating Mode (for details see "Operating Modes for the DuSLIC Chip Set" on Page 78) Sleep, Power Down (PDRx) Power Down High Impedance (PDH) Any Active mode Ringing (ACTR Burst On) Active with Metering Ground Start Ring Pause CIDD Bit 7 M2A ) Data Downstream C/I - Channel Byte 6 M1A 5 M0A 4 M2B 3 M1B 2 M0B 1 MR N 0 MX M2A, M1A, M0A M2B, M1B, M0B MR, MX Select operating mode for DuSLIC channel A Select operating mode for DuSLIC channel B Handshake bits Monitor Receive and Transmit (see "IOM-2 Interface Monitor Transfer Protocol" on Page 148) Data Sheet 312 2000-07-14 DuSLIC-S/-S2 Preliminary SLICOFI-2x Command Structure and Programming Data Upstream C/I - Channel Byte (Transmit) - IOM-CIDU This byte is used to quickly transfer the most important and time-critical information from the DuSLIC. Each transfer from the DuSLIC lasts for at least two consecutive frames. CIDU Bit 7 Data Upstream C/I - Channel Byte 6 5 4 3 2 00H 1 MR N 0 MX INT-CHA HOOKA GNDKA INT-CHB HOOKB GNDKB INT-CHA Interrupt information channel A INT-CHA = 0 No interrupt in channel A INT-CHA = 1 Interrupt in channel A Hook information channel A HOOKA = 0 On-hook channel A HOOKA = 1 Off-hook channel A Ground key information channel A GNDKA = 0 No longitudinal current detected GNDKA = 1 Longitudinal current detected in channel A Interrupt information channel B INT-CHB = 0 No interrupt in channel B INT-CHB = 1 Interrupt in channel B Hook information channel B HOOKB = 0 On-hook Channel B HOOKB = 1 Off-hook Channel B Ground key information channel B GNDKB = 0 No longitudinal current detected GNDKB = 1 Longitudinal current detected in channel B HOOKA GNDKA INT-CHB HOOKB GNDKB MR, MX Handshake bits Monitor Receive and Transmit (see "IOM-2 Interface Monitor Transfer Protocol" on Page 148) Data Sheet 313 2000-07-14 DuSLIC-S/-S2 Preliminary SLICOFI-2x Command Structure and Programming 6.3.4 6.3.4.1 Programming Examples of the SLICOFI-2S/-2S2 Microcontroller Interface SOP Write to Channel 0 Starting After the Channel-Specific Read-Only Registers 01000100 00010101 00000000 00000000 00010001 00000000 00000000 First command byte (SOP write for channel 0) Second command byte (offset to BCR1 register) Contents of BCR1 register Contents of BCR2 register Contents of BCR3 register Contents of BCR4 register Contents of BCR5 register Command DIN DCLK CS ezm220121.wmf Offset BCR1 BCR2 BCR3 BCR4 BCR5 Figure 76 Waveform of Programming Example SOP Write to Channel 0 SOP Read from Channel 1 Reading Out the Interrupt Registers 11001100 00000111 First command byte (SOP read for channel 1). Second command byte (offset to Interrupt register 1). The SLICOFI-2S/-2S2 will send data when it has completely received the second command byte. 11111111 11000000 00000010 00000000 00000000 Dump byte (this byte is always FFH). Interrupt register INTREG1 (an interrupt has occurred, Off-hook was detected). Interrupt register INTREG2 (IO pin 2 is `1'). Interrupt register INTREG3 Interrupt register INTREG4 Command DIN DOUT DCLK CS ezm220122.emf Offset Dump Intreg 1 Intreg 2 Intreg 3 Intreg 4 Figure 77 Data Sheet Waveform of Programming Example SOP Read from Channel 0 314 2000-07-14 DuSLIC-S/-S2 Preliminary SLICOFI-2x Command Structure and Programming 6.3.4.2 IOM-2 Interface An example with the same programming sequence as before, using the IOM-2 interface is presented here to show the differences between the microcontroller interface and the IOM-2 interface. SOP Write to Channel 0 Starting After the Channel-Specific Read-Only Registers Monitor MR/MX Monitor data down data up 10000001 10000001 01000100 01000100 00010101 00010101 00000000 00000000 00000000 00000000 00010001 00010001 00000000 00000000 11111111 11111111 10 10 11 10 11 10 11 10 11 10 11 10 11 10 11 11 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 MR/MX Comment 11 01 01 11 01 11 01 11 01 11 01 11 01 11 01 11 IOM-2 address first byte IOM-2 address second byte First command byte (SOP write for channel 0) First command byte second time Second command byte (offset to BCR1 register) Second command byte second time Contents of BCR1 register Contents of BCR1 register second time Contents of BCR2 register Contents of BCR2 register second time Contents of BCR3 register Contents of BCR3 register second time Contents of BCR4 register Contents of BCR4 register second time No more information (dummy byte) Signaling EOM (end of message) by holding MX bit at `1'. Since the SLICOFI-2S/-2S2 has an open command structure, no fixed command length is given. The IOM-2 handshake protocol allows for an infinite length of a data stream, therefore the host has to terminate the data transfer by sending an end-of-message signal (EOM) to the SLICOFI-2S/-2S2. The SLICOFI-2S/-2S2 will abort the transfer only if the host tries to write or read beyond the allowed maximum offsets given by the different types of commands. Each transfer has to start with the SLICOFI-2S/-2S2specific IOM-2 Address (81H) and must end with an EOM of the handshake bits. Appending a command immediately to its predecessor without an EOM in between is not allowed. When reading interrupt registers, SLICOFI-2S/-2S2 stops the transfer after the fourth register in IOM-2 mode. This is to prevent some host chips reading 16 bytes because they can't terminate the transfer after n bytes. Data Sheet 315 2000-07-14 DuSLIC-S/-S2 Preliminary SLICOFI-2x Command Structure and Programming SOP-Read from Channel 1 Reading Out the Interrupt Registers Monitor MR/MX Monitor data down data up 10000001 10000001 11001100 11001100 00001000 00001000 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 10 10 11 10 11 10 11 11 01 01 11 01 11 01 11 01 11 11 11 11111111 11111111 11111111 11111111 11111111 11111111 11111111 10000001 10000001 11000000 11000000 00000010 00000010 00000000 00000000 00000000 00000000 01001101 11111111 MR/MX Comment 11 01 01 11 01 11 01 10 10 11 10 11 10 11 10 11 10 11 11 IOM-2 address first byte IOM-2 address second byte First command byte (SOP read for channel 1) First command byte second time Second command byte (offset to interrupt register 1) Second command byte second time Acknowledgement for the second command byte IOM-2 Address first byte (answer) IOM-2 Address second byte Interrupt register INTREG1 Interrupt register INTREG1 second time Interrupt register INTREG2 Interrupt register INTREG2 second time Interrupt register INTREG3 Interrupt register INTREG3 second time Interrupt register INTREG4 Interrupt register INTREG4 second time SLICOFI-2S/-2S2 sends the next register SLICOFI-2S/-2S2 aborts transmission Data Sheet 316 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7 7.1 7.1.1 Parameter Electrical Characteristics Electrical Characteristics PEB 4264/-2 (SLIC-S/-S2) Absolute Maximum Ratings PEB 4264/-2 (SLIC-S/-S2) Symbol min. Limit Values max. 0.4 0.4 50 95 7 0.4 V V V V V V referred to Unit Test Condition Battery voltage L Battery voltage Auxiliary supply voltage VBATL - 65 VBATL - VBATH - 0.4 VBATH - 70 VHR - 0.4 - 0.4 - 0.4 VBGND referred to VBGND referred to VBGND - referred to Total battery supply VHR - VBATH voltage, continuous VDD supply voltage VDD Ground voltage difference VAGND VBGND - - 0.4 VAGND Input voltages VDCP, VDCN, - 0.4 VACP, VACN, VC1, VC2, VCMS Voltages on current VIT, VIL - 0.4 outputs RING, TIP voltages, VR, VT continuous - referred to VDD + 0.4 V VAGND VDD + 0.4 V V V referred to VAGND VBATL - 0.4 0.4 VBATH - 0.4 0.4 ACTL ACTH, PDRH, PDRHL ACTR, PDH, HIT, HIR all modes all modes all modes VBATH - 0.4 VHR + 0.4 V RING,TIP voltages, VR, VT pulse < 10 ms RING,TIP voltages, VR, VT pulse < 1 ms RING, TIP voltages, VR, VT pulse < 1 s t.b.d t.b.d V V V VBATH - 10 VHR + 10 VBATH - 10 VHR + 30 Data Sheet 317 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.1.1 Parameter Absolute Maximum Ratings PEB 4264/-2 (SLIC-S/-S2) (cont'd) Symbol min. - - - Limit Values max. 1 150 2) kV C SDM (Socketed Device Model)1) Unit Test Condition ESD voltage, all pins Junction temperature 1) 2) Tj EOS/ESD Assn. Standard DS5.3-1993. Even higher value is possible when internal junction temperature protection is operative. Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; even if only one of these values is exceeded, the integrated circuit may be irreversibly damaged. Data Sheet 318 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.1.2 Parameter Operating Range PEB 4264/-2 (SLIC-S/-S2) Symbol 1) 1) Limit Values min. max. - 15 - 20 45 90 5.25 0.4 125 - 60 - 65 5 - Unit Test Condition V V V V V V C referred to VBGND referred to VBGND referred to VBGND - referred to VAGND - simulated for a lifetime of 15 years referred to VAGND referred to VAGND Battery voltage L Auxiliary supply voltage Battery voltage H VBATL VBATH VHR VHR - VBATH Total battery supply voltage VDD supply voltage Ground voltage difference VDD 4.75 VBGND - VAGND - 0.4 - Junction temperature Tj Voltage at pins IT, IL Input range VDCP, VDCN, VACP, VACN 1) VIT, VIL VACDC - 0.4 0 3.5 3.3 V V If the battery switch is not used both pins VBATL and VBATH should be connected together externally. In this case the full voltage range of - 15 V to - 65 V can be used. 7.1.3 Parameter Thermal Resistances PEB 4264/-2 (SLIC-S/-S2) Symbol Limit Values <2 < 50 Unit Test Condition K/W - K/W without heatsink Junction to case Junction to ambient Rth, jC Rth, jA Data Sheet 319 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.1.4 Electrical Parameters PEB 4264/-2 (SLIC-S/-S2) Minimum and maximum values are valid within the full operating range. Functionality and performance is guaranteed for TA = 0 to 70 C by production testing. Extented temperature range operation at - 40 C < TA < 85 C is guaranteed by design, characterization and periodically sampling and testing production devices at the temperature extremes. Testing is performed according to the specific test figures. Unless otherwise stated, load impedance RL = 600 , VBATH = - 48 V, VBATL = - 24 V, VHR = + 32 V and VDD = + 5 V, RIT = 1 k, RIL = 2 k,=CEXT = 470 nF. Typical values are tested at TA = 25 C. Supply Currents and Power Dissipation (IR = IT = 0 A; VCMS = VACP = VACN = VDCP = VDCN = 1.5 V) No. Parameter Symbol Mode Limit Values min. typ. Power Down High Impedance, Power Down Resistive High 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. max. Unit VDD current VBATH current VBATL current VHR current IDD IBATH IBATL IHR PDH PDRH PDH PDRH PDH PDRH PDH PDRH PDH PDRH - - - - - - - - - - 120 120 65 80 0 0 0 0 3.7 4.4 - - - - - - - - - - A A A A mW Quiescent power dissipation PQ Active Low 11. 12. 13. 14. 15. VDD current VBATH current VBATL current VHR current IDD IBATH IBATL IHR Quiescent power dissipation PQ ACTL ACTL ACTL ACTL ACTL - - - - - 1000 1200 A 25 0 45 10 A A mW 2800 3400 A 73.4 89.8 Data Sheet 320 2000-07-14 DuSLIC Preliminary Electrical Characteristics Supply Currents and Power Dissipation (IR = IT = 0 A; VCMS = VACP = VACN = VDCP = VDCN = 1.5 V) (cont'd) No. Parameter Symbol Mode Limit Values min. typ. Active High 16. 17. 18. 19. 20. max. Unit VDD current VBATH current VBATL current VHR current IDD IBATH IBATL IHR Quiescent power dissipation PQ ACTH ACTH ACTH ACTH ACTH - - - - - 1000 1300 A 3500 4300 A 0 0 173 10 10 A A 213.5 mW Active Ring 21. 22. 23. 24. 25. VDD current VBATH current VBATL current VHR current IDD IBATH IBATL IHR Quiescent power dissipation PQ ACTR ACTR ACTR ACTR ACTR - - - - - 500 0 225 700 10 271 A A mW 3100 3700 A 2300 2800 A High Impedance on RING, High Impedance on TIP 26. 27. 28. 29. 30. VDD current VBATH current VBATL current VHR current IDD IBATH IBATL IHR Quiescent power dissipation PQ HIR, HIT HIR, HIT HIR, HIT HIR, HIT HIR, HIT - - - - - 500 0 151 700 10 199 A A mW 2100 2600 A 1500 2200 A Data Sheet 321 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.1.5 Power Calculation PEB 4264/-2 (SLIC-S/-S2) The total power dissipation consists of the quiescent power dissipation PQ given above, the current sensor power dissipation PI (see Table 71), the gain stage power dissipation correction PG1) (see Table 72) and the output stage power dissipation PO (see Table 73): Ptot = PQ + PI + PG + PO with PQ = VDD x IDD + IVBATHI x IBATH + IVBATLI x IBATL + VHR x IHR For the calculation of PI, PG and PO see the following tables: Table 71 Operating Mode PDH PDRH, PDRHL ACTL ACTH ACTR HIR, HIT HIRT 1) PI Calculation PEB 4264/-2 (SLIC-S/-S2) Equation for PI Calculation PI = 0 (no DC loop current) PI = ITrans=x=ITrans=x=(10000 + 500 + 16) + ITrans x (0.6 + 0.425 x |VBATH|) PI = 0.055 x ITrans x |VBATL| + 0.04 x ITrans x VDD PI = 0.055 x ITrans x |VBATH| + 0.04 x ITrans x VDD PI = 0.015 x ITrans x VHR + 0.055 x ITrans x |VBATH| + 0.04 x ITrans x VDD PI = 0.015 x ITorR1) x VHR + 0.04 x ITorR x |VBATH| + 0.02 x ITorR x VDD PI = 0 (no DC loop current) ITorR = ITIP or IRING . 1) The gain stage power dissipation correction PG is a correcting term necessary to ensure a correct power calculation if other as the defined supply voltages are used. Data Sheet 322 2000-07-14 DuSLIC Preliminary Table 72 Operating Mode PDH, PDRH Electrical Characteristics PG Calculation PEB 4264/-2 (SLIC-S/-S2) Equation for PG Calculation PG = 0 (gain stage not working) ACTL PG = (VBATL2 - 242) x (1/60k + 1/216k) ACTH, PDRHL PG = (VBATH2 - 482) x (1/60k + 1/216k) ACTR PG = (VHR + |VBATH|) x (|VHR + VBATH + VTIP/RING| + |VHR + VBATH -VTIP/RING| - 2 x |VHR + VBATH|)/120k + (VHR2 - 322 + VBATH2 - 482) x (1/60k + 1/216k) HIR, HIT, HIRT PG = (VHR + |VBATH|) x (|VHR + VBATH + expVTIP/RING1)| + |VHR + VBATH - VTIP/RING| - 2 x |VHR + VBATH|)/120k + (VHR2 - 322 + VBATH2 - 482) x (1/60k + 1/216k) 1) Expected VTIP/RING when SLIC-S/-S2 output buffer in high impedance. Table 73 PO Calculation PEB 4264/-2 (SLIC-S/-S2) Equation for PO Calculation Operating Mode ACTL ACTH ACTR HIR, HIT HIRT 1) PDH, PDRH, PDRHL PO = 0 (output stage not working) PO = (|VBATL| - VTIP/RING) x ITrans PO = (|VBATH| - VTIP/RING) x ITrans PO = (VHR + |VBATH| - VTIP/RING) x ITrans PO = VSupply-TorR1) x ITorR PO = 0 (output stage not working) VSupply-TorR = VSupply - VTIP or VRING 7.1.6 Power Up Sequence PEB 4264/-2 (SLIC-S/-S2) The supply voltages of the SLIC-S/-S2 have to be applied in the following order to the respective pin: 1) Ground to pins AGND and BGND 2) VDD to pin VDD 3) VBATH to pin VBATH 4) VHR to pin VHR and VBATL to pin VBATL If the VDD voltage is applied more than one second later as VBATH, VHR or VBATL thermal damage of the SLIC-S/-S2 can accur. If the above sequence of the battery voltages can not be guaranteed, a diode (1N4007) has to be inserted in the VBATH line Data Sheet 323 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.2 7.2.1 Parameter Electrical Characteristics PEB 4265/-2 (SLIC-E/-E2) Absolute Maximum Ratings PEB 4265/-2 (SLIC-E/-E2) Symbol min. Limit Values max. 0.4 - 0.4 90 160 7 0.4 V V V V V V V referred to VBGND referred to VBGND referred to VBGND - referred to VAGND - referred to VAGND - 85 - 0.4 - 90 - 0.4 - Unit Test Condition Battery voltage L Battery voltage H Auxiliary supply voltage VBATL VBATL - VBATH VBATH VHR Total battery supply VHR - VBATH voltage, continuous VDD supply voltage VDD - 0.4 Ground voltage VBGND - VAGND - 0.4 difference Input voltages VDCP, VDCN, - 0.4 VACP, VACN, VC1, VC2, VCMS Voltages on current VIT, VIL - 0.4 outputs RING, TIP voltages, VR, VT continuous VDD + 0.4 V VDD + 0.4 V V V referred to VAGND ACTL ACTH, PDRH, PDRHL ACTR, PDH, HIRT, HIT, HIR all modes all modes all modes SDM (Socketed Device Model)1) VBATL - 0.4 0.4 VBATH - 0.4 0.4 VBATH - 0.4 VHR + 0.4 V RING, TIP voltages, VR, VT pulse < 10 ms RING, TIP voltages, VR, VT pulse < 1 ms RING, TIP voltages, VR, VT pulse < 1 s ESD voltage, all pins Junction temperature 1) 2) t.b.d t.b.d V VBATH - 10 VHR + 10 V VBATH - 10 VHR + 30 V - - 1 150 2) kV C - Tj EOS/ESD Assn. Standard DS5.3-1993. Even higher value is possible when internal junction temperature protection is operative. Data Sheet 324 2000-07-14 DuSLIC Preliminary Electrical Characteristics Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; even if only one of these values is exceeded, the integrated circuit may be irreversibly damaged. 7.2.2 Parameter Operating Range PEB 4265/-2 (SLIC-E/-E2) Symbol Limit Values min. max. - 15 - 20 85 150 5.25 0.4 125 3.5 3.3 V V V V V V C V V referred to VBGND referred to VBGND referred to VBGND - referred to VAGND - simulated for a lifetime of 15 years referred to VAGND referred to VAGND - 80 - 85 5 - Unit Test Condition Battery voltage L1) VBATL Battery voltage H1) VBATH Auxiliary supply voltage VHR Total battery supply VHR - VBATH voltage VDD supply voltage Ground voltage difference Junction temperature Voltage at pins IT, IL Input range VDCP, VDCN, VACP, VACN 1) VDD 4.75 VBGND - VAGND - 0.4 Tj VIT, VIL VACDC - - 0.4 0 If the battery switch is not used both pins VBATL and VBATH should be connected together externally. In this case the full voltage range of - 15 V to - 85 V can be used. 7.2.3 Parameter Thermal Resistances PEB 4265/-2 (SLIC-E/-E2) Symbol Limit Values <2 < 50 Unit Test Condition K/W - K/W without heatsink Junction to case Junction to ambient Rth, jC Rth, jA Data Sheet 325 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.2.4 Electrical Parameters PEB 4265/-2 (SLIC-E/-E2) Minimum and maximum values are valid within the full operating range. Functionality and performance is guaranteed for TA = 0 to 70 C by production testing. Extented temperature range operation at - 40 C < TA < 85 C is guaranteed by design, characterization and periodically sampling and testing production devices at the temperature extremes. Testing is performed according to the specific test figures. Unless otherwise stated, load impedance RL = 600 , VBATH = - 48 V, VBATL = - 24 V, VHR = + 32 V and VDD = + 5 V, RIT = 1 k, RIL = 2 k,=CEXT = 470 nF. Typical values are tested at TA = 25 C. Supply Currents and Power Dissipation (IR = IT = 0 A; VCMS = VACP = VACN = VDCP = VDCN = 1.5 V) No. Parameter Symbol Mode Limit Values min. typ. Power Down High Impedance, Power Down Resistive High 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. max. Unit VDD current VBATH current VBATL current VHR current Quiescent power dissipation IDD IBATH IBATL IHR PQ PDH PDRH PDH PDRH PDH PDRH PDH PDRH PDH PDRH - - - - - - - - - - 120 120 65 80 0 0 0 0 3.7 4.4 - - - - - - - - - - A A A A mW Active Low 11. 12. 13. 14. 15. VDD current VBATH current VBATL current VHR current IDD IBATH IBATL IHR Quiescent power dissipation PQ ACTL ACTL ACTL ACTL ACTL - - - - - 1000 1200 A 25 0 45 10 A A mW 2800 3400 A 73.4 89.8 Data Sheet 326 2000-07-14 DuSLIC Preliminary Electrical Characteristics Supply Currents and Power Dissipation (IR = IT = 0 A; VCMS = VACP = VACN = VDCP = VDCN = 1.5 V) (cont'd) No. Parameter Symbol Mode Limit Values min. typ. Active High 16. 17. 18. 19. 20. max. Unit VDD current VBATH current VBATL current VHR current IDD IBATH IBATL IHR Quiescent power dissipation PQ ACTH ACTH ACTH ACTH ACTH - - - - - 1000 1300 A 3500 4300 A 0 0 173 10 10 A A 213.5 mW Active Ring 21. 22. 23. 24. 25. VDD current VBATH current VBATL current VHR current IDD IBATH IBATL IHR Quiescent power dissipation PQ ACTR ACTR ACTR ACTR ACTR - - - - - 500 0 225 700 10 271 A A mW 3100 3700 A 2300 2800 A High Impedance on RING, High Impedance on TIP 26. 27. 28. 29. 30. VDD current VBATH current VBATL current VHR current IDD IBATH IBATL IHR Quiescent power dissipation PQ HIR, HIT HIR, HIT HIR, HIT HIR, HIT HIR, HIT - - - - - 500 0 151 700 10 199 A A mW 2100 2600 A 1500 2200 A High Impedance on RING and TIP 31. 32. 33. 34. 35. VDD current VBATH current VBATL current VHR current IDD IBATH IBATL IHR Quiescent power dissipation PQ 327 HIRT HIRT HIRT HIRT HIRT - - - - - 500 0 600 700 10 800 A A A 1000 1500 A 69.7 101.3 mW Data Sheet 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.2.5 Power Calculation PEB 4265/-2 (SLIC-E/-E2) The total power dissipation consists of the quiescent power dissipation PQ given above, the current sensor power dissipation PI (see Table 74), the gain stage power dissipation correction PG1) (see Table 75) and the output stage power dissipation PO (see Table 76): Ptot = PQ + PI + PG + PO with PQ = VDD x IDD + IVBATHI x IBATH + IVBATLI x IBATL + VHR x IHR For the calculation of PI, PG and PO see the following tables: Table 74 PI Calculation PEB 4265/-2 (SLIC-E/-E2) Operating Equation for PI Calculation Mode PDH PDRH, PDRHL ACTL ACTH ACTR HIR, HIT HIRT PI = 0 (no DC loop current) PI = ITrans x ITrans x (10000 + 500 + 16) + ITrans x (0.6 + 0.425 x |VBATH|) PI = 0.055 x ITrans x |VBATL| + 0.04 x ITrans x VDD PI = 0.055 x ITrans x |VBATH| + 0.04 x ITrans x VDD PI = 0.015 x ITrans x VHR + 0.055 x ITrans x |VBATH| + 0.04 x ITrans x VDD PI = 0.015 x ITorR x VHR + 0.04 x ITorR x |VBATH| + 0.02 x ITorR x VDD PI = 0 (no DC loop current) 1) The gain stage power dissipation correction PG is a correcting term necessary to ensure a correct power calculation if other as the defined supply voltages are used. Data Sheet 328 2000-07-14 DuSLIC Preliminary Table 75 PDH, PDRH ACTL ACTH, PDRHL ACTR Electrical Characteristics PG Calculation PEB 4265/-2 (SLIC-E/-E2) Operating Mode Equation for PG Calculation HIR, HIT, HIRT PG = 0 (gain stage not working) PG = (VBATL2 - 242) x (1/60k + 1/216k) PG = (VBATH2 - 482) x (1/60k + 1/216k) PG = (VHR + |VBATH|) x (|VHR + VBATH + VTIP/RING| + |VHR + VBATH - VTIP/RING| - 2 x |VHR +VBATH|)/120k + (VHR2 - 322 + VBATH2 - 482) x (1/60k + 1/216k) PG = (VHR + |VBATH|) x (|VHR + VBATH + expVTIP/RING1)| + |VHR + VBATH - expVTIP/RING| - 2 x |VHR +VBATH|)/120k + (VHR2 - 322 + VBATH2 - 482) x (1/60k + 1/216k) 1) Expected VTIP/RING when SLIC-E/-E2 output buffer in high impedance. Table 76 PO Calculation PEB 4265/-2 (SLIC-E/-E2) Equation for PO Calculation Operating Mode ACTL ACTH ACTR HIR, HIT HIRT PDH, PDRH, PDRHL PO = 0 (output stage not working) PO = (|VBATL| - VTIP/RING) x ITrans PO = (|VBATH| - VTIP/RING) x ITrans PO = (VHR + |VBATH| - VTIP/RING) x ITrans PO = VSupply-TorR x ITorR PO = 0 (output stage not working) 7.2.6 Power Up Sequence PEB 4265/-2 (SLIC-E/-E2) The supply voltages of the SLIC-E/-E2 have to be applied in the following order to the respective pin: 1) Ground to pins AGND and BGND 2) VDD to pin VDD 3) VBATH to pin VBATH 4) VHR to pin VHR and VBATL to pin VBATL If the VDD voltage is applied more than one second later as VBATH, VHR or VBATL thermal damage of the SLIC-E/-E2 can accur. If the above sequence of the battery voltages can not be guaranteed, a diode (1N4007) has to be inserted in the VBATH line. Data Sheet 329 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.3 7.3.1 Parameter Electrical Characteristics PEB 4266 (SLIC-P) Absolute Maximum Ratings PEB 4266 (SLIC-P) Symbol min. Limit Values max. 0.4 0.4 0.4 160 7 0.4 V V V V V V referred to VBGND referred to VBGND referred to VBGND - referred to VAGND - referred to VAGND - 145 - 0.4 - 150 - 155 - 0.4 - Unit Test Condition VBATL VBATL - VBATH Battery voltage H VBATH Battery voltage R VBATR VBATH - VBATR Total battery supply VDD - VBATR Battery voltage L voltage, continuous VDD supply voltage VDD - 0.4 Ground voltage VBGND - VAGND - 0.4 difference VDCP, VDCN, - 0.4 VACP, VACN, VCMS VC1, VC2, VC3 Voltages on current VIT, VIL - 0.4 Input voltages outputs RING, TIP voltages, VR, VT continuous VDD + 0.4 V VDD + 0.4 V V V V referred to VAGND ACTL ACTH, PDRH, PDRHL ACTR, PDH, PDRR, PDRRL, HIRT, HIT, HIT, ROT, ROR all modes all modes all modes VBATL - 0.4 + 0.4 VBATH - 0.4 + 0.4 VBATR - 0.4 + 0.4 RING,TIP voltages, VR, VT pulse < 10 ms RING,TIP voltages, VR, VT pulse < 1 ms RING, TIP voltages, VR, VT pulse < 1 s t.b.d t.b.d V V V VBATR - 10 + 10 VBATR - 10 + 30 Data Sheet 330 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.3.1 Parameter Absolute Maximum Ratings PEB 4266 (SLIC-P) (cont'd) Symbol min. - - - Limit Values max. 1 150 2) kV C SDM (Socketed Device Model)1) Unit Test Condition ESD voltage, all pins Junction temperature 1) 2) Tj EOS/ESD Assn. Standard DS5.3-1993. Even higher value is possible when internal junction temperature protection is operative. Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; even if only one of these values is exceeded, the intergated circuit may be irreversibly damaged. Data Sheet 331 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.3.2 Parameter Operating Range PEB 4266 (SLIC-P) Symbol 1) 1) Limit Values min. max. - 15 - 20 - 25 155 5.5 0.4 125 - 140 - 145 - 150 - Unit Test Condition V V V V V V C referred to VBGND referred to VBGND referred to VBGND - referred to VAGND - simulated for a lifetime of 15 years referred to VAGND referred to VAGND Battery voltage L Battery voltage H Battery voltage R1) Total battery supply voltage VBATL VBATH VBATR VDD - VBATR VDD supply voltage Ground voltage difference VDD 3.1 VBGND - VAGND - 0.4 - Junction temperature Tj Voltage at pins IT, IL Input range VDCP, VDCN, VACP, VACN 1) VIT, VIL VACDC - 0.4 0 3.5 3.3 V V Internal ringing: If the battery switch is not used both pins VBATL and VBATH should be connected together externally. In this case the full voltage range of - 15 V to - 145 V can be used. External ringing: If only one negative battery voltage is used the pins VBATL, VBATH and VBATR should be connected together externally. In this case the full voltage range of - 15 V to - 145 V can be used. 7.3.3 Parameter Thermal Resistances PEB 4266 (SLIC-P) Symbol Limit Values 2 50 Unit Test Condition K/W - K/W without heatsink Junction to case Junction to ambient Rth, jC Rth, jA Data Sheet 332 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.3.4 Electrical Parameters PEB 4266 (SLIC-P) Minimum and maximum values are valid within the full operating range. Functionality and performance is guaranteed for TA = 0 to 70 C by production testing. Extented temperature range operation at - 40 C < TA < 85 C is guaranteed by design, characterization and periodically sampling and testing production devices at the temperature extremes. Testing is performed according to the test figures with external circuitry as indicated in the tables. Unless otherwise stated, load impedance RL = 600 , VBATH = - 48 V, VBATR = - 80 V and VDD = + 5 V, RIT = 1 k, RIL = 2 k, VBATL = - 24 V, CEXT = 470 nF. Typical values are tested at TA = 25 C. Supply Currents and Power Dissipation (IR = IT = 0 A; VCMS = VACP = VACN = VDCP = VDCN = 1.5 V) No. Parameter Symbol Mode Limit Values min. Power Down High Impedance, Power Down Resistive Ring, Power Down Resistive High 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. typ. max. Unit VDD current IDD PDH PDRR PDRH PDH PDRR PDRH PDH PDRR PDRH PDH PDRR PDRH PDH PDRR PDRH - 130 140 140 0 0 60 0 0 0 75 90 35 6.7 7.9 6.4 180 190 190 10 10 120 10 10 10 110 150 90 10.4 13.7 14.1 A A A A A A A A A A A A VBATH current IBATH - VBATL current IBATL - VBATR current IBATR - Quiescent power dissipation PQ - mW mW mW Data Sheet 333 2000-07-14 DuSLIC Preliminary Electrical Characteristics Supply Currents and Power Dissipation (IR = IT = 0 A; VCMS = VACP = VACN = VDCP = VDCN = 1.5 V) (cont'd) No. Parameter Symbol Mode Limit Values min. Active Low 16. 17. 18. 19. 20. typ. max. Unit VDD current VBATH current VBATL current VBATR current IDD IBATH IBATL IBATR Quiescent power dissipation PQ ACTL ACTL ACTL ACTL ACTL - - - - - 900 10 2100 10 56.1 1100 15 2700 25 73.0 A A A A mW Active High 21. 22. 23. 24. 25. VDD current VBATH current VBATL current VBATR current IDD IBATH IBATL IBATR Quiescent power dissipation PQ ACTH ACTH ACTH ACTH ACTH - - - - - 900 2700 0 10 1100 3400 10 25 A A A A 134.9 170.9 mW Active Ring1) 26. 27. 28. 29. 30. VDD current VBATH current VBATL current VBATR current IDD IBATH IBATL IBATR Quiescent power dissipation PQ ACTR ACTR ACTR ACTR ACTR - - - - - 900 0 0 3500 1200 10 10 4400 A A A A 284.5 358.7 mW Ring on Ring, Ring on Tip 31. 32. 33. 34. 35. VDD current VBATH current VBATL current VBATR current IDD IBATH IBATL IBATR Quiescent power dissipation PQ ROR, ROT - ROR, ROT - ROR, ROT - ROR, ROT - ROR, ROT - 800 0 0 2400 196 1100 10 10 2800 230.2 A A A A mW Data Sheet 334 2000-07-14 DuSLIC Preliminary Electrical Characteristics Supply Currents and Power Dissipation (IR = IT = 0 A; VCMS = VACP = VACN = VDCP = VDCN = 1.5 V) (cont'd) No. Parameter Symbol Mode Limit Values min. High Impedance on RING, High Impedance on TIP 36. 37. 38. 39. 40. typ. max. Unit VDD current VBATH current VBATL current VBATR current IDD IBATH IBATL IBATR Quiescent power dissipation PQ HIR, HIT HIR, HIT HIR, HIT HIR, HIT HIR, HIT - - - - - 700 0 0 3000 900 10 10 3900 A A A A 243.5 317.2 mW High Impedance on RING and TIP 41. 42. 43. 44. 45. 1) VDD current VBATH current VBATL current VBATR current IDD IBATH IBATL IBATR Quiescent power dissipation PQ HIRT HIRT HIRT HIRT HIRT - - - - - 500 0 0 2400 800 10 10 2900 A A A A 194.5 236.7 mW ROR and ROT for IR = IT = 0 and VTR = VBATR/2 Data Sheet 335 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.3.5 Power Calculation PEB 4266 (SLIC-P) The total power dissipation includes the quiescent power dissipation PQ given above, the current sensor power dissipation PI (see Table 77), the gain stage power dissipation correction PG1) (see Table 78), and the output stage power dissipation PO (see Table 79): Ptot = PQ + PI + PG + PO with PQ = VDD x IDD + IVBATRI x IBATR+ IVBATHI x IBATH + VBATL x IBATL For the calculation of PI, PG and PO see the following tables: Table 77 PDH PDRH, PDRHL PDRR, PDRRL ACTL ACTH ACTR ROR, ROT HIR, HIT HIRT PI Calculation PEB 4266 (SLIC-P) Equation for PI Calculation Operating Mode PI = 0 (no DC loop current) PI = ITrans x ITrans x (10000 + 500 + 24) + ITrans x (0.6 + 0.425 x |VBATH|) PI = ITrans x ITrans x (10000 + 500 + 16) + ITrans x (0.6 + 0.425 x |VBATR|) PI = 0.055 x ITrans x |VBATL| + 0.04 x ITrans x VDD PI = 0.055 x ITrans x |VBATH| + 0.04 x ITrans x VDD PI = 0.055 x ITrans x |VBATR| + 0.04 x ITrans x VDD PI = 0.055 x ITrans x |VBATR| + 0.04 x ITrans x VDD PI = 0.055 x ITorR x |VBATR| + 0.04 x ITorR x VDD PI = 0 (no DC loop current) 1) The gain stage power dissipation correction PG is a correcting term necessary to ensure a correct power calculation if other as the defined supply voltages are used. Data Sheet 336 2000-07-14 DuSLIC Preliminary Table 78 Electrical Characteristics PG Calculation PEB 4266 (SLIC-P) Equation for PG Calculation Operating Mode PDH, PDRH, PDRR ACTL ACTH, PDRHL ACTR, PDRRL, HIR, HIT, HIRT ROR, ROT PG = 0 (gain stage not working) PG = (VBATL2 - 242) x (1/60k + 1/216k) PG = (VBATH2 - 482) x (1/60k + 1/216k) PG = (VBATR2 - 802) x (1/60k + 1/216k) PG = (VTIP/RING2 - (VBATR/2)2)/60k + (VBATR2 - 802 x (1/60k + 1/216k) Table 79 PO Calculation PEB 4266 (SLIC-P) Equation for PO Calculation Operating Mode PDH, PDRH, PDRHL, PO = 0 (output stage not working) PDRR, PDRRL ACTL ACTH ACTR ROR, ROT HIR, HIT HIRT PO = (|VBATL| - VTIP/RING) x ITrans PO = (|VBATH| - VTIP/RING) x ITrans PO = (|VBATR| - VTIP/RING) x ITrans PO = (|VBATR| - VTIP/RING) x ITrans PO = VSupply-TorR x ITorR PO = 0 (output stage not working) 7.3.6 Power Up Sequence PEB 4266 (SLIC-P) The supply voltages of the SLIC-P have to be applied in the following order to the respective pin: 1) Ground to pins AGND and BGND 2) VDD to pin VDD 3) VBATR to pin VBATR 4) VBATH to pin VBATH and VBATL to pin VBATL If the VDD voltage is applied more than one second later as VBATR, VBATH or VBATL thermal damage of the SLIC-P can accur. If the above sequence of the battery voltages can not be guaranteed, a diode (1N4007) has to be inserted in the VBATR line. Data Sheet 337 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.4 Electrical Characteristics PEB 3265/PEB 3264/PEB 3264-2 (SLICOFI-2/-2S/-2S2) Absolute Maximum Ratings Symbol - Limit Values min. max. 4.6 V - -=0.3 Unit Test Condition 7.4.1 Parameter1) Supply pins (VDDi) referred to the corresponding ground pin (GNDi) Ground pins (GNDi) referred to - any other ground pin (GNDj) Supply pins (VDDi) referred to any other supply pin (VDDj) Analog input and output pins Digital input and output pins - - - -=0.3 -=0.3 -=0.3 -=0.3 - 0.3 0.3 3.6 5.5 100 V V V V mA - - VDDA = 3.3 V, VGNDA/B = 0 V VDDD = 3.3 V, VGNDD = 0 V - DC input and output current at - any input or output pin (free from latch-up) TSTG Ambient temperature under bias TA Power dissipation PD Storage temperature ESD voltage ESD voltage, all pins 1) 2) 3) - 65 - 40 - - - 125 85 1 2 1 C C W kV kV - - - Human body model2) SDM (Socketed Device Model)3) - - i, j = A, B, D, R, PLL MIL STD 883D, method 3015.7 and ESD Assn. standard S5.1-1993. EOS/ESD Assn. Standard DS5.3-1993. Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Functional operation under these conditions is not guaranteed. Exposure to conditions beyond those indicated in the recommended operational conditions of this specification may affect device reliability. Data Sheet 338 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.4.2 Operating Range VGNDD = VGNDPLL = VGNDR = VGNDA/B = 0 V Parameter Supply pins (VDDi) referred to the corresponding ground pin (GNDi) (i = A, B, D, R, PLL) Analog input pins referred to the ground pin (GNDj) (j = A, B) ITj, ILj, ITACj, VCMITj Analog output pins referred to the ground pin (GNDj) (j = A, B) ACPj, DCPj, ACNj, DCNj, VCMS, VCM C1, C2 Analog pins for passive devices to ground pin (GNDj) (j = A, B) CDCPj, CDCNj CREF Digital input and output pins Ambient temperature Symbol Limit Values min. 3.135 typ. 3.3 max. 3.465 V Unit Test Condition 0 - 3.3 V VDDj = 3.3 V VGNDj = 0 V VDDj = 3.3 V VGNDj = 0 V 0.3 1.3 0 - - - 2.7 1.7 3.3 V V V VDDj = 3.3 V VGNDj = 0 V 0 1.3 0 - - - - 3.3 1.7 5 + 85 V V V TA - 40 C Data Sheet 339 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.4.3 Power Dissipation PEB 3265 (SLICOFI-2) TA = - 40 C to 85 C, unless otherwise stated. VDDD = VDDA = VDDB = VDDR = VDDPLL = 3.3 V 5 %; VGNDA = VGNDB = VGNDR = VGNDD = VGNDPLL = 0 V Parameter Symbol Limit Values min. typ. max. 7 30 46 50 55 70 90 25 104 160 174 191 243 315 mA mA mA mA mA mA mA mW mW mW mW mW mW mW (MCLK, PCLK = 2 MHz) - without EDSP2) with 8 MIPS (DTMF detection) with 16 MIPS without EDSP with 32 MIPS (MCLK, PCLK = 2 MHz) - without EDSP with 8 MIPS (DTMF detection) with 16 MIPS without EDSP with 32 MIPS Unit Test Condition VDD supply current 1) Sleep both channels Power Down both channels Active one channel IDDSleep - IDDPDown - IDDAct1 - - - 5 24 39 43 47 55 70 17 79 129 142 155 182 231 Active both channels Power dissipation1) Sleep both channels Power Down both channels Active one channel IDDAct2 - - PDDSleep - PDDPDown - PDDAct1 - - - Active both channels 1) 2) PDDAct2 - - Power dissipation and supply currents are target values EDSP features are DTMF detection, Caller ID generation, Line Echo Cancellation (LEC) and Universal Tone Detection (UTD). Data Sheet 340 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.4.4 Power Dissipation PEB 3264, PEB 3264-2 (SLICOFI-2S/-2S2) TA = - 40 C to 85 C, unless otherwise stated. VDDD = VDDA = VDDB = VDDR = VDDPLL = 3.3 V 5 %; VGNDA = VGNDB = VGNDR = VGNDD = VGNDPLL = 0 V Parameter Symbol Limit Values min. typ. max. 30 46 70 104 160 243 mA mA mA mW mW mW - - Unit Test Condition VDD supply current 1) Power Down both channels Active one channel Active both channels Power dissipation1) Power Down both channels Active one channel Active both channels 1) IDDPDown - IDDAct1 IDDAct2 - - 24 39 55 79 129 182 PDDPDown - PDDAct1 PDDAct2 - - Power dissipation and supply currents are target values 7.4.5 Power Up Sequence for Supply Voltages The power up of VDDA, VDDB, VDDR, VDDD and VDDPLL should be performed simultaneously. No voltage should be supplied to any input or output pin before the VDD voltages are applied. Data Sheet 341 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.4.6 Digital Interface TA = - 40 to + 85 C, unless otherwise stated. VDD = VDDD = VDDA/B = 3.3 V 5%; VGNDD = VGNDA/B = 0 V Parameter For all input pins (including IO pins): Symbol Limit Values min. typ. max. Unit Test Condition VT+ High-input neg.-going VTInput hysteresis VH Spike rejection for reset trej Low-input pos.-going For all output pins except DU, DXA, DXB, IO1, IO2 (including IO pins): Low-output voltage High-output voltage for pins DU, DXA, DXB Low-output voltage High-output voltage for pins IO1, IO2 Low-output voltage - 1.13 0.48 1 1.70 1.20 0.5 - 1.82 - 0.56 4 V V V s see Figure 78 see Figure 78 VH = VT+ - VT- VOL VOH VOLDU VOHDU VOLDU VOLDU - 2.7 - 2.7 - - 2.7 0.35 3.0 0.35 3.0 0.35 0.35 3.0 0.4 - 0.4 - 0.4 0.4 - V V V V V V V IO = -=3.6 mA IO = 3.3 mA IO = -=6 mA IO = 5.3 mA IO = -=50 mA (PEB 3265) IO = -=30 mA (PEB 3264/-2) High-output voltage VOHDU VOUT IO = 3.3 mA V T- VT+ VIN ezm04122.emf Figure 78 Data Sheet Hysteresis for Input Pins 342 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.5 AC Transmission DuSLIC The target figures in this specification are based on the subscriber linecard requirements. The proper adjustment of the programmable filters (transhybrid balancing, impedance matching, frequency-response correction) requires the consideration of the complete analog environment of the SLICOFI-2x device. Functionality and performance is guaranteed for TA = 0 to 70 C by production testing. Extented temperature range operation at - 40 C < TA < 85 C is guaranteed by design, characterization and periodically sampling and testing production devices at the temperature extremes. Test Conditions TA = - 40 C to 85 C, unless otherwise stated. VDDD = VDDA = VDDB = VDDR = VDDPLL = 3.3 V 5%; VGNDA = VGNDB = VGNDR = VGNDD = VGNDPLL = 0 V RL > 600 ; CL < 10 pF LR = 0 ... - 10 dBr LX = 0 ... + 3 dBr f = 1014 Hz; 0 dBm0; A-Law or -Law; R STAB 30 tra n sm it (x) 0dBm 0 T IP 600 x r C STAB 1n R STAB 30 R IN G S LIC PEB 426x S LIC O F I-2 x P E B 3 2 6x 600 IOM(R)-2 PCM r 2*0.775V rm s x 0.775V rm s C STAB 1n re ce ive (r) 0dBm 0 ezm22018.emf Figure 79 Signal Definitions Transmit, Receive Note: To ensure the stability of the SLIC output buffer, RSTAB and CSTAB have to be set to the values RSTAB = 30 and CSTAB 300 pF (1 nF in the test circuit Figure 79). For electromagnetic compatibility CSTAB must be set to the much higher value of CSTAB = 15 nF (see Figure 98). Data Sheet 343 2000-07-14 DuSLIC Preliminary The 0 dBm0 definitions for Receive and Transmit are: A 0 dBm0 AC signal in Transmit direction is equivalent to 0.775 Vrms (referred to an impedance of 600 ). A 0 dBm0 AC signal in Receive direction is equivalent to 0.775 Vrms (referred to an impedance of 600 ). LR = - 10 dBr means: A signal of 0 dBm0 at the digital input correspond to -10 dBm at the analog interface. LX = + 3 dBr means: A signal of 3 dBm at the analog interface correspond to 0 dBm0 at the digital output. Table 80 Parameter Longitudinal current capability AC Overload level AC Transmission Symbol Conditions Limit Values min. typ. - - max. - - mArms 30 2.3 Unit Electrical Characteristics Ill VRT per active line 300 - 4000 Hz Vrms Transmission Performance (2-wire) Return loss RL 200 - 3600 Hz 26 - - dB Insertion Loss (2-wire to 4-wire and 4-wire to 2-wire) Gain accuracy - Transmit Gain accuracy - Receive Gain variation with temperature - 40 ... + 85 C GX GR - 0 dBm0, 1014 Hz 0 dBm0, 1014 Hz - - 0.25 - - 0.25 - - - + 0.25 dB + 0.25 dB 0.1 dB Data Sheet 344 2000-07-14 DuSLIC Preliminary Table 80 Parameter AC Transmission (cont'd) Symbol Conditions Limit Values min. Frequency Response (see Figure 81 and Figure 82) Receive loss Frequency variation GRAF Reference frequency 1014 Hz, signal level 0 dBm0, HFRR = 1 typ. max. Unit Electrical Characteristics f = 0 - 300 Hz f = 300 - 400 Hz f = 400 - 600 Hz f = 600 - 2400 Hz f = 2400 - 3000 Hz f = 3000 - 3400 Hz f = 3400 - 3600 Hz Transmit loss Frequency variation GXAF - 0.25 - - 0.25 - - 0.25 - - 0.25 - - 0.25 - - 0.25 - - 0.25 - - 0.9 0.65 0.25 0.45 1.4 - dB dB dB dB dB dB dB Reference frequency 1014 Hz, signal level 0 dBm0, HFRX= 1 f = 0 - 200 Hz f = 200 - 300 Hz f = 300 - 400 Hz f = 400 - 600 Hz f = 600 - 2400 Hz f = 2400 - 3000 Hz f = 3000 - 3400 Hz f = 3400 - 3600 Hz 0 - - - 0.9 0.65 0.25 0.45 1.4 - dB dB dB dB dB dB dB dB - 0.25 - - 0.25 - - 0.25 - - 0.25 - - 0.25 - - 0.25 - - 0.25 - Data Sheet 345 2000-07-14 DuSLIC Preliminary Table 80 Parameter AC Transmission (cont'd) Symbol Conditions Limit Values min. Gain Tracking (see Figure 83 and Figure 84) Transmit gain Signal level variation GXAL Sinusoidal test method f = 1014 Hz, reference level - 10 dBm0 VFXI = - 55 to - 50 dBm0 VFXI = - 50 to - 40 dBm0 VFXI = - 40 to + 3 dBm0 Receive gain Signal level variation GRAL - 1.4 - 0.5 - - 1.4 0.5 0.25 dB dB dB typ. max. Unit Electrical Characteristics - 0.25 - Sinusoidal test method f = 1014 Hz, reference level - 10 dBm0 DR0 = - 55 to - 50 dBm0 DR0 = - 50 to - 40 dBm0 DR0 = - 40 to + 3 dBm0 - 1.4 - 0.5 - - 1.4 0.5 0.25 - dB dB dB dB - 0.25 - 26 - Balance return loss Group Delay (see Figure 85) Transmit delay, absolute Receive delay, absolute DXA DRA 300 - 3400 Hz f = 500 - 2800 Hz f = 500 - 2800 Hz 400 290 490 380 585 475 s s Group delay, Receive DXR and Transmit, relative to 1500 Hz f = 500 - 600 Hz f = 600 - 1000 Hz f = 1000 - 2600 Hz f = 2600 - 2800 Hz f = 2800 - 3000 Hz - - - - - - - - - - - - - 300 150 100 150 300 - s s s s s - Overload compression OC A/D Data Sheet 346 2000-07-14 DuSLIC Preliminary Table 80 Parameter AC Transmission (cont'd) Symbol Conditions Limit Values min. Longitudinal Balance (according to ITU-T O.9) Longitudinal conversion loss L-T 300 - 1000 Hz DuSLIC-S/-E/-P DuSLIC-S2/-E2 3400 Hz DuSLIC-S/-E/-P DuSLIC-S2/-E2 300 - 1000 Hz DuSLIC-S/-E/-P DuSLIC-S2/-E2 3400 Hz DuSLIC-S/-E/-P DuSLIC-S2/-E2 300 - 4000 Hz 300 - 4000 Hz 53 60 52 56 53 60 52 56 46 46 58 65 55 59 58 65 55 59 - - - - - - - - - - - - dB dB dB dB dB dB dB dB dB dB typ. max. Unit Electrical Characteristics Input longitudinal interference loss L-4 Transversal to longitudinal Longitudinal signal generation T-L 4-L TTX Signal Generation TTX signal VTTX at 200 - - 2.5 Vrms Out-of-Band Noise (Single Frequency Inband - 25 dBm0) Transversal Longitudinal VRT VRT 12 kHz - 200 kHz 12 kHz - 200 kHz - - - 55 - 50 - 55 - 50 dBm dBm Out-of-Band Idle Channel Noise at Analog Output Measured with 3 kHz Bandwidth VRT VRT VRT VRT 10 kHz 300 kHz 500 kHz 1000 kHz - - - - - - - - - 50 - 50 - 70 - 70 dBm dBm dBm dBm Data Sheet 347 2000-07-14 DuSLIC Preliminary Table 80 Parameter AC Transmission (cont'd) Symbol Conditions Limit Values min. typ. max. Unit Electrical Characteristics Out-of-Band Signals at Analog Output (Receive) (see Figure 86) Out-of-Band Signals at Analog Input (Transmit) (see Figure 87) Total Harmonic Distortion 2-wire to 4-wire 4-wire to 2-wire Idle Channel Noise 2-wire port (receive) A-law NRP Psophometric TTX disabled TTX enabled C message TTX disabled TTX enabled Psophometric TTX disabled TTX enabled C message TTX disabled TTX enabled - - - - - - - - - - - - - - - - - 74 - 70 16 20 - 69 - 67 18 20 dBmp dBmp dBrnC dBrnC dBm0p dBm0p dBrnC dBrnC THD4 THD2 - 7 dBm0, 300 - 3400 Hz - 7 dBm0, 300 - 3400 Hz - - - 50 - 44 - 50 - 44 dB dB -law NRC PCM side (transmit) A-Law NTP -Law NTC Data Sheet 348 2000-07-14 DuSLIC Preliminary Table 80 Parameter AC Transmission (cont'd) Symbol Conditions Limit Values min. typ. max. Unit Electrical Characteristics Distortion (Sinusoidal Test Method, see Figure 89, Figure 88 and Figure 90) Signal to total distortion Transmit STDX Output connection: LX = 0 dBr f = 1014 Hz (C message-weighted for -law, psophometrically weighted for A-law) - 45 dBm0 - 40 dBm0 - 30 dBm0 - 20 dBm0 - 10 dBm0 3 dBm0 Signal to total distortion Receive STDR 22 27 34 36 36 36 - - - - - - - - - - - - dB dB dB dB dB dB Input connection: LR = - 7 dBr f = 1014 Hz (C message-weighted for -law, psophometrically weighted for A-law) - 45 dBm0 - 40 dBm0 - 30 dBm0 - 20 dBm0 - 10 dBm0 3 dBm0 17 22 31 35.5 36 36 - - - - - - - - - - - - dB dB dB dB dB dB Signal to total distortion Receive STDR Input connection: LR = 0 dBr f = 1014 Hz (C message-weighted for -law, psophometrically weighted for A-law) - 45 dBm0 - 40 dBm0 - 30 dBm0 - 20 dBm0 - 10 dBm0 3 dBm0 22 27 34 36 36 36 - - - - - - - - - - - - dB dB dB dB dB dB Data Sheet 349 2000-07-14 DuSLIC Preliminary Table 80 Parameter AC Transmission (cont'd) Symbol Conditions Limit Values min. Power Supply Rejection Ratio typ. max. Unit Electrical Characteristics VDD/VRT (SLIC) VDDi/VRT (SLICOFI-2x) i = A, B, D, R, PLL PSRR PSRR 300 - 3400 Hz ACTL, ACTH 300 - 3400 Hz ACTL, ACTH 300 - 3400 Hz 33 27 - - - - dB dB VBATH/VRT, VBATL/VRT (SLIC) PSRR 33 - - dB 9 8 7 6 4.5 4.2 5 4 3 2 Fundamental Output Power (dBm0) 1 0.25 0 -0.25 -1 3.4 0 1 2 3 4 5 6 7 8 9 Fundamental Input Power (dBm0) ezm14009.emf Figure 80 Overload Compression Data Sheet 350 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.5.1 dB Frequency Response 2 Attenuation 1.4 0.9 0.65 0.45 0.25 1 0 -0.25 x -1 0 .2 .3 .4 .6 1.0 2.0 2.4 3.0 3.4 3.6 Frequency kHz ezm00110.emf Figure 81 Frequency Response Transmit Reference frequency 1 kHz, signal level 0 dBm0, HFRX = 1 dB 2 Attenuation 1.4 0.9 0.65 0.45 0.25 1 0 -0.25 x -1 0 .3 .4 .6 1.0 2.0 2.4 3.0 3.4 3.6 Frequency kHz ezm00111.emf Figure 82 Frequency Response Receive Reference frequency 1 kHz, signal level 0 dBm0, HFRR = 1 Data Sheet 351 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.5.2 Gain Tracking (Receive or Transmit) The gain deviations stay within the limits in the figures below. dB G +2 + 1.4 +1 + 0.5 + 0.25 - 0.25 - 0.5 -1 - 1.4 -2 -70 -60 -55 -50 -40 -30 -20 Input level -10 0 3 10 dBm0 ezm00117.emf Figure 83 Gain Tracking Receive Measured with a sine wave of f = 1014 Hz, the reference level is - 10 dBm0. dB G +2 + 1.4 +1 + 0.5 + 0.25 - 0.25 - 0.5 -1 - 1.4 -2 -70 -60 -55 -50 -40 -30 -20 Input level -10 0 3 10 dBm0 ezm00118.emf Figure 84 Gain Tracking Transmit Measured with a sine wave of f = 1014 Hz, the reference level is - 10 dBm0. Data Sheet 352 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.5.3 Group Delay Minimum delays occure when the SLICOFI-2x is operating with disabled Frequency Response Receive and Transmit filters (bit FRR-DIS and bit FRX-DIS in register BCR4 set to 1) including the delay through A/D and D/A converters. Specific filter programming may cause additional group delays. Absolute Group delay also depends on the programmed time slot. Group delay distortion stays within the limits in the figures below. Table 81 Parameter Transmit delay Receive delay Group Delay Absolute Values: Signal level 0 dBm0 Symbol Limit Values min. typ. 490 380 max. 585 475 400 290 Unit Test Condition Fig. - - DXA DRA s s f = 1.5 kHz f = 1.5 kHz s TG 500 400 300 200 150 100 0 0 0.5 0.6 1 1.5 2 2.6 2.8 3 Frequency 3.5 4 kHz ezm00112.emf Figure 85 Group Delay Distortion Receive and Transmit Signal level 0 dBm0 Data Sheet 353 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.5.4 Out-of-Band Signals at Analog Output (Receive) With a 0 dBm0 sine wave with a frequency of f (300 Hz to 3.4 kHz) applied to the digital input, the level of any resulting out-of-band signal at the analog output will stay at least X dB below a 0 dBm0, 1 kHz sine wave reference signal at the analog output. 45 dB 40 35 30 Receive Out-of-Band Discrimination X 28 25 20 15 10 5 0 0 0.06 0.1 3.4 4.0 4.6 6.0 10.0 18.0 200 f kHz 3.4 ... 4.6 kHz: Figure 86 4000 - f X = - 14 ae sin ae -------------------- o - 1o e e 1200 itd09762.emf Out-of-Band Signals at Analog Output (Receive) Data Sheet 354 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.5.5 Out-of-Band Signals at Analog Input (Transmit) With a 0 dBm0 out-of-band sine wave signal with a frequency of f (< 100 Hz or 3.4 kHz to 100 kHz) applied to the analog input, the level of any resulting frequency component at the digital output will stay at least X dB below a 0 dBm0, 1 kHz sine wave reference signal at the analog input.1) dB 40 35 32 30 25 20 15 10 Transmit Out-of-Band Discrimination X 0 0 0.06 0.1 3.4 4.0 4.6 6.0 10.0 18.0 100 kHz f 3.4 ... 4.0 kHz: 4.0 ... 4.6 kHz: Figure 87 4000 - f X = - 14 ae sin ae --------------------o - 1o e e 1200 4000 - f 7 X = - 18 ae sin ae --------------------o - -- o e e 1200 9 itd09763.emf Out-of-Band Signals at Analog Input (Transmit) 1) Poles at 12 kHz 150 Hz and 16 kHz 150 Hz respectively and harmonics will be provided Data Sheet 355 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.5.6 Total Distortion Measured with Sine Wave The signal to total distortion ratio exceeds the limits in the following figure: dB S/D 40 36 34 30 27 22 20 10 0 -60 -50 -45 -40 -30 -20 -10 0 3 Input level dBm0 ezm00120.emf Figure 88 Total Distortion Transmit (LX = 0 dBr) Measured with a sine wave of f = 1014 Hz (C message-weighted for-law, psophometrically weighted for A-law). dB 40 35,5 31 36 S/D 30 22 20 17 10 0 -60 -50 -45 -40 -30 -20 -10 0 3 Input level dBm0 ezm00119.emf Figure 89 Total Distortion Receive (LR = - 7 dBr) Measured with a sine wave of f = 1014 Hz (C message-weighted for -law, psophometrically weighted for A-law). Data Sheet 356 2000-07-14 DuSLIC Preliminary Electrical Characteristics dB S/D 40 36 34 30 27 22 20 10 0 -60 -50 -45 -40 -30 -20 -10 0 3 Input level dBm0 ezm00120.emf Figure 90 Total Distortion Receive (LR = 0 dBr) Measured with a sine wave of f = 1014 Hz (C message-weighted for -law, psophometrically weighted for A-law). Data Sheet 357 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.6 Table 82 Parameter DC Characteristics DC Characteristics Symbol Conditions Limit Values min. typ. max. Unit TA = - 40 C to 85 C, unless otherwise stated. Line Termination Tip, Ring Sinusoidal Ringing Max. ringing voltage VRNG0 VHR - VBATH = 150 V, 85 VDC = 20 V for ring trip (DuSLIC-E/-E2) 85 - VBATR = 150 V, VDC = 20 V for ring trip (DuSLIC-P) VHR - VBATH = 90 V, 45 VDC = 20 V for ring trip (DuSLIC-S/-S2) - - Vrms Vrms - - Vrms Output impedance Harmonic distortion Output current limit ROUT THD SLIC output buffer and - 61 - - 105 90 - - 5 130 110 3 % mA mA % RSTAB - - 80 70 - - 0.75 5 5 - |IR, max.|, Modes: Active |IT, max.| SLIC-E/-E2/-S/-S2: SLIC-P: - - - - Loop current gain accuracy Loop current offset error1) Loop open resistance TIP to VBGND Loop open resistance RING to VBAT Ring trip function Ring trip DC voltage 0.75 mA - - - k k - Vdc Vdc Vdc RTG RBG - - Modes: Power Down - IT = 2 mA, TA = 25 C Modes: Power Down - IR = 2 mA, TA = 25 C - SLIC-E/-E2/-S/-S2: SLIC-P: balanced SLIC-P: unbalanced - 0 0 - 30 30 VBATR/2 - Data Sheet 358 2000-07-14 DuSLIC Preliminary Table 82 Parameter DC Characteristics (cont'd) Symbol Conditions - - Limit Values min. Ring trip detection time - delay Ring off time delay 1) Electrical Characteristics Unit max. 2 2 periods periods typ. - - - - - can be reduced with current offset error compensation described in Chapter 4.8.2.8 Data Sheet 359 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.7 DuSLIC Timing Characteristics TA = - 40 C to 85 C, unless otherwise stated. 7.7.1 MCLK/FSC Timing t MCLK MCLK 50% t MCLKh t FSC t FSC_S FSC t FSC_H ezm35000.emf Figure 91 Parameter MCLK / FSC-Timing Symbol min. 1) Limit Values typ. 1953.13 651.04 488.28 244.141 139.509 122.070 0.5 x tMCLK 125 50 50 max. Unit ns Period MCLK 512 kHz 100 ppM 1536 kHz 100 ppM 2048 kHz 100 ppM 4096 kHz 100 ppM 7168 kHz 100 ppM 8192 kHz 100 ppM MCLK high time Period FSC1) FSC setup time FSC hold time FSC (or PCM) jitter time 1) tMCLK 1952.93 650.98 488.23 244.116 139.495 122.058 1953.32 651.11 488.33 244.165 139.523 122.082 0.6 x tMCLK - - - + 0.2 x tMCLK tMCLKh tFSC tFSC_s tFSC_h 0.4 x tMCLK - 10 40 - 0.2 x tMCLK s s ns ns ns The MCLK frequency must be an integer multiple of the FSC frequency. Data Sheet 360 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.7.2 7.7.2.1 PCM Interface Timing Single-Clocking Mode t PCLK t PCLKh PCLK 50% t FSC t FSC_S FSC t DR_S t DR_H DRA/B t dDX t dDXhz High Imp. DXA/B t dTCon t dTCoff t FSC_H TCA/B ezm22013.wmf Figure 92 Parameter Period PCLK PCM Interface Timing - Single-Clocking Mode Symbol min. 1) Limit Values typ. max. 1/8192 0.4 x tPCLK - 10 40 10 10 25 1/(n*64) with 1/128 2 n 128 0.5 x tPCLK 125 50 50 50 50 - 0.6 x tPCLK - - - - - tdDX_min + 0.4 x CLoad[pF] Unit ms tPCLK tPCLKh tFSC tFSC_s tFSC_h tDR_s tDR_h tdDX PCLK high time Period FSC1) FSC setup time FSC hold time DRA/B setup time DRA/B hold time DXA/B delay time2) s s ns ns ns ns ns Data Sheet 361 2000-07-14 DuSLIC Preliminary Parameter DXA/B delay time to high Z TCA/B delay time on Symbol min. Electrical Characteristics Limit Values typ. - - - max. 50 tdTCon_min + 0.4 x CLoad[pF] tdTCoff_min + (RPullup[k] x CLoad[pF]) ns ns ns 25 25 25 Unit tdDXhz tdTCon tdTCoff TCA/B delay time off 1) 2) The PCLK frequency must be an integer multiple of the FSC frequency. All delay times are made up by two components: an intrinsic time (min-time), caused by internal processings, and a second component caused by external circuitry (CLoad, RPullup > 1.5 k) 7.7.2.2 Double-Clocking Mode t PCLK PCLK 50% t PCLKh t FSC t FSC_S FSC t DR_S t DR_H t FSC_H DRA/B t dDX t dDXhz High Imp. DXA/B t dTCon t dDTCoff TCA/B ezm22014.wmf Figure 93 PCM Interface Timing - Double-Clocking Mode Data Sheet 362 2000-07-14 DuSLIC Preliminary Parameter Symbol min. Period PCLK1) PCLK high time Period FSC1) FSC setup time FSC hold time DRA/B setup time DRA/B hold time DXA/B delay time2) DXA/B delay time to high Z TCA/B delay time on Electrical Characteristics Limit Values typ. max. ms 1/8192 0.4 x tPCLK - 10 40 10 10 25 25 25 25 1/(n*64) with 1/256 2 n 64 0.5 x tPCLK 125 50 50 50 50 - - - - 0.6 x tPCLK - - - - - tdDX_min + 0.4 x CLoad[pF] 50 tdTCon_min + 0.4 x CLoad[pF] tdTCoff_min + (RPullup[k] x CLoad[pF]) Unit tPCLK tPCLKh tFSC tFSC_s tFSC_h tDR_s tDR_h tdDX tdDXhz tdTCon tdTCoff s s ns ns ns ns ns ns ns ns TCA/B delay time off 1) 2) The PCLK frequency must be an integer multiple of the FSC frequency. All delay times are made up by two components: an intrinsic time (min-time), caused by internal processings, and a second component caused by external circuitry (CLoad, RPullup > 1.5 k) Data Sheet 363 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.7.3 Microcontroller Interface Timing t DCLK DCLK 50% t DCLKh t CS_S t CS_h CS t DIN_S t DIN_H DIN t dDOUT t dDOUThz High Imp. DOUT ezm22015.wmf Figure 94 Parameter Period DCLK Microcontroller Interface Timing Symbol min. Limit Values typ. - 0.5 x max. - - - - - - tdDOUT_min + 0.4 x CLoad[pF] 50 ms 1/8192 - 10 30 10 10 30 30 Unit DCLK high time CS setup time CS hold time DIN setup time DIN hold time DOUT delay time1) DOUT delay time to high Z 1) tDCLK tDCLKh tCS_s tCS_h tDIN_s tDIN_h tdDOUT tdDOUThz s ns ns ns ns ns ns tDCLK 50 50 50 50 - - All delay times are made up by two components: an intrinsic time (min-time), caused by internal processings, and a second component caused by external circuitry (CLoad) Data Sheet 364 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.7.4 7.7.4.1 IOM-2 Interface Timing Single-Clocking Mode t DCL t DCLh DCL 50% t FSC t FSC_S FSC t DD_S t DD_H DD t dDU t dDUhz High Imp. DU ezm22016.wmf t FSC_H Figure 95 Parameter Period DCL 1) IOM-2 Interface Timing - Single-Clocking Mode Symbol min. Limit Values typ. 1/2048 0.5 x tDCL 125 50 50 50 50 - - max. - 0.6 x tDCL - - - - - tdDX_min + 0.4 x CLoad[pF] 50 ms - 0.4 x tDCL - 10 40 10 10 25 25 Unit DCL high time Period FSC1) FSC setup time FSC hold time DD setup time DD hold time DU delay time2) tDCL tDCLh tFSC tFSC_s tFSC_h tDD_s tDD_h tdDX s s ns ns ns ns ns ns DU delay time to high Z tdDXhz 1) 2) The DCL frequency must be an integer multiple of the FSC frequency. All delay times are made up by two components: an intrinsic time (min-time), caused by internal processings, and a second component caused by external circuitry (CLoad, RPullup > 1.5 k) Data Sheet 365 2000-07-14 DuSLIC Preliminary Electrical Characteristics 7.7.4.2 Double-Clocking Mode t DCLh t DCL DCL 50% t FSC t FSC_S FSC t DD_S t DD_H t FSC_H DD t dDU t dDUhz High Imp. DU ezm22017.wmf Figure 96 Parameter Period DCL1) IOM-2 Interface Timing - Double-Clocking Mode Symbol min. Limit Values typ. 1/4096 0.5 x tDCL 125 50 50 50 50 - - max. - 0.6 x tDCL - - - - - tdDX_min + 0.4 x CLoad[pF] 50 ms - 0.4 x tDCL - 10 40 10 10 25 25 Unit DCL high time Period FSC1) FSC setup time FSC hold time DD setup time DD hold time DU delay time2) tDCL tDCLh tFSC tFSC_s tFSC_h tDD_s tDD_h tdDX s s ns ns ns ns ns ns DU delay time to high Z tdDXhz 1) 2) The DCL frequency must be an integer multiple of the FSC frequency. All delay times are made up by two components: an intrinsic time (min-time), caused by internal processings, and a second component caused by external circuitry (CLoad, RPullup > 1.5 k) Data Sheet 366 2000-07-14 DuSLIC Preliminary Application Circuits 8 Application Circuits Application circuits are shown for internal ringing with DuSLIC-E/-E2/-S/-P (balanced and unbalanced) and for external unbalanced ringing with DuSLIC-E/-E2/-S/-S2/-P for one line. Channel A and the SLIC have to be duplicated in the circuit diagrams to show all components for 2 channels. 8.1 Internal Ringing (Balanced/Unbalanced) Internal balanced ringing is supported up to 85 Vrms for DuSLIC-E/-E2/-P and up to 45 Vrms for DuSLIC-S. Internal unbalanced ringing is supported for SLIC-P with ringing amplitudes up to 50 Vrms without any additional external components. Off-hook detection and ring trip detection are also fully internal in the DuSLIC chip set. Data Sheet 367 2000-07-14 DuSLIC Preliminary Application Circuits 8.1.1 Circuit Diagram Internal Ringing VH VCCS V BATH V BATL V C CA V C CA V CC A V C CA C1 C1 C1 C1 C1 C1 C1 C1 BG N D VHR AGND V DD V BATH BGND V B A TL BGND AG N D VDDA AGND V DD R VDDD AGND V DD PLL S E LC LK AGND ACP AC N DCP DCN C1 C2 AC P A AC N A DCPA DCNA C 1A C 2A IO 2A CDC CDCNA Channel A PC M /IO M -2 FS C D C L /PC LK D D /D R B D U /D O U T TS0 /D IN TS 1/D C LK TS2 /C S IN T M C LK AG N D * TIP CSTAB RSTAB C3 CITACA IT CDCPA ITAC A SE L24 /D R A D XA D XB TC A Protection CSTAB BG N D RIT1A ITA TC B RIT2A R IN G CVCMITA VC M ITA RILA IL ILA R SY N C R E SE T TES T AG N D IO 4B IO 3B VC M VCMS VC M S CREF GNDR C EX T CEXT GNDA AGND RSTAB SLIC-E/-E2 SLIC-S SLIC-P P EB 4265/-2 PE B 4264 PE B 4266 BG N D AGND CREF SLIC OFI-2 SLICOFI-2S (Channel A, B) IO 2B IO 1B IO 4A IO 3A PE B 3265 PE B 3264 GNDD IO 2A IO 1A G N D P LL * optiona l for S L IC -P BGND AGND AG N D AG N D AGND AGND AG N D ezm14042.emf Figure 97 Application Circuit, Internal Ringing (Balanced & Unbalanced) As sown in Figure 97 both balanced and unbalanced internal ringing uses the same line circuit. Note: Only the codec/SLIC combinations shown in Table 1 "DuSLIC Chip Sets" on Page 16 are possible. Data Sheet 368 2000-07-14 DuSLIC Preliminary Application Circuits 8.1.2 Protection Circuit for SLIC-E/-E2 and SLIC-S A typical overvoltage protection circuit for SLIC-E/S is shown in Figure 98. Other proved application schemes are available on request. . VHR RPROT 20 Ohm fuseable resistor TIP 30 Ohm CSTAB Tip Gp CP Gn LCP02 GND Ring CP SLIC-E/-E2 PEB 4265/-2 CSTAB SLIC-S PEB 4264 30 Ohm RING RPROT 20 Ohm fuseable resistor VBATH ezm14070.emf Figure 98 Typical Overvoltage Protection for SLIC-E/-E2 and SLIC-S The LCP02 (from STM) protects against overvoltage strikes exceeding VHR and VBATH. Protection resistors must be rated for lightning pulses. In case of power contact, protection resistors must become high impedance or additional fuses are needed. Data Sheet 369 2000-07-14 DuSLIC Preliminary Application Circuits 8.1.3 Protection Circuit for SLIC-P A typical protection circuit for SLIC-P is shown in Figure 99. Other proved application schemes are available on request. Protection RPROT 20Ohm fusable resistor RSTAB 30Ohm TIP B1160CC BGND CSTAB 15nF MB2S BGND CSTAB 15nF SLIC-P PEB 4266 RING RPROT 20Ohm fusable resistor RSTAB 30Ohm VBATR ezm14048.emf Figure 99 Typical Overvoltage Protection for SLIC-P The gate trigger voltage of the Battrax B1160CC (Teccor) can be set down to the battery voltage of VBATR (- 150 V). Protection resistors must be rated for lightning pulses. In case of power contact, protection resistors must become high impedance or additional fuses are needed. Data Sheet 370 2000-07-14 DuSLIC Preliminary Application Circuits 8.1.4 Bill of Materials (Including Protection) Table 83 shows the external passive components needed for a dual channel solution consisting of one SLICOFI-2/-2S and two SLIC-E/-E2/-S/-P. Table 83 No. Symbol 2 2 2 4 4 4 2 2 2 1 2 12 2 External Components in Application Circuit for DuSLIC-E/-E2/-S/-P Value 470 680 1.6 30 20 15 120 680 680 68 470 100 Unit Tolerance Rating 1% 1% 1% 0.1 % 0.1 % 10 % 10 % 10 % 10 % 20 % 20 % 10 % - according to supply voltage VBATR see 1) 10 V 10 V 10 V 10 V 10 V DuSLIC DuSLIC -E/-E2/-S -P x x x x x x x x x x x x x x x x x x x x x x x x x RIT1 RIT2 RIL RSTAB RPROT CSTAB CDC k nF nF nF nF nF nF nF CITAC CVCMIT CREF CEXT C1 Battrax B1160CC - 2 2 4 Diodebridge STM MB2S LCP-02 220 nF 20 % x according to x supply voltage VBATH and VHR x CP 1) according to the highest used battery voltage IVBATRI for SLIC-P and IVHRI or IVBATHI for SLIC-E/-E2/-S For handling higher electromagnetic compatibility (EMC) requirements, additional effort in the circuit design may be necessary, e.g., a current-compensated choke of 470 H in the Ring/Tip lines. Additionally to the capacitors C1 a 22 F capacitor per 8 Ring/Tip lines is recommended for buffering the supply voltages. Data Sheet 371 2000-07-14 DuSLIC Preliminary Application Circuits 8.2 External Unbalanced Ringing with DuSLIC-E/-E2/-S/-S2/-P External unbalanced ringing applications are shown for a standard solution (see Figure 100) and for a solution dedicated to higher loop lenghts (see Figure 101). Note: Only the codec/SLIC combinations shown in Table 1 "DuSLIC Chip Sets" on Page 16 are possible. VCCS V B ATH V B ATL VCCA VCCA VCCA VCCA C1 C2 C2 C1 C1 C1 C1 AGND VHR RSYNC / SLICOFI-2 BGND V B ATH V BA TL BGND AGND VDDA AGND VDDR VDDD AGND V D D P LL AGND VDD External Ring Generator SELCLK ACP ACN DCP DCN C1 C2 ACPA ACNA DCPA DCNA C 1A C 2A IO 2 A CDC TIP R STAB CSTAB P C M /IO M -2 FS C Channel A D C L /P C L K D D /D R B D U /D O U T TS 0 /D IN TS 1 /D C L K T S 2/C S IN T AGND * C3 CDCNA CITACA IT CDCPA IT AC A MCLK S E L2 4 /D R A DXA DXB Protection CSTAB BGND RIT1A IT A RIT2A R IN G R STAB TCA TCB CVCMITA V C M ITA RSYNC RESET TEST AGND RILA IL IL A + 5V 1N4148 IO 4 B IO 3 B 1N4148 SLIC-E /-E2 SLIC-S /-S2 SLIC-P PEB 4265/-2 PEB 4264/-2 PEB 4266 BGND AGND VCM VCM S S LICO FI-2 IO 2 B SLICO FI-2S/-2S2IO 1 B (C hannel A, B ) P EB 3265 P EB 3264/-2 GNDD IO 4 A IO 3 A IO 2 A IO 1 A G N D PL L CREF VCMS CREF GNDR CEXT CEXT GNDA * optional for SLIC-P BGND AGND AGND AGND AGND AGND AGND ezm14044.emf Figure 100 Application Circuit, External Unbalanced Ringing This circuit senses the ring current on only one line (Tip line). It is therefore restricted to applications with low longitudinal influence (short lines). Data Sheet 372 2000-07-14 DuSLIC Preliminary Application Circuits 5V VB ATH V BA TL VCCA VCCA VCCA VCCA C1 C2 C2 C1 C1 C1 C1 AG N D VHR VDD VB ATH B G ND VB ATL BG N D A G ND V DD A AGND V D DR VDDD AG N D V D D P LL AGND AC P AC N DC P DCN C1 C2 A CP A A CN A D CP A D CN A C 1A C 2A IO 2 CDC C DC N A S ELC LK P CM /IO M -2 F SC Ch annel A D CL/P C LK DD /D R B D U/D O U T TS 0/DIN T S1/D C LK TS 2/C S A G ND * C3 TIP TIP RPROT CSTAB RSTAB CITACA IT RIT1A CSTAB BG N D RIT2A RIN G RPROT RSTAB + 5V IL CVCMITA C DC P A ITA C A IN T M C LK S EL24/D R A D XA Protection ITA D XB T CA T CB V CM IT A RILA ILA RING RS YN C R ES ET TE ST IO 4B A G ND 1N4148 Relay 1N4148 SLIC-E/-E2 SLIC-S/-S2 SLIC-P PEB 4265/-2 PEB 4264/-2 P EB 4266 VC M S CREF SLICO FI-2 IO 3B SLICOFI-2S/-2S2IO 2B V CM S (Channel A, B) IO 1B V CM C RE F G N DR 150 P EB 3265 PEB 3264/-2 GNDD IO 4A IO 3A IO 1A 2M 2M 68k BG N D AG N D C EX T CEXT G N DA Ring Generator -48 VDC 80VRMS 2M 2M G ND P LL - LM358 + 68k IO 3A or IO 4A of S LICO F I-2/-2S/-2S 2 BGND AG N D A G ND AGND A G ND AGND A G ND VC M S/S LIC O F I-2/-2S /-2S2 150 zero crossing signal (T TL level) R SY N C/S LIC O F I-2/-2S /-2S2 * optional for SLIC-P ezm35003.emf Figure 101 Application Circuit, External Unbalanced Ringing for Long Loops For handling higher electromagnetic compatibility (EMC) requirements, additional effort in the circuit design may be necessary, e.g., a current-compensated choke of 470 H in the Ring/Tip lines. This circuit senses the ring current in both Tip and Ring lines. Longitudinal influence is cancelled out. This circuit therefore is recommended for long line applications. Data Sheet 373 2000-07-14 DuSLIC Preliminary Application Circuits 8.3 DuSLIC Layout Recommendation * For each of the supply pins of SLICOFI-2x and SLIC, 100 nF capacitors should be used. These capacitors should be placed as close as possible to the supply pin of the associated ground/supply pins * SLICOFI-2x and SLIC should be placed as close to each other as possible. * SLICOFI-2x and SLIC should be placed in such way that lines ACP, ACN, DCP, DCN, IT, ITAC are as short as possible * ACP/ACN lines should be placed parallel and symmetrical; via holes should be avoided ACP/ACN lines should be run above a GND plane; * DCP/DCN lines should be placed parallel and symmetrical; via holes should be avoided DCP/DCN lines should be run above a GND plane * VCMITA and VCM should be connected directly (VCMITA via CVCMITA) at resistor RIT2A (680 ) * VCMITB and VCM should be connected directly (VCMITB via CVCMITB) at resistor RIT2B (680 ) * Use separate traces for connecting VCM/VCMITA and VCM/VCMITB these two VCM traces should be connected directly at the VCM pin of SLICOFI-2x * In case of a multilayer board it is recommended to use one common ground layer (AGND, BGND, GNDD, GNDA, GNDB, GNDPLL connected together and share one ground layer) * In case of a two-layer board a common ground should be used for AGND, BGND, GNDD, GNDA, GNDB and GNDPLL. Ground traces should be layed out as large as possible. Connections to and from groud pins should be as short as possible. Any unused area of the board should be filled with ground (copper pouring) * The connection of GND, VH and VBAT to the protection devices should be lowimpedance in order to avoid, e.g., a GND shift due to the high impulse currents in case of an overvoltage strike. * Tip/ring traces from the SLIC should be symmetrical Data Sheet 374 2000-07-14 DuSLIC Preliminary Application Circuits Parallel/symmetrical as short as possible no via holes, should run above a GND plane ACNA ACPA DCNB DCPB IT A C A R IT 1 A R IT 2 A R IL A IT A V C M IT A C V C M IT A Connection directly at resistor S L IC A IL-A IT -A VCM C V C M IT B R IT 2 B R IT 1 B IT -B IL -B R IL B S L IC O F I-2 x Connection directly at SLICOFI-2 V C M IT B IT B IT A C B S L IC B ACNB ACPB DCPB DCNB Parallel/symmetrical as short as possible no via holes, should run above a GND plane layout_r.emf Figure 102 DuSLIC Layout Recommendation Data Sheet 375 2000-07-14 DuSLIC Preliminary Package Outlines 9 Package Outlines P-DSO-20-5 (Plastic Dual Small Outline) Top View Gps05755.eps Figure 103 PEB426x (SLIC-S/-S2, SLIC-E/-E2, SLIC-P) Note: The SLIC is only available in a P-DSO-20-5 package with heatsink on top. Please note that the pin counting for the P-DSO-20-5 package is clockwise (top view) in contrast to similar type packages which mostly count counterclockwise. Sorts of Packing Package outlines for tubes, trays etc. are contained in our data book "Package Information". SMD = Surface Mounted Device Data Sheet 376 Dimensions in mm 2000-07-14 DuSLIC Preliminary P-MQFP-64-1 (Plastic Metric Quad Flat Package) Package Outlines Top View Gpm05250.eps Figure 104 PEB 3264, PEB 3264-2, PEB 3265 (SLICOFI-2x) Sorts of Packing Package outlines for tubes, trays etc. are contained in our data book "Package Information". SMD = Surface Mounted Device Data Sheet 377 Dimensions in mm 2000-07-14 DuSLIC Preliminary Glossary 10 10.1 ACTL ACTH ACTR ADC AR AX BP CMP Codec COP CRAM DAC DSP DUP DuSLIC EXP FRR FRX LSSGR Glossary List of Abbreviations Active with VBATL and VBGND Active with VBATH and VBGND Active with VBATR and VGND or VHR and VBATH Analog Digital Converter Attenuation Receive Attenuation Transmit Band Pass Compander Coder Decoder Coefficient Operation Coefficient RAM Digital Analog Converter Digital Signal Processor Data Upstream Persistence Counter Dual Channel Subscriber Line Interface Concept Expander Frequency Response Receive Filter Frequency Response Transmit Filter Local area transport access Switching System Generic Requirements Pulse Code Modulation Power Down High Impedance 378 2000-07-14 PCM PDH Data Sheet DuSLIC Preliminary PDRHL PDRRL PDRH PDRR POFI PREFI RECT SLIC SLIC-S/-S2 SLIC-E/-E2 SLIC-P SLICOFI-2x SLICOFI-2 Power Down Load Resistive on VBATH and VBGND Power Down Load Resisitve on VBATR and VBGND Power Down Resistive on VBATH and VBGND Power Down Resistive on VBATR and VBGN Post Filter Antialiasing Pre Filter Rectifier (Testloops, Levelmetering) Subscriber Line Interface Circuit (synonym for all versions) Subscriber Line Interface Circuit Standard Feature Set PEB 4264/-2 Subscriber Line Interface Circuit Enhanced Feature Set PEB 4265/-2 Subscriber Line Interface Circuit Enhanced Power Management PEB 4266 Dual Channel Signal Processing Subscriber Line Interface Codec Filter (synonym for all versions) Dual Channel Signal Processing Subscriber Line Interface Codec Filter PEB 3265 Glossary SLICOFI-2S/-2S2 Dual Channel Signal Processing Subscriber Line Interface Codec Filter PEB 3264/-2 SOP TG TH THFIX TS TTX Status Operation Tone Generator Transhybrid Balancing Transhybrid Balancing Filter (fixed) Time Slot Teletax Data Sheet 379 2000-07-14 DuSLIC Preliminary Index POP Commands 228 Power Dissipation 340 External Components DuSLIC-P 371 External conference 75 External Ringing 31, 55, 107, 192, 289 11 Index 52 Numerics 170V technology A Active 93, 157, 160, 161 Active High 78, 80, 82, 84, 86 Active Low 78, 80, 82, 84, 86 Active Ring 78, 80, 82, 84, 87, 154, 157, 160 Active State 59, 95 Active with HIR 78, 81, 83, 85, 87 Active with HIT 78, 80, 83, 85, 87 Active with Metering 78, 81, 164, 262, 312 F Fiber in the Loop 22 First Command Byte 163, 264, 265, 314, 315 Frequency response 33, 345 FSK 34 G Ground Key 60, 175, 275 Ground Start 81 B Balanced ringing 53, 367 Battery feed 33 H Hybrid 33 Hybrid balance 33 C Caller ID 19, 34, 66, 71, 180 Central Office 22 Coding 33 Constant Current Zone 42 Constant Voltage Zone 44 COP-command 164, 165, 224, 308 CRAM coefficients 226, 310 I Impedance matching 33, 51 Intelligent NT 22 Internal conference 75 IOM-2 interface 29, 138, 145, 262, 265, 312, 315 ISDN Terminal Adapters 22 D DC characteristic 45 Digital Loop Carrier 22 DTMF 34, 71, 178, 198, 200, 228, 294 DTMF decoder 19, 34 DTMF generator 19, 34, 63 DuSLICOS 33, 224, 308 L Layout Recommendation 374 Levelmeter AC 117 DC 112 TTX 121 LIN mode 77 LIN16 mode 77 Line Echo Cancellation 34, 69, 71, 199 POP Commands 239 Line Resistance 102, 125 Line Testing 107 E Enhanced Digital Signal Processor 174, 180 MIPS Requirements 71 63, Data Sheet 380 2000-07-14 DuSLIC Preliminary Index SLIC-P 333 SLIC-S/-S2 320 Power Down 93, 164, 190, 262, 312 Power Down High Impedance 78, 80, 156, 159, 160, 164, 193, 262, 290, 312 Power Down Resistive 78, 80, 82, 84, 86, 153, 156, 159, 160 Power Down state 60, 75, 95, 154, 160, 161, 218, 220, 302, 304 Power Management 17, 19, 80, 93 Private Branch Exchange 22 M Message waiting 19, 72 Metering 19, 61, 202, 204, 206, 296, 297 Microcontroller interface 138, 143 Monitor Channel Operation 148 Monitor Receiver 151 Monitor Transfer Protocol 148 Monitor Transmitter 150 O Operating Modes CIDD byte SLICOFI-2 262 CIDD byte SLICOFI-2S/-2S2 CIOP byte 164 DuSLIC 78 DuSLIC-E/-E2 84 DuSLIC-P 86 DuSLIC-S/-S2 82 Power Management 93 SLIC-E 156 SLIC-P 159 SLIC-S 153 Overvoltage protection 33 312 R Ramp generator 72, 83, 85, 87 Read command 143 Receive gain 33 Receive path 50, 199, 218, 220, 222, 302, 304, 306 Register Description Example 165 Reset 88, 164 Status 177, 277 Resistive Zone 43 Ring on Ring 80, 160 Ring on Tip 80, 160 Ring Pause 79, 81, 83, 85, 87 Ring Trip 52, 81, 358 Ringer Equivalence Number 52 Ringing 33, 52, 78, 80, 82, 85, 87, 94, 160, 164, 262, 312 P PCM channel 142 PCM interface 30, 50, 138, 173, 176, 273, 276, 361 PCM mode 76, 92, 210, 214, 298, 300 PCM/C interface 76, 138, 194, 291 PCM16 mode 77 PCM-active 75 PCM-off 75 Polarity Reversal 19, 62 POP command 165, 228 Power Dissipation Operating Modes 93 SLIC 95 SLIC output stage 46 SLIC-E/-E2 326 SLICOFI-2 94, 340 SLICOFI-2/-2S2 341 S Second Command Byte 143, 165, 264, 265, 314, 315 Signaling 33, 59, 65, 265, 315 Sleep 78, 79, 84, 86, 164, 262, 312, 340 SLIC Interface 153, 156 Soft reversal 62, 192, 289 SOP-command 164, 167, 267 Supervision 33, 59 T Teletax Metering 34 2000-07-14 Data Sheet 381 DuSLIC Index Test Loops 132 Three-party Conferencing 74, 194 Time Slot Assignment 50, 147 TIP/RING interface 138, 152 Transmit gain 33, 346 Transmit path 50, 199, 218, 220, 222, 302, 304, 306 TTX 33, 61, 81, 192, 220, 225, 304, 309 U Unbalanced ringing 53, 94, 190, 287 Universal Tone Detection 34, 70, 71, 179, 193 POP Commands 253 Universal Tone detection 198 V Voice over IP 22 Voltage reserve 41, 47 W Wireless Local Loop 22 Write command 143 Data Sheet 382 2000-07-14 Infineon goes for Business Excellence "Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction." Dr. Ulrich Schumacher http://www.infineon.com Published by Infineon Technologies AG |
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