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INTEGRATED CIRCUITS
74LV74 Dual D-type flip-flop with set and reset; positive-edge trigger
Product specification Supersedes data of 1996 Nov 07 IC24 Data Handbook 1998 Apr 20
Philips Semiconductors
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive edge-trigger
74LV74
FEATURES
* Wide operating voltage: 1.0 to 5.5V * Optimized for Low Voltage applications: 1.0 to 3.6V * Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V * Typical VOLP (output ground bounce) t 0.8V @ VCC = 3.3V, * Typical VOHV (output VOH undershoot) u 2V @ VCC = 3.3V, * Output capability: standard * ICC category: flip-flops
QUICK REFERENCE DATA
GND = 0V; Tamb = 25C; tr =tf v2.5 ns SYMBOL PARAMETER tPHL/tPLH Propagation delay nCP to nQ, nQ nSD to nQ, nQ nRD to nQ, nQ Maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop Tamb = 25C Tamb = 25C
DESCRIPTION
The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. The 74LV74 is a dual positive edge triggered, D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
CONDITIONS CL = 15pF VCC = 3.3V CL = 15pF VCC = 3.3V Notes 1 and 2
TYPICAL 11 14 14 76 3.5 24
UNIT ns
fmax CI CPD
MHz pF pF
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W) VCC2 x fi )S (CL VCC2 fo) where: PD = CPD fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; VCC2 fo) = sum of the outputs. S (CL 2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES 14-Pin Plastic DIL 14-Pin Plastic SO 14-Pin Plastic SSOP Type II 14-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +125C -40C to +125C -40C to +125C -40C to +125C OUTSIDE NORTH AMERICA 74LV74 N 74LV74 D 74LV74 DB 74LV74 PW NORTH AMERICA 74LV74 N 74LV74 D 74LV74 DB 74LV74PW DH PKG. DWG. # SOT27-1 SOT108-1 SOT337-1 SOT402-1
PIN DESCRIPTION
PIN NUMBER 1, 13 2, 12 3, 11 4, 10 5, 9 6, 8 7 14 SYMBOL 1RD, 2RD 1D, 2D 1CP, 2CP 1SD, 2SD 1Q, 2Q 1Q, 2Q GND VCC FUNCTION Asynchronous reset-direct input (active-LOW) Data inputs Clock input (LOW-to-HIGH), edge-triggered) Asynchronous set-direct input (active-LOW) True flip-flop outputs Complement flip-flop outputs Ground (0V) Positive supply voltage
FUNCTION TABLE INPUTS SD RD CP L H X H L X L L X
INPUTS SD H H
H L X Qn+1 2 = = = = =
OUTPUTS D X X X D L H Q H L H Qn+1 L H Q L H H Qn+1 H L
OUTPUTS
RD H H
CP
HIGH voltage level LOW voltage level don't care LOW-to-HIGH CP transition state after the next LOW-to-HIGH CP transition
1998 Apr 20
853-1888 19258
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive edge-trigger
74LV74
PIN CONFIGURATION
LOGIC SYMBOL
1RD 1D
1 2 3 4 5 6
14 13
VCC 2RD 2D 2CP 2SD RD
2Q
4 10 1SD 2SD 2 1D 12 2D 3 1CP 11 2CP SD D CP Q FF Q 1Q 2Q 6 8 1Q 2Q 5 9
1CP 1SD 1Q 1Q
12 11 10 9
GND
7
8
2Q
1RD 1
2RD 13
SV00330
SV00331
LOGIC SYMBOL (IEEE/IEC)
4 3 2 1 S C1 1D R 6
FUNCTIONAL DIAGRAM
5
4
1SD D SD Q 1Q 5
2 1D 3 1CP
CP FF1 Q 1Q 6
10 11 12 13
S C2 2D R
9
RD 1 1RD 10 2SD SD 2Q 9
8 12 2D D Q
SV00332
11 2CP
CP FF2 Q RD 2Q 8
13
2RD
SV00333
1998 Apr 20
3
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive edge-trigger
74LV74
LOGIC DIAGRAM (ONE FLIP-FLOP)
Q C C
C C D
C
C Q
C RD
C
SD
CP
C C
SV00334
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VO Tamb Input voltage Output voltage Operating ambient temperature range in free air Input rise and fall times except for Schmitt-trigger inputs See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V PARAMETER DC supply voltage CONDITIONS See Note1 MIN 1.0 0 0 -40 -40 - - - - - - - - TYP. 3.3 - - MAX 5.5 VCC VCC +85 +125 500 200 100 50 UNIT V V V C
tr, tf
ns/V
NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK IOK IO IGND, ICC Tstg PARAMETER DC supply voltage DC input diode current DC output diode current DC output source or sink current - standard outputs DC VCC or GND current for types with -standard outputs Storage temperature range Power dissipation per package -plastic DIL -plastic mini-pack (SO) -plastic shrink mini-pack (SSOP and TSSOP) for temperature range: -40 to +125C above +70C derate linearly with 12mW/K above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI < -0.5 or VI > VCC + 0.5V VO < -0.5 or VO > VCC + 0.5V -0.5V < VO < VCC + 0.5V CONDITIONS RATING -0.5 to +7.0 20 50 25 50 -65 to +150 750 500 400 UNIT V mA mA mA mA C
Pt t tot
mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Apr 20 4
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive edge-trigger
74LV74
DC CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VCC = 1.2V VIH HIGH level Input voltage VCC = 2.0V VCC = 2.7 to 3.6V VCC = 4.5 to 5.5V VCC = 1.2V VIL LOW level Input voltage VCC = 2.0V VCC = 2.7 to 3.6V VCC = 4.5 to 5.5 VCC = 1.2V; VI = VIH or VIL; -IO = 100A VOH HIGH level output voltage all outputs out uts voltage; VCC = 2.0V; VI = VIH or VIL; -IO = 100A VCC = 2.7V; VI = VIH or VIL; -IO = 100A VCC = 3.0V; VI = VIH or VIL; -IO = 100A VCC = 4.5V;VI = VIH or VIL; -IO = 100A VOH HIGH level output voltage; g STANDARD outputs VCC = 3.0V;VI = VIH or VIL; -IO = 6mA VCC = 4.5V;VI = VIH or VIL; -IO = 12mA VCC = 1.2V; VI = VIH or VIL; IO = 100A VCC = 2.0V; VI = VIH or VIL; IO = 100A VCC = 2.7V; VI = VIH or VIL; IO = 100A VCC = 3.0V;VI = VIH or VIL; IO = 100A VCC = 4.5V;VI = VIH or VIL; IO = 100A VOL LOW level output voltage; g STANDARD outputs Input leakage current Quiescent supply current; flip-flops Additional quiescent supply current per input VCC = 3.0V;VI = VIH or VIL; IO = 6mA VCC = 4.5V;VI = VIH or VIL; IO = 12mA VCC = 5.5V; VI = VCC or GND VCC = 5.5V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC -0.6V 1.8 2.5 2.8 4.3 2.40 3.60 1.2 2.0 2.7 3.0 4.5 2.82 4.20 0 0 0 0 0 0.25 0.35 0.2 0.2 0.2 0.2 0.40 0.55 1.0 20.0 500 0.2 0.2 0.2 0.2 0.50 V 0.65 1.0 80 850 A A A V 1.8 2.5 2.8 4.3 2.20 V 3.50 V 0.9 1.4 2.0 0.7*VCC 0.3 0.6 0.8 0.3*VCC -40C to +85C TYP1 MAX -40C to +125C MIN 0.9 1.4 2.0 0.7*VCC 0.3 0.6 0.8 0.3*VCC V V MAX UNIT
VOL
LOW level output voltage out uts voltage; all outputs
II ICC ICC
NOTE: 1. All typical values are measured at Tamb = 25C.
1998 Apr 20
5
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive edge-trigger
74LV74
AC CHARACTERISTICS
GND = 0V; tr = tf v 2.5ns; CL = 50pF; RL = 1K SYMBOL PARAMETER WAVEFORM CONDITION VCC(V) 1.2 2.0 tPHL/tPLH Propagation delay nCP to nQ, nQ Figures, 1, 3 2.7 3.0 to 3.6 4.5 to 5.5 1.2 2.0 tPHL/tPLH Propagation delay nSD to nQ, nQ Figures 2, 3 2.7 3.0 to 3.6 4.5 to 5.5 1.2 2.0 tPHL/tPLH Propagation delay nRD to nQ, nQ Figures 2, 3 2.7 3.0 to 3.6 4.5 to 5.5 2.0 tW Clock pulse width HIGH to LOW Figure 1 2.7 3.0 to 3.6 4.5 to 5.5 2.0 tW Set or reset pulse width LOW Figure 2 2.7 3.0 to 3.6 4.5 to 5.5 1.2 2.0 trem Removal time set or reset Figure 2 2.7 3.0 to 3.6 4.5 to 5.5 1.2 2.0 tsu Set up time Set-up nD to nCP Figure 1 2.7 3.0 to 3.6 4.5 to 5.5 1.2 2.0 th Hold time nD to nCP Figure 1 2.7 3.0 to 3.6 4.5 to 5.5 2.0 fmax Maximum clock pulse frequency Figure 1 2.7 3.0 to 3.6 4.5 to 5.5 NOTE: 1. Unless otherwise stated, all typical values are at Tamb = 25C. 2. Typical value measured at VCC = 3.3V. 3. Typical value measured at VCC = 5.0V. MIN - - - - - - - - - - - - - - - 34 25 20 15 34 25 20 15 - 14 10 8 6 - 22 12 8 6 - 3 3 3 3 14 50 60 70 LIMITS -40 to +85 C TYP1 70 24 18 132 9.53 90 31 23 172 123 90 31 23 172 123 10 8 72 63 10 8 72 63 5 2 1 12 13 10 4 3 22 12 -10 -2 -2 -22 -23 40 90 1002 1103 MAX - 44 28 26 17 - 46 34 27 19 - 46 34 27 19 - - - - - - - - - - - - - - - - - - - - - - - - - - - LIMITS -40 to +125 C MIN - - - - - - - - - - - - - - - 41 30 24 18 41 30 24 18 - 15 11 9 7 - 26 15 10 8 - 3 3 3 3 12 40 48 56 MAX - 56 41 33 23 - 58 43 34 24 - 58 43 34 24 - - - - - - - - - - - - - - - - - - - - - - - - - - - MHz ns ns ns ns ns ns ns ns UNIT
1998 Apr 20
6
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive edge-trigger
74LV74
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V v 3.6V VM = 0.5 * VCC at VCC t 2.7V and w 4.5V VOL and VOH are the typical output voltage drop that occur with the output load.
TEST CIRCUIT
Vcc
Vl VI PULSE GENERATOR VM RT D.U.T.
VO
50pF CL
nD INPUT GND
nCP INPUT GND
VOH nQ OUTPUT VOL VOH nQ OUTPUT VOL tPLH tPHL VM VM
Figure 1.The clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP setup times, the nCP to nD hold times, the output transition times and the maximum clock pulse frequency NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
nCP INPUT GND VI nSD INPUT GND VI nRD INPUT GND VOH nQ OUTPUT VOL VOH nQ OUTPUT VOL VM tPHL tPLH tPLH VM tPHL VM tW VM tW
Figure 2.The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths and the nRD to nCP removal time 1998 Apr 20 7
III IIII III III IIII III
th th tsu tsu VI 1/fmax VM
tW
RL= 1k
Test Circuit for Outputs DEFINITIONS
RL = Load resistor CL = Load capacitance includes jig and probe capacitiance RT = Termination resistance should be equal to ZOUT of pulse generators.
tPHL
tPLH TEST tPLH/tPHL VCC < 2.7V 2.7-3.6V 4.5 V VI VCC 2.7V VCC
SV00902
Figure 3. Load circuitry for switching times
SV00335
VI VM trem
SV00336
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive edge-trigger
74LV74
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
1998 Apr 20
8
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive edge-trigger
74LV74
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
1998 Apr 20
9
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive edge-trigger
74LV74
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
1998 Apr 20
10
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive edge-trigger
74LV74
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
1998 Apr 20
11
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive edge-trigger
74LV74
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04414
Philips Semiconductors

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