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STW50N10 N - CHANNEL ENHANCEMENT MODE POWER MOS TRANSISTOR TYPE ST W50N10 s s s s s s s V DSS 100 V R DS(on) < 0.035 ID 50 A TYPICAL RDS(on) = 0.027 AVALANCHE RUGGED TECHNOLOGY 100% AVALANCHE TESTED REPETITIVE AVALANCHE DATA AT 100oC HIGH CURRENT CAPABILITY 175oC OPERATING TEMPERATURE APPLICATION ORIENTED CHARACTERIZATION TO-247 3 2 1 APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s POWER MOTOR CONTROL s DC-DC & DC-AC CONVERTERS s SYNCRONOUS RECTIFICATION INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol V DS VDGR V GS ID ID I DM (*) P t ot Parameter Drain-source Voltage (V GS = 0) Drain- gate Voltage (R GS = 20 k) Gate-source Voltage Drain Current (continuous) at T c = 25 C Drain Current (continuous) at T c = 100 o C Drain Current (pulsed) Total Dissipation at Tc = 25 C Derating Factor T stg Tj St orage Temperature Max. Operating Junction Temperature o o Value 100 100 20 50 35 200 180 1.2 -65 to 175 175 Uni t V V V A A A W W/ o C o o C C (*) Pulse width limited by safe operating area ISD 60 A, di/dt 200 A/s, VDD V(BR)DSS, Tj TJMAX January 1998 1/8 STW50N10 THERMAL DATA R t hj-ca se R t hj- amb R thc- si nk Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Thermal Resistance Case-sink Maximum Lead Temperature For Soldering Purpose Max Max T yp 0.83 30 0.1 300 o o C/W C/W o C/W o C AVALANCHE CHARACTERISTICS Symb ol I AR E AS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max, < 1%) Single Pulse Avalanche Energy (starting Tj = 25 o C, I D = IAR , VDD = 25 V) Max Valu e 50 400 Unit A mJ ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symb ol V (BR)DSS I DSS Parameter Drain-source Breakdown Voltage Test Cond ition s I D = 250 A V GS = 0 Min. 100 1 10 100 Typ . Max. Un it V A A nA Zero G ate Voltage V DS = Max Rating Drain Current (VGS = 0) V DS = Max Rating o C Gate-body Leakage Current (V DS = 0) V GS = 20 V T c = 125 I GSS ON () Symb ol V GS(th) R DS( on) ID(o n) Parameter Gate Threshold Voltage V DS = VGS Test Cond ition s ID = 250 A ID = 25 A 50 Min. 2 Typ . 3 0.027 Max. 4 0.035 Un it V A Static Drain-source On V GS = 10 V Resistance On State Drain Current V DS > I D(on) x R DS(on) max V GS = 10 V DYNAMIC Symb ol g fs () C iss C oss C rss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse T ransfer Capacitance Test Cond ition s V DS > I D(on) x R DS(on) max V DS = 25 V f = 1 MHz I D = 25 A VGS = 0 Min. 20 Typ . 45 4100 600 150 5200 800 200 Max. Un it S pF pF pF 2/8 STW50N10 ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symb ol t d(on) tr Qg Q gs Q gd Parameter Turn-on Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Cond ition s V DD = 50 V R G = 4.7 V DD = 80 V ID = 25 A VGS = 10 V I D = 50 A V GS = 10 V Min. Typ . 25 75 120 20 50 Max. 35 105 170 Un it ns ns nC nC nC SWITCHING OFF Symb ol t r(Vof f) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Cond ition s V DD = 80 V I D = 50 A R G = 4.7 V GS = 10 V Min. Typ . 30 35 65 Max. 45 50 95 Un it ns ns ns SOURCE DRAIN DIODE Symb ol I SD I SDM (*) V SD () t rr Q rr I RRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 50 A I SD = 50 A V DD = 30 V V GS = 0 di/dt = 100 A/s o Tj = 150 C Test Cond ition s Min. Typ . Max. 50 200 1.5 200 1.4 14 Un it A A V ns C A () Pulsed: Pulse duration = 300 s, duty cycle 1.5 % (*) Pulse width limited by safe operating area (1) ISD 60 A, di/dt 200 A/s, VDD V(BR)DSS, Tj TJMAX Safe Operating Area Thermal Impedance 3/8 STW50N10 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8 STW50N10 Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/8 STW50N10 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STW50N10 TO-247 MECHANICAL DATA mm MIN. A D E F F3 F4 G H L L3 L4 L5 M Dia 2 3.55 15.3 19.7 14.2 34.6 5.5 3 3.65 0.079 0.140 4.7 2.2 0.4 1 2 3 10.9 15.9 20.3 14.8 0.602 0.776 0.559 0.413 1.362 0.217 0.118 0.144 TYP. MAX. 5.3 2.6 0.8 1.4 2.4 3.4 MIN. 0.185 0.087 0.016 0.039 0.079 0.118 0.429 0.626 0.779 0.582 inch TYP. MAX. 0.209 0.102 0.031 0.055 0.094 0.134 DIM. P025P 7/8 STW50N10 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. (c) 1998 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A . .. 8/8 |
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