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VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7128
Features
* Supports ANSI X3T11 1.0625Gb/s FC-AL Disk Attach for Resiliency * Dual Repeaters (CRUs) Improve Signal Quality * Six Port Bypass Circuits (PBCs) for Resiliency * Dual Digital Signal Detect Units (SDUs)
Hex Port Bypass Circuit / Dual Repeater for 1.0625 Gb/s FC-AL Disk Arrays
* Fully Differential for Minimum Jitter * Selectable REFCLK: 53.125 / 106.25MHz * TTL Bypass Select * 3.3V Supply, 1.3W * 64-Pin, 14 mm Thermally Enhanced PQFP
General Description
The VSC7128 contains six Port Bypass Circuits (PBCs), dual embedded Clock Recovery Unit repeaters (CRU) and dual Signal Detect Units (SDU). These functions are integrated into a single part to minimize circuit size, part count, cost, high frequency routing and jitter accumulation. Together, they allow for optimized designs of FC-AL JBOD systems that provide resiliency and hot insertion/removal of disk drives. The PBCs configure the FC-AL loop to either include or exclude each drive. Repeaters retime the incoming signal thereby attenuating jitter so that downstream devices see high amplitude, low jitter signals. The SDUs determine whether the output of the CRU is a valid Fibre Channel signal. Disk drives are connected directly to the LSO/LSI/SEL pins while the IN/OUT pins can be connected to any FC-AL devices.
VSC7128 Block Diagram
DISK DRIVE #1 DISK DRIVE #2 DISK DRIVE #3 DISK DRIVE #4 DISK DRIVE #5 DISK DRIVE #6
LSO1+ LSO1LSI1+ LSI1SEL1
LSO2+ LSO2LSI2+ LSI2SEL2
LSO3+ LSO3LSI3+ LSI3SEL3
LSO4+ LSO4LSI4+ LSI4SEL4
LSO5+ LSO5LSI5+ LSI5SEL5
SDU1
FAIL1-
Previous Device
IN1+ IN1-
CRU1
1 0
1 0
1 0
1 0
1 0
1 0
1 0
OUT2+ OUT2-
PBC1
OUT1+ OUT1-
PBC2
PBC3
PBC4
PBC5 MUX7
0 1
PBC6
IN2+ IN2-
CRU2 SDU2
FAILSEL RFSEL REFCLK (106/53 MHz)
CMU
FAIL2SEL8 SEL7
G52177-0, Rev. 2.3 8/31/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Next Device
Page 1
MUX8
LSO6+ LSO6LSI6+ LSI6SEL6
VITESSE
SEMICONDUCTOR CORPORATION
Hex Port Bypass Circuit / Dual Repeater for 1.0625 Gb/s FC-AL Disk Arrays
Advance Product Information
VSC7128
Functional Description
A Port Bypass Circuit contains a differential 2:1 mux operating at 1.0625 Gb/s. The input to the PBC is always passed to the LSOx output of the PBC to let the disk drive monitor loop activity. The mux selects either the disk drive's input, LSIx, or the input from the previous PBC as determined by the SELx input which is normally connected directly to the disk drives EN_BYP output. When SELx is HIGH, the mux selects the disk drive input, LSIx. When SELx is LOW, the mux bypasses the disk drive input and passes the output of the previous PBC to the output of the PBC. Two extra muxes help route serial signals. MUX7 passes either the output of PBC6 (bypass mode) or the output of CRU2 (normal mode) to MUX8/OUT1 depending whether SEL7 is LOW or HIGH. MUX8 passes either the output of CRU1 or the output of MUX7 to PBC1 depending on whether SEL8 is HIGH or LOW. A TTL reference clock, REFCLK, is used by the internal Clock Multiplier Unit (CMU) to generate a baud rate clock at 1.0625 Gb/s. If RFSEL is HIGH, the CMU multiplies REFCLK (nominally 106.25MHz) by a factor of 10. If RFSEL is LOW, the CMU multiplies REFCLK (nominally 53.125MHz) by a factor of 20. The user must ensure that RFSEL is properly set in order to match the frequency of REFCLK. Two fully integrated Clock Recovery Units (CRUs) are provided to improve signal quality and determine whether the input to the repeater is a valid Fibre Channel signal. Each repeater consists of a Clock Recovery Unit (CRU) and a digital Signal Detect Unit (SDU). The CRU locks onto the incoming signal, generates a recovered clock (at 1.0625 GHz) and uses this clock to resynchronize the incoming signal. The recovered data has improved signal quality due to amplification and jitter attenuation. Recovered data is retimed to the recovered clock, not to REFCLK. The design of the CRU eliminates the need for any Lock-to-Reference signal since, in the absence of data, the CRU locks onto REFCLK automatically thereby eliminating the need for any external control circuitry. The Signal Detect Units (SDUs) tests the output of the CRUs for valid Fibre Channel data by detecting run length errors (more than 5 consecutive 1's or 0's) and the absence of a seven bit pattern found in the K28.5 character of either disparity (`0000101' or `1111010'). This K28.5 pattern should occur multiple times between frames. The maximum length of a Fibre Channel frame is 2148 bytes (or 21,480 encoded bits) and the SDU divides time into ~31 microsecond time intervals (2^15 bit times). At the end of each interval, any run length or K28.5 errors which occurred during the interval are stored internally for use by the state machine which drives the SDU output, FAILx-. The FAILSEL input controls both SDUs and the FAILx- outputs provide the status of each SDU. FAILSEL selects two different modes generated by the SDU; Single Frame (LOW) or Multiple Frame (HIGH) Error Mode. In Single Frame Error Mode, any error condition that occurs within an interval causes FAILx- to be asserted LOW immediately after that interval. FAILx- remains asserted until immediately after an error-free interval occurs. In Multiple Frame Error Mode, FAILx- is asserted after four consecutive intervals containing errors and remains asserted until four consecutive error-free intervals occur. The intent of the Multiple Frame Error Mode is to allow FAIL1- or FAIL2- to be directly connected to the mux controls, SEL8 or SEL7, in order to configure the part to isolate IN1 or IN2 whenever valid data is not present. Single Frame Error Mode allows the user to develop their own algorithm for monitoring data and controlling MUX8 or MUX7.
Page 2
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52177-0, Rev. 2.3 8/31/98
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7128
AC Characteristics
Hex Port Bypass Circuit / Dual Repeater for 1.0625 Gb/s FC-AL Disk Arrays
Figure 1: AC Timing Diagrams INx+/-, LSIx+/LSOx+/-, OUTx+/Tp Tp Ts 80% 20% Ts
REFCLK Tt Th Tt Tl T
VIH(MIN) VIL(MAX)
Table 1: AC Characteristics (Over recommended operating conditions). Parameters Description
Differential Inputs/Outputs Tp Ts Latency from IN, LSI to LSO, OUT Differential Output Rise/Fall time Reference Clock Requirements Tt F REFCLK input rise/fall times REFCLK Frequency -- 105 52.5 9.2 18.5 -200 35 2.5 2.0 108 54 9.53 19.0 +200 65 -- ns MHz Between VIL(MAX) and VIH(MIN) 106.25 MHz Nominal if RFSEL is HIGH 53.125 MHz Nominal if RFSEL is LOW RFSEL = HIGH RFSEL = LOW Maximum frequency offset between 10 or 20 times REFCLK and the data rate of the serial input to the CRU. Measured at 1.5V From VIL(min) to VIH(min) or VIH(max) to VIL(max) 0.25 -- 7.0 300 ns ps 75 Ohm Load Between 20% and 80% Tested on a sample basis
Min.
Max.
Units
Conditions
T Fo DC Th, Tl
REFCLK Period Frequency Offset REFCLK Duty Cycle REFCLK Input HIGH/LOW time
ns ppm % ns.
G52177-0, Rev. 2.3 8/31/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
Hex Port Bypass Circuit / Dual Repeater for 1.0625 Gb/s FC-AL Disk Arrays
Advance Product Information
VSC7128
DC Characteristics (Over recommended operating conditions).
Parameters
VIH VIL IIH IIL VOH VOL VDD PD IDD VIN(DF) VOUT75 VOUT50
Description
Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH current (TTL) Input LOW current (TTL) Output HIGH Voltage (TTL) Output LOW Voltage (TTL) Supply voltage Power Dissipation Supply current PECL input swing PECL output swing: LSO, OUT PECL output swing: LSO, OUT
Min
2.0 0 -- -- 2.4 -- 3.14 -- -- 300 1200 1200
Typ
-- -- 50 -- -- -- -- 1.3 390 -- -- --
Max
5.5 0.8 500 -500 -- 0.5 3.47 2.1 620 2600 2200 2200
Units
V V A A V V V W mA mVp-p mVp-p mVp-p --
Conditions
VIN = 2.4 V VIN = 0.5 V IOH = -1.0mA IOL= +1.0mA VDD = 3.3V + 5% Outputs open, VDD = VDD max Outputs open, VDD = VDD max AC Coupled. Internally biased at VDD/2 75 to VDD - 2.0 V 50 to VDD - 2.0 V
Absolute Maximum Ratings (1)
Power Supply Voltage (VDD)..............................................................................................................-0.5V to +4V PECL DC Input Voltage ......................................................................................................... -0.5V to VDD +0.5V TTL DC Input Voltage.......................................................................................................................-0.5V to 5.5V DC Voltage Applied to TTL Outputs .................................................................................... -0.5V to VDD + 0.5V TTL Output Current ................................................................................................................................. +/-50mA PECL Output Current ............................................................................................................................... +/-50mA Case Temperature Under Bias ........................................................................................................ -55 to +125oC Storage Temperature...................................................................................................................... -65 to + 150oC Maximum Input ESD (Human Body Model) .............................................................................................. 1500 V
Recommended Operating Conditions
Power Supply Voltage................................................................................................................3.3V +/- 5% Ambient Operating Temperature Range...............................................................0C Ambient to +90C Case
Notes: 1) CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability.
Page 4
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52177-0, Rev. 2.3 8/31/98
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7128
Input Structures
Hex Port Bypass Circuit / Dual Repeater for 1.0625 Gb/s FC-AL Disk Arrays
Two input structures exists in this part; TTL and High Speed, Differential Inputs. The TTL Inputs will interface with any TTL or 3.3V or 5V CMOS outputs. The High Speed, Differential Inputs are intended to be AC Coupled per the FC-PH specification. Being AC Coupled, the High Speed, Differential Input buffers are biased at VDD/2. Refer to Figure 2 for High Speed, Differential Input structure.
Figure 2: Input Structures
VDD +3.3 V
INPUT
Current Limit
R
R GND
REFCLK and TTL Inputs
A
VDD +3.3 V
INPUT
INPUT
All Resistors 3.3K GND
High Speed Differential Input (RX+/RX-)
B
G52177-0, Rev. 2.3 8/31/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 5
VITESSE
SEMICONDUCTOR CORPORATION
Hex Port Bypass Circuit / Dual Repeater for 1.0625 Gb/s FC-AL Disk Arrays
Advance Product Information
VSC7128
Package Pin Descriptions
Figure 3: Pin Diagram
VSS OUT2+ OUT2LSO6+ LSO6SEL6
VDD4
LSI6+
LSI5+ 51
VDD
IN2+
LSI6-
63 SEL7 REFCLK REFSEL FAIL1VDD VSS TEST1 VDDA VSS TEST2 TEST3 FAILSEL SEL8 FAIL2IN1IN1+ 15 17 19 13 11 9 7 5 3 1
IN2-
61
59
57
55
53
VSS
LSI5-
49 VDD 47 45 43 41 39 37 35 33 LSO5+ LSO5VDD3 LSO4+ LSO4SEL4 LSI4+ LSI4VSS LSI3+ LSI3SEL3 LSO3+ LSO3VDD2
21
23
25
27
29
31
OUT1-
OUT1+
LSO1-
LSO1+
(Top View)
NOTE: Heatsink is not internally connected electrically. It should not be connected electrically by the user.
Page 6
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
LSO2+
LSO2-
SEL1
VDD1
LSI1+
LSI1-
LSI2-
LSI2+
VDD
VSS
VDD
SEL2
SEL5
G52177-0, Rev. 2.3 8/31/98
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7128
Table 2: Pin Description Pin #
16, 15 63, 62 20, 19 60, 59 26, 25 29, 28 38, 37 41, 40 51, 50 54, 53 23, 22 32, 31 35, 34 44, 43 47, 46 57, 56 24, 30 36, 42 49, 55 1, 13 2 3 4, 14 12 7, 10, 11 5, 17, 27, 48, 64 21, 33, 45, 58 8 6, 9, 18, 39, 52, 61
Hex Port Bypass Circuit / Dual Repeater for 1.0625 Gb/s FC-AL Disk Arrays
Name
IN1+, IN1IN2+, IN2OUT1+, OUT1OUT2+, OUT2LSI1+, LSI1LSI2+, LSI2LSI3+, LSI3LSI4+, LSI4LSI5+, LSI5LSI6+, LSI6LSO1+, LSO1LSO2+, LSO2LSO3+, LSO3LSO4+, LSO4LSO5+, LSO5LSO6+, LSO6SEL1, SEL2 SEL3, SEL4 SEL5, SEL6 SEL7, SEL8 REFCLK RFSEL FAIL1FAIL2FAILSEL TEST1 TEST2 TEST3 VDD VDD1, VDD2, VDD3, VDD4 VDDA VSS
Description
INPUT - Differential. Serial input to CRU1/CRU2 (AC Coupling recommended) (Biased internally at VDD/2). OUTPUT - Differential. Serial output from MUX7/PBC6 (AC Coupling recommended).
INPUT - Differential. Serial input from disk drive `x' to PBCx (AC Coupling recommended) (Biased internally at VDD/2).
OUTPUT - Differential. Serial output from PBCx to disk drive `x' (AC Coupling recommended).
INPUT - TTL. A LOW bypasses the disk drive input and passes the output from the previous PBC to the output of PBCx. A HIGH selects the disk drive input (LSIx) as the output of the PBC. SEL7 configures MUX7. SEL8 configures MUX8. INPUT - TTL.. REFerence CLocK at 1/10th or 1/20th the baud rate (Nominally 53.125 or 106.25 MHz) as determined by RFSEL. Used for internal clock multiplier unit. INPUT - TTL. ReFclk SELect. When HIGH, REFCLK is 1/10th the baud rate and would normally be 106.25 MHz. When LOW, REFCLK is 1/20th the baud rate (53.125 MHz) OUTPUT - TTL. When LOW, indicates that the output of CRU1/2 does not contain valid Fibre Channel data. INPUT - TTL. Selects the algorithm to drive the FAIL1-/FAIL2- outputs. When HIGH, the "Multiple Frame Error Mode" is used. When LOW, the "Single Frame Error Mode" is selected. INPUT - TTL. LOW for factory test, HIGH for normal operation. Power Supply. 3.3V Supply. High-Speed Output Power Supply. 3.3V Supply for PECL drivers. VDD1 powers OUT1 and LSO1, VDD2 powers LSO2 and LSO3, VDD3 powers LSO4 and LSO5, VDD4 powers LSO6 and OUT2. If the pair of outputs are not used, VDDx may be grounded to conserve power. Analog Power Supply. 3.3V for Clock Multiplier PLL. Ground.
G52177-0, Rev. 2.3 8/31/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 7
VITESSE
SEMICONDUCTOR CORPORATION
Hex Port Bypass Circuit / Dual Repeater for 1.0625 Gb/s FC-AL Disk Arrays
Advance Product Information
VSC7128
Package Information
64 Pin PQFP Package Drawings F G
Item
64 49 48 1
14 mm
2.45 2.00 0.35 17.20 14.00 17.20 14.00 0.80 0.80 N/A
Tol.
MAX +0.10 0.05 0.25 0.10 0.25 0.10 0.15 BASIC 0.50 DIA.
A D E F I H G H I
L
16 33
J K L
17
10 TYP
o
32
A
D
100 TYP
K
0.30 RAD. TYP.
A
0.20 RAD. TYP.
STANDOFF
0.25 MAX.
0.17 MAX. 0.25 NOTES: Drawing not to scale. All units in mm unless otherwise noted. Heat spreader is not electrically connected. J
0 o- 8 o
0.102 MAX. LEAD non-planariity
E
Page 8
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52177-0, Rev. 2.3 8/31/98
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7128
Package Thermal Characteristics
Hex Port Bypass Circuit / Dual Repeater for 1.0625 Gb/s FC-AL Disk Arrays
The VSC7128 is packaged into a thermally enhanced plastic quad flatpack with an exposed heat spreader. This package adheres to industry standard EIAJ footprints for a 14x14mm body, 64 lead PQFP. The package construction and thermal properties are shown below. The user must ensure that the maximum case temperature specification (90o C) is not violated. Given the thermal resistance of the package in still air, the user may operate the VSC7128 in still air if the ambient temperature does not exceed 32o C ( 90o C - 1.7W o C * 35 oC/W = 32o C). If operation above this ambient temperature is required, an appropriate heatsink must be used with the part or adequate airflow must be provided. The thermal resistances given above are for a PCB which is not thermally saturated since significant amounts of heat can transfer through the leadframe and into the PCB.
Figure 4: Package Cross Reference
Exposed Heat Slug Insulator
Plastic Molding Compound
Lead
Wire Bond
Die
Table 3: Thermal Resistance Symbol
jc ca-0 ca-100 ca-200 ca-400 ca-600
Description
Thermal resistance from junction to case Thermal resistance from case to ambient, still air Thermal resistance from case to ambient, 100 LFPM air Thermal resistance from case to ambient, 200 LFPM air Thermal resistance from case to ambient, 400 LFPM air Thermal resistance from case to ambient, 600 LFPM air
Value
2.5 35 29 26 22 19
Units
oC/W oC/W oC/W oC/W oC/W oC/W
Moisture Sensitivity Level
This device is rated with a moisture sensitivity level 3 rating. Refer to Application Note AN-20 for appropriate handling procedures.
G52177-0, Rev. 2.3 8/31/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 9
VITESSE
SEMICONDUCTOR CORPORATION
Hex Port Bypass Circuit / Dual Repeater for 1.0625 Gb/s FC-AL Disk Arrays
Advance Product Information
VSC7128
Ordering Information
The order number for this product is formed by a combination of the device number and package type.
VSC7128
Device Type VSC7128 - Hex PBC/Dual Repeater
QS
Package Type QS: 64 Pin Thermally Enhanced PQFP, 14x14mm Body
Marking Information
The package is marked with three lines of text as shown below (QS Package):
Pin Identifier
VITESSE
Exposed Heat Spreader
VSC7128QS
Part Number ####AAAA Date Code Lot Tracking Code Package Suffix
Notice
This document contains information about a new product during its fabrication or early sampling phase of development. The information in this document is based on design targets, simulation results or early prototype test results. Characteristic data and other specifications are subject to change without notice. Therefore the reader is cautioned to confirm that this datasheet is current prior to design or order placement.
Warning
Vitesse Semiconductor Corporation's products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without the written consent is prohibited.
Page 10
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52177-0, Rev. 2.3 8/31/98

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