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PRELIMINARY DATA SHEET
MICRONAS
DAC 3555A Stereo Audio DAC
Edition Jan. 8, 2002 6251-575-1PD
MICRONAS
DAC 3555A
Contents Page 3 3 3 6 6 7 7 7 7 7 7 8 8 9 9 9 10 10 10 11 11 12 12 13 15 15 15 15 16 16 17 18 20 20 21 23 28 28 28 29 29 30 30 30 31 34 Section 1. 1.1. 1.2. 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 2.7. 2.8. 2.9. 2.10. 2.10.1. 2.10.2. 2.11. 2.12. 2.13. 2.14. 2.15. 3. 3.1. 3.2. 3.3. 3.3.1. 3.3.2. 3.3.3. 3.3.4. 3.3.5. 3.4. 3.5. 3.6. 3.6.1. 3.6.2. 3.6.3. 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.5.1. 4.5.2. 4.6. 5. Title Introduction Main Features Differences between DAC 3555A and DAC 3550A Functional Description I2S Interface Interpolation Filter Variable Sample and Hold 3rd-order Noise Shaper and Multibit DAC Analog Low-pass Input Select and Mixing Matrix Postfilter Op Amps, Deemphasis Op Amps, and Line-Out Analog Volume Headphone Amplifier Clock System Standard Mode MPEG Mode I2C Bus Interface Registers Chip Select Power Modes Oscillator Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Power Supply Pins Analog Audio Pins Oscillator and Clock Pins Other Pins Pin Configuration Pin Circuits Control Registers Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Characteristics
PRELIMINARY DATA SHEET
Applications Line Output Details Recommended Low-Pass Filters for Analog Outputs Recommendations for Filters and Deemphasis Recommendations for MegaBass Filter without Deemphasis Power-up/down Sequence Power-up Sequence Power-down Sequence Typical Applications Data Sheet History
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DAC 3555A
Stereo Audio DAC 1. Introduction The DAC 3555A is a single-chip, high-precision, stereo digital-to-analog converter designed for audio applications. The employed conversion technique is based on oversampling with noise-shaping. With Micronas' unique multibit sigma-delta technique, less sensitivity to clock jitter, high linearity, and a superior S/N ratio have been achieved. The DAC 3555A is controlled via I2C bus. Digital audio input data is received by a versatile I S interface. The analog back-end consists of internal analog filters and op amps for cost-effective additional external sound processing. The DAC 3555A provides line-out, headphone/speaker amplifiers, and volume control. Moreover, mixing additional analog audio sources to the D/A-converted signal is supported. The DAC 3555A is designed for all kinds of applications in the audio and multimedia field, such as: MPEG players, CD players, DVD players, CD-ROM players, mobile phones, etc. The DAC 3555A ideally complements the MP3 audio decoders MAS 3507D, MAS 35x9F, and PUC 303xA. No crystal or external clock required for standard applications with sample rates from 32 to 48 kHz and 96 kHz. It is required for automatic sample rate detection below 32 kHz, MPEG mode (refer to Section 2.10.1.), and use of clock output CLKOUT.
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- SNR of 103 dB(A) - I2C bus, I2S bus - internal clock oscillator - sample rates from 8 kHz to 96 kHz - analog deemphasis for 44.1 kHz - analog volume and balance: +18...-75 dB and mute - THD better than 0.01% - two additional analog stereo inputs (AUX) with source selection and mixing - supply range: 2.7 V...5.5 V - zero-power mode - additional line-out - on-chip op amps for cost-effective external analog sound processing - pin-compatible to DAC 3550A - PMQFP44 or PQFN40 package
1.2. Differences between DAC 3555A and DAC 3550A - new zero-power mode - operation in I2C mode only. Stand-alone operation is not supported. - new quiet wake-up mode: after power-on, the DAC 3555A switches into zero-power mode. Waking-up is done via I2C command. This feature avoids audible "plops". - sample rates up to 96 kHz - not register-compatible to DAC 3550A
1.1. Main Features - no master main input clock required - no external crystal required - integrated stereo headphone amplifier and mono speaker amplifier
Analog Inputs
WSI CLI DRI I 2S
Interpolation Filter
DAC
Input Select and Mixing
Volume and Headphone Amplifier
OUTL OUTR
SDA SCL
Line Out I2C
Fig. 1-1: Block diagram of the DAC 3555A
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PRELIMINARY DATA SHEET
Display, Keyboard I2C
USB PC
PUC 303xA
MP3, WMA, AAC
clock input1) I2S
Line Out
DAC 3555A
UART SDMI compliant SD-Card, MMC Compact Flash Microdrive IDE R/W Fig. 1-2: Typical application: Secure Music Player Line in
1)
only necessary for automatic sample rate detection
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DAC 3555A
CLI 23
DAI 24
WSI 25 18 Vdd Vss
IS
2
Digital Supply
17
Sample Rate Detection
9
AVDD0 AVDD1 AVSS0 AVSS1 VREF AGNDC
Interpolation Filter Analog Supply
10 3 2 44
PLL Variable S & H
1
16 CLKOUT 14
SDA SCL
3rd-order Noise Shaper & Multibit DAC Osc. Analog Low-pass Filter
IC
2
15
27 26
TESTEN PORQ DEECTRL MCS1 MCS2
XTO
13 21 19 20
XTI
12
Control
AUX2L
29
32
AUX1R
AUX1L
31
Input Select Switch Matrix
30
AUX2R
DEEML FOPL FOUTL FINL
34 38 37 39
35
DEEMR FOPR FOUTR FINR
Postfilter Op Amps Deemphasis Op Amps Line-Out
42 41 43
Analog Volume
Headphone Amplifier
5 OUTL 7 OUTR
Fig. 1-3: Block diagram of the DAC 3555A
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2. Functional Description 2.1. I2S Interface The I2S interface is the digital audio interface between the DAC 3555A and external digital audio sources such as CD/DAT players, MPEG decoders etc. It covers most of the I2S-compatible formats. All modes have two common features: 1. The MSB is left justified to an I2S frame identification (WSI) transition. 2. Data is valid on the rising edge of the bit clock CLI. 16-bit mode In this case, the bit clock is 32 x fsaudio. Maximum word length is 16 bit. 32-bit mode In this case, the bit clock is 64 x fsaudio. Maximum word length is 32 bit.
PRELIMINARY DATA SHEET
Automatic Detection No I2C control is required to switch between 16- and 32-bit mode. It is recommended to switch the DAC 3555A into mute position during changing between 16- and 32-bit mode. For high-quality audio, it is recommended to use the 32-bit mode of the I2S interface to make use of the full dynamic range (if more than 16 bits are available). Left-Right Selection Standard I2S format defines an audio frame always starting with left channel and low-state of WSI. However, I2C control allows changing the polarity of WSI. Delay Bit Standard I2S format requires a delay of one clock cycle between transitions of WSI and data MSB. In order to fit other formats, however, this characteristic can be switched off and on by I2C control. Note: Volume mute should be applied before changing I2S mode in order to avoid audible clicks.
Vh
CLI
Vl
Vh
DAI
15 14 13 12 11 10 9 8
Vl
7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
76543210
programmable delay bit
WSI
Vh Vl
left 16-bit audio sample
right 16-bit audio sample
Fig. 2-1: I2S 16-bit mode (LR_SEL = 0)
Vh
CLI
Vl
Vh
DAI
31 30 29 28 27 26 25 24
Vl
7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 7 6 5 4 3 2 1 0
programmable delay bit
WSI
Vh Vl
left 32-bit audio sample
right 32-bit audio sample
Fig. 2-2: I2S 32-bit mode (LR_SEL = 0)
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DAC 3555A
2.6. Input Select and Mixing Matrix This block is used to switch between or mix the auxiliary inputs and the signals coming from the DAC. A switch matrix allows to select between mono and stereo mode as shown in Fig. 2-1.
)287/ '$ )2875 $8;/ $8;5 $8;/ $8;5
2.2. Interpolation Filter The interpolation filter increases the sampling rate by a factor of 8. The characteristic for fsaudio = 48 kHz is shown in Fig. 2-1.
dB 0 -0.02 -0.04 -0.06 -0.08 -0.1 -0.12 -0.14 0 5000 10000 15000 20000 f/Hz
'$' '$, :6,
$8;B06 ,16(/B$8; ,16(/B$8; ,16(/B'$&
Fig. 2-1: 18 Interpolation filter; frequency range: 0...22 kHz
Fig. 2-1: Switch matrix 2.3. Variable Sample and Hold The advantage of this system is that even at low sample frequencies the out-of-band noise is not scaled down to audible frequencies. Mono mode is realized by adding left and right channel.
2.4. 3rd-order Noise Shaper and Multibit DAC The 3rd-order noise shaper converts the oversampled audio signal into a 5-bit noise-shaping signal at a high sampling rate. This technique results in extremely low quantization noise in the audio band.
2.7. Postfilter Op Amps, Deemphasis Op Amps, and Line-Out This block contains the active components for the analog postfilters and the deemphasis network. The op amps and all I/O-pins for this block are shown in Fig. 2-2.
2.5. Analog Low-pass The analog low-pass is a first order filter with a cut-off frequency of approximately 1.4 MHz which removes the high-frequency components of the noise-shaping signal.
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PRELIMINARY DATA SHEET
optional line-out
AVSS
AGNDC +
3.3 F/100 nF
For external components, see section "Applications"
AVOL_R
+ OUTL 150 F 1.5 k Speaker >16 @5 VAVDD >10 @3 VAVDD 10 ...47 10 ...47 16...32
VREF
FOUTL
from switch matrix
FINL FINR
DEEML
FOPL FOPR
FOUTR DEEMR
-
150 F 1.5 k +
Headphones
AVDD
to mC (HP-switch)
Fig. 2-2: Postfilter op amps, deemphasis op amps, and line-out
2.8. Analog Volume The analog volume control covers a range from +18 dB to -75 dB. The lowest step is the mute position. Step size is split into a 3-dB and a 1.5-dB range:
Table 2-1: Volume Control Volume/dB 18.0 16.5 15.0 13.5 AVOL 111000 110111 110110 110101
-75 dB...-54 dB: 3 dB step size -54 dB...+18 dB: 1.5 dB step size
2.9. Headphone Amplifier The headphone amplifier output is provided at the OUTL and OUTR pins connected either to stereo headphones or a mono loudspeaker. The stereo headphones require external 10...47- serial resistors in both channels. If a loudspeaker is connected to these outputs, the power amplifier for the right channel must be switched to inverse polarity. In order to optimize the available power, the source of the two output amplifiers should be identical, i.e. a monaural signal. Please note, that if a speaker is connected, it should strictly be connected as shown in Fig. 2-2. Never use a separate connector for the speaker, because electrostatic discharge could damage the output transistors.
AVOL_L
For external components, see section "Applications"
-
0.0
IRPA
OUTR
-
101100 (default) 101011
-1.5 - -54.0 -57.0 - -75
Mute
-
001000 000111
-
000001 000000
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PRELIMINARY DATA SHEET
DAC 3555A
2.10.1. Standard Mode In standard mode, sample rates from 48 kHz to 32 kHz are handled without I2C control automatically. The setting for this range is the default setting. Other sample rates require an I2C control to set the PLL divider. This ensures that even at low sample rates, the DAC 3555A runs at a high clock rate. This avoids audible effects due to the noise-shaping technique of the DAC 3555A. Sample rate range is continuous from 8 to 48 kHz. The I2C setting of non-standard sample rates must follow Table 2-2. An additional mode allows automatic sample rate detection. In this case, the clock oscillator is required and must run at frequencies between 13.3 MHz to 17 MHz. This mode, however, does not support continuous sample rates. Only the following sample rates are allowed: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 24 kHz, 32 kHz, 44.1 kHz, and 48 kHz 22.05 kHz,
2.10. Clock System The advantage of the DAC 3555A clock system is that no external master clock is needed. Most DACs need 256 x fsaudio, 384 x fsaudio, or at least an asynchronous clock. All internal clocks are generated by a PLL circuit, which locks to the I2S bit clock (CLI). If no I2S clock is present, the PLL runs free, and it is guaranteed that there is always a clock to keep the IC controllable by I2C. The device can be set to two different modes: - Standard mode - MPEG mode In the standard mode, I2C subaddressing is possible (ADR0, ADR1, ADR2). MPEG mode always uses ADR3. To select the modes, the MCS1/MCS2 pins must be set according to Table 2-2. Table 2-2: Operation Modes
MCS1 MCS2 Mode Subaddress ADR0 ADR1 ADR2 ADR3 Default Sample Rate 32-48 kHz 32-48 kHz 32-48 kHz Automatic
The sample rate detection allows a tolerance of 200 ppm at WSI. 2.10.2. MPEG Mode This mode should be used in conjunction with PUC 30x3A in MPEG player applications. All MPEG sample rates from 8 to 48 kHz can be detected if the PUC 30x3A sends a clock signal between 13.3 MHz and 17 MHz to the DAC 3555A. The internal processing and the DAC itself are automatically adjusted to keep constant performance throughout the entire range. I2C control for sample rate adjustment is not needed in this case. The MPEG sample rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz As in standard mode, the sample rate detection allows a tolerance of 200 ppm at WSI. Subaddressing is not possible in MPEG mode; this means, in multi-DAC systems, only one DAC 3555A can run in MPEG mode.
0 0 1 1
0 1 0 1
Standard Standard Standard MPEG
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2.11. I2C Bus Interface The DAC 3555A is equipped with an I2C bus slave interface. The I2C bus interface uses one level of subaddressing: The I2C bus address is used to address the IC. The subaddress allows chip select in multi DAC applications and selects one of the three internal registers. The registers are write-only. The I2C bus chip address is given below. Device Address = 4Dhex. The registers of the DAC 3555A have 8- or 16-bit data size; 16-bit registers are accessed by writing two 8-bit data words. 2.13. Chip Select
PRELIMINARY DATA SHEET
Table 2-3: I2C Register Address RA1 0 1 1 RA0 1 0 1 Mnemonics SR_REG AVOL GCFG
2.12. Registers In Section 3.5. "Control Registers" on page 18, a definition of the DAC 3555A control registers is shown. A hardware reset initializes all control registers to 0. The automatic chip initialization loads a selected set of registers with the default values given in the table. All registers are write-only. The register address is coded by 3 bits (RA1, RA0) according to Table 2-3.
Chip select allows to connect up to four DAC 3555A to an I2C control bus. The chip subaddresses are defined by the MCS1/MCS2 (Mode and Chip Select) pins. Only in standard mode, chip select is possible. MPEG mode always uses chip subaddress 3. Register address and chip select are mapped into the subaddress field in Table 2-4. Table 2-4: I2C Subaddress 7 MCS2 6 MCS1 5 4 3 2 1 RA1 0 RA0
S
4Dhex 4Dhex
w
Ack sub_adr
Ack 1 byte data
Ack P
8-bit I2C write access Ack P 16-bit I2C write access
S
w
Ack sub_adr
Ack 1 byte data
Ack
1 byte data
SDA SCL S
1 0
P
W R Ack Nak S P
= = = = = =
0 1 0 1 Start Stop
Fig. 2-1: I2C bus protocols for write operations
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DAC 3555A
2.15. Oscillator The I2C-controlled oscillator (see Section 3.5. "Control Registers" on page 18) switches on in the following modes, only: 1. DAC ON - Standard Mode - automatic sample rate detection 2. DAC ON - MPEG Mode In all other modes the oscillator is not required internally and therefore switched off. For test purpose it is possible to switch on the oscillator in all modes (control register AVOL, bit 15). It is not recommended to use this option in normal applications.
2.14. Power Modes The DAC 3555A supports four different power modes, which can be selected by I2C. 1. Zero Power This is the default mode after power up. In this mode digital and analog blocks are inactive. Please note that minimum power consumption is only achieved if all digital input pins connected to peripheral circuits are low or tristate. 2. Analog Stand-by This mode activates the internal analog reference system and allows a fast and quiet transition to the active modes below. 3. Aux to Line This active mode is used, if no digital audio signals are present. Only the analog back-end is active. 4. Full Power All blocks are active in this mode. Start-up sequence: The recommended sequence for stepping through the power modes is shown in Section 4.5. "Power-up/down Sequence" on page 30.
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3. Specifications 3.1. Outline Dimensions
10 x 0.8 = 8 0.1 0.17 0.06 33 34 13.2 0.2 23 22 10 0.1 0.8 0.8
PRELIMINARY DATA SHEET
44 1 11 13.2 0.2
12
2.0 0.1 2.15 0.2 0.1 10 0.1
0.34 0.05
SPGS706000-5(P44)/1E
Fig. 3-1: 44-Pin Plastic Metric Quad Flat Package (PMQFP44) Weight approximately 0.4 g Dimensions in mm
exposed die pad
10 x 0.8 = 8 0.1
SPGS709000-1(P40)/2E
Fig. 3-2: 40-Pin Plastic Quad Flat No leads package (PQFN40) Weight approximately 0.096 g Dimensions in mm
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DAC 3555A
3.2. Pin Connections and Short Descriptions NC LV VSS X VDD = not connected, leave vacant = if not used, leave vacant = if not used, connect to VSS = obligatory; connect as described in application diagram = connect to VDD
Pin No.
PMQFP 44-pin PQFN 40-pin
Pin Name
Type
Connection
(If not used)
Short Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
31 32 33 16 34 26 37 35 38 40 36 1 2 3 4 5 6 7 8 9 10 39 11 12 13
AGNDC AVSS1 AVSS0 NC OUTL NC OUTR NC AVDD0 AVDD1 NC XTI XTO CLKOUT SCL SDA VSS VDD MCS1 MCS2 DEECTRL NC CLI DAI WSI
IN/OUT IN IN
X X X LV
Analog reference Voltage VSS 1 for audio back-end VSS 0 for audio output amplifiers Not connected Audio Output: Headphone left or Speaker + Not connected Audio Output: Headphone right or Speaker - Not connected VDD 0 for audio output amplifiers VDD 1 for audio back-end Not connected Quartz oscillator pin 1 Quartz oscillator pin 2 Clock Output I2C clock I2C data Digital VSS Digital VDD I2C Chip Select 1 I2C Chip Select 2 Deemphasis on/off Control Not connected I2S Bit Clock I2S Data I2S Frame Identification
OUT
LV LV
OUT
LV LV
IN IN
X X LV
IN IN/OUT OUT IN IN/OUT IN IN IN IN IN IN
X X LV LV LV X X X X VSS LV VSS
IN IN
VSS VSS
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PRELIMINARY DATA SHEET
Pin No.
PMQFP 44-pin PQFN 40-pin
Pin Name
Type
Connection
(If not used)
Short Description
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
14 15 16 17 18 19 20 - 21 22 - 23 24 25 - 27 28 29 30
PORQ TESTEN NC AUX2L AUX2R AUX1L AUX1R NC DEEML DEEMR NC FOUTL FOPL FINL NC FOUTR FOPR FINR VREF
IN IN
VDD X LV
Power-On Reset, active-low Test Enable Not connected AUX2 left input for external analog signals (e.g. tape) AUX2 right input for external analog signals (e.g. tape) AUX1 left input for external analog signals (e.g. FM) AUX1 right input for external analog signals (e.g. FM) Not connected Deemphasis Network Left Deemphasis Network Right Not connected Output to left external filter Filter op amp inverting input, left Input for FOUTL or filter op amp output (line out) Not connected Output to right external filter Right Filter op amp inverting input Input for FOUTR or filter op amp output (line out) Analog reference Ground
IN IN IN IN
LV LV LV LV LV
OUT OUT
LV LV LV
OUT IN/OUT IN/OUT
X X X LV
OUT IN/OUT IN/OUT IN
X X X X
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DAC 3555A
FOUTL FOPL FINL FOUTR FOPR FINR Filter op amps are provided in the analog baseband signal paths. These inverting op amps are freely accessible for external use by these pins. The FOUTL/R pins are connected with the buffered output of the internal switch matrix. The FOPL/R-pins are directly connected with the inverting inputs of the filter op amps. The FINL/R pins are connected with the outputs of the op amps. The driving capability of the FOUTL/R pins is not sufficient for standard line output signals. Only the FINL/R pins are suitable for line output. OUTL OUTR The OUTL/R pins are connected to the internal output amplifiers. They can be used for either stereo headphones or a mono loudspeaker. The signal of the right channel amplifier can be inverted for mono loudspeaker operation. Caution: A short circuit at these pins for more than a momentary period may result in destruction of the internal circuits.
3.3. Pin Descriptions 3.3.1. Power Supply Pins The DAC 3555A combines various analog and digital functions which may be used in different modes. For optimized performance, major parts have their own power supply pins. All VSS power supply pins must be connected. VDD VSS The VDD and VSS power supply pair are connected internally with all digital parts of the DAC 3555A. AVDD0 AVSS0 AVDD0 and AVSS0 are separate power supply pins that are exclusively used for the on-chip headphone/ loudspeaker amplifiers. AVDD1 AVSS1 The AVDD1 and AVSS1 pins supply the analog audio processing parts, except for the headphone/loudspeaker amplifiers.
3.3.2. Analog Audio Pins AGNDC Reference for analog audio signals. This pin is used as reference for the internal op amps. This pin must be blocked against VREF with a 3.3 F capacitor. Note: The pin has a typical DC-level of 1.5/2.25 V. It can be used as reference input for external op amps when no current load is applied. VREF Reference ground for the internal band-gap and biasing circuits. This pin should be connected to a clean ground potential. Any external distortions on this pin will affect the analog performance of the DAC 3555A. AUX1L AUX1R AUX2L AUX2R The AUX pins provide two analog stereo inputs. Auxiliary input signals, e.g. the output of a conventional receiver circuit or the output of a tape recorder can be connected with these inputs. The input signals have to be connected by capacitive coupling.
3.3.3. Oscillator and Clock Pins XTI XTO The XTI pin is connected to the input of the internal crystal oscillator, the XTO pin to its output. Both pins should be directly connected to the crystal and two ground-connected capacitors (see application diagram). CLKOUT The CLKOUT pin provides a buffered output of the crystal oscillator. Caution: Power dissipation limit may be exceeded in case of short to VSS or VDD. CLI DAI WSI These three pins are inputs for the digital audio data DAI, frame indication signal WSI, and bit clock CLI. The digital audio data is transmitted in an I2S-compatible format. Audio word lengths of 16 and 32 bits are supported, as well as SONY and Philips I2S protocol. SCL SDA SCL (serial clock) and SDA (serial data) provide the connection to the serial control interface (I2C).
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3.3.4. Other Pins TESTEN Test enable. This pin is for test purposes only and must always be connected to VSS. PORQ This pin may be used to reset the chip. If not used, this pin must be connected to VDD.
PRELIMINARY DATA SHEET
DEEML DEEMR These pins connect an external analog deemphasis network to the signal path in the analog back-end. This connection can be switched on and off by an internal switch which is controlled either by I2C or the DEECTRL-pin. DEECTRL Deemphasis can be switched on and off with this pin. MCS1 MCS2 Mode select pins to select MPEG, Standard Mode, and I2C subaddress.
3.3.5. Pin Configuration
NC AUX2L AUX2R AUX1L AUX1R NC TESTEN PORQ WSI DAI CLI 30 29 28 27 26 25 24 23 22 21 33 32 31 30 29 28 27 26 25 24 23 DEEML DEEMR NC FOUTL FOPL FINL NC FOUTR FOPR FINR VREF 34 35 36 37 38 39 40 41 42 43 44 1 AGNDC AVSS1 AVSS0 NC OUTL NC NC OUTR 2 3 4 5 6 7 8 9 10 11 NC AVDD1 AVDD0 22 21 20 19 18 NC DEECTRL MCS2 MCS1 VDD VSS SDA SCL CLKOUT XTO XTI XTI XTO CLKOUT SCL SDA AGNDC AVSS1 AVSS0 OUTL NC NC OUTR AVDD0 NC AVDD1 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 DEECTRL MCS2 MCS1 VDD VSS 20 19 18 17 AUX1R AUX1L AUX2R AUX2L NC TESTEN PORQ WSI DAI CLI FOUTR FOPR FINR VREF
NC
FINL FOPL FOUTL DEEMR DEEML
DAC 3555A
16 15 14 13 12 11
DAC 3555A
17 16 15 14 13 12
Fig. 3-2: PQFN40 package
Fig. 3-1: PMQFP44 package
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PRELIMINARY DATA SHEET
DAC 3555A
3.4. Pin Circuits VDD
FOUTn N VSS Fig. 3-3: Input/Output Pins SDA, SCL AGNDC Fig. 3-9: Output Pins FOUTL, FOUTR
AGNDC Fig. 3-4: Input Pins PORQ, DAI
125 k
VREF AVSS0/1
15 k
Fig. 3-10: Pins AGNDC, VREF
Fig. 3-5: Input Pins WSI, CLI
XTO
VDD P N VSS Fig. 3-6: Output Pin CLKOUT AUXnL XTI
500 k
Fig. 3-11: Input/Output Pins XTI, XTO
sel/nonsel
ext. filter network FOUTn DEEM FOPn FINn
AGNDC
mono/stereo
AGNDC
mono/stereo
AUXnR
sel/nonsel
(DEEMCTRL)
AGNDC Fig. 3-12: Input Pins AUX1R, AUX1L, AUX2R, AUX2L, AGNDC
Fig. 3-7: Pins FINR, FOPR, FINL, FOPL, DEEML, DEEMR
VDD OUTn VSS Fig. 3-13: Input Pins MCS1, MCS2, DEECTRL Fig. 3-8: Output Pins OUTL, OUTR
AGNDC
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3.5. Control Registers
I2C Subaddress (hex) Number of Bits Mode Function
PRELIMINARY DATA SHEET
Default Values (hex)
Name
SAMPLE RATE CONTROL SR_REG 01 8 w sample rate control bit[7:5] bit[4] not used, set to 0 L/R-bit 0 (WSI = 0 left channel)1) 1 (WSI = 0 right channel)1) Delay-Bit 0 No Delay 1 1 bit Delay sample rate control 000 32-48 kHz 001 26-32 kHz 010 20-26 kHz 011 14-20 kHz 100 10-14 kHz 101 8-10 kHz 110 96 kHz2) 111 automatic detection3) LR_SEL 0hex
bit[3]
SP_SEL
bit[2:0]
SRC_48 SRC_32 SRC_24 SRC_16 SRC_12 SRC_8 SRC_96 SRC_A
ANALOG VOLUME AVOL 02 16 w audio volume control bit[15] Oscillator on/off (for test purpose only) 0 Oscillator on if internally required 1 Oscillator always on deemphasis on/off 0 deemphasis off 1 deemphasis on 0hex OSC
bit[14]
DEEM
bit[13:8] analog audio volume level left: 000000 mute 000001 -75 dB 101100 +0 dB (default) 111000 +18 dB bit[7:6] bit[5:0] not used, set to 0 analog audio volume level right 000000 mute -75 dB 000001 101100 +0 dB (default) 111000 +18 dB
AVOL_L
AVOL_R
1) 2) 3)
see Fig. 2-1 and Fig. 2-2 on page 6 96 kHz allowed for VDD =5 V only 96 kHz is not supported by automatic detection
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PRELIMINARY DATA SHEET
DAC 3555A
I2C Subaddress (hex)
Number of Bits
Mode
Function
Default Values (hex)
Name
Global Configuration GCFG 03 8 w global configuration bit[7] select 3 V - 5 V mode 0 3V 1 5V DAC and Power-Mode bit[5] 0 1 0 1 x1) x1) bit[4] 0 0 0 0 1 1 DAC off - Zero Power DAC off - Analog Standby DAC off - Aux to Line DAC off - Full Power DAC on - Aux to Line DAC on - Full Power INSEL_AUX2 0hex SEL_53V
bit[6:4] bit[6] 0 0 1 1 0 1 bit[3]
PWMD
AUX2 select 0 AUX2 off 1 AUX2 on AUX1 select 0 AUX1 off 1 AUX1 on aux-mono/stereo 0 stereo 1 mono invert right power amplifier 0 not inverted 1 inverted
bit[2]
INSEL_AUX1
bit[1]
AUX_MS
bit[0]
IRPA
1)
don't care
Micronas
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DAC 3555A
3.6. Electrical Characteristics 3.6.1. Absolute Maximum Ratings Symbol TA TS Pmax VSUPA VSUPD VIdig1 Parameter Ambient Temperature Range Storage Temperature Power Dissipation Analog Supply Voltage1) Digital Supply Voltage Input Voltage, digital inputs AVDD0/1 VDD MCS1, MCS2, DEECTRL WSI, CLI, DAI, PORQ, SCL, SCI Pin Name Min.
PRELIMINARY DATA SHEET
Max. 85 125 500
Unit
-40 -40
C C
mW V V V
-0.3 -0.3 -0.3
6 6 VSUPD + 0.3
VIdig2
Input Voltage, digital inputs
-0.3
6
V
IIdig VIana IIana IOaudio IOdig
1) 2) 3)
Input Current, all digital inputs Input Voltage, all analog inputs Input Current, all analog inputs Output Current, audio output2) Output Current, all digital outputs3) OUTL/R
-5 -0.3 -5 -0.2 -10
+5 VSUPA + 0.3 +5 0.2 10
mA V mA A mA
Both pins have to be connected together! These pins are NOT short-circuit proof! Total chip power dissipation must not exceed absolute maximum rating
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
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Micronas
PRELIMINARY DATA SHEET
DAC 3555A
3.6.2. Recommended Operating Conditions Symbol Parameter Pin Name Min. Typ. Max. Unit
Temperature Ranges and Supply Voltages TA TAE VSUPA1 VSUPD VSUPD96 Ambient Temperature Range1) Extended Ambient Temperature Range1) Analog Audio Supply Voltage Digital Supply Voltage Digital Supply Voltage (if sample rate is 96 kHz) AVDD0/1 VDD VDD 0 70 85 3.3 3.3 5.0 5.5 5.5 5.5
C C
V V V
-40
3.02) 2.7 4.75
Relative Supply Voltages VSUPA Analog Audio Supply Voltage in relation to the Digital Supply Voltage AVDD0/1 VSUPD -0.25 V 5.5 V
Analog Reference CAGNDC1 CAGNDC2 Analog Reference Capacitor Analog Reference Capacitor AGNDC AGNDC 1.0 3.3 10
F
nF
Analog Audio Inputs VAI VAI Analog Input Voltage AC, SEL_53V = 0 Analog Input Voltage AC, SEL_53V = 1 AUXnL/R3) AUXnL/R3) 0.35 0.525 0.7 1.05 Vrms Vrms
Analog Filter Input and Output ZAFLO ZAFLI
1) 2) 3) 4)
Analog Filter Load Output4) Analog Filter Load Input4)
FOUTL/R FINL/R
7.5 6 5.0 7.5
k pF k pF
The functionality of the IC in the extended temperature range has been verified by electrical characterization based on sample tests. All data sheet parameters are valid for normal operating temperature range, only. typically operable down to 2.7 V, without loss of performance n = 1 or 2 Please refer to Section 4.2. "Recommended Low-Pass Filters for Analog Outputs" on page 28.
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DAC 3555A
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Analog Audio Output ZLO ZAOL_HP ZAOL_SP Audio Line Output1) (680 Series Resistor required) Analog Output Load HP (47 Series Resistor required) Analog Output Load SP (bridged) Analog Output Load SP (Stereo) I2C Input fI2C Digital Inputs VIH VIL Input High Voltage Input Low Voltage CLI, WSI, DAI, PORQ, SCL, SDA 0.5x VDD 0.2x VDD
V
FINL/R OUTL/R OUTL/R
10 1.0 32 400 32 50 16 100
k nF
pF pF pF
I2C Clock Frequency
SCL
400
kHz
V
External Clock Input VIHx2) VIL I2SDut1_96 I2SDut1_48 Ext. Clock High Voltage Input Low Ext. Clock Duty Cycle of I2S input clock (sample rate=96 kHz) Duty Cycle of I2S input clock (sample rate <=48 kHz) XTI XTI CLI CLI 45 40 0.25x VDDmax 0.75x VDDmin 55 60
V
V
%
%
Crystal Characteristics FP REQ C0 Load Resonance Frequency at Cl = 20 pF Equivalent Series Resistance Shunt (parallel) Capacitance 13.3 14.725 12 3 17 30 5 MHz
pF
Load at CLKOUT Output Cload
1) 2)
Capacitance
CLKOUT
0
50
pF
Please refer to Section 4.1. "Line Output Details" on page 28. extended clock should be AC-coupled via 10 nF
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Micronas
PRELIMINARY DATA SHEET
DAC 3555A
3.6.3. Characteristics At TA = 0 to 70 C, VSUPD = 2.7 to 5.5 V, VSUPA = 3.0 to 5.5 V; typical values at TJ = 27 C, VSUPD = VSUPA = 3.3 V, positive current flows into the IC
Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
Digital Supply IVDD Current Consumption VDD 3.7 5.0 mA A DAC ON1) DAC OFF2) VSUPD = 3.3 V (see I2C register GCFG) 7.0 5.0 mA A DAC ON1) DAC OFF2) VSUPD = 5 V Digital Input Pin - Leakage II Input Leakage Current DAI, TESTEN, PORQ, DEECTRL, MCS1/2
1
A
VGND VI VSUP
Digital Output Pin - Clock Out VOH VOL I2C Bus Ron Output Impedance SCL, SDA 60 Iload = 5 mA, VSUPD = 2.7 V Output High Voltage Output Low Voltage CLKOUT
-0.3
VSUPD 0.3
V V
no load at output
Analog Supply IAVDD Current Consumption Analog Audio AVDD0/1 1.0 630 3.6 8.2 A A mA mA Zero Power Analog Standby Aux to Line Full Power SEL_53 = 0 AVDD = 3.3 V3) 1.0 750 6.0 12.9 A A mA mA Zero Power Analog Standby Aux to Line Full Power SEL_53 = 1 AVDD = 5 V3) (see I2C register GCFG)
1) 2 I S active, 32-bit 2) No I2C traffic 3) 2
mode, fs = 48 kHz
DAC on, I S active, 32-bit mode, fs = 48 kHz, 1 kHz @ 0 dBFS volume = 0 dB
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DAC 3555A
PRELIMINARY DATA SHEET
Symbol PSRRAA
Parameter Power Supply Rejection Ratio for Analog Audio Output
Pin Name AVDD0/1, OUTL/R
Min.
Typ. 50 20
Max.
Unit dB dB dB dB
Test Conditions 1 kHz sine at 100 mVrms 100 kHz sine at 100 mVrms 1 kHz sine at 100 mVrms 100 kHz sine at 100 mVrms
PSRRLO
Power Supply Rejection Ratio for Line Output
AVDD0/1, FINL/R
50 40
Reference Frequency Generation VDCXTI CLI Vxtalout DC Voltage at Oscillator Pins Input Capacitance at Oscillator Pin Voltage Swing at Oscillator Pins, pp Oscillator Start-Up Time Analog Audio VAO Analog Output Voltage AC OUTL/R, FOUTL/R, FINL/R 0.65 0.7 0.75 Vrms SEL_53V = 0, RL > 5 k, Analog Gain = 0 dB Input = 0 dBFS digital 1.0 GAUX Gain from Auxiliary Inputs to Line Outputs Output Power (Headphone) AUXnL/R, FINL/R OUTL/R 1.05 0 1.1 0.5 Vrms dB SEL_53V = 1 f = 1 kHz, sine wave, RL > 5 k 0.5 Vrms to AUXnL/R SEL_53V = 0, RL = 32 , Analog Gain = +3 dB, distortion < 1%, external 47 series resistor required 12 PSP Output Power (Speaker) OUTL/R 120 mW mW SEL_53V = 1 RL = 32 (bridged), Analog Gain = +3 dB, distortion < 10%, SEL_53V = 0, IRPA = 1 SEL_53V = 1 XTI/O XTI/O XTI/O 60 0.5x VSUPA 3 100 50 V pF % VSUPA ms AVDD/VDD 2.5 V
-0.5
PHP
5
mW
280 GAO dGAO1 dGAO2 EGA1 Analog Output Gain Setting Range Analog Output Gain Step Size Analog Output Gain Step Size Analog Output Gain Error OUTL/R OUTL/R OUTL/R OUTL/R
mW 18 dB dB dB 2 dB
-75
3.0 1.5
-75 dB...-54 dB -54 dB...+18 dB -46.5 dBAnalog Gain -54 dB
Analog Gain:
Analog Gain:
-2
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Micronas
PRELIMINARY DATA SHEET
DAC 3555A
Symbol EGA2 EGA3 EdGA SNRAUX
Parameter Analog Output Gain Error Analog Output Gain Error Analog Output Gain Step Size Error Signal-to-Noise Ratio from Analog Input to Line Output Signal-to-Noise Ratio from Analog Input to Headphone Output
Pin Name OUTL/R OUTL/R OUTL/R AUXn, FINL/R AUXn, OUTn
Min.
Typ.
Max. 1 0.5 0.5
Unit dB dB dB dB dB
Test Conditions
-1 -0.5 -0.5
98 93
-40.5 dBAnalog Gain -45 dB -39 dB -48 dB
+18 dBAnalog Gain +18 dBAnalog Gain
SEL_53V = 0: input -40 dB below 0.7 Vrms Analog Gain = 0 dB, BW =20 Hz...20 kHz unweighted
SNR1
Signal-to-Noise Ratio
OUTL/R
89
91
dB
RL 32 (external 47 series resistor required) BW =20 Hz...0.5 fs1) unweighted, Analog Gain = 0 dB, Input = -20 dBFS
FINL/R
90
92
dB
RL 5 k, Rdec 612 BW etc. as above 16 bit I2S, SEL_53V = 0
94 96 98 103 SNR2 Signal-to-Noise Ratio OUTL/R 62
dB dB dB dB(A) dB
32 bit I2S, SEL_53V = 0 16 bit I2S, SEL_53V = 1 32 bit I2S, SEL_53V = 1 32 bit I2S, SEL_53V = 1 RL 32 (external 47 series resistor required) BW = 20 Hz..0.5 fs1) unweighted Analog Gain= -40.5 dB, Input = -3 dBFS
LevMute
Mute Level
OUTL/R
-110
dBV
BW = 20 Hz...22 kHz unweighted, no digital input signal, Analog Gain = Mute 0...0.446 fs (no external filters used) 0.55...7.533 fs (no external filters used) (no external filters used)
RD/A
D/A Pass Band Ripple
OUTL/R, FOUTL/R
-0.1
dB
AD/A
D/A Stop Band Attenuation
40
dB
BWAUX
1)
Bandwidth for Auxiliary Inputs
AUXnL/R, FINL/R
760
kHz
BW = 20 Hz...22 kHz if fs = 96 kHz
Micronas
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DAC 3555A
PRELIMINARY DATA SHEET
Symbol THDALO
Parameter Total Harmonic Distortion from Auxiliary Inputs to Line Outputs
Pin Name AUXnL/R, FINL/R
Min.
Typ.
Max. 0.01
Unit %
Test Conditions BW = 20 Hz...22 kHz, unweighted, RL > 5 k Input 1 kHz at 0.5 Vrms Rdec 612 BW = 20 Hz...0.5 fs1), unweighted, RL > 5 k Input 1 kHz at -3 dBFS Rdec 612 BW = 20 Hz...0.5 fs1), unweighted, RL 32 (47 series resistor required), Analog Gain = 0 dB, Input 1 kHz at -3 dBFS BW = 20 Hz...0.5 fs1), unweighted, RL 32 (speaker bridged), Analog Gain = 0 dB, Input 1 kHz at -3 dBFS f = 1 kHz, sine wave, RL > 7.5 k Analog Gain = 0 dB, Input = -3 dBFS or 0.5 Vrms to AUXnL/R f = 1 kHz, sine wave, OUTL/R: RL 32 (47 series resistor required) Analog Gain = 0 dB, Input = -3 dBFS or 0.5 Vrms to AUXnL/R f = 1 kHz, sine wave, FOUTL/R: RL > 7.5 k OUTL/R: RL 32 (47 series resistor required) Analog Gain = 0 dB, Input = -3 dBFS and 0.5 Vrms to AUXnL/R SEL_53V = 0 RL >> 10 M, referred to VREF SEL_53V = 1 RL >> 10 M, referred to VREF
THDDLO
Total Harmonic Distortion (D/A converter to Line Output)
FINL/R
0.01
%
THDHP
Total Harmonic Distortion (Headphone)
OUTL/R
0.05
%
THDSP
Total Harmonic Distortion (Speaker)
OUTL/R
0.5
%
XTALKLO
Cross-Talk Left/Right Channel (Line Output)
AUXnL/R, FOUTL/R, FINL/R
-70
-80
dB
XTALKHP
Crosstalk Left/Right Channel (Headphone)
OUTL/R
-70
-80
dB
XTALK2
Crosstalk between Input Signal Pairs
AUXnL/R
-70
-80
dB
VAGNDC
Analog Reference Voltage
AGNDC
1.5
V
2.25
V
1)
BW = 20 Hz...22 kHz if fs = 96 kHz
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Micronas
PRELIMINARY DATA SHEET
DAC 3555A
Symbol RIAUX
Parameter Input Resistance at Input Pins
Pin Name AUXnL/R
Min. 12.1 11.6
Typ. 15
Max. 17.9 19.0
Unit k k
Test Conditions TJ = 27 C TA = 0 to 70 C1) Input selected, Aux to Line i = 10 A, referred to VREF TJ = 27 C TA = 0 to 70 C1) Input not selected i = 10 A, referred to VREF TJ = 27 C Analog Standby i = 200 A, referred to VREF full power, Mute i = 10 A, referred to VREF referred to AGNDC Mute referred to AGNDC analog standby, referred to AGNDC analog standby, referred to AGNDC Analog Gain = Mute, switched from analog standby to full power
24.2 23.3
30
35.8 37.9
k k
ROOUT
Output Resistance at Output Pins
OUTL/R
700
ROFILT
Output Resistance of Filter Pins Offset Voltage at Input Pins Offset Voltage at Output Pins Offset Voltage at Filter Output Pins Offset Voltage at Filter Input Pins Difference of DC Voltage at Output Pins
FINL FINR
15 11.25
k k 20 10 20 20 10 mV mV mV mV mV
VOffI VOffO VOffFO VOffFI dVDCPD
AUXnL/R OUTL/R FOUTL/R FINL/R OUTL/R
-20 -10 -20 -20 -10
1)
BW = 20 Hz...22 kHz if fs = 96 kHz
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DAC 3555A
4. Applications 4.1. Line Output Details
Rdec FINL(R) Cline
AVSS
Rin
PRELIMINARY DATA SHEET
2nd-order
11 k 11 k
11 k 220 pF
1.0 nF
AVSS
FOUTL(R)
FOPL(R)
FINL(R)
-
Fig. 4-1: Use of FINL/R as Line Outputs Table 4-1: Load at FINL/R when used as Line Output for external amplifier Filter Order 1st, 2nd, 3rd Rdec 680 Rin > 10 k Frequency 24 kHz 30 kHz Gain Fig. 4-2: 2nd-order low-pass filter Table 4-3: Attenuation of 2nd-order low-pass filter
Rdec:Resistor used for decoupling Cline from FINL(R) to achieve stability
Cline: Capacitive load according to e.g. cable,
-1.5 dB -3.0 dB
amplifier Rin: Input resistance of amplifier
3rd-order
15 k 7.5 k 7.5 k 120 pF
4.2. Recommended Low-Pass Filters for Analog Outputs1)
1st-order
15 k 330 pF FOUTL(R) 15 k
7.5 k
1.8 nF
AVSS
1.8 nF
FOPL(R)
FINL(R)
-
FOUTL(R)
FOPL(R)
FINL(R)
Fig. 4-3: 3rd-order low-pass filter Table 4-4: Attenuation of 3rd-order low-pass filter
-
Fig. 4-1: 1st-order low-pass filter Table 4-2: Attenuation of 1st-order low-pass filter Frequency 24 kHz 30 kHz Gain
Frequency 18 kHz 24 kHz
Gain 0.17 dB
-0.23 dB -3.00 dB
-2.2 dB -3.0 dB
30 kHz
1)
without deemphasis circuit
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Micronas
PRELIMINARY DATA SHEET
DAC 3555A
4.4. Recommendations for MegaBass Filter without Deemphasis
R1 R2 R3 R4 R5 C2
ON OFF
4.3. Recommendations for Filters and Deemphasis
R3 R1 R2 R4 C3 R5 C4
C1 C1 C2
AVSS AVSS AVSS
FOUTL(R)
FOPL(R)
FINL(R)
DEEML(R)
FOUTL(R)
FOPL(R)
FINL(R)
-
-
Fig. 4-4: General circuit schematic Table 4-5: Resistor and Capacitor values 1st order R1 (k) C1 (pF) R2 (k) C2 (pF) R3 (k) C3 (pF) R4 (k) R5 (k) C4 (nF) 0 open 18 open 18 180 0 18 1.8 11 1000 11 180 11 22 1.0 2nd order 3rd order 7.5 560 7.5 270 15 82 7.5 22 1.0
Fig. 4-1: General circuit schematic Table 4-6: Resistor and Capacitor values DC-Gain = 10 dB fc1 = 100 Hz fc2 = 330 Hz R1 (k) C1 (nF) R2 (k) R3 (k) R4 (k) R5 (k) C2 (nF) 13 47 0 15 15 13 47
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DAC 3555A
4.5. Power-up/down Sequence In order to get a click-free power-up/down characteristic, it is recommended to use the following sequences:
90% VDDmax
PRELIMINARY DATA SHEET
VDD
4.5.1. Power-up Sequence 1. Start VDD from 0 to +3.3 V and start AVDD0/1 from 0 to +3.3 V/+5 V. See Fig. 4-2. 2. Release PORQ from 0 to VDD. See Fig. 4-2. 3. Follow the logical power-up sequence in Fig. 4-3.
<0.4 xVDD >1 ms
PORQ
0.6x VDD
AVDD0/1
90% VDD
4.5.2. Power-down Sequence Follow the logical power-down sequence in Fig. 4-3.
Fig. 4-2: Electrical power-up sequence
Power-on Sequence: (Power-down Sequence: vice versa)
- switch on VDD and AVDD0/1 - release PORQ
Zero Power muted
Wait Period t
Power-down Sequence 0s 0s 0s 0s 0s Power-up Sequence 0s 0s 0.5 s DAC on Full Power muted 0s 0s DAC on Full Power unmuted
- prepare analog back-end for line mode or headphone mode. Note: wait 0.5 s before transition to active modes - no wait time required to go back to zero-power mode
Analog Stand-by muted
- switch on active modes Note: Direct transition from zero-power mode to active modes causes plops.
DAC off Aux to Line muted
- set volume - start I2S if applicable1) - mute before leaving this state
1
DAC off Aux to Line unmuted
) if the application allows switching on and off the I2S input, it should be done here
Fig. 4-3: Logical power-up/down sequence
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Micronas
PRELIMINARY DATA SHEET
DAC 3555A
4.6. Typical Applications
A
Fig. 4-4: Application circuit schematic 1: Standard application with analog deemphasis. Oscillator not needed. Package: PMQFP44
Micronas
n
31
DAC 3555A
PRELIMINARY DATA SHEET
A
n
optional
Fig. 4-5: Application circuit schematic 2: MPEG application with analog Megabass and 14.31818 MHz clock input. Package: PMQFP44
32
PUC 303xA extCLK
A
Micronas
PRELIMINARY DATA SHEET
DAC 3555A
Micronas
33
DAC 3555A
5. Data Sheet History 1. Preliminary data sheet: "DAC 3555A Stereo Audio DAC", Jan. 8, 2002, 6251-575-1PD. First release of the preliminary data sheet.
PRELIMINARY DATA SHEET
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-575-1PD
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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Micronas

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