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| Z9960 2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer Features * 2.5V or 3.3V operation * Output frequency up to 200 MHz * Supports PowerPC, and Pentium(R) processors * 21 clock outputs: drive up to 42 clock lines * LVPECL or LVCMOS/LVTTL clock input * Output-to-output skew < 150 ps * Split 2.5V/3.3V outputs * Spread spectrum compatible * Glitch-free output clocks transitioning * Output disable control * Pin-compatible with MPC9600 * Industrial temperature range: -40C to +85C * 48-pin LQFP package S E L A 0 1 S E L B 0 1 S E L C 0 1 Table 1. Frequency Table[1] F B _ S E L 0 1 QA VCO/2 VCO/4 QB VCO/2 VCO/4 QC VCO/2 VCO/4 FB_OUT VCO/8 VCO/12 Block Diagram AVDD Pin Configuration A PLL 0 1 /2 /4 /8 /12 0 1 DQ 0 1 REF FB 1 2 3 4 5 6 0 1 2 3 4 5 C FB_IN SELA VSS FB_IN QA0 QA1 VDDA QA2 QA3 VSSA QA4 QA5 QA6 VDDA 48 47 46 45 44 43 42 41 40 39 38 37 VSS TCLK PECL_CLK PECL_CLK# VDD REF_SEL FB_SEL AVDD SELA SELB SELC VSSC 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 VSSA FB_OUT QB0 QB1 VDDB QB2 QB3 VSSB QB4 QB5 QB6 VDDB REF_SEL TCLK PECL_CLK PECL_CLK# 0 0 1 B DQ SELB Z9960 0 1 DQ 6 0 1 2 3 4 5 6 SELC 13 14 15 16 17 18 19 20 21 22 23 24 VDDC OE# QC6 QC5 VSSC QC4 QC3 VDDC QC2 QC1 QC0 VSSB OE# 0 1 FB DQ FB_OUT FB_SEL Note: 1. Input frequency range: 16 MHz to 33 MHz (FB_SEL = 1), or 25 MHz to 50 MHz (FB_SEL = 0). Cypress Semiconductor Corporation Document #: 38-07087 Rev. *C * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised May 03, 2004 Z9960 Pin Definition Pin Name PECL_CLK PECL_CLK# TCLK QA(6:0) QB(6:0) QC(6:0) FB_OUT No. 3 4 2 38, 39, 40, 42, 43, 45, 46 26, 27, 28, 30, 31, 33, 34 15, 16, 18, 19, 21, 22, 23 35 Type I, PD I, PU I, PD VDDA O VDDB O VDDC O VDD I, PU I, PU I, PU I, PU I, PD I, PU I, PD O PECL Clock Input. PECL Clock Input. External Reference/Test Clock Input. Clock Outputs. See Table 1 for frequency selections. Clock Outputs. See Table 1 for frequency selections. Clock Outputs. See Table 1 for frequency selections. Feedback Clock Output. Connect to FB_IN for normal operation. The divider ratio for this output is set by FB_SEL; see Table 1. A bypass delay capacitor at this output will control Input Reference/ Output Banks phase relationships. Frequency Select Inputs. These inputs select the divider ratio at QA(0:6) outputs. See Table 1. Frequency Select Inputs. These inputs select the divider ratio at QB(0:6) outputs. See Table 1. Frequency Select Inputs. These inputs select the divider ratio at QC(0:6) outputs. See Table 1. Feedback Select Inputs. These inputs select the divide ratio at FB_OUT output. See Table 1. Feedback Clock Input. Connect to FB_OUT for accessing the PLL. Reference Select Input. When high, the PECL clock is selected. And when low, TCLK is the reference clock. Output Enable Input. When asserted low, enables all of the outputs. When pulled high, disables to high impedance all of the outputs except FB_OUT. Power Supply for Bank A Clock Buffers. Power Supply for Bank B Clock Buffers. Power Supply for Bank C Clock Buffers. Power Supply for Core Power Supply for PLL. When AVDD is set low, PLL is bypassed. Common Ground for Bank A. Common Ground for Bank B. Common Ground for Bank C. Common Ground. Pin Description SELA SELB SELC FB_SEL FB_IN REF_SEL OE# VDDA VDDB VDDC VDD AVDD VSSA VSSB VSSC VSS 9 10 11 7 47 6 14 37, 44 25, 32 13, 20 5 8 36, 41 24, 29 12, 17 1, 48 A bypass capacitor (0.1F) should be placed as close as possible to each positive power pin (< 0.2"). If these bypass capacitors are not close to the pins, their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces. Document #: 38-07087 Rev. *C Page 2 of 7 Z9960 Function Table Control Pin REF_SEL AVDD OE# SELA SELB SELC FB_SEL TCLK PLL Bypass, Outputs Controlled by OE# Outputs Enabled Output Bank A at VCO/2 Output Bank B at VCO/2 Output Bank C at VCO/2 Feedback Output at VCO/8 0 PECL_CLK PLL Power Outputs Disabled (except FB_OUT) Output Bank A at VCO/4 Output Bank B at VCO/4 Output Bank C at VCO/4 Feedback Output at VCO/12 1 Overview The Z9960 has an integrated PLL that provides low skew and low jitter clock outputs for high-performance microprocessors. Three independent banks of seven outputs as well as an independent PLL feedback output, FB_OUT, provide exceptional flexibility for possible output configurations. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 400 MHz. This allows a wide range of output frequencies up to 200 MHz. The phase detector compares the input reference clock to the external feedback input. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by FB_SEL select inputs; refer to Table 1. The VCO frequency is then divided down to provide the required output frequencies. Zero Delay Buffer When used as a zero delay buffer the Z9960 will likely be in a nested clock tree application. For these applications the Z9960 offers a low-voltage PECL clock input as a PLL reference. This allows the user to use LVPECL as the primary clock distribution device to take advantage of its far-superior skew performance. The Z9960 then can lock onto the LVPECL reference and translate with near zero delay to low skew outputs. By using one of the outputs as a feedback to the PLL, the propagation delay through the device is eliminated. The PLL works to align the output edge, with the input reference edge thus producing a near-zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. Because the static phase offset is a function of the reference clock, the Tpd of the Z9960 is a function of the configuration used. Document #: 38-07087 Rev. *C Page 3 of 7 Z9960 Absolute Maximum Ratings[2] Input Voltage Relative to VSS:...............................VSS - 0.3V Input Voltage Relative to VDD: ............................. VDD + 0.3V Storage Temperature: .................................-65C to + 150C Operating Temperature: ................................-40C to + 85C Maximum ESD Protection................................................ 2kV Maximum Power Supply: ................................................5.5V Maximum Input Current:.................................................. 20mA Note: 2. The voltage on any input or I/O or pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, VIN and VOUT should be constrained to the range VSS < (VIN or VOUT) < VDD. Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Electrical Characteristics VDD = 2.5V 5%, TA = -40C to +85C Parameter VIL [3] Description Input Low Voltage Input High Voltage Peak-to-Peak Input Voltage PECL_CLK Common Mode Range PECL_CLK Input Low Current (@ VIL = VSS) Input High Current (@ VIH = VDD) Output Low Voltage Output High Voltage Quiescent Supply Current Input Pin Capacitance Test Condition Min. VSS 1.7 500 VDD -1.4 - - Typ. - - - - - - - - 10 4 Max. 0.7 VDD 1000 VDD -0.6 -120 120 0.6 13 - Unit V V mV V A A V V mA pF VIH[3] VPP VCMR[4] IIL[5] IIH[5] VOL[6] VOH [6] IOL = 15 mA IOH = -15 mA VDD and AVDD - 1.8 - - IDD CIN DC Electrical Characteristics VDD = 3.3V +5%, TA = -40C to +85C Parameter VIL[3] VIH [3] Description Input Low Voltage Input High Voltage Peak-to-Peak Input Voltage PECL_CLK Common Mode Range PECL_CLK Input Low Current (@ VIL = VSS) Input High Current (@ VIH = VDD) Output Low Voltage Output High Voltage Quiescent Supply Current Input Pin Capacitance Test Condition Min. VSS 2.0 500 VDD -1.4 - - Typ. - - - - - - - - 15 4 Max. 0.8 VDD 1000 VDD -0.6 -120 120 0.55 - 20 - Unit V V mV V A A V V mA pF VPP VCMR[4] IIL [5] IIH[5] VOL[6] VOH[6] IDD CIN IOL = 24 mA IOH = -24 mA VDD and AVDD - 2.4 - - Notes: 3. The LVCMOS inputs threshold is at 30% of VDD. 4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when HIGH input is within the VCMR range and the input lies within the VPP specification. 5. Inputs have pull-up/pull-down resistors that affect input current. 6. Driving series or parallel terminated 50 (or 50 to VDD/2) transmission lines. Document #: 38-07087 Rev. *C Page 4 of 7 Z9960 AC Electrical Characteristics VDD = 2.5V 5% or 3.3V 5%, TA = -40C to +85C[7] Symbol Fref FrefDC Fvco Tlock Tr / Tf Fout FoutDC tpZL, tpZH tpLZ, tpHZ TCCJ Tskew Tskew Tskew(pp) Tpd Parameter Reference Input Frequency Reference Input Duty Cycle PLL VCO Lock Range Maximum PLL lock Time Output Clocks Rise / Fall Time[8],[9] Maximum Output Frequency Output Duty Cycle[8],[9] Output Enable outputs) Time[8] (all 0.55V to 2.0V, VDD = 3.3V 0.5V to 1.8V, VDD = 2.5V Q (/2) Q (/4) Test Condition FB_SEL = 1 FB_SEL = 0 Min. 16 25 25 200 - 0.1 - 100 50 45 2 2 - Same frequency Different frequency Banks at different voltages VDD = 3.3V VDD = 2.5V - - - - 0 25 Typ. - - - - - - - - - 50 - - 100 - - - - 100 125 Max. 33 50 75 400 10 1.0 - 200 100 55 10 8 - 150 300 400 450 200 225 ps ps ps % ns ns ps ps MHz % MHz ms ns Unit MHz Output Disable Time[8] (all outputs) Cycle to Cycle Jitter[8],[9] Any Output to Any Output Skew[8],[9] Bank to Bank Skew Part to Part Phase Error[8],[9] Skew[10] TCLK or PECL_CLK to FB_IN Note: 7. Parameters are guaranteed by design and characterization. Not 100% tested in production. 8. Outputs loaded with 30pF each. 9. 50 transmission line terminated into VDD/2. 10. Part to Part skew at a given temperature and voltage Document #: 38-07087 Rev. *C Page 5 of 7 Z9960 Ordering Information Ordering Code IMIZ9960AL IMIZ9960ALT 48 LQFP 48 LQFP - Tape and Reel Package Name Package Type Industrial, -40C to +85C Industrial, -40C to +85C Package Drawing and Dimension 48-Lead Thin Plastic Quad Flat Pack (7x7x1.4 mm) A48 51-85135-** PowerPC is a trademark of IBM(R). Pentium(R) is a trademark of Intel Corporation. All product or company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07087 Rev. *C Page 6 of 7 (c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Z9960 Document History Document Title: Z9960 2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer Document #: 38-07087 Rev. *C Rev. ** *A *B *C ECN No. 107123 108715 122772 223804 Issue Date 06/06/01 11/07/01 12/21/02 See ECN Orig. of Change IKA NDP RBI RGL Description of Change Convert from IMI to Cypress Updated AVDD Pin Functionality. Add power up requirements to maximum ratings information Corrected the Ordering information entry Document #: 38-07087 Rev. *C Page 7 of 7 |
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