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| PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT Rev. 02 -- 19 July 2006 Product data sheet 1. General description The PCA9698 provides 40-bit parallel input/output (I/O) port expansion for I2C-bus applications organized in 5 banks of 8 I/Os. At 5 V supply voltage, the outputs are capable of sourcing 10 mA and sinking 25 mA with a total package load of 1 A to allow direct driving of 40 LEDs. Any of the 40 I/O ports can be configured as an input or output. The PCA9698 is the first GPIO device in a new Fast-mode Plus (Fm+) family. Fm+ devices offer higher frequency (up to 1 MHz) and longer, more densely populated bus operation (up to 4000 pF). The device is fully configurable: output ports can be programmed to be totem-pole or open-drain and logic states can change at either the Acknowledge (bank change) or the Stop Command (global change), each input port can be masked to prevent it from generating interrupts when its state changes, I/O data logic state can be inverted when read by the system master. An open-drain interrupt output pin (INT) allows monitoring of the input pins and is asserted each time a change occurs in one or several input ports (unless masked). The Output Enable pin (OE) 3-states any I/O selected as output and can be used as an input signal to blink or dim LEDs (PWM with frequency > 80 Hz and change duty cycle). A `GPIO All Call' command allows to program multiple Advanced GPIOs at the same time even if they have different I2C-bus addresses. This allows optimal code programming when more than one device needs to be programmed with the same instruction or if all outputs need to be turned on or off at the same time (for example, LED test). The Device ID, hard coded in the PCA9698, allows the system master to read manufacturer, part type and revision information. The SMBus Alert feature allows the SMBALERT pins of multiple devices with this feature to be connected together to form a wired-AND signal and to be used in conjunction with the SMBus Alert Response Address. The internal Power-On Reset (POR) or hardware reset pin (RESET) initializes the 40 I/Os as inputs. Three address select pins configure one of 64 slave addresses. The PCA9698 is available in 56-pin TSSOP and HVQFN packages and is specified over the -40 C to +85 C industrial temperature range. 2. Features I 1 MHz Fast-mode Plus I2C-bus serial interface I Compliant with I2C-bus Fast-mode (400 kHz) and Standard-mode (100 kHz) Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT I 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os I 40 configurable I/O pins that default to inputs at power-up I Outputs: N Programmable totem-pole (10 mA source, 25 mA sink) or open-drain (25 mA sink) with controlled edge rate output structure. Default to totem-pole on power-up. N Active LOW Output Enable (OE) input pin 3-states all outputs. Polarity can be programmed to active HIGH through the I2C-bus. Defaults to OE on power-up. N Output state change programmable on the Acknowledge or the STOP Command to update outputs byte-by-byte or all at the same time respectively. Defaults to Acknowledge on power-up. I Inputs: N Open-drain active LOW Interrupt (INT) output pin allows monitoring of logic level change of pins programmed as inputs N Programmable Interrupt Mask Control for input pins that do not require an interrupt when their states change N Polarity Inverter register allows inversion of the polarity of the I/O pins when read I Active LOW SMBus Alert (SMBALERT) output pin allows to initiate SMBus `Alert Response Address' sequence. Own slave address sent when sequence initiated. I Active LOW Reset (RESET) input pin resets device to power-up default state I GPIO All Call address allows programming of more than one device at the same time with the same parameters I 64 programmable slave addresses using 3 address pins I Readable Device ID (manufacturer, device type and revision) I Designed for live insertion in PICMG applications N Minimize line disturbance (IOFF and power-up 3-state) N Signal transient rejection (50 ns noise filter and robust I2C-bus state machine) I Low standby current I -40 C to +85 C operation I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA I Packages offered: TSSOP56, and HVQFN56 3. Applications I I I I I I I I Servers RAID systems Industrial control Medical equipment PLCs Cell phones Gaming machines Instrumentation and test measurement PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 2 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 4. Ordering information Table 1. Ordering information Tamb = -40 C to +85 C Type number PCA9698DGG PCA9698BS Topside mark PCA9698DGG PCA9698BS Package Name TSSOP56 HVQFN56 Description plastic thin shrink small outline package; 56 leads; body width 6.1 mm plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 x 8 x 0.85 mm Version SOT364-1 SOT684-1 5. Block diagram OE PCA9698 IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5 IO0_6 IO0_7 AD0 AD1 AD2 8-bit ADDRESS DECODER read pulse 0 write pulse 0 INPUT/ OUTPUT PORTS BANK 0 BANK 1 SCL SDA LOW PASS INPUT FILTERS I2C-BUS/SMBUS CONTROL BANK 2 BANK 3 IO4_0 IO4_1 IO4_2 IO4_3 IO4_4 IO4_5 IO4_6 IO4_7 8-bit VDD VSS RESET POWER-ON RESET read pulse 4 write pulse 4 INPUT/ OUTPUT PORTS BANK 4 INTERRUPT MANAGEMENT INT/SMBALERT LP FILTER 002aab935 Remark: All I/Os are set to inputs at power-up and RESET. Fig 1. Block diagram of PCA9698 PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 3 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT configuration port register data (Cx[y]) output port register data (Ox[y]) OE OEPOL I/O configuration register data from shift register D FF write configuration pulse CK Q IOx_y Q OUTx VDD data from shift register D FF write pulse CK STOP pulse Q OCH output port register D FF CK INTERRUPT MANAGEMENT input port register D FF read pulse CK polarity inversion register data from shift register write polarity pulse D FF CK 002aab936 Q Mx[y] INT Q input port register data (Ix[y]) Q polarity inversion register data (Px[y]) On power-up or RESET, all registers return to default values. Fig 2. Simplified schematic of the I/Os (IO0_0 to IO4_7) PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 4 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 6. Pinning information 6.1 Pinning SDA SCL IO0_0 IO0_1 IO0_2 VSS IO0_3 IO0_4 IO0_5 1 2 3 4 5 6 7 8 9 56 RESET 55 INT/SMBALERT 54 IO4_7 53 IO4_6 52 IO4_5 51 VSS 50 IO4_4 49 IO4_3 48 IO4_2 47 IO4_1 46 VDD 45 IO4_0 44 IO3_7 43 IO3_6 42 IO3_5 41 IO3_4 40 IO3_3 39 VSS 38 IO3_2 37 IO3_1 36 IO3_0 35 IO2_7 34 VSS 33 IO2_6 32 IO2_5 31 IO2_4 30 OE 29 AD2 002aab932 IO0_6 10 VSS 11 IO0_7 12 IO1_0 13 IO1_1 14 IO1_2 15 IO1_3 16 IO1_4 17 VDD 18 IO1_5 19 IO1_6 20 IO1_7 21 IO2_0 22 VSS 23 IO2_1 24 IO2_2 25 IO2_3 26 AD0 27 AD1 28 PCA9698DGG Fig 3. Pin configuration for TSSOP56 PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 5 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 48 INT/SMBALERT 49 RESET 56 IO0_3 54 IO0_2 53 IO0_1 52 IO0_0 47 IO4_7 46 IO4_6 45 IO4_5 terminal 1 index area IO0_4 IO0_5 IO0_6 VSS IO0_7 IO1_0 IO1_1 IO1_2 IO1_3 1 2 3 4 5 6 7 8 9 43 IO4_4 42 IO4_3 41 IO4_2 40 IO4_1 39 VDD 38 IO4_0 37 IO3_7 36 IO3_6 35 IO3_5 34 IO3_4 33 IO3_3 32 VSS 31 IO3_2 30 IO3_1 29 IO3_0 IO2_7 28 002aab934 50 SDA 51 SCL 55 VSS PCA9698BS IO1_4 10 VDD 11 IO1_5 12 IO1_6 13 IO1_7 14 IO2_0 15 VSS 16 IO2_1 17 IO2_2 18 IO2_3 19 AD0 20 AD1 21 AD2 22 OE 23 IO2_4 24 IO2_5 25 IO2_6 26 VSS 27 Transparent top view Fig 4. Pin configuration for HVQFN56 6.2 Pin description Table 2. Symbol SDA SCL IO0_0 to IO0_7 IO1_0 to IO1_7 IO2_0 to IO2_7 IO3_0 to IO3_7 IO4_0 to IO4_7 VSS VDD AD0 AD1 PCA9698_2 Pin description Pin TSSOP 1 2 3, 4, 5, 7, 8, 9, 10, 12 13, 14, 15, 16, 17, 19, 20, 21 22, 24, 25, 26, 31, 32, 33, 35 36, 37, 38, 40, 41, 42, 43, 44 45, 47, 48, 49, 50, 52, 53, 54 6, 11, 23, 34, 39, 51 18, 46 27 28 HVQFN 50 51 52, 53, 54, 56, 1, 2, 3, 5 6, 7, 8, 9, 10, 12, 13, 14 15, 17, 18, 19, 24, 25, 26, 28 29, 30, 31, 33, 34, 35, 36, 37 38, 40, 41, 42, 43, 45, 46, 47 4, 16, 27, 32, 44, 55[1] 11, 39 20 21 input/output input input/output input/output input/output input/output input/output power supply power supply input input serial data line serial clock line input/output bank 0 input/output bank 1 input/output bank 2 input/output bank 3 input/output bank 4 supply ground supply voltage address input 0 address input 1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Type 44 VSS Description Product data sheet Rev. 02 -- 19 July 2006 6 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT Pin description ...continued Pin TSSOP HVQFN 22 23 48 input input output address input 2 active LOW output enable active LOW interrupt output/ active LOW SMBus alert output active LOW reset input 29 30 55 Type Description Table 2. Symbol AD2 OE INT/SMBALERT RESET [1] 56 49 input HVQFN package die supply ground is connected to both VSS pins and exposed center pad. VSS pins must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the printed-circuit board in the thermal pad region. 7. Functional description Refer to Figure 1 "Block diagram of PCA9698". 7.1 Device address Following a START condition the bus master must send the address of the slave it is accessing and the operation it wants to perform (read or write). The address of the PCA9698 is shown in Figure 5. Slave address pins AD2, AD1 and AD0 choose 1 of 64 slave addresses. To conserve power, no internal pull-up resistors are incorporated on AD2, AD1 and AD0. Address values depending on AD2, AD1 and AD0 can be found in Table 12 "PCA9698 address map". slave address A6 A5 A4 A3 A2 A1 A0 R/W programmable 002aab937 Fig 5. PCA9698 device address The last bit of the first byte defines the operation to be performed. When set to logic 1 a read is selected while a logic 0 selects a write operation. PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 7 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 7.2 Alert response, GPIO All Call and Device ID addresses Three other different addresses can be sent to the PCA9698. * Alert Response address: allows to perform an `SMBus Alert' operation as defined in the SMBus specification. This address is always used to perform a Read operation. See Section 7.11 "SMBus Alert output (SMBALERT)" for more information. * GPIO All Call address: allows to program several Advanced GPIO devices at the same time. This address is always used to perform a Write operation. See Section 7.6 "GPIO All Call" for more information. * Device ID address: allows to read ID information from the device (manufacturer, part identification, revision). See Section 7.5 "Device ID - PCA9698 ID field" for more information. R/W 0 0 0 1 1 0 0 1 1 1 0 1 1 1 0 R/W 0 1 1 1 1 1 0 0 R/W 002aab938 002aab939 002aab940 Fig 6. Alert Response address Fig 7. GPIO All Call address Fig 8. Device ID address 7.3 Command register Following the successful acknowledgement of the slave address + R/W bit, the bus master will send a byte to the PCA9698, which will be stored in the Command register. AI 1 - 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 default at power-up or after RESET register number Auto-Increment 002aab941 Fig 9. Command register The lowest 6 bits are used as a pointer to determine which register will be accessed. Registers are divided into 2 categories: 5-bank register category, and 1-bank register category. Only a command register code with the 7 least significant bits equal to the 28 allowable values as defined in Table 3 "Register summary" will be acknowledged. Reserved or undefined command codes will not be acknowledged. At power-up, this register defaults to 80h, with the AI bit set to `1', and the lowest 7 bits set to `0'. During a write operation, the PCA9698 will acknowledge a byte sent to the OP, PI, IOC, MSK, OUTCONF, ALLBNK, and MODE registers, but will not acknowledge a byte sent to the IPx registers since these are read-only registers. PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 8 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 7.3.1 5-bank register category * * * * * IP - Input registers OP - Output registers PI - Polarity Inversion registers IOC - I/O Configuration registers MSK - Mask interrupt registers If the Auto-Increment flag is set (AI = 1), the 3 least significant bits are automatically incremented after a read or write. This allows the user to program and/or read the 5 register banks sequentially. If more than 5 bytes of data are written and AI = 1, previous data in the selected registers will be overwritten or reread. Reserved registers are skipped and not accessed (refer to Table 3). If the Auto-Increment flag is cleared (AI = 0), the 3 least significant bits are not incremented after data is read or written, only one register will be repeatedly read or written. 7.3.2 1-bank register category * OUTCONF - Output Structure Configuration register * ALLBNK - All Bank Control register * MODE - Mode Selection register If more than 1 byte of data is written or read, previous data in the same register is overwritten independently of the value of AI. 7.4 Register definitions Table 3. Reg # 00h 01h 02h 03h 04h 05h 06h 07h Register summary D5 0 0 0 0 0 0 0 0 D4 0 0 0 0 0 0 0 0 D3 0 0 0 0 0 0 0 0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Name IP0 IP1 IP2 IP3 IP4 Type read only read only read only read only read only Function Input Port register bank 0 Input Port register bank 1 Input Port register bank 2 Input Port register bank 3 Input Port register bank 4 reserved for future use reserved for future use reserved for future use Input Port registers PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 9 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT Table 3. Reg # 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah Register summary ...continued D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 D4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 D3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Name OP0 OP1 OP2 OP3 OP4 PI0 PI1 PI2 PI3 PI4 IOC0 IOC1 IOC2 IOC3 IOC4 MSK0 MSK1 MSK2 MSK3 MSK4 OUTCONF ALLBNK MODE Type read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write Function Output Port register bank 0 Output Port register bank 1 Output Port register bank 2 Output Port register bank 3 Output Port register bank 4 reserved for future use reserved for future use reserved for future use Polarity Inversion register bank 0 Polarity Inversion register bank 1 Polarity Inversion register bank 2 Polarity Inversion register bank 3 Polarity Inversion register bank 4 reserved for future use reserved for future use reserved for future use I/O Configuration register bank 0 I/O Configuration register bank 1 I/O Configuration register bank 2 I/O Configuration register bank 3 I/O Configuration register bank 4 reserved for future use reserved for future use reserved for future use Mask interrupt register bank 0 Mask interrupt register bank 1 Mask interrupt register bank 2 Mask interrupt register bank 3 Mask interrupt register bank 4 reserved for future use reserved for future use reserved for future use output structure configuration control all banks PCA9698 mode selection Output Port registers Polarity Inversion registers I/O Configuration registers Mask Interrupt registers Miscellaneous PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 10 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 7.4.1 IP0 to IP4 - Input Port registers These registers are read-only. They reflect the incoming logic levels of the port pins regardless of whether the pin is defined as an input or an output by the I/O Configuration register. If the corresponding Px[y] bit in the PI registers is set to 0, or the inverted incoming logic levels if the corresponding Px[y] bit in the PI register is set to 1. Writes to these registers have no effect. Table 4. IP0 to IP4 - Input Port registers (address 00h to 04h) bit description Legend: * default value `X' determined by the externally applied logic level. Address 00h 01h 02h 03h 04h Register IP0 IP1 IP2 IP3 IP4 Bit 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 Symbol I0[7:0] I1[7:0] I2[7:0] I3[7:0] I4[7:0] Access R R R R R Value XXXX XXXX* XXXX XXXX* XXXX XXXX* XXXX XXXX* XXXX XXXX* Description Input Port register bank 0 Input Port register bank 1 Input Port register bank 2 Input Port register bank 3 Input Port register bank 4 The Polarity Inversion register can invert the logic states of the port pins. The polarity of the corresponding bit is inverted when Px[y] bit in the PI register is set to 1. The polarity of the corresponding bit is not inverted when Px[y] bits in the PI register is set to 0. 7.4.2 OP0 to OP4 - Output Port registers These registers reflect the outgoing logic levels of the pins defined as outputs by the I/O Configuration register. Bit values in these registers have no effect on pins defined as inputs. In turn, reads from these registers reflect the values that are in the flip-flops controlling the output selection, not the actual pin values. Ox[y] = 0: IOx_y = 0 if IOx_y defined as output (Cx[y] in IOC register = 0). Ox[y] = 1: IOx_y = 1 if IOx_y defined as output (Cx[y] in IOC register = 0). Where `x' refers to the bank number (0 to 4); `y' refers to the bit number (0 to 7). Table 5. OP0 to OP4 - Output Port registers (address 08h to 0Ch) bit description Legend: * default value. Address 08h 09h 0Ah 0Bh 0Ch Register OP0 OP1 OP2 OP3 OP4 Bit 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 Symbol O0[7:0] O1[7:0] O2[7:0] O3[7:0] O4[7:0] Access R/W R/W R/W R/W R/W Value 0000 0000* 0000 0000* 0000 0000* 0000 0000* 0000 0000* Description Output Port register bank 0 Output Port register bank 1 Output Port register bank 2 Output Port register bank 3 Output Port register bank 4 PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 11 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 7.4.3 PI0 to PI4 - Polarity Inversion registers These registers allow inversion of the polarity of the corresponding Input Port register. Px[y] = 0: The corresponding Input Port register data polarity is retained. Px[y] = 1: The corresponding Input Port register data polarity is inverted. Where `x' refers to the bank number (0 to 4); `y' refers to the bit number (0 to 7). Table 6. PI0 to PI4 - Polarity Inversion registers (address 10h to 14h) bit description Legend: * default value. Address 10h 11h 12h 13h 14h Register PI0 PI1 PI2 PI3 PI4 Bit 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 Symbol P0[7:0] P1[7:0] P2[7:0] P3[7:0] P4[7:0] Access R/W R/W R/W R/W R/W Value 0000 0000* 0000 0000* 0000 0000* 0000 0000* 0000 0000* Description Polarity Inversion register bank 0 Polarity Inversion register bank 1 Polarity Inversion register bank 2 Polarity Inversion register bank 3 Polarity Inversion register bank 4 7.4.4 IOC0 to IOC4 - I/O Configuration registers These registers configure the direction of the I/O pins. Cx[y] = 0: The corresponding port pin is an output. Cx[y] = 1: The corresponding port pin is an input. Where `x' refers to the bank number (0 to 4); `y' refers to the bit number (0 to 7). Table 7. IOC0 to IOC4 - I/O Configuration registers (address 18h to 1Ch) bit description Legend: * default value. Address 18h 19h 1Ah 1Bh 1Ch Register IOC0 IOC1 IOC2 IOC3 IOC4 Bit 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 Symbol C0[7:0] C1[7:0] C2[7:0] C3[7:0] C4[7:0] Access R/W R/W R/W R/W R/W Value 1111 1111* 1111 1111* 1111 1111* 1111 1111* 1111 1111* Description I/O Configuration register bank 0 I/O Configuration register bank 1 I/O Configuration register bank 2 I/O Configuration register bank 3 I/O Configuration register bank 4 PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 12 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 7.4.5 MSK0 to MSK4 - Mask interrupt registers These registers mask the interrupt due to a change in the I/O pins configured as inputs. `x' refers to the bank number (0 to 4); `y' refers to the bit number (0 to 7). Mx[y] = 0: A level change at the I/O will generate an interrupt if IOx_y defined as input (Cx[y] in IOC register = 1). Mx[y] = 1: A level change in the input port will not generate an interrupt if IOx_y defined as input (Cx[y] in IOC register = 1). Table 8. MSK0 to MSK4 - Mask interrupt registers (address 20h to 24h) bit description Legend: * default value. Address 20h 21h 22h 23h 24h Register MSK0 MSK1 MSK2 MSK3 MSK4 Bit 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 Symbol M0[7:0] M1[7:0] M2[7:0] M3[7:0] M4[7:0] Access R/W R/W R/W R/W R/W Value 1111 1111* 1111 1111* 1111 1111* 1111 1111* 1111 1111* Description Mask Interrupt register bank 0 Mask Interrupt register bank 1 Mask Interrupt register bank 2 Mask Interrupt register bank 3 Mask Interrupt register bank 4 7.4.6 OUTCONF - output structure configuration register Table 9. Bit Symbol Default OUTCONF - output structure configuration register (address 28h) description 7 OUT4 1 6 OUT3 1 5 OUT2 1 4 OUT1 1 3 OUT067 1 2 OUT045 1 1 OUT023 1 0 OUT001 1 This register controls the configuration of the output ports as open-drain or totem-pole. The 4 least significant bits control the output architecture for bank 0, 2 bits at a time. OUT001 controls the output structure for IO0_0 and IO0_1 OUT023 controls the output structure for IO0_2 and IO0_3 OUT045 controls the output structure for IO0_4 and IO0_5 OUT067 controls the output structure for IO0_6 and IO0_7 The 4 most significant bits control the output architectures for bank 1 to bank 4, each bit controlling one bank. OUT1 controls the output structure for bank 1 (IO1_0 to IO1_7) OUT2 controls the output structure for bank 2 (IO2_0 to IO2_7) OUT3 controls the output structure for bank 3 (IO3_0 to IO3_7) OUT4 controls the output structure for bank 4 (IO4_0 to IO4_7) OUTx = 0: The I/Os are configured with an open-drain structure. OUTx = 1: The I/Os are configured with a totem-pole structure. PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 13 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 7.4.7 ALLBNK - All Bank control register Table 10. Bit Symbol Default ALLBNK - All Bank control register (address 29h) description 7 BSEL 1 6 X 0 5 X 0 4 B4 0 3 B3 0 2 B2 0 1 B1 0 0 B0 0 This register allows all the I/Os configured as outputs to be programmed with the same logic value. This programming is applied to all the banks or a selection of banks. When this register is programmed, values in the Output Port registers are not changed and do not reflect the states of I/Os configured as outputs anymore. * B0 to B4 controls the logic level to be applied to Bank 0 to Bank 4, respectively. - Bx = 0: All the I/Os configured as outputs in the corresponding Bank x are programmed with 0s. - Bx = 1: All the I/Os configured as outputs in the corresponding Bank x are programmed with 1s. * Bit 5 and bit 6 are not used and can be programmed to either `1' or `0'. * BSEL is a filter bit that allows programming of some banks only, and not the others. - BSEL = 0: When Bx = 0, all the I/Os configured as output in the corresponding Bank x are programmed with 0s. When Bx = 1, all the I/Os configured as output in the corresponding Bank x are programmed with their actual value from the corresponding output register. - BSEL = 1: When Bx = 0, all the I/Os configured as output in the corresponding Bank x are programmed with their actual value from the corresponding output register. When Bx = 1, all the I/Os configured as output in the corresponding Bank x are programmed with 1s. 7.4.7.1 Examples * If ALLBNK = 0XX0 0000: All I/Os configured as outputs in Bank 0 to Bank 4 will be programmed with 0s, overwriting values programmed in the five Output Port registers. * If ALLBNK = 1XX1 1111: All I/Os configured as outputs in Bank 0 to Bank 4 will be programmed with 1s, overwriting values programmed in the five Output Port registers. * If ALLBNK = 0XX0 0110: All I/Os configured as outputs in Banks 0, 3, and 4 only will be programmed with 0s, overwriting values programmed in the Output Port registers 0, 3, and 4, while I/Os configured as outputs in Bank 1 and Bank 2 are programmed with values in Output Port registers 1 and 2. PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 14 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT * If ALLBNK = 1XX0 1100: All I/Os configured as outputs in Bank 2 and 3 will be programmed with 1s, overwriting values programmed in the Output Port registers 2 and 3, while I/Os configured as outputs in Bank 0, 1, and 4 are programmed with values in Output Port registers 0, 1, and 4. 7.4.8 MODE - PCA9698 mode selection register Table 11. Bit Symbol Default MODE - mode selection register (address 2Ah) description 7 X 0 6 X 0 5 X 0 4 SMBA 0 3 IOAC 0 2 X 0 1 OCH 1 0 OEPOL 0 This register allows programming of the PCA9698 modes. * OEPOL bit controls the polarity of OE pin. - OEPOL = 0: OE pin is active LOW. - OEPOL = 1: OE pin is active HIGH (equivalent to OE pin). * OCH bit selects the I2C-bus event where the state of the I/Os configured as outputs change. - OCH = 0: outputs change on STOP command. - OCH = 1: outputs change on ACK. * IOAC bit controls the ability of the device to respond to a `GPIO All Call' command (see Section 7.6 "GPIO All Call" for more information), allowing programming of more than one device at the same time. - IOAC = 0: The device cannot respond to a `GPIO All Call' command. - IOAC = 1: The device can respond to a `GPIO All Call' command. Remark: The `GPIO ALL CALL' command defined for the PCA9698 is different from the I2C-bus protocol `General Call' command. * SMBA bit controls the capability of the PCA9698 to respond to a SMBAlert command. - SMBA = 0: PCA9698 does not respond to an Alert Response Address. - SMBA = 1: PCA9698 responds to an Alert Response Address. Bits 5, 6 and 7 are reserved and must be programmed with 0s. * Unused bits (bits 2, 5, 6 and 7) must be programmed with 0s for proper device operation. PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 15 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 7.5 Device ID - PCA9698 ID field The Device ID field is a 3 byte read-only (24 bits) word giving the following information: * 12 bits with the manufacturer name, unique per manufacturer (e.g., Philips) * 9 bits with the part identification, assigned by manufacturer (e.g., PCA9698) * 3 bits with the die revision, assigned by manufacturer (e.g., RevX) The Device ID is read-only, hard-wired in the device and can be accessed as follows: 1. START command 2. The master sends the Reserved Device ID I2C-bus address followed by the R/W bit set to `0' (write): `1111 1000'. 3. The master sends the I2C-bus slave address of the slave device it needs to identify. The LSB is a `Don't care' value. Only one device must acknowledge this byte (the one that has the I2C-bus slave address). 4. The master sends a Re-START command. Remark: A STOP command followed by a START command will reset the slave state machine and the Device ID Read cannot be performed. Also, a STOP command or a Re-START command followed by an access to another slave device will reset the slave state machine and the Device ID Read cannot be performed. 5. The master sends the Reserved Device ID I2C-bus address followed by the R/W bit set to `1' (read): `1111 1001'. 6. The Device ID Read can be done, starting with the 12 manufacturer bits (first byte + 4 MSBs of the second byte), followed by the 9 part identification bits (4 LSBs of the second byte + 5 MSBs of the third byte), and then the 3 die revision bits (3 LSBs of the third byte). 7. The master ends the reading sequence by NACKing the last byte, thus resetting the slave device state machine and allowing the master to send the STOP command. Remark: The reading of the Device ID can be stopped anytime by sending a NACK command. If the master continues to ACK the bytes after the third byte, the PCA9698 rolls back to the first byte and keeps sending the Device ID sequence until a NACK has been detected. For the PCA9698, the Device ID is as shown in Figure 10. manufacturer 0 0 0 0 0 0 0 0 0 0 0 0 part identification 0 0 0 0 0 0 0 0 0 revision 0 0 0 002aab942 Fig 10. PCA9698 ID field PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 16 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 7.6 GPIO All Call A `GPIO All Call' command allows the programming of multiple advanced GPIOs with different I2C-bus addresses at the same time. This allows to optimize code programming when the master needs to send the same instruction to several devices. To respond to such a command and sequence, the PCA9698 needs to have its IOAC bit (register 2Ah, bit 3) set to 1. Devices that have this bit set to 0 do not participate in any `GPIO All Call' sequence. The `GPIO All Call' command can be performed only for a write operation and cannot be used in conjunction with a read operation. * Master initiates a command sequence with the START command, the `GPIO All Call' command associated with a Write command: Start - 1101 110 + Write * All the devices that are programmed to respond to this command will acknowledge * The master then sends the data and all the devices that are programmed to respond acknowledge the byte(s) * The master ends the sequence by sending a STOP or Repeated START command. If the master initiates a `GPIO All Call' sequence with a Read command, none of the slave devices acknowledge. 7.7 Output state change on ACK or STOP State change of the I/Os programmed as outputs can be done either: * during the ACK phase every time an Output Port register is modified. The output state is then updated one-by-one (at a bank level): OCH bit = 1 (register 2Ah, bit 1) * at a STOP command allowing all the outputs to change at the exact same moment: OCH bit = 0 (register 2Ah, bit 1). Change of the outputs at the STOP command allows synchronizing of all the programmed banks in a single device, and also allows synchronizing outputs of more than one PCA9698. Example 1: Only one PCA9698 is used on the I2C-bus and all the outputs need to change at the same time. * OCH bit (Mode Selection Register, bit 1) must be equal to `0'. * The master accesses the device and programs the Output Port register(s) that has (have) to be changed (up to 5 ports). * When done, the master must generate a STOP command. * At the STOP command, the PCA9698 will update the Output Port register(s) that has (have) been programmed and change the output states all at the same time. Example 2: More than one PCA9698 is used on the I2C-bus and all the outputs need to change at the same time. * OCH bit (Mode Selection Register, bit 1) must be equal to `0' in all the devices. * The master device must access the devices one-by-one. * Access to each device must be separated by a Re-START command. PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 17 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT * When all the devices have been accessed, the master must generate a STOP command. * At the STOP command, all the PCA9698s that have been accessed will update their Output Port registers that have been programmed and change the output states all at the same time. Remark: After programming a PCA9698, its state machine will be in a `wait-for-STOP-condition' until a STOP condition is received to update the Output Port registers. Since this state machine will be in a `wait-state', the part will not respond to its own address until this state machine gets out to the idle condition, which means that the device can be programmed only once and is not addressable again until a STOP condition has been received. Remark: The PCA9698 has one level of buffers to store 5 bytes of data, and the actual Output Port registers will get updated on the STOP condition. If the master sends more than 5 bytes of data (with AI = 1), the data in the buffer will get overwritten. 7.8 Power-on reset When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9698 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9698 registers and I2C-bus/SMBus state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device. 7.9 RESET input A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The PCA9698 registers and I2C-bus state machine will be held in their default state until the RESET input is once again HIGH. 7.10 Interrupt output (INT) The open-drain active LOW interrupt is activated when one of the port pins changes state and the port pin is configured as an input and the interrupt on it is not masked. The interrupt is deactivated when the port pin input returns to its previous state or the Input Port register is read. It is highly recommended to program the MSK register, and the IOC registers during the initialization sequence after power-up, since any change to them during Normal mode operation may cause undesirable interrupt events to happen. Remark: Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. Only a Read of the Input Port register that contains the bit(s) image of the input(s) that generated the interrupt clears the interrupt condition. If more than one input register changed state before a read of the Input Port register is initiated, the interrupt is cleared when all the input registers containing all the inputs that changed are read. Example: If IO0_5, IO2_3, and IO3_7 change state at the same time, the interrupt is cleared only when INREG0, INREG2, and INREG3 are read. PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 18 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 7.11 SMBus Alert output (SMBALERT) The interrupt output pin (INT) can also be used as an Alert line (SMBALERT). The SMBALERT pins of multiple devices with this feature can be connected together to form a wired-AND signal and can be used in conjunction with the SMBus Alert Response Address. `SMBus Alert' message is 2 bytes long and allows the master to determine which device generated the Alert (SMBALERT going LOW). When SMBA bit = 1 (register 2Ah, bit 4), the PCA9698 supports the SMBus Alert function and its INT/SMBALERT pin may be connected as an SMBus Alert signal. When a master device senses that an `SMBus Alert' condition is present on the ALERT line (SMBALERT pin of the PCA9698 and/or other devices going LOW): * It accesses the slave device(s) through the Alert Response Address (ARA) associated with a Read Command: Start - 0001 100 + R/W = 1. * If the PCA9698 is the device that generated the `SMBus Alert' condition (and its SMBA bit = 1), it will acknowledge the SMBus Alert command and respond by transmitting its slave address on the SDA line. The 8th bit (LSB) of the slave address byte will be a zero. * The device will acknowledge an ARA command only if the SMBALERT signal has been previously asserted (SMBALERT = LOW). * If more than one device pulls its SMBALERT pin LOW, the highest priority (lowest I2C-bus address) device will win communication rights via standard I2C-bus arbitration during the slave address transfer. * If the PCA9698 wins the arbitration, its SMBALERT pin will become inactive (will go HIGH) at the completion of the slave address transmission (9th clock pulse, NACK phase). * If the PCA9698 loses the arbitration, its SMBALERT pin will remain active (will stay LOW). * The master ends the sequence by sending a NACK and then STOP command. * If the SMBALERT is still LOW after transfer is complete, it means that more than one device made the request. Another full transaction is then required. Remark: If the master initiates an `SMBus Alert' sequence with a Write Command, none of the slave devices acknowledge. The SMBALERT is open-drain and requires a pull-up resistor to VDD. Remark: If the master sends an ACK after reading the I2C-bus slave address, the slave device keeps sending `1's until a NACK is received. PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 19 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 7.12 Output enable input (OE) The configurable active LOW or active HIGH output enable pin allows to enable or disable all the I/Os at the same time. * When a LOW level is applied to the OE pin, with OEPOL = 0 (register 2Ah, bit 4) or a HIGH level is applied to the OE pin, with OEPOL = 1 (register 2Ah, bit 0), all the I/Os configured as outputs are enabled and the logic value programmed in their respective OP registers is applied to the pins. * When a HIGH level is applied to the OE pin, with OEPOL = 0 (register 2Ah, bit 0) or a LOW level is applied to the OE pin, with OEPOL = 1 (register 2Ah, bit 0), all the I/Os configured as outputs are 3-stated. For applications requiring LED blinking with brightness control, this pin can be used to control the brightness by applying a high frequency PWM signal on the OE pin. LEDs can be blinked using the Output Port registers and can be dimmed using the PWM signal on the OE pin thus controlling the brightness by adjusting the duty cycle. Default is OEPOL = 0, so if the OE pin is held HIGH, the outputs are disabled. The OE pin needs to be pulled LOW or OEPOL changed to `1' to enable the outputs. It is recommended to define the required polarity of the OE input by programing the value of OEPOL before programming the configuration registers (IOC register). 7.13 Live insertion The PCA9698 is fully specified for live-insertion applications using IOFF, power-up 3-states, robust state machine, and 50 ns noise filter. The IOFF circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-states circuitry places the outputs in the high-impedance state during power-up and power-down, which prevents driver conflict and bus contention. The robust state machine does not respond until it sees a valid START condition and the 50 ns noise filter will filter out any insertion glitches. The PCA9698 will not cause corruption of active data on the bus nor will the device be damaged or cause damage to devices already on the bus when similar featured devices are being used. 7.14 Standby The PCA9698 goes into standby when the I2C-bus is idle. Standby supply current is lower than 1.0 A (typical). PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 20 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 7.15 Address map Table 12. AD2 VSS VSS VSS VSS VDD VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD VDD PCA9698 address map AD0 VSS VDD VSS VDD VSS VDD VSS VDD SCL SDA SCL SDA SCL SDA SCL SDA VSS VDD VSS VDD VSS VDD VSS VDD SCL SDA SCL SDA SCL SDA SCL SDA A6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh AD1 SCL SCL SDA SDA SCL SCL SDA SDA SCL SCL SDA SDA SCL SCL SDA SDA VSS VSS VDD VDD VSS VSS VDD VDD VSS VSS VDD VDD VSS VSS VDD VDD PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 21 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT PCA9698 address map ...continued AD0 VSS VDD VSS VDD VSS VDD VSS VDD SCL SDA SCL SDA SCL SDA SCL SDA VSS VDD VSS VDD VSS VDD VSS VDD SCL SDA SCL SDA SCL SDA SCL SDA A6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 Address A0h A2h A4h A6h A8h AAh ACh AEh B0h B2h B4h B6h B8h BAh BCh BEh C0h C2h C4h C6h C8h CAh CCh CEh E0h E2h E4h E6h E8h EAh ECh EEh Table 12. AD2 SCL SCL SCL SCL SDA SDA SDA SDA SCL SCL SCL SCL SDA SDA SDA SDA SCL SCL SCL SCL SDA SDA SDA SDA SCL SCL SCL SCL SDA SDA SDA SDA AD1 SCL SCL SDA SDA SCL SCL SDA SDA SCL SCL SDA SDA SCL SCL SDA SDA VSS VSS VDD VDD VSS VSS VDD VDD VSS VSS VDD VDD VSS VSS VDD VDD PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 22 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 8. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 8.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 11). SDA SCL data line stable; data valid change of data allowed mba607 Fig 11. Bit transfer 8.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 12.) SDA SDA SCL S START condition P STOP condition SCL mba608 Fig 12. Definition of START and STOP conditions PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 23 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 8.2 System configuration A device generating a message is a `transmitter'; a device receiving is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves' (see Figure 13). SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER SLAVE 002aaa966 Fig 13. System configuration 8.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; setup and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition 1 2 8 clock pulse for acknowledgement 002aaa987 9 Fig 14. Acknowledgement on the I2C-bus PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 24 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 8.4 Bus transactions Data is transmitted to the PCA9698 registers using `Write Byte' transfers (see Figure 15, Figure 16, Figure 17, and Figure 18). Data is read from the PCA9698 registers using `Read Byte' and `Receive Byte' transfers (see Figure 19 and Figure 20). PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 25 of 47 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 02 -- 19 July 2006 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. PCA9698_2 Philips Semiconductors acknowledge from slave acknowledge from slave slave address command register acknowledge from slave acknowledge from slave acknowledge from slave acknowledge from slave acknowledge from slave STOP condition SDA S A6 A5 A4 A3 A2 A1 A0 0 A 1 0 0 0 1 0 0 0 A DATA BANK 0 A DATA BANK 1 A DATA BANK 2 A DATA BANK 3 A DATA BANK 4 A P START condition R/W AI = 1 write to port when OCH = 0 tv(Q) data out from port when OCH = 0 data valid all banks write to port when OCH = 1 tv(Q) data out from port when OCH = 1 data valid bank 0 data valid bank 1 data valid bank 2 data valid bank 3 data valid bank 4 002aab944 Output Port register bank 0 is selected 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT OE is LOW (with OEPOL = 0) or HIGH (with OEPOL = 1) to observe a change in the outputs. If more than 5 bytes are written, previous data are overwritten. Fig 15. Write to the 5 output ports PCA9698 26 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT slave address acknowledge from slave 0 0 1 D2 D1 D0 A acknowledge from slave bank X determined by D2, D1, D0 DATA BANK X acknowledge from slave AP SDA S A6 A5 A4 A3 A2 A1 A0 0 A AI 0 START condition R/W STOP condition write to port tv(Q) data out from port data X valid 002aab945 OE is LOW (with OEPOL = 0) or HIGH (with OEPOL = 1) to observe a change in the outputs. OCH = 0. When OCH = 1, the change in the port happens at the acknowledge phase. Two, three, or four adjacent banks can be programmed by using the Auto-Increment feature (AI = 1) and change at the corresponding output port becomes effective at the STOP command when OCH = 0, or at each acknowledge when OCH = 1. Fig 16. Write to a specific output port acknowledge from slave slave address SDA S A6 A5 A4 A3 A2 A1 A0 0 A 1 START condition R/W command register acknowledge from slave acknowledge from slave acknowledge from slave 0 D5 D4 D3 D2 D1 D0 A DATA BANK 0 A DATA BANK 1 A 01 0000 for Polarity Inversion register programming bank 0 01 1000 for Configuration register programming bank 0 10 0000 for Mask interrupt register programming bank 0 acknowledge from slave acknowledge from slave acknowledge from slave AI = 1 DATA BANK 2 A DATA BANK 3 A DATA BANK 4 A P STOP condition 002aab946 The programing becomes effective at the Acknowledge. Less than 5 bytes can be programmed by using the same scheme. `D5 D4 D3 D2 D1 D0' refers to the first register to be programmed. If more than 5 bytes are written, previous data are overwritten (the sixth configuration register will roll over to the first addressed configuration register, the sixth Polarity Inversion register will roll over to the first addressed Polarity Inversion register, the sixth Mask interrupt register will roll over to the first addressed Mask interrupt register. Fig 17. Write to the I/O Configuration, Polarity Inversion, or Mask interrupt registers (5 banks) PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 27 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT acknowledge from slave slave address SDA S A6 A5 A4 A3 A2 A1 A0 0 A X START condition R/W 0 command register 1 0 1 acknowledge from slave DATA acknowledge from slave AP STOP condition 0 D1 D0 A AI = 'don't care' 00 for output structure configuration programming 01 for all bank control register programming 10 for mode selection register programming 002aab947 The programming becomes effective at the Acknowledge. If more than 1 byte is written, previous data is overwritten. Fig 18. Write to the output structure configuration, all bank control, or mode selection acknowledge from slave slave address SDA S A6 A5 A4 A3 A2 A1 A0 0 A 1 START condition R/W acknowledge from slave command register acknowledge from slave slave address 0 D5 D4 D3 D2 D1 D0 A Sr A6 A5 A4 A3 A2 A1 A0 1 A repeated START condition R/W AI = 1 D[5:0] = 00 0000 for Input Port register bank 0 D[5:0] = 00 1000 for Output Port register bank 0 D[5:0] = 01 0000 for Polarity Inversion register bank 0 D[5:0] = 01 1000 for Configuration register bank 0 D[5:0] = 10 0000 for Mask Interrupt register bank 0 no acknowledge from master AP STOP condition 002aab948 data from register DATA first byte register determined by D4 D3 D2 D1 D0 A data from register DATA second byte acknowledge from master data from register DATA last byte If AI = 0, the same register is read during the whole sequence. If AI = 1, the register value is incremented after each read. When the last register bank is read, it rolls over to the first byte of the category (see category definition in Section 7.3 "Command register"). The INT signal is released only when the last register containing an input that changed has been read. For example, when IO2_4 and IO4_7 change at the same time and an Input Port register read sequence is initiated, starting with IP0, INT is released after IP4 is read (and not after IP2 is read). Fig 19. Read from Input Port, Output Port, I/O Configuration, Polarity Inversion, or Mask interrupt registers PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 28 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT acknowledge from slave slave address SDA S A6 A5 A4 A3 A2 A1 A0 0 A X START condition R/W 0 acknowledge from slave command register 1 0 1 acknowledge from slave slave address no acknowledge from master data from register DATA last byte AP STOP condition 0 D1 D0 A Sr A6 A5 A4 A3 A2 A1 A0 1 A repeated START condition R/W AI = 'don't care' 00 for output structure configuration register reading 01 for for all bank control register reading 10 for mode selection register reading At this moment master-transmitter becomes master-receiver, and slave-receiver becomes slave-transmitter. 002aab949 If AI = 0 or 1, the same register is read during the all sequence. Fig 20. Read from output structure configuration, all bank control or mode selection registers acknowledge from slave that generated the alert SMBus Alert response address S0 0 0 1 1 0 0 PCA9698 I2C-bus slave address no acknowledge from master 1 A A6 A5 A4 A3 A2 A1 A0 0 A P R/W R/W STOP condition START condition At this moment master-transmitter becomes master-receiver and slave receiver becomes slave-transmitter. SMBALERT signal is released (assuming that only one device generated the alert) SMBALERT 002aab950 Fig 21. SMBus Alert procedure acknowledge from one or several slaves Device ID address S1 1 1 1 1 0 0 I2C-bus slave address of the device to be identified acknowledge from slave to be identified Device ID address 1 1 1 1 0 0 acknowledge from slave to be identified 0 A A6 A5 A4 A3 A2 A1 A0 0 A Sr 1 R/W don't care 1A R/W START condition repeated START condition acknowledge from master acknowledge from master no acknowledge from master MM 11 10 M9 M8 M7 M6 M5 M4 A M3 M2 M1 M0 P8 P7 P6 P5 A P4 P3 P2 P1 P0 R2 R1 R0 A P STOP condition manufacturer name = 000000000000 part identification = 000000000 revision = 000 002aab951 If more than 3 bytes are read, the slave device loops back to the first byte (manufacturer byte) and keeps sending data until the master generates a `No Acknowledge'. Fig 22. Device ID field reading PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 29 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT acknowledge from slave GPIO All Call address SDA S 1 1 0 1 1 1 0 0A1 R/W command register acknowledge from slave(s) acknowledge from slave(s) acknowledge from slave(s) 0 D5 D4 D3 D2 D1 D0 A DATA BANK 0 A DATA BANK 1 A 00 1000 for Output Port register programming bank 0 01 0000 for Polarity Inversion register programming bank 0 01 1000 for Configuration register programming bank 0 10 0000 for Mask interrupt register programming bank 0 acknowledge from slave(s) acknowledge from slave(s) acknowledge from slave START condition AI = 1 DATA BANK 2 A DATA BANK 3 A DATA BANK 4 A P STOP condition 002aab952 Only slave devices with bit IOAC = 1 answer to the GPIO All Call transaction. Output Port register programming becomes effective at the STOP command if OCH = 0, at each acknowledge if OCH = 1. Configuration, Polarity Inversion, and Mask interrupt registers become effective at the acknowledge. Less than 5 bytes can be programmed by using the same scheme. `D5 D4 D3 D2 D1 D0' refers to the first register to be programmed. If more than 5 bytes are written, previous data are overwritten (the sixth Configuration register will roll over to the first addressed Configuration register, the sixth Polarity Inversion register will roll over to the first addressed Polarity Inversion register, the sixth Mask interrupt register will roll over to the first addressed Mask interrupt register). Fig 23. GPIO All Call write to the Output Port, I/O Configuration, Polarity Inversion, or Mask interrupt registers acknowledge from slave(s) slave address SDA S 1 1 0 1 1 1 0 0AX R/W 0 acknowledge from slave(s) command register 1 0 1 0 D1 D0 A acknowledge from slave(s) DATA AP STOP condition START condition AI = 'don't care' 00 for Output structure configuration register programming 01 for All Bank Control register programming 10 for Mode selection register programming 002aab953 Only slave devices with bit 0 IOAC = 1 answer the GPIO All Call transaction. The programming becomes effective at the acknowledge. If more than 1 byte is written, previous data is overwritten. Fig 24. GPIO All Call write to the Output structure configuration, All Bank Control, or Mode selection registers PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 30 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 9. Application design-in information 5V VDD 1.6 k 1.6 k 1.1 k (optional) 2 k 1.1 k (optional) 2 k VDD MASTER CONTROLLER SCL SDA RESET INT OE VSS VDD PCA9698 SCL SDA RESET IO0_0 IO0_1 IO0_2 SUBSYSTEM 1 (e.g., temp. sensor) INT RESET SUBSYSTEM 2 (e.g., counter) A enable controlled switch (e.g., CBT device) B ALARM SUBSYSTEM 3 (e.g., alarm system) INT/SMBALERT IO0_3 OE IO0_4 IO0_5 IO1_0 IO3_7 IO4_0 IO4_7 AD2 AD1 AD0 VSS 24 LED MATRIX VDD ALPHANUMERIC KEYPAD 002aab954 Device address configured as `0010 000x' for this example. IO0_0, IO0_2, IO0_3, IO1_0 to IO3_7 are configured as outputs. IO0_1, IO0_4, IO4_0 to IO4_7 are configured as inputs. Fig 25. Typical application PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 31 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 10. Limiting values Table 13. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VI II VI/O IO(IOx_y) IDD ISS Ptot Tstg Tamb Tj Parameter supply voltage input voltage input current voltage on an input/output pin output current on pin IOx_y supply current ground supply current total power dissipation storage temperature ambient temperature junction temperature operating operating storage Conditions Min -0.5 VSS - 0.5 VSS - 0.5 -20 -65 -40 Max +6 5.5 20 5.5 +50 500 1100 500 +150 +85 125 150 Unit V V mA V mA mA mA mW C C C C PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 32 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 11. Static characteristics Table 14. Static characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Supplies VDD IDD supply voltage supply current Operating mode; no load; fSCL = 1 MHz; AD0, AD1, AD2 = static H or L VDD = 2.3 V VDD = 3.3 V VDD = 5.5 V Istb standby current no load; fSCL = 0 kHz; I/O = inputs; VI = VDD VDD = 2.3 V VDD = 3.3 V VDD = 5.5 V VPOR VIL VIH IOL IL Ci I/Os VIL VIH IOL LOW-level input voltage HIGH-level input voltage LOW-level output current VOL = 0.5 V; VDD = 2.3 V VOL = 0.5 V; VDD = 3.0 V VOL = 0.5 V; VDD = 4.5 V IOL(tot) total LOW-level output current VOL = 0.5 V; VDD = 4.5 V TSSOP56 package HVQFN56 package VOH HIGH-level output voltage IOH = -10 mA; VDD = 2.3 V IOH = -10 mA; VDD = 3.0 V IOH = -10 mA; VDD = 4.5 V ILIH ILIL Ci Co HIGH-level input leakage current LOW-level input leakage current input capacitance output capacitance VDD = 3.6 V; VI/O = VDD VDD = 5.5 V; VI/O = VSS [2] [2] [2] [2] [2] Parameter Conditions Min 2.3 Typ - Max 5.5 Unit V - 135 250 550 200 400 800 A A A [1] 0.15 0.25 0.75 1.70 5 6 6 11 12 15.5 2.0 +0.3VDD 5.5 +1 10 +0.3VDD 5.5 0.86 1.0 +1 +1 7 7 A A A V V V mA A pF V V mA mA mA A A V V V A A pF pF power-on reset voltage LOW-level input voltage HIGH-level input voltage LOW-level output current leakage current input capacitance no load; VI = VDD or VSS -0.5 0.7VDD Input SCL; input/output SDA VOL = 0.4 V VI = VDD or VSS VI = VSS 20 -1 -0.5 2 12 17 25 1.6 2.3 4.0 -1 -1 - PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 33 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT Table 14. Static characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol IOL Co VIL VIH ILI IOH Ci VIL VIH ILI Ci [1] [2] Parameter LOW-level output current output capacitance LOW-level input voltage HIGH-level input voltage input leakage current HIGH-level output current input capacitance LOW-level input voltage HIGH-level input voltage input leakage current input capacitance Conditions VOL = 0.4 V Min 6 -0.5 2 -1 -1 -0.5 0.7VDD -1 - Typ 3 3 3.5 Max 5 +0.8 5.5 +1 +1 5 +0.3VDD 5.5 +1 5 Unit mA pF V V A A pF V V A pF Interrupt INT Inputs RESET and OE Inputs AD0, AD1, AD2 VDD must be lowered to 0.2 V in order to reset part. Each bit must be limited to a maximum of 25 mA and the total package limited to the package maximum limit due to internal busing limits. 11.1 Performance curves 002aab955 002aab956 1.2 IDD (A) 0.8 1.2 IDD (A) 0.8 VDD = 5 V VDD = 5 V 3.3 V 0.4 2.3 V 0.4 3.3 V 2.3 V 0 -50 0 50 Tamb (C) 100 0 -50 0 50 Tamb (C) 100 fSCL = 400 kHz; all I/Os unloaded SCL = VDD; all I/Os unloaded Fig 26. Supply current as a function of temperature Fig 27. Standby current as a function of temperature PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 34 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 600 IDD (A) 400 002aab957 50 Isink (mA) 40 Tamb = -40 C +25 C +85 C 002aab958 30 fSCL = 1 MHz 200 400 kHz 100 kHz 0 2.0 0 3.0 4.0 5.0 VDD (V) 6.0 0 10 20 0.2 0.4 VOL (V) 0.6 All I/Os unloaded; address pins static HIGH or LOW Fig 28. Supply current as a function of supply voltage Fig 29. I/O sink current as a function of LOW-level output voltage (VDD = 2.3 V) 50 Isink (mA) 40 Tamb = -40 C +25 C +85 C 002aab960 50 Isink (mA) 40 Tamb = -40 C +25 C +85 C 002aab959 30 30 20 20 10 10 0 0 0.2 0.4 VOL (V) 0.6 0 0 0.2 0.4 VOL (V) 0.6 Fig 30. I/O sink current as a function of LOW-level output voltage (VDD = 3.0 V) 30 Isource (mA) 20 002aab961 Fig 31. I/O sink current as a function of LOW-level output voltage (VDD = 4.5 V) 50 Isource (mA) 40 002aab962 Tamb = -40 C +25 C +85 C Tamb = -40 C +25 C +85 C 30 20 10 10 0 0 0.2 0.4 0.6 0.8 VDD - VOH (V) 0 0 0.2 0.4 0.6 0.8 VDD - VOH (V) Fig 32. I/O source current as a function of HIGH-level output voltage (VDD = 2 V) Fig 33. I/O source current as a function of HIGH-level output voltage (VDD = 3.3 V) PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 35 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 50 Isource (mA) 40 002aab965 400 VOL (mV) 300 (1) 002aab963 Tamb = -40 C +25 C +85 C 30 200 20 (2) 10 100 (3) 0 0 0.2 0.4 0.6 VDD - VOH (V) 0 -50 (4) 0 50 100 Tamb (C) (1) VDD = 5 V; Isink = 10 mA (2) VDD = 2.3 V; Isink = 10 mA (3) VDD = 5 V; Isink = 1 mA (4) VDD = 2.3 V; Isink = 1 mA Fig 34. I/O source current as a function of HIGH-level output voltage (VDD = 5 V) 600 VDD - VOH (V) 400 Fig 35. I/O LOW-level output voltage as a function of temperature 002aab964 (1) 200 (2) 0 -50 0 50 Tamb (C) 100 (1) VDD = 2.3 V; Isource = 10 mA (2) VDD = 5 V; Isource = 10 mA Fig 36. HIGH-level output voltage as a function of temperature PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 36 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 12. Dynamic characteristics Table 15. Dynamic characteristics Conditions Standard-mode I2C-bus Min fSCL tBUF SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition set-up time for a repeated START condition set-up time for STOP condition data hold time data valid acknowledge time data valid time data set-up time LOW period of the SCL clock HIGH period of the SCL clock fall time of both SDA and SCL signals rise time of both SDA and SCL signals pulse width of spikes that must be suppressed by the input filter enable time disable time data output valid time data input setup time data input hold time valid time on pin INT output output [4][6] [1] [3] Symbol Parameter Fast-mode I2C-bus Min 0 1.3 Max 400 - Fast-mode Plus Unit I2C-bus Min 0 0.5 Max 1000 kHz s Max 100 - 0 4.7 tHD;STA tSU;STA tSU;STO tHD;DAT tVD;ACK tVD;DAT tSU;DAT tLOW tHIGH tf tr tSP 4.0 4.7 4.0 0 0.1 300 250 4.7 4.0 - 3.45 300 1000 50 0.6 0.6 0.6 0 0.1 75 100 1.3 0.6 20 + 0.1Cb[5] 20 + 0.1Cb[5] - 0.9 300 300 50 0.26 0.26 0.26 0 0.05 75 50 0.5 0.26 - 0.45 450 120 120 50 s s s ns s ns ns s s ns ns ns [2] [4][6] [7] Port timing ten tdis tv(Q) tsu(D) th(D) tv(INT_N) Reset tw(rst) trec(rst) trst [1] 100 250 4 0 100 80 40 250 4 4 - 100 250 4 0 100 80 40 250 4 4 - 100 250 4 0 100 80 40 250 4 4 - ns ns ns ns ns s s ns ns ns Interrupt timing trst(INT_N) reset time on pin INT reset pulse width reset recovery time reset time tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. PCA9698_2 Product data sheet Rev. 02 -- 19 July 2006 37 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT [2] [3] [4] [5] [6] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation. A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to bridge the undefined region of SCL's falling edge. Cb = total capacitance of one bus line in pF. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns. [7] SDA tBUF tLOW SCL tr tf tHD;STA tSP tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr tSU;STA tSU;STO P 002aaa986 Fig 37. Definition of timing on the I2C-bus protocol START condition (S) tSU;STA bit 7 MSB (A7) tLOW tHIGH bit 6 (A6) bit 0 (R/W) acknowledge (A) STOP condition (P) 1/f SCL SCL tBUF tr tf SDA tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO 002aab175 Rise and fall times refer to VIL and VIH. Fig 38. I2C-bus timing diagram PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 38 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT START SCL ACK or read cycle SDA 30 % trst RESET 50 % trec(rst) tw(rst) trst IOx_y 50 % output off 002aac018 50 % 50 % Fig 39. Reset timing 13. Test information 2VDD open VSS VDD PULSE GENERATOR VI DUT RT VO RL 500 CL 50 pF 500 002aac019 RL = load resistance. CL = load capacitance includes jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generators. Fig 40. Test circuitry for switching times PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 39 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 14. Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 D E A X c y HE vMA Z 56 29 Q A2 A1 pin 1 index Lp L (A 3) A 1 e bp wM 28 detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 14.1 13.9 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.5 0.1 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 41. Package outline SOT364-1 (TSSOP56) PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 40 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT HVQFN56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 x 8 x 0.85 mm SOT684-1 D B A terminal 1 index area E A A1 c detail X e1 e 15 L 14 1/2 e C b 28 29 e vMCAB wMC y1 C y Eh 1/2 e e2 1 terminal 1 index area 56 Dh 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D(1) 8.1 7.9 Dh 4.45 4.15 E(1) 8.1 7.9 Eh 4.45 4.15 e 0.5 43 42 X 2.5 scale e1 6.5 e2 6.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 5 mm Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT684-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22 Fig 42. Package outline SOT684-1 (HVQFN56) PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 41 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 15. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling integrated circuits. 16. Soldering 16.1 Introduction to soldering surface mount packages There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 16.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow temperatures range from 215 C to 260 C depending on solder paste material. The peak top-surface temperature of the packages should be kept below: Table 16. SnPb eutectic process - package peak reflow temperatures (from J-STD-020C July 2004) Volume mm3 < 350 240 C + 0/-5 C 225 C + 0/-5 C Volume mm3 350 225 C + 0/-5 C 225 C + 0/-5 C Package thickness < 2.5 mm 2.5 mm Table 17. Pb-free process - package peak reflow temperatures (from J-STD-020C July 2004) Volume mm3 < 350 260 C + 0 C 260 C + 0 C 250 C + 0 C Volume mm3 350 to 2000 260 C + 0 C 250 C + 0 C 245 C + 0 C Volume mm3 > 2000 260 C + 0 C 245 C + 0 C 245 C + 0 C Package thickness < 1.6 mm 1.6 mm to 2.5 mm 2.5 mm Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 16.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 42 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 16.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C. 16.5 Package related soldering information Table 18. Package[1] BGA, HTSSON..T[3], LBGA, LFBGA, SQFP, SSOP..T[3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC[5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L[8], PCA9698_2 Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable[4] Reflow[2] suitable suitable suitable not recommended[5][6] not recommended[7] WQCCN..L[8] not suitable suitable suitable suitable not suitable (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. PMFP[9], Product data sheet Rev. 02 -- 19 July 2006 43 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT [1] [2] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages. [3] [4] [5] [6] [7] [8] [9] 17. Abbreviations Table 19. Acronym CDM DUT ESD GPIO HBM I2C-bus LED MM PICMG PLC POR PWM RAID SMBus Abbreviations Description Charged Device Model Device Under Test ElectroStatic Discharge General Purpose Input/Output Human Body Model Inter-Integrated Circuit bus Light Emitting Diode Machine Model PCI Industrial Computer Manufacturers Group Programmable Logic Controller Power-On Reset Pulse Width Modulation Redundant Array of Independent Discs System Management Bus PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 44 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 18. Revision history Table 20. Revision history Release date 20060719 Data sheet status Product data sheet Change notice Supersedes PCA9698_1 Document ID PCA9698_2 Modifications: * * * * Descriptive title of data sheet modified (added "Fm+") Section 1 "General description": 2nd paragraph re-written Table 12 "PCA9698 address map": filled fields for AD0 for addresses E0h through EEh Table 14 "Static characteristics": added Table note 2 and references to it under subsection "I/Os", symbols IOL and IOL(tot) Product data sheet - PCA9698_1 (9397 750 13751) 20060224 PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 45 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 19. Legal information 19.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.semiconductors.philips.com. 19.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Philips Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Philips Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. to result in personal injury, death or severe property or environmental damage. Philips Semiconductors accepts no liability for inclusion and/or use of Philips Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- Philips Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.semiconductors.philips.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Philips Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 19.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, Philips Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- Philips Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- Philips Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a Philips Semiconductors product can reasonably be expected 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of Koninklijke Philips Electronics N.V. 20. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com PCA9698_2 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 -- 19 July 2006 46 of 47 Philips Semiconductors PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 21. Contents General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 7 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 7 Alert response, GPIO All Call and Device ID addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.3 Command register . . . . . . . . . . . . . . . . . . . . . . 8 7.3.1 5-bank register category. . . . . . . . . . . . . . . . . . 9 7.3.2 1-bank register category. . . . . . . . . . . . . . . . . . 9 7.4 Register definitions . . . . . . . . . . . . . . . . . . . . . . 9 7.4.1 IP0 to IP4 - Input Port registers . . . . . . . . . . . 11 7.4.2 OP0 to OP4 - Output Port registers . . . . . . . . 11 7.4.3 PI0 to PI4 - Polarity Inversion registers. . . . . . 12 7.4.4 IOC0 to IOC4 - I/O Configuration registers. . . 12 7.4.5 MSK0 to MSK4 - Mask interrupt registers . . . 13 7.4.6 OUTCONF - output structure configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.4.7 ALLBNK - All Bank control register. . . . . . . . . 14 7.4.7.1 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.4.8 MODE - PCA9698 mode selection register . . 15 7.5 Device ID - PCA9698 ID field . . . . . . . . . . . . . 16 7.6 GPIO All Call. . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.7 Output state change on ACK or STOP . . . . . . 17 7.8 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 18 7.9 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.10 Interrupt output (INT) . . . . . . . . . . . . . . . . . . . 18 7.11 SMBus Alert output (SMBALERT) . . . . . . . . . 19 7.12 Output enable input (OE) . . . . . . . . . . . . . . . . 20 7.13 Live insertion . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.14 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.15 Address map. . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 Characteristics of the I2C-bus. . . . . . . . . . . . . 23 8.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.1.1 START and STOP conditions . . . . . . . . . . . . . 23 8.2 System configuration . . . . . . . . . . . . . . . . . . . 24 8.3 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.4 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 25 9 Application design-in information . . . . . . . . . 31 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 10 11 11.1 12 13 14 15 16 16.1 16.2 16.3 16.4 16.5 17 18 19 19.1 19.2 19.3 19.4 20 21 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Performance curves . . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Test information. . . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 33 34 37 39 40 42 42 42 42 42 43 43 44 45 46 46 46 46 46 46 47 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. For more information, please visit: http://www.semiconductors.philips.com. For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com. Date of release: 19 July 2006 Document identifier: PCA9698_2 |
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