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| INTEGRATED CIRCUITS DATA SHEET SAA2520 Stereo filter and codec for MPEG layer 1 audio applications Preliminary specification File under Integrated Circuits, IC01 August 1993 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications FEATURES * Stereo filtering and codec functions in a single chip * MPEG coded interface * Filtered data interface * Baseband audio data interface * LT interface to microcontroller * Clock generator * Low operating voltage capability. ORDERING INFORMATION EXTENDED TYPE NUMBER SAA2520GP(1) Note 1. SOT205-1; 1996 August 26. PACKAGE PINS 44 PIN POSITION QFP MATERIAL plastic GENERAL DESCRIPTION SAA2520 The SAA2520 performs the sub-band filtering and audio frame codec functions to provide efficient audio compression/decompression for MPEG (11172-3) Layer1 applications. It is capable of functioning as a stand-alone decoder but requires the addition of an adaptive masking threshold processor (SAA2521) in order to function as a highly efficient encoder. CODE SOT205AG handbook, full pagewidth CLK22 CLK24 X22OUT X24OUT X22IN X24IN 39 40 41 42 43 V DD 28,44 8 SBDA SBCL SBWS SBMCLK 38 1 FS256 CLOCK GENERATOR SAA2520 SBDIR SBEF 7 11 SUB-BAND SERIAL INTERFACE 9 10 12 STEREO SUB-BAND FILTER PROCESSOR 2 CODEC 3 4 MUTEDAC DEEMDAC ATTDAC SWS SCL SDA 20 19 21 BASEBAND SERIAL INTERFACE FILTERED DATA INTERFACE MICROPROCESSOR INTERFACE & CONTROL 5,37 V SS 18 17 16 15 FRESET 14 13 36 35 34 33 32 22 29 6 MLB125 FDAF FDAC SYNCDAI LTCNT0 LTCLK LTENA PWRDWN URDA FSYNC FDIR LTCNT1 LTDATA RESET Fig.1 Block diagram. August 1993 2 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 43 X24OUT 41 X22OUT 35 LTCNT0 36 LTCNT1 handbook, full pagewidth FS256 MUTEDAC DEEMDAC ATTDAC V SS URDA SBDIR SBDA SBCL 34 LTENA 39 CLK24 38 CLK22 42 X24IN 40 X22IN 44 VDD 37 V SS 1 2 3 4 5 6 7 8 9 33 LTCLK 32 LTDATA 31 T0 30 T1 29 RESET SAA2520 28 VDD 27 DSC0 26 DSC1 25 DSC2 24 DSC3 23 DSC4 SBWS 10 SBEF 11 12 SYNCDAI 13 14 15 FSYNC 16 17 18 19 20 21 22 MLB126 SBMCLK SWS SDA Fig.2 Pin configuration. handbook, full pagewidth AUDIO AMPLIFIER digital audio interface DAC control SAA2520 system micro interface MICROCONTROLLER power down reset MLB127 MPEG interface PWRDWN FDIR FDAC FRESET FDAF SCL MPEG source Fig.3 MPEG decoder system data flow diagram. August 1993 3 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications PINNING SYMBOL FS256 MUTEDAC DEEMDAC ATTDAC VSS URDA SBDIR SBDA SBCL SBWS SBEF SBMCLK SYNCDAI FDIR FRESET FSYNC FDAF FDAC SCL SWS SDA PWRDWN DSC4 DSC3 DSC2 DSC1 DSC0 VDD RESET T1 T0 LTDATA LTCLK PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 (Filtered)-I2S DESCRIPTION SAA2520 TYPE I/O O O O I I I/O I/O I/O I O O O O O I/O I/O I/O I/O I/O I clock; 256 x sample frequency. 12 mA 3-state output + CMOS input with pull-down DAC control/output expander DAC control/output expander DAC control/output expander supply ground (0 V) unreliable drive processing data; CMOS level sub-band I2S direction: (SWBS, SBCL, SBDA); CMOS level sub-band I2S data; 4 mA, 3-state output + CMOS input with pull-down sub-band I2S bit clock; 4 mA, 3-state output + CMOS input with pull-down sub-band sub-band I2S I2S word select; 4 mA, 3-state output + CMOS input with pull-down byte error flag; CMOS level sub-band I2S clock, 6.144 MHz locked to FS256; 8 mA, 3-state output + CMOS input with pull-down DAI synchronization pulse (Filtered)-I2S direction: (FDAC, FDAF, SDA); reset signal for SAA2521 Filtered-I2S sync signal for SAA2521 Filtered-I2S pull-down Filtered-I2S sub-band codec data; 4 mA, 3-state output + CMOS input with pull-down I2S bit clock; 4 mA, 3-state output + CMOS input with pull-down I2S-word select; 4 mA, 3-state output + CMOS input with pull-down I2S baseband data filter; 4 mA, 3-state output + CMOS input with pull-down power-down mode; CMOS level test pin test pin test pin test pin test pin positive supply voltage (+5 V) system reset; CMOS level with pull-down and hysteresis test pin; do not connect test pin; do not connect LT interface data; 4 mA, 3-state output + CMOS input with pull-down LT interface bit clock; CMOS level sub-band filter data; 4 mA, 3-state output + CMOS input with I I/O I August 1993 4 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SYMBOL LTENA LTCNT0 LTCNT1 VSS CLK22 CLK24 X22IN X22OUT X24IN X24OUT VDD PIN 34 35 36 37 38 39 40 41 42 43 44 DESCRIPTION LT interface enable; CMOS level LT interface control; CMOS level LT interface control; CMOS level supply ground (0 V) 22.5792 MHz buffered output 24.576 MHz buffered output 22.5792 MHz crystal input 22.5792 MHz crystal output 24.576 MHZ crystal input 24.576 MHz crystal output positive supply voltage (+5 V) SAA2520 TYPE I I I O O I O I O August 1993 5 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 handbook, full pagewidth from SAA2521 ALLOCATION & SCALE FACTOR INFORMATION TABLE allocation information and scale factor indices SYNC AND CODING INFORMATION base band samples SUB-BAND FILTER sub - band samples SCALING & QUANTIZATION FORMATTER quantized samples MPEG OUTPUT DATA MLB128 Fig.4 Encoding mode. handbook, full pagewidth sync/coding CONTROL allocation scale factor MPEG input data DE- FORMATTER quantized samples SCALE FACTOR ARRAY & ALLOCATION sub-band samples DEQUANTIZATION MULTIPLY OUTPUT CONTROL SUB-BAND FILTER base band samples MLB129 Fig.5 Decoding mode. August 1993 6 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications FUNCTIONAL DESCRIPTION Coding System MPEG coding achieves highly efficient digital encoding of audio signals by using an algorithm based on the characteristics of the human auditory system. The broad-band audio signal is split into 32 sub-band signals during encoding. For each of the sub-band signals the masking threshold is calculated. The samples of the sub-bands are incorporated in the signal with an accuracy that is determined by the signal to masking threshold ratio for that sub-band. During decoding, the sub-band signals are reconstructed and combined into a broadband audio signal. The integrated filter processor performs the splitting (encoding) and joining (decoding) including the corresponding formatting functions. For encoding, a SAA2521 is necessary to calculate the masking threshold and required accuracy of the sub-band samples. Encoding (See Fig.4) An encoding algorithm table is used during the coding process but, due to the Adaptive Allocation functions of the SAA2521, this may change with every frame. The table is therefore calculated for each frame by the SAA2521 and then transferred to the SAA2520. A frame contains 2 x 384 samples of Left and Right audio data. This results in 12 samples per sub-band (32 sub-bands). The samples of the greatest amplitude are used to determine the scale factor for a given sub-band. All samples are then scaled to represent a fraction of the greatest amplitude. Once scaled, the samples are quantized to reduce the number of bits to correspond with the allocation table as calculated by the SAA2521. Synchronization and coding information data is then added to result in a fully encoded MPEG signal. Decoding (See Fig.5) All essential information (synchronization, system information, scale factors and encoded sub-band samples) are conveyed by incoming data. Decoding is repeated for every frame. SAA2520 After sync and coding information, allocation data and the scale factors are used to correctly fill the scale factor array. This is followed by a process of multiplication to provide de-quantization and de-scaling of the samples. The decoded sub-band samples, which are represented in 24-bit two's complement notation, are processed by the sub-band filters and reconstituted into a single digital audio signal. RESET Reset must be active under the following conditions: 1. From system power-up until CLK24 has executed more than 24 clock cycles. 2. From the falling edge of PWRDWN for a period equivalent to 24 cycles of CLK24 + oscillator start-up time. This is typically >1 ms, however, this value is crystal dependent. PWRDWN A HIGH input applied to this pin will halt all internally generated clock signals. As a result, chip activity will halt completely with outputs frozen in the state which was current at the time of PWRDWN activation. The bi-directional outputs: LTDATA, FDAC, FDAF, SDA, SBWS, SBCL and SBDA will be 3-stated. Crystal Oscillators A 24.576 MHz crystal together with some external components form the 24.576 MHz oscillator (pins 42 and 43). Similarly a 22.5792 MHz oscillator (pins 40 and 41) is formed by similar peripheral components together with an appropriate crystal (see Fig.6). The component values shown apply only to crystals from the Philips 4322 156 series which exhibit an equivalent series resistance of 40 . August 1993 7 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 handbook, full pagewidth C2 33 pF 22.5792 MHz X1 R1 1 M X22IN 40 C1 33 pF X22OUT R2 1 k X24IN 41 42 SAA2520 C3 33 pF 24.576 MHz X2 R4 1 M X24OUT R3 1 k MLB130 43 C4 33 pF Component values apply only to crystals from the Philips 4322 156 series. Fig.6 Crystal oscillator components. channel SWS left 32 bits right SCL 1 SDA bit : 1 7 MSB 1 6 1 5 1 4 0 2 0 1 0 0 LSB 1 7 MSB 1 6 1 5 1 4 MLA923 - 2 18 bits 13 bits Fig.7 Transfer of SDA data (Standard I2S default format). August 1993 8 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 channel SWS left 32 bits right SCL 18 bits SDA bit : 1 7 1 6 1 5 1 4 1 3 0 2 0 1 0 0 LSB 1 7 1 6 1 5 1 4 MLA924 - 2 14 bits MSB MSB Fig.8 Transfer of SDA data (alternative format). channel SWS left 32 bits right SCL 1 FDAC/ FDAF bit : 2 3 MSB 2 2 2 1 2 0 0 2 0 1 0 0 LSB 2 3 MSB 2 2 2 1 2 0 MLA925 - 2 7 bits Fig.9 Transfer of FDAF and FDAC (filtered) data. August 1993 9 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 channel SWS L R L R L R L R L R L R L R FSYNC sub-band 31 0 1 31 0 1 MBC148 - 1 Fig.10 SWS related to phase of FSYNC. Baseband Interface Signals The interface between the SAA2520 and the baseband input/output circuitry consists of the following signals: SWS SCL SDA FDIR bi-directional bi-directional bi-directional output word (channel) select bit clock baseband data decoding mode (direction control) FS 64FS The SWS signal indicates the channel of the sample signal (either LEFT or RIGHT) and is equal to the sampling frequency FS. Operating at a frequency of 64 times that is used for sampling, the bit clock dictates that each SWS period contains 64 SDA data bits. Of these, a maximum of 36 are used to transfer data (samples may have a length up to 18-bits). Samples are transferred most significant bit first. Both SWS and SDA change state at the negative edge of SCL. This baseband data is transferred between the SAA2520 and the input/output using either Standard I2S (default) or the alternative format shown in Fig.8. August 1993 10 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications Interface between SAA2520 and SAA2521 consists of the following signals: FILTERED-I2S INTERFACE SWS SCL FDAC FDAF FSYNC bi-directional bi-directional bi-directional bi-directional output word select (common to I2S) bit clock (common to codec data filter data synchronization FS/32 I2S) FS 64FS SAA2520 Filtered data is transferred between SAA2520 filter/codec functions and the SAA2521 using the format shown in Fig.9. The frequency of the SWS signal is equal to the sample frequency FS and the bit clock SCL is 64 times the sample frequency. Each period of SWS contains 64 data-bits, 48 of which are used to transfer data. The half period in which SWS is LOW is used to transfer the information of the LEFT channel while the following half period during which SWS is HIGH carries the data of the RIGHT channel. The 24-bit samples are transferred most significant bit first. This bit is transferred in the bit clock period with a 1-bit delay following the change in SWS. Both SWS and FDAF/FDAC change state at the negative edge of SCL. The SAA2521 may be synchronized to the sub-band codec using the FSYNC signal, which defines the SWS period in which the samples of sub-band 0 (containing the lowest frequency components) are transferred (see Fig.10). SAA2521 AND INPUT/OUTPUT MODE CONTROL The operation of SAA2521 and the input/output circuitry is controlled by three signals shown in Table 1. FRESET and SYNCDAI are given whenever: - - - - - FS256, SCL and SWS outputs switch between high and low impedance FS256 frequency is changed (12.288/11.2896/8.192 MHz) FDIR is switching bit rate is changing system reset is active MPEG CODED INTERFACE The interface that carries the MPEG coded signal uses the following signals: The MPEG I2S interface SBWS SBCL SBDA SBEF SBDIR URDA bi-directional bi-directional bi-directional input input input word selection bit clock sub-band coded data error signal direction of data flow unreliable encoded data signal Operation is further controlled by: The SBMCLK signal is the main frequency from which other clock signals are derived. In encode mode this division is performed internally. In decode mode the external source should provide SBWS and SBCL. The frequency of the signal is equal to 1/32nd of the bit rate. The frequency of the bit clock SBCL is twice that of the bit rate. Some examples of the frequencies are given in Table 2. August 1993 11 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications Table 1 FRESET FDIR SYNCDAI Table 2 SAA2521 input/output control. output output output request a general reset of SAA2521 SAA2520 '1' for decoding and '0' for encoding mode (common to I2S) pulse for synchronization of digital input/output (TDA1315) Frequency examples. SBWS FREQUENCY (kHz) 12 8 6 4 SBCL FREQUENCY (kHz) 768 512 384 256 BIT RATE (k BITS/s) 384 256 192 128 ENCODE MODE The following modes are supported: Stereo or 2-channel mono with allowable bit rates of 384, 256, 192 and 128 kbits/s; audio sampling frequencies of 48, 44.1 and 32 kHz. DECODE MODE The following modes are supported: Stereo and joint stereo, 2-channel mono and 1-channel mono with allowable bit rates in the range 448 to 32 k bits/s; audio sampling frequencies of 48, 44.1 and 32 kHz. August 1993 12 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 T t fH t fL FS256 t d1 SCL t sL t h2 SWS, SDA, FDAF, FDAC, FSYNC output t d2 t su t h1 Tc t sH t d1 SDA, FDAF, FDAC input MEA642 - 3 Fig.11 Filtered I2S interface timing (master mode - FS256, SCL and SWS are input). Notes to Fig.11 T FS256 cycle time (fs = 48 kHz) FS256 cycle time (fs = 44.1 kHz) FS256 cycle time (fs = 32 kHz) SCL cycle time FS256 HIGH time (fs = 48 kHz) FS256 HIGH time (fs = 44.1 kHz) FS256 HIGH time (fs = 32 kHz) FS256 LOW time (fs = 48 kHz) FS256 LOW time (fs = 44.1 kHz) FS256 LOW time (fs = 32 kHz) SCL HIGH time SCL LOW time SDA, FDAF, FDAC input set-up before FS256 HIGH SDA, FDAF, FDAC input hold after FS256 HIGH SDA, FDAF, FDAC output hold after FS256 HIGH FS256 HIGH to SCL, SWS, SDA, FDAF, FDAC output valid 81.4 ns nominal 88.6 ns nominal 122.1 ns nominal 4T ns nominal 35 ns 38 ns 35 ns 35 ns 38 ns 75 ns 2T - 20 ns 2T - 20 ns 20 ns 30 ns 0 ns 50 ns Tc tfH tfL tSH tSL tS tH1 tH2 tD1, 2 August 1993 13 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 t fL FS256 Tc T t fH t sH SCL t sL t h1 SDA, FDAF, FDAC, FSYNC output td t su SWS, SDA, FDAF, FDAC input t h2 MEA644 - 3 Fig.12 Filtered I2S interface timing (slave mode - FS256, SCL and SWS are input). Notes to Fig.12 tfH tfL tsH tsL tH1 tD ts tH2 FS256 HIGH time FS256 LOW time SCL HIGH time SCL LOW time SDA, FDAF, FDAC output hold after SCL HIGH SCL HIGH to SDA, FDAF FDAC output valid SDA, FDAF, FDAC input valid after SCL HIGH SDA, FDAF, FDAC input hold after SCL HIGH 35 ns 35 ns T + 35 ns T + 35 ns 2T - 15 ns 3T + 60 ns 20 ns T + 20 ns August 1993 14 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 FRESET SYNCDAI FDIR SDA FDAF FDAC , t d0 t d2 t d3 t d4 t d6 t d7 HIGH Z t sH t d1 t d5 HIGH Z SDA HIGH Z HIGH Z SWS FS256 SCL t d8 FDAF FDAC HIGH Z HIGH Z t d9 SWS FS256 SCL MEA646 - 1 Fig.13 Mode switch timing. Notes to Fig.13 tDO tSH tD1 tD2 tD3 tD4 FRESET HIGH to SYNCDAI HIGH SYNCDAI HIGH time SYNCDAI LOW to FRESET LOW FDIR hold to FRESET HIGH FRESET HIGH to FDIR valid SDA change to high impedance after FRESET HIGH SDA remains high impedance after FRESET LOW FDAF, FDAC change to high impedance after FRESET HIGH FDAF, FDAC remain high impedance 300 ns 1280 ns 790 ns 20 ns 20 ns 0 ns 170 ns 0 ns 170 ns 20 ns tD5 tD6 tD7 August 1993 15 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications Notes to Fig.13 after FRESET HIGH tD8 tD9 FS256, SWS, SCL change to high impedance before SYNCDAI HIGH FS256, SWS, SCL remain HIGH impedance after SYNCDAI HIGH 460 ns 140 ns 140 ns SAA2520 32 bits SBWS SBCL 1 SBDA bit : 00 01 MSB 0 2 0 3 1 0 1 1 1 2 1 3 1 4 1 5 LSB 11 67 MSB 1 8 1 9 2 0 2 1 2 2 15 bits 1 SBEF byte 0 byte 1 byte 2 MEA649 - 2 Fig.14 Transferring MPEG data to and from the SAA2520. August 1993 16 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications MPEG Coded Interface (Sub-band I2S) The MPEG coded data is transferred to and from the SAA2520 using the format shown in Fig.14. Each period of SBWS contains 64 data bits, 32 of which are used to convey data. The half-period during which SBWS is logic 0 is used to transfer the first 16-bits (0 to 15) of a sub-band slot. The remaining half-period during which SBWS is logic 1 carries the remaining 16-bits (16 to 31). Thus one period of SBWS corresponds with one slot of the sub-band signal. Bits 0 and 16 are transferred in the bit clock period, one bit-time after the change in SBWS. Both SBWS and SBDA change state during the negative edge of SBCL. In decode mode a byte error flag SBEF is also transferred. This occurs approximately in the middle of the corresponding byte (byte 0 = bits 0 to 7, byte 1 = bits 8 to 15 etc). Table 3 Modes and source signals. source of: Mode Encode Encode Decode Decode Notes 1. During encoding the SBEF signal is `don't care'. FDIR 0 0 1 1 SBDIR 0 1 0 1 SBWS INT EXT INT EXT SBCL INT EXT INT EXT SBDA INT EXT INT EXT SBEF ------EXT EXT SBMCLK INT INT INT INT Encoding mode SAA2520 SBCL, SBWS and SBDA are generated by the SAA2520. However, if the SBDIR signal is logic 1, the output buffers are not enabled and these signals do not appear on the pins. This mode is available to permit a change of operating mode whilst the bus signals are driven from an external source. Decoding mode SBCL, SBWS and SBDA are generated by an external source. Table 3 contains a summary of the source signals in the various modes. note 1 note 2 note 3 2. Incoming data is not decoded. The SAA2520 operates in the encoding mode and the data does not enter the interface. 3. Operation is undefined. The SAA2520 is in decoding mode whilst the SBWS, SBCL and SBDA output drivers are enabled. August 1993 17 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 t mL SBMCLK Ts t mH SBCL SBWS SBDA Fig.15 Sub-band I2S interface timing (master mode - SBCL, SBWS and SBDA are output). t cL t cH t d1 t d2 Tsc MEA645 - 2 Notes to Fig.15 T tmH tmL Tc SBMCLK cycle time SBMCLK HIGH time SBMCLK LOW time SBCL cycle time (384 kB/s) SBCL cycle time (256 kB/s) SBCL cycle time (192 kB/s) SBCL cycle time (128 kB/s) SBCL HIGH time (384 kB/s) SBCL HIGH time (256 kB/s) SBCL HIGH time (192 kB/s) SBCL HIGH time (128 kB/s) SBCL LOW time (384 kB/s) SBCL LOW time (256 k/Bs) SBCL LOW time (192 kB/s) SBCL LOW time (128 kB/s) SBWS, SBDA hold to SBCL LOW SBCL LOW to SBWS, SBDA valid 120 to 205 ns (163 ns nominal) 35 ns 75 ns 8T ns nominal 12T ns nominal 16T ns nominal 24T ns nominal 4T - 20 ns 6T - 20 ns 8T - 20 ns 12T - 20 ns 4T - 20 ns 6T - 20 ns 8T - 20 ns 12T - 20 ns 20 ns 20 ns tCH tCL tD1 tD2 August 1993 18 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 SBWS SBCL SBDA SBEF SBCL Fig.16 Sub-band I2S interface timing (slave mode - SBCL, SBWS and SBDA are input). ,, ,,, ,, 0 1 2 3 4 5 6 7 8 9 10 11 12 t cL Tsc t cH t su1 t h1 SBWS SBDA t h2 SBEF MEA648 - 2 t su2 Notes to Fig.16 TC tCH tCL tS1 tH1 tS2 tH2 SBCL cycle time (see note 1) SBCL HIGH time SBCL LOW time SBWS, SBDA input set-up before SBCL HIGH SBWS, SBDA input hold after SBCL HIGH SBCL HIGH to SBEF valid SBEF hold after SBCL HIGH Note 1: Minimum at bit rate = 448 kB/s Nominal at bit rate = 384 kB/s Maximum at bit rate = 32 kB/s 6.86T to 96T ns (8T ns nominal) T + 30 ns T + 30 ns T + 30 ns 30 ns T - 30 ns 2T- 30 ns August 1993 19 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 SBDIR t d1 HIGH Z t d2 HIGH Z SBCL SBWS SBDA MEA647 - 1 Fig.17 Sub-band I2S mode switch timing. Notes to Fig.17 tD1 tD2 SBDIR HIGH to SBCL, SBWS, SBDA high impedance SBCL, SBWS, SBDA after SBDIR LOW high impedance 50 ns 240 ns August 1993 20 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications Microcontroller interface SAA2520 The SAA2520 has an interface connection to the serial interface of a microcontroller. The following signals are used: LTCLK LTDATA LTCNT0 LTCNT1 LTENA input bi-directional input input input bit clock serial data control line 0 control line 1 enable During the transfer of 8-bit units, the least significant bit is first to be transferred. When 16-bit units are transferred the most significant byte is sent first. EXTENDED SETTINGS (LTCNT1 = 0, LTCNT0 = 0) Four information bits together with four address bits are transferred in this mode. The order in which the bits appear on the interface is: D0..D1..D2..D3..A0..A1..A2..A3 The SAA2520 microcontroller interface is enabled only if LTENA (pin 34) is logic 1. Information to or from the SAA2520 is conveyed in serial 8 or 16-bit units, whilst the type of information is controlled by LTCNT0 (pin 35) and LTCNT1 (pin 36). A transfer commences when the microcontroller sets the control lines to the correct combination for the required action. LTENA is set to logic 1. The SAA2520 determines its required action and prepares to transfer data. When the microcontroller supplies the LTCLK, data is transferred to or from the SAA2520 in units of 8-bits. 16-bit transfers are conveyed as two 8-bit units during which LTENA remains high. Table 4 Extended Settings. BIT A2 0 0 0 .. 1 Extended Settings. DESIGNATION MUTEDAC ATTDAC DEEMDAC HOLDCLKOK 1 0 0 0 BIT A1 0 0 1 .. 1 BIT A3 0 0 0 .. 1 Table 5 BIT A0 0 1 0 .. 1 DESCRIPTION CODEC external settings (see Table 5) FILTER settings (see note 1) not used .. not used BIT D0 D1 D2 D3 Note DEFAULT FUNCTION connected to DAC mute input connected to DAC attenuation input emphasis control for DAC circuit selects CLKOK hold mode If not used for DAC control, the MUTEDAC, ATTDAC and DEEMDAC can be used as general purpose output expanders. August 1993 21 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications Bits D0 to D3 are copied directly to the corresponding output pins/mode flip-flop. For HOLDCLKOK = logic 1. When CLKOK drops it will remain LOW until set by an encode/decode mode, sample frequency, external 256FS or bit rate index change. Note 1. When D0 = logic 1 (default) I2S mode is selected. For D0 = logic 0 the alternative mode is selected. The setting of D0 remains dormant until activated by the occurrence of FRESET. ALLOCATION/SCALE FACTOR INFORMATION (LTCNT1 = 0, LTCNT0 = LOGIC 1) SAA2520 This is then followed by the scale factor information. In the event that only internal settings information is sent, then a default allocation of logic 0 will be assigned to all sub-bands. If in addition no internal settings are sent then the previous settings remain valid. The allocation information is transferred in 4-bit units. Each of these units contains the number of bits allocated to the sub-band, MINUS 1, except in the case of a logic 0 value, which indicates that no bits are allocated to that sub-band. Scale factor information is transferred in units of 8-bits, containing the 6-bit scale factor which is extended to 8-bits by adding two logic 0's at the most significant end. In the case of stereo encoding the channels are indicated by L (left) and R (right). This changes to I and II in the case of 2 channel mono encoding. LOGIC For encoding, the allocation and scale factor arrays can be filled using this mode. To completely fill the allocation array 16 complete transfers of 16-bits are required. After the first transfer of allocation information a check must be made to determine when the SAA2520 is ready to receive the remaining information. This will ensure synchronization with the internal program of the SAA2520. Transfer of the allocation information is completed by sending the internal settings. Table 6 Allocation information format. msb bits B14 B10 B6 B2 B13 B9 B5 B1 lsb B12 B8 B4 B0 channel L or I R or II L or I R or II sub-band 0 .. 30 (even) 0 .. 30 (even) 1 .. 31 (odd) 1 .. 31 (odd) B15 B11 B7 B3 Table 7 Scalefactor information format. msb B15 B7 bits ................ ................ lsb B8 B0 channel L or I R or II 0 .. 31 0 .. 31 sub-band August 1993 22 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications INTERNAL SETTINGS (LTCNT1 = LOGIC 1, LTNCT 0 = LOGIC 0) The operation of the codec is controlled by the bits transferred in this mode. Table 8 msb S15 S11 S9 S8 S7 S6 S5 S4 S3 S1 Table 9 ... ... S2 S0 CH1 Tr0 to Tr1 EMPHASIS ... ... Internal Settings (LTCNT1 = logic 1, LTNCT 0 = logic 0). lsb S12 S10 name bit rate index sample frequency decode EXT 256FS 2-channel mono MUTE function bit rate indication 44.1, 48 or 32 kHz indication 1 = decode; 0 = encode 1 = external; 0 = internal 256FS 1 = 2-CH mono; 0 = stereo 1 = mute; 0 = no mute not used 1 = CH1; 0 = CH2 transparent bits emphasis indication decode encode encode encode encode SAA2520 valid in encode/decode encode/decode encode encode/decode Internal Settings (LTCNT1 = logic 1, LTCNT0 = logic 0). lsb 1 0 1 1 0 0 1 0 0 0 0 0 bit rate 384 kbits/s 256 kbits/s 192 kbits/s 128 kbits/s CH1 is utilized in the decoding mode to select one of the 2-channel mono signals to be decoded (default is I - channel 1). A value of 0 results in channel 2 being decoded). The transparent bits are copied in the sub-band signal, default is 00. The information from S15 to S10, S7 and S3 to S0 will be copied into the sub-band signal. default value msb 1 1 0 0 The bit rate index indicates the bit rate of the encoded signal and is only effective in the encode mode. The decode bit determines the operation mode of the SAA2520. The default value is logic 1 (decoding mode). EXT 256FS in the encoding mode determines whether or not the SAA2520 is master or slave of the Filtered-I2S interface (default is logic 0, master mode). 2CH MONO is used in the encoding mode to determine whether the sub-band signal is generated as a stereo or 2-channel mono signal. Default value is logic 0. MUTE is used in both the encoding and decoding modes to mute the information to or from the Filtered-I2S interface (the default value is logic 0). August 1993 23 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications Table 10 Sample frequency indication. msb 0 0 1 1 Table 11 EMPHASIS indication. msb 0 0 1 1 lsb 0 1 0 1 50/15 s reserved CCITT J.17 emphasis no emphasis lsb 0 1 0 1 sample frequency 44.1 kHz 48 kHz 32 kHz not used SAA2520 default value default value Before sending internal settings the microcontroller should check whether or not the SAA2520 is ready-to-receive. However, this does not apply for the transfer of internal settings to end a transfer of allocation information. STATUS (LTCNT = LOGIC 1, LTNCT0 = LOGIC 1) Table 12 Status information 16-bit units. msb T15 T11 T9 T8 T7 T5 T4 T3 T1 ... T2 T0 T6 ... ... lsb T12 T10 name bit rate index sample frequency ready-to-receive not used MODE SYNC CLKOK Tr0 to Tr1 EMPHASIS sub-band signal mode indication synchronization indication 1 = o.k.; 0 = not o.k. transparent bits emphasis indication encode/decode decode encode/decode encode/decode encode/decode function bit rate indication 44.1, 48 or 32 kHz indication 1 = ready; 0 = not ready valid in encode/decode encode/decode encode/decode The bit rate index indicates the bit rate of the sub-band signal in units of 32 kbits/s. bit rate index 0000 indicates the `free format' condition. bit rate 1111 is illegal and should not be found. The coding of the sample frequency indication is equal to the one in the internal settings. August 1993 24 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications Table 13 MODE identification. msb 0 0 1 1 lsb 0 1 0 1 stereo joint stereo 2 channel mono 1 channel mono mode L and R L and R SAA2520 output I or II as selected mono; no selection Ready-to-receive indicates whether the SAA2520 is ready to receive allocation, scale factor or internal setting transfers. This should be checked in order to synchronize the transfer of such information. In 2 channel mono decode mode the selected samples are transferred to both output channels. The same occurs with all samples in 1-channel mono decode mode. In both of these instances the L and R filter output channels are identical. In decode mode the SYNC bit is logic 0 when the SAA2520 is unable to decode the sub-band frames. This will occur in the following situations: * with the loss of synchronisation * when in correct allocation information is received for two or more subsequent frames (SBEF was HIGH). * when the URDA input pin is HIGH In these situations the SAA2520 data output will be muted. The SYNC bit will return to logic 1 as soon as the decoder is resynchronized to the incoming sub-band data. CLKOK indicates whether the 256FS clock corresponds to specified sample frequency. The CLKOK bit is set to logic 1 after a change in sample frequency, operation mode or EXT256FS setting. It drops to logic 0 as soon as the 256FS clock deviates from the nominal frequency by more than approximately 0.2%. Return to logic 1 will only occur automatically when the extended setting CLKOK-hold-mode is logic 0. The transparent bits are copied from the MPEG coded signal. The EMPHASIS indication is as defined in the internal settings. It can be used to apply the correct de-emphasis. Note: the two bytes of the status are 'sampled' at different moments so the information may not result from the same sub-band frame. August 1993 25 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 handbook, full pagewidth LTENA LTCNT0/1 LTCLK LTDATA 0 lsb 1 2 3 4 5 6 7 msb MLB131 Fig.18 Transfer of data on SAA2520 microcontroller interface. handbook, full pagewidth LTENA 16 bits allocation / scale factor information LTCLKC 16 bits allocation / scale factor information MLB132 Fig.19 The LTENA line must return to logic 0 between information transfers. August 1993 26 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 handbook, full pagewidth LTENA LTCNT0/1 LTCLK LTDATA bit : 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 MLB133 Fig.20 Order of settings and status bits on the SAA2520 microcontroller interface. handbook, full LTENA pagewidth LTENA must remain HIGH LTCNT0/1 LTCLK t D6 LTDATA OUTPUT 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 MLB134 tD6 delay LTCLK HIGH to LTDATA valid output for bit 0 in 16-bit transfers Fig.21 16-bit transfers. August 1993 27 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 t el handbook, full pagewidth LTENA t D1 LTCNT0 LTCNT1 t D5 t CL t CH t H4 t S1 t H1 LTCLK t S2 LTCDATA input t D3 t H3 t D6 t H2 t D4 t D2 LTCDATA output hiZ MLB135 hiZ Fig.22 Microcontroller interface timing. Notes to Fig.22 teL tCH tCL tD1 tD2 tD3 tD4 tH4 tD5 tD6 LTENA LOW time LTCLK HIGH time LTCLK LOW time LTENA HIGH to LTCLK HIGH LTENA HIGH to LTDATA output low impedance LTENA HIGH to LTDATA output valid LTENA LOW to LTDATA high impedance LTENA hold after LTCLK HIGH LTCLK HIGH to LTENA HIGH LTCLK HIGH to LTDATA output valid for bit 0 (see Fig.21) for first bit in the second 8-bit unit LTCNT0/1 set-up before LTENA HIGH LTCNT0/1 hold after LTENA HIGH LTDATA set-up before LTCLK HIGH LTDATA input hold after LTCLK HIGH LTDATA output hold after LTCLK HIGH LTENA hold after LTCLK HIGH 190 ns 190 ns 190 ns 190 ns 0 ns 380 ns 50 ns 355 ns 190 ns 355 ns 520 ns 190 ns 190 ns 190 ns 30 ns 145 ns 355 ns 28 tS1 tH1 tS2 tH2 tH3 tH4 August 1993 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134). SYMBOL VDD VI ISS IDD II IO Ptot Tstg Tamb Ves1 Ves2 Notes 1. Input voltage should not exceed 6.5 V unless otherwise specified 2. Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor 3. Equivalent to discharging a 200 pF capacitor through a 0 series resistor. DC CHARACTERISTICS Tamb = -40 to 85 C; VDD = 3.8 to 5.5 V unless otherwise specified. SYMBOL Supply VDD IDD IDD VIH VIL -II +II supply voltage range operating current operating current VDD = 5 V (note 1) VDD = 3.8 V (note 1) 3.8 - - 5.0 82 58 - - - - 5.5 110 80 - 0.3VDD 10 10 PARAMETER CONDITIONS MIN. TYP. MAX. supply voltage input voltage supply current from VSS supply current in VDD input current output current total power dissipation storage temperature range operating ambient temperature range electrostatic handling electrostatic handling note 2 note 3 note 1 PARAMETER CONDITIONS MIN. -0.5 -0.5 - - -10 -20 - -55 - 40 -1500 -70 MAX. 6.5 SAA2520 UNIT V V mA mA mA mA mW C C V V VDD + 0.5 160 160 10 20 880 150 85 1500 70 UNIT V mA mA Inputs URDA, SBDIR, SBEF, LTCLK, LTCNT0, LTNCT1, X22IN, X24IN HIGH level input voltage LOW level input voltage input current input current Vi = 0 V; Tamb = 25 C Vi = 5.5 V; Tamb = 25 C 0.7VDD - - - V V A A Inputs PWRDWN, LTENA VIH VIL +II HIGH level input voltage LOW level input voltage input current Vi = VDD; Tamb = 25 C 0.7VDD - 40 - - - - 0.3VDD 250 V V A August 1993 29 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SYMBOL Input RESET Vtlh Vthl Vhys +II positive-going threshold negative-going threshold hystersis input current (Vtlh - Vthl) Vi = VDD; Tamb = 25 C +Io = 2 mA -Io = 2 mA +Io = 8 mA -Io = 8 mA +Io = 2 mA -Io = 2 mA - 0.2VDD - 40 - - 1.5 - 0.8VDD - - 250 PARAMETER CONDITIONS MIN. TYP. MAX. SAA2520 UNIT V V V A Outputs MUTEDAC, DEEMDAC, ATTDAC, SYNCDAI, FDIR, FRESET, FSYNC, CLK22 VOH VOL VOH VOL VOH VOL VIH VIL II HIGH level output voltage LOW level output voltage VDD-0.5 - VDD-0.5 - VDD-0.5 - - - - - - - - - - - 0.4 - 0.4 - 0.4 - 0.3VDD 250 V V Outputs CLK24 HIGH level output voltage LOW level output voltage V V Inputs/outputs SBDA, SBCL, SBWS, FDAF, FDAC, SCL, SWS, SDA, LTDATA HIGH level output voltage LOW level output voltage V V Outputs SBDA, SBCL, SBWS, FDAF, FDAC, SCL, SWS, SDA, LTDATA in 3-state HIGH level input voltage LOW level input voltage input current Vi = VDD; Tamb = 25 C +Io = 8 mA -Io = 8 mA 0.7VDD - 40 V V A Input/output SBMCLK VOH VOL VIH VIL II HIGH level output voltage LOW level output voltage VDD-0.5 - - - - - - - 0.4 - 0.3VDD 250 V V Output SBMCLK in 3-state HIGH level input voltage LOW level input voltage input current Vi = VDD; Tamb = 25 C +Io = 12 mA -Io = 12 mA 0.7VDD - 40 V V A Input/output FS256 VOH VOL VIH VIL II Note 1. For load impedances representative of the application. HIGH level output voltage LOW level output voltage VDD-0.5 - - - - - - - 0.4 - 0.3VDD 250 V V Output FS256 in 3-state HIGH level input voltage LOW level input voltage input current Vi = VDD; Tamb = 25 C 0.7VDD - 40 V V A August 1993 30 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications AC CHARACTERISTICS Tamb = -40 to 85 C; VDD = 3.8 to 5.5 V unless otherwise specified. SYMBOL Inputs CI f f gm Av Cfb CO Outputs CO tSU tHD td tSU tHD td tSU tHD td FS256 T T T TC FS256 cycle time FS256 cycle time FS256 cycle time SCL cycle time fs = 48 kHz fs = 44.1 kHz fs = 32 kHz - - - - 81.4 88.6 122.1 4T - - - - output capacitance - - - - - - - - - - - 10 - - input capacitance - - 10 PARAMETER CONDITIONS MIN. TYP. SAA2520 MAX. UNIT pF X24IN and X22IN crystal frequency at X22OUT, CLK22 crystal frequency at X24OUT, CLK24 mutual conductance small signal gain feedback capacitance output capacitance note 1 note 1 100 kHz Av = gm.Ro 21 23 1.5 3.5 - - 22.5792 24.576 - - - - 24 26 - - 5 10 MHz MHz mA/V V/V pF pF pF Inputs URDA, RESET, LTDATA, LTCLK, LTENA, LTCNT0, LTCNT1 setup time to X24IN hold time to X24IN 15 60 - ns ns Outputs LTDATA, MUTEDAC, DEEMDAC, ATTDAC, SYNCDAI, FDIR, FRESET propagation delay from X24IN 80 - - ns Inputs FDAF, FDAC, SDA, SCL, SWS setup time to FS256 hold time to FS256 15 25 - ns ns Outputs FDAF, FDAC, SDA, SCL, SWS, FSYNC propagation delay from FS256 50 - - ns Inputs SBDA, SBCL, SBWS, URDA, SBDIR, SBEF setup time to SBMCLK hold time to SBMCLK 15 25 - ns ns Outputs SBDA, SBCL, SBWS propagation delay from SBMCLK 50 ns ns ns ns ns August 1993 31 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SYMBOL PARAMETER CONDITIONS MIN. - - - - - - - - - - - - TYP. - - - - - - - - - - - 50 SAA2520 MAX. UNIT FS256 master mode (FS256,SCL and SWS are output) tfH tfH tfH tfL tfL tfL tsH tsL ts tH1 tH2 tD1,2 FS256 HIGH time FS256 HIGH time FS256 HIGH time FS256 LOW time FS256 LOW time FS256 LOW time SCL HIGH time SCL LOW time SDA, FDAF, FDAC input setup time before FS256 HIGH SDA, FDAF, FDAC input hold time after FS256 HIGH SDA, FDAF, FDAC output hold time after FS256 HIGH FS256 HIGH-to SCL, SWS, SDA, FDAF, FDAC output valid fs = 48 kHz fs = 44.1 kHz fs = 32 kHz fs = 48 kHz fs = 44.1 kHz fs = 32 kHz 35 38 75 35 38 75 2T-20 2T-20 20 30 0 - ns ns ns ns ns ns ns ns ns ns ns ns FS256 slave mode (FS256, SCL and SWS are input) tfH tfL tsH tsL tH1 tD tS tH2 SBMCLK T tmH tmL SBMCLK cycle time SBMCLK HIGH time SBMCLK LOW time 120 35 75 163 - - 205 - - ns ns ns FS256 HIGH time FS256 LOW time SCL HIGH time SCL LOW time SDA, FDAF, FDAC output hold time after SCL HIGH SCL HIGH-to SDA, FDAF, FDAC output valid SDA, FDAF, FDAC input valid after SCL HIGH SDA, FDAF, FDAC input hold time after SCL HIGH 35 35 T+35 T+35 2T-15 - 20 T+20 - - - - - - - - - - - - - 3T+60 - - ns ns ns ns ns ns ns ns August 1993 32 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SYMBOL PARAMETER CONDITIONS - - - - 4T - 20 6T - 20 8T - 20 12T - 20 4T - 20 6T - 20 8T - 20 12T - 20 - MIN. TYP. - - - - - - - - - - - - - 20 SAA2520 MAX. UNIT SBMCLK master mode (SBCL, SBWS and SBDA are output) TC TC TC TC tcH tcH tcH tcH tcL tcL tcL tcL tD1 tD2 TC tcH tcL tS1 tH1 tS2 tH2 Notes 1. % deviation from nominal frequency must be the same for X24, X22, and FS256 inputs to within 0.2% 2. Minimum value for bit rate = 448 kB/s Typical value for bit rate = 384 kB/s Maximum value for bit rate = 32 kB/s SBCL cycle time SBCL cycle time SBCL cycle time SBCL cycle time SBCL HIGH time SBCL HIGH time SBCL HIGH time SBCL HIGH time SBCL LOW time SBCL LOW time SBCL LOW time SBCL LOW time SBWS, SBDA hold SBWS, SBDA valid 384 kB/s 256 kB/s 192 kB/s 128 kB/s 384 kB/s 256 kB/s 192 kB/s 128 kB/s 384 kB/s 256 kB/s 192 kB/s 128 kB/s after SBCL 0 8T 12T 16T 24T - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns to SBCL LOW 20 SBMCLK slave mode (SBCL, SBWS and SBDA are input) SBCL cycle time SBCL HIGH time SBCL LOW time SBWS, SBDA setup time SBWS, SBDA hold time delay before SBEF valid SBEF hold time before SBCL HIGH after SBCL HIGH after SBCL HIGH after SBCL HIGH note 2 6.86T T + 30 T + 30 T + 30 30 - 2T - 30 8T - - - - - - 96T - - - - T - 30 - ns ns ns ns ns ns ns August 1993 33 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm SAA2520 SOT205-1 c y X 33 34 23 22 ZE A e E HE wM bp pin 1 index 44 1 11 ZD bp D HD wM B vM B 12 detail X L Lp A A2 A1 (A 3) e vM A 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.60 A1 0.25 0.05 A2 2.3 2.1 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 14.1 13.9 E (1) 14.1 13.9 e 1 HD 19.2 18.2 HE 19.2 18.2 L 2.35 Lp 2.0 1.2 v 0.3 w 0.15 y 0.1 Z D (1) Z E (1) 2.4 1.8 2.4 1.8 7 0o o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT205-1 REFERENCES IEC 133E01A JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-08-01 August 1993 34 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. SAA2520 If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. August 1993 35 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values SAA2520 This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. August 1993 36 |
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