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THC63LVD104S Rev.1.0
THC63LVD104S
112MHz 30Bits Color LVDS Receiver
General Description
The THC63LVD104S receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA resolutions. The THC63LVD104S converts the LVDS data streams back into 35bits of CMOS/TTL data with rising edge or falling edge clock for convenient with a variety of LCD panel controllers.At a transmit clock frequency of 112MHz, 30bits of RGB data and 5bits of timing and control data (HSYNC,VSYNC,DE,CNTL1,CNTL2) are transmitted at an effective rate of 784Mbps per LVDS channel.Using a 112MHz clock, the data throughput is 490Mbytes per second.
Features
* Wide dot clock range: 8-112MHz suited for NTSC,
VGA, SVGA, XGA, and SXGA
* * * * * * * *
PLL requires no external components 50% output clock duty cycle TTL clock edge and position programmable(3 step) Power down mode Low power single 2.5V CMOS design TQFP 64pin Pin compatible with THC63LVD104A Fail-safe for Open CLK Input
Block Diagram
LVDS INPUT SERIAL TO PARALLEL
RA+/RB+/RC+/7 7 7 7 7
CMOS/TTL OUTPUT
RA6-RA0 RB6-RB0 RC6-RC0 RD6-RD0 RE6-RE0 CLKOUT
RD+/RE+/RCLK+/(8 to112MHz)
PLL
CMOS/TTL INPUT
R/F DK PD OE
Copyright 2004 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD104S Rev.1.0
Pin Out
RARA+ RBRB+ LVCC RCRC+ RCLKRCLK+ LGND RDRD+ RERE+ PGND PVCC
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VCC RA0 RA1 RA2 GND RA3 RA4 RA5 RA6 RB0 RB1 VCC RB2 RB3 RB4 RB5
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
RB6 CLKOUT GND RC0 RC1 RC2 RC3 RC4 RC5 VCC RC6 RD0 RD1 RD2 RD3 RD4
Copyright 2004 THine Electronics, Inc. All rights reserved
GND DK PD OE R/F RE6 RE5 RE4 VCC RE3 RE2 RE1 RE0 RD6 RD5 GND
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THine Electronics, Inc.
THC63LVD104S Rev.1.0
Pin Description
Pin Name RA+, RARB+, RBRC+, RCRD+, RDRE+,RERCLK+, RCLKRA6 ~ RA0 RB6 ~ RB0 RC6 ~ RC0 RD6 ~ RD0 RE6 ~ RE0 PD Pin No. 50, 49 52, 51 55, 54 60, 59 62, 61 57, 56 40,41,42,43,45,46,47 32,33,34,35,36,38,39 22,24,25,26,27,28,29 14,15,17,18,19,20,21 6,7,8,10,11,12,13 3 I/O Type LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN OUT OUT OUT OUT OUT Power down and Output Control.(Table1) IN H: Normal operation L: Power down OE 4 IN Output Enable. See Table1. H:Output enable. L:Output disable Output Clock Delay Timing Select.(Fig5) tRCP=Output Clock Cycle DK 2 IN ( 3-Level ) L: Offset 0[nsec]
RCP M: Offset - 3 ------------- (typ) [nsec] 14 t
Description
LVDS Data In.
LVDS Clock In.
CMOS/TTL Data Outputs.
H: Offset +
t RCP 3 ------------14
(typ)[nsec]
Output Clock Triggering Edge Select.(Fig5) R/F 5 IN H: Rising Edge L: Falling Edge VCC CLKOUT GND LVCC LGND PVCC PGND 9,23,37,48 31 1,16,30,44 53 58 64 63 Power OUT Ground Power Ground Power Ground Power Supply Pins for TTL outputs and digital circuitry. Clock out. Ground Pins for TTL outputs and digital circuitry. Power Supply Pin for LVDS inputs. Ground Pin for LVDS inputs. Power Supply Pin for PLL circuitry. Ground Pin for PLL circuitry.
Copyright 2004 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD104S Rev.1.0
Pin Description (Continued)
Table 1. Output Control PD L L H H OE L H L H ** Rxn Data Outputs (Rxn) Hi-Z All Low Hi-Z Data Out x = A,B,C,D,E CLKOUT Hi-Z Fixed Low Hi-Z CLK Out
n = 0,1,2,3,4,5,6
Absolute Maximum Ratings
Supply Voltage (VCC) CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Receiver Input Voltage Output Current Junction Temperature Storage Temperature Range Resistance to soldering heat Maximum Power Dissipation @+25 C -0.3V ~ +3.0V -0.3V ~ (VCC + 0.3V) -0.3V ~ (VCC + 0.3V) -0.3V ~ (VCC + 0.3V) -30mA ~ 30mA +125 C -55 C ~ +150 C +260 C /10sec 1.4W
Recommended Operating Conditions
Parameter All Supply Voltage Operating Ambient Temperature Differential CLKIN Frequency Differential CLKIN High Time(tRCIH) (Fig1) Differential CLKIN Low Time(tRCIL) (Fig1) Min 2.3 0 8
t RCIP 2 --------------7 t RCIP 2 --------------7
Typ 2.5
Max 2.7 70 112
t RCIP 5 --------------7 t RCIP 5 --------------7
Units V
C
MHz nsec nsec
tRCIH
tRCIL
Vdiff = 0V
Vdiff = 0V
Vdiff = 0V
RCLK+ (Differential)
tRCIP
Fig1. Differential CLKIN
Copyright 2004 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD104S Rev.1.0
Electrical Characteristics CMOS/TTL DC Specifications
VCC=VCC=PVCC=LVCC Symbol VIH VIL VIH3 VIM3 VIL3 VOH VOL IIL Parameter High Level Input Voltage PD, OE,R/F Pin Low Level Input Voltage High Level Input Voltage Middle Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current IOH= -2mA IOL= 2mA PD, OE,R/F Pin
0V V IN V CC 10
Conditions
Min 1.7 GND 2.1
Typ
Max V CC 0.7 V CC
Units V V V V V V
3-Level Inputs(DK Pin)
1.05 GND 2.1
1.25
1.45 0.4
0.4
V uA
3-Level Inputs(DK Pin) IIL3 3-Level Input Leakage Current
0V V IN V CC 10
uA
LVDS Receiver DC Specifications
VCC=VCC=PVCC=LVCC Symbol VTH VTL IILD Parameter Differential Input High Threshold Differential Input Low Threshold Differential Input Leakage Current Conditions V IC= 1.2V V IC= 1.2V VIN= 2.4V / 0V -100
200
Min
Typ
Max 100
Units mV mV uA
Supply Current
VCC=VCC=PVCC=LVCC Symbol Parameter Receiver Supply Current IRCCW Checker Pattern(Worst Case) (Fig 2) IRCCS Receiver Power Down Supply Current Conditions fCLKOUT=65MHz fCLKOUT=85MHz fCLKOUT=112MHz PD = L, Ta=RT CL=8pF Min Typ Max 125 152 184 10 Units mA mA mA uA
Copyright 2004 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD104S Rev.1.0
Electrical Characteristics (Continued)
Checker Pattern CLKOUT Rx0 Rx1 Rx2 Rx3 Rx4 Rx5 Rx6
x=A,B,C,D,E
Fig2. Test Pattern
Copyright 2004 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD104S Rev.1.0
Switching Characteristics
VCC=VCC=PVCC=LVCC Symbol tRCP tRCH tRCL tRS tRH tTLH tTHL Parameter CLKOUT Period (Fig4) CLKOUT High Time (Fig4) CLKOUT Low Time (Fig4) TTL Data Setup to CLKOUT TTL Data Hold to CLKOUT TTL Low to High Transition Time (Fig 3) TTL High to Low Transition Time (Fig 3) Receiver Skew Margin (Fig6) tRIP1 tRIP0 tRIP6 tRIP5 tRIP4 tRIP3 tRIP2 tRPLL tRCIP=85MHz tRCIP=112MHz -400 -350 -tSK
t RCIP ------------ - t SK 7 tRCIP 2 ------------ - tSK 7 tRCIP 3 ------------ - tSK 7 tRCIP 4 ------------ - tSK 7 tRCIP 5 ------------ - tSK 7 tRCIP 6 ------------ - tSK 7
Min. 8.93
Typ. T
T -2 T -2
Max. 125.0
Units ns ns ns ns ns
0.50tRCP-1.5 0.35tRCP-1.0 1.3 1.3 0 0 0
t RCIP -----------7 tRCIP 2 -----------7 tRCIP 3 -----------7 tRCIP 4 -----------7 tRCIP 5 -----------7 tRCIP 6 -----------7
3.0 3.0 400 350 +tSK
t RCIP ------------ + t SK 7 t RCIP 2 ------------ + t SK 7 t RCIP 3 ------------ + t SK 7 t RCIP 4 ------------ + t SK 7 t RCIP 5 ------------ + t SK 7 t RCIP 6 ------------ + t SK 7
ns ns ps ps ns ns ns ns ns ns ns ms
tSK
Input Data Position0 (Fig6) Input Data Position1 (Fig6) Input Data Position2 (Fig6) Input Data Position3 (Fig6) Input Data Position4 (Fig6) Input Data Position5 (Fig6) Input Data Position6 (Fig6) Phase Lock Loop Set (Fig7) RCLK +/- to CLK OUT Delay (Fig8) (Fig6) tRCIP=75MHz
10.0
tRCD
45.5
48.5
ns
tRCIP
CLKIN Period
8.93
125.0
ns
Copyright 2004 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD104S Rev.1.0
AC Timing Diagrams
TTL Output CL=8pF 20% 20% 80% 80%
TTL Output Load tTLH tTHL
Fig3. CMOS/TTL Output Load and Transition Time
tRCP
tRCH
tRCL
CLKOUT
VCC/2
VCC/2
VCC/2
VCC/2
Fig4. CLKOUT Period and High/Low Time
tRCP
R/F=L CLKOUT DK=L
tRS
V CC/2
R/F=H
tRH
R/F=H CLKOUT DK=M
VCC/2
R/F=L
t RCP 3 ------------14
CLKOUT DK=H
R/F=L
VCC/2
R/F=H
t RCP 3 ------------14
Rxn
VCC/2
VCC/2
x = A,B,C,D,E n = 0~6
Fig5. CLKOUT Position and Setup/Hold Timing
Copyright 2004 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD104S Rev.1.0
AC Timing Diagrams (Continued)
tRCIP V diff = 0V Vdiff = 0V
RCLK+ (Differential)
RA3' RA2' RA1' RA0' RA6 RA5 RA4 RA3 RA2 RA1 RA0 RA6''
RA+/-
RB+/-
RB3' RB2' RB1'
RB0'
RB6
RB5
RB4
RB3
RB2
RB1
RB0
RB6''
RC+/-
RC3' RC2' RC1'
RC0'
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RC6''
RD+/-
RD3' RD2' RD1' RD0'
RD6
RD5
RD4
RD3
RD2
RD1
RD0
RD6''
RE+/-
RE3'
RE2'
RE1'
RE0'
RE6
RE5
RE4
RE3
RE2
RE1
RE0
RE6''
Previous Cycle
Current Cycle
Next Cycle
tRIP1 tRIP0 tRIP6 tRIP5 tRIP4 tRIP3 tRIP2
Fig6. LVDS Input Data Position
RCLK+/-
PD
1.7V
tRPLL
CLKOUT Fig7. PLL Lock Loop Set Time
Copyright 2004 THine Electronics, Inc. All rights reserved 9
VCC/2
THine Electronics, Inc.
THC63LVD104S Rev.1.0
AC Timing Diagrams (Continued)
RCLK+
Vdiff = 0V tRCD
Vdiff = 0V
CLKOUT R/F=L
Note: 1) Vdiff = (RCLK+) - (RCLK-)
VCC/2
Fig8. RCLK +/- to CLK OUT Delay
Copyright 2004 THine Electronics, Inc. All rights reserved
10
THine Electronics, Inc.
THC63LVD104S Rev.1.0
Package
48 33
49
0.5TYP
THine
THC63LVD104S
10.0TYP 16 17 12.0TYP
THine Electronics, Inc.
0.22
INDEX D PIN No.1
1.00TYP
1.2MAX
64
32
UNITS: mm
Copyright 2004 THine Electronics, Inc. All rights reserved
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THC63LVD104S Rev.1.0
Notes to Users:
1. The contents of this data sheet are subject to change without prior notice. 2. Circuit diagrams shown in this data sheet are examples of application. Therefore, please pay sufficient attention when designing circuits. EVEN IF THERE ARE INCORRECT DESCRIPTIONS, THINE IS NOT RESPOSIBLE FOR ANY PROBLEM DUE TO THEM. Please note that incorrect descriptions sometimes cannot be corrected immediately if found. 3. THine's copyright, know-how and other intellectual property rights are included in this data sheet. Duplication of the data sheet and disclosure to other persons are strictly prohibited without THine's prior written permission. 4. THINE IS NOT RESPONSIBLE FOR ANY PROBLEMS OF INTELLECTUAL PROPERTY RIGHTS OCCURRING DURING THC63LVD104S USE, EXCEPT FOR DAMAGES RESULTING FROM INFRINGEMENT CAUSED ONLY BY THC63LVD104HS WITHOUT ANY ITEM NOT SOLD BY THINE AND/OR ANY USERS' ACTION. THINE IS NOT RESPONSIBLE FOR PROBLEMS CAUSED BY SPECIFICATIONS SUPPLIED BY USERS. THC63LVD104S is designed on the premise that it should be used for ordinary electronic devices. Therefore, it shall not be used for applications that require extremely high-reliability (space equipment, nuclear control equipment, medical equipment that affects people's lives, etc.). In addition, when using THC63LVD104S for traffic signals, safety devices and control/safety units in transportation equipment, etc., appropriate measures should be taken. 5. THINE IS MAKING THE UTMOST EFFORT TO IMPROVE THE QUALITY AND RELIABILITY OF THINE'S PRODUCTS. HOWEVER, THERE IS A VERY SLIGHT POSSIBILITY OF FAILURE IN SEMICONDUCTOR DEVICES. To avoid damage to social or official organizations, much care should be taken to provide sufficient redundancy and fail-safe design. 6. No radiation-hardened design is incorporated in THC63LVD104S. 7. Judgment on whether THC63LVD104S comes under strategic products prescribed by the Foreign Exchange and Foreign Trade Control Law is the user's responsibility. 8. This technical document was provisionally created during development of THC63LVD104S, so there is a possibility of differences between it and the product's final specifications. When designing circuits using THC63LVD104S, be sure to refer to the final technical documents.
THine Electronics, Inc. Wakamatsu Bldg, 6F 3-3-6, Nihombashi-Honcho, Chuo-ku, Tokyo, 103-0023 Japan Tel: 81-3-3270-0666 Fax: 81-3-3270-0688
Copyright 2004 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.

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