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P r el i m i n a ry D a t a S h e et , R e v . 1. 3 , D e c . 20 0 4
TLE 7259 G
LIN Transceiver
Automotive Power
Never
stop
thinking.
Edition 2004-12-13 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany
(c) Infineon Technologies AG 2004.
All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
LIN Transceiver
TLE 7259 G
Features * * * * * * * * * * * * Transmission rate up to 20 kBaud Compatible to LIN specification 1.2, 1.3 and 2.0 Support of K-line function Very low current consumption in sleep mode Very low leakage current in unpowered state Control output for voltage regulator Wake up source recognition (local/remote) For 3.3 V and 5 V C I/O Suitable for 12V and 24V boardnet Bus short to VBAT protection Bus short to GND handling Overtemperature protection
P-DSO-8-3, -6, -7, -8, -9
Description The TLE 7259 G is a monolithic integrated circuit in a P-DSO-8-3 package. It works as an interface between the protocol controller and the physical bus. The TLE 7259 G is especially suitable to drive the bus line in LIN systems in automotive and industrial applications. In order to reduce the current consumption, the TLE 7259 G offers a sleep operation mode. In this mode the voltage regulator can be switched off by the TLE 7259 G to minimize the current consumption of the whole application. A wake-up caused by a message on the bus or a signal at the wake (WK) pin, enables the voltage regulator and sets the device to standby operation mode. The TLE 7259 G has a BUS short to GND feature implemented, to avoid a battery discharge. The TLE 7259 G offers a very good EMC performance within a broad frequency range independent from battery voltage. This is achieved by implementing a slope control mechanism based on a constant slew rate. The TLE 7259 G can also be used with 3.3 V and 5 V micro controllers.
Type TLE 7259 G
Preliminary Data Sheet
Ordering Code Q67006-A9694
3
Package P-DSO-8-3
Rev. 1.3, 2004-12-13
TLE 7259 G
The IC is based on the Smart Power Technology SPT(R) which allows bipolar and CMOS control circuitry in accordance with DMOS power devices existing on the same monolithic circuit. The TLE 7259 G is designed to withstand the severe conditions of automotive applications.
P-DSO-8-3
RxD
EN WK TxD 1 2 3 4 8 7 6 5 INH
VS
Bus GND
AEP02832_7259
Figure 1 Table 1 Pin No. 1 2 3 4 5 6 7 8
Pin Configuration (top view) Pin Definitions and Functions Symbol RxD EN WK TxD GND Bus Function Receive data output; external pull-up used, LOW in dominant state, active LOW after a wake-up event Enable input; integrated 30 k pull-down, transceiver in normal operation mode when HIGH Wake input; active LOW, negative edge triggered, internal pull-up Transmit data input; integrated pull-down, LOW in dominant state; active LOW after wake-up via WK pin Ground Bus output/input; internal 30 k pull-up, LOW in dominant state Battery supply input Inhibit output; to control a voltage regulator, becomes HIGH (VS), when wake-up via LIN bus or WK pin occurs
VS
INH
Preliminary Data Sheet
4
Rev. 1.3, 2004-12-13
TLE 7259 G
VS
7
TLE 7259
8
INH
Supply
5V
30 k 6
Output Stage
Driver Temp.Protection Current Limit
Mode Control
2 30 k
EN
TxD Input 4 Timeout 30 k TxD
Bus
Receiver Filter Wake and Bus Comparator 3 Filter
1
RxD
5
GND
WK
TOAEB03513_1.VSD
Figure 2
Functional Block Diagram
Preliminary Data Sheet
5
Rev. 1.3, 2004-12-13
TLE 7259 G
Operation Modes
Start Up Power Up
Normal Mode EN High INH High EN High
Stand-By EN Low EN High EN Low RxD Low Floating 2)
1)
TxD Low High 4)
3)
INH High
Sleep Mode EN Low INH Floating Wake Up via Bus: t > twak e,bus via Wake: t > t wak e
1) After wake up (via Bus or Wake) 2) After start up 3) After wake up via Wake (internal strong pull down, > 1.9 mA) 4) After wake up via Bus (internal weak pull down, 350 k )
AEA03514.VSD
Figure 3
Operation Mode State Diagram
Standby Mode After a power up, wake-up or low supply condition, the TLE 7259 G is automatically transferred to the standby mode (see Figure 3). This is realized, by setting EN = low due to a pull-down. The INH output is automatically switching to high level (= VS), to turn on the system voltage regulator. In the standby mode, no communication on the bus is possible. The bus driver is disabled. In the standby mode, the C can detect if a wake-up from sleep mode is caused by the WK pin or a bus message. This is realized by monitoring the RxD and TxD pin (see Figure 3).
Preliminary Data Sheet 6 Rev. 1.3, 2004-12-13
TLE 7259 G
Normal Mode The TLE 7259 G is entering the normal mode after the C is setting EN = high (see Figure 3). In this mode it is possible to transmit and receive messages on the bus. Sleep Mode In order to reduce the current consumption the TLE 7259 G offers a sleep operation mode. This mode is selected by switching the enable input EN low from the normal mode (see Figure 3). In the sleep mode, a voltage regulator will be switched off via the INH output in order to minimize the current consumption of the whole application. A wake-up caused by a message on the communication bus (for t > tWK,bus) or the WK pin (for t > tWK), automatically enables the voltage regulator by switching the INH output high. In parallel the wake-up is indicated by setting the RxD output LOW. The TxD input automatically is set to LOW if the source of the wake-up was the WK-pin, otherwise TxD is HIGH. So, the RxD pin can be used as a flag to indicate a wake-up from sleep mode and the TxD flag can be used as an indicator for the wake-up source (see Figure 3). When entering the normal mode these wake-up flags are reset and the RxD output and TxD input is released to receive/transmit the bus data. In case the voltage regulator control input is not connected to INH output or the microcontroller is active respectively, the TLE 7259 G can be set in normal operation mode without a wake-up via the communication bus. Application Information Master Termination To achieve the required timings for the dominant to recessive transition of the bus signal an additional external termination resistor of 1 k is mandatory. It is recommended to place this resistor at the master node. To avoid reverse currents from the bus line into the battery supply line it is recommended to place a diode in series to the external pullup. For small systems (low bus capacitance) the EMC performance of the system is supported by an additional capacitor of at least 1 nF in the master node (see Figure 6 and Figure 7, application circuit). BUS short to GND Feature The TLE 7259 G has a feature implemented to protect the battery from running out of charge in the case of BUS short to GND. In this failure case a normal master termination connection like described above, 1 k resistor and diode between bus and VS, would cause a constantly drawn current even in sleep mode. The resulting resistance of this short to GND is lower than 1 k. To avoid this current during a generator off state, like a parked car, the sleep mode has a bus short to GND feature implemented in the TLE 7259 G. This feature is only applicable, if the
Preliminary Data Sheet 7 Rev. 1.3, 2004-12-13
TLE 7259 G
master termination is connected with the INH pin, instead of the VS (see Figure 6 and Figure 7). Internally, the 30 k path is also switched off from supply (see Figure 2). External Capacitors A capacitor of 22 F at the supply voltage input VS buffers the input voltage. In combination with the required reverse polarity diode this prevents the device from detecting power down conditions in case of negative transients on the supply line. The 100 nF capacitors close to the VS pins of the TLE 7259 G and the voltage regulator help to improve the EMC behavior of the system. Oscillator Tolerance According to the LIN Calculation table, an oscillator clock tolerance < 2% is possible with TLE 7259 G. 3.3 V and 5 V Logic Capability The TLE 7259 G can be used for 3.3 V and 5 V micro controllers. The inputs and the outputs are capable to operate with both voltage levels. The inputs (TxD, EN) take the reference voltage from the connected C pins. The RxD output must have an external pull-up resistance to the C supply, to define the output voltage level. LIN Specifications 1.2, 1.3 and 2.0 The difference between LIN specification 1.2 and 1.3 is mainly the physical layer specification. The reason was to improve the compatibility between the nodes. The difference between LIN specification 1.3 and 2.0 is that the 2.0 version is a superset of the 1.3 version. The 2.0 version offers some new features. However, it is possible to use the LIN 1.3 slave node in a 2.0 node cluster, as long as the new features are not used. Vice versa it is possible to use a LIN 2.0 node in the 1.3 cluster without using the new features. LIN 2.0 is the latest version of the LIN specification, released in September 2003.
Preliminary Data Sheet
8
Rev. 1.3, 2004-12-13
TLE 7259 G
Table 2 Parameter Voltages
Absolute Maximum Ratings Symbol Limit Values Min. Max. 40 V (LIN Spec 1.3(2.0); Line 10.1.3 (3.1.3)) Unit Remarks
Battery supply voltage Bus input voltage versus GND versus VS
VS
-0.3
t<1s
-40 -40 -40 -40 -0.3 40 40 40 40 5.5 V V V V V - -
VBUS,G VBUS,Vs Wake input versus GND VWK,G Wake input versus VS VWK,Vs Logic voltages at EN, TxD, VIO
RxD Inhibit Voltage versus GND Versus VS Output current at INH Electrostatic discharge voltage at VS, Bus, Wk versus GND Electrostatic discharge voltage Jedec Norm Temperatures Junction temperature
VINH,G VINH, Vs IINH VESD
-0,3 -40 -150 -4
40 0,3 80 4
V V mA kV pos. output current is internally limited human body model (100 pF via 1.5 k) human body model (100 pF via 1.5 k) -
VESD
-2
2
kV
Tj
-40
150
C
Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit.
Preliminary Data Sheet
9
Rev. 1.3, 2004-12-13
TLE 7259 G
Table 3 Parameter
Operating Range Symbol Limit Values Min. Max. 40 150 185 170 10 V C K/W 190 - (LIN Spec 1.3 (2.0); Line 10.1.2 (3.1.2)) - - C K 5 -40 - 150 - Unit Remarks
Supply Voltage range VS Junction temperature Thermal Resistances Junction ambient Thermal shutdown temp. Thermal shutdown hyst.
VS Tj Rthj-a TjSD
T
Thermal Shutdown (Junction Temperature)
Preliminary Data Sheet
10
Rev. 1.3, 2004-12-13
TLE 7259 G
Table 4
Electrical Characteristics
7.0 V < VS < 27 V; RL = 500 ; VEN > VEN,ON; -40 C < Tj < 125 C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. Parameter Current Consumption Current consumption at VS Symbol Limit Values Min. Typ. 0.8 Max. 1.5 mA recessive state, without RL; VTxD = VCC dominant state, without RL; VTxD = 0 V sleep mode, VWK = VS; VBUS = VS stand-by mode, VWK = VS; VBUS = VS Unit Remarks
IS
-
-
1.3
2.5
mA
Current consumption in sleep mode Current consumption in stand-by mode Receiver Output RxD HIGH level leakage current LOW level output current HIGH level input voltage threshold TxD input hysteresis LOW level input voltage threshold TxD pull-down resistance TxD low level leakage current
IS
-
-
14
A
IS
-
-
1.5
mA
IRD,H IRD,L
-5 1.9
0 -
+5 -
A mA
VRxD = 5 V; VBUS = VS VRxD = 0.9 V; VBUS = 0 V
recessive state - dominant state
Transmission Input TxD
VTD,H VTD,hys VTD,L RTD ITD
- - 0.3 x
-
0.7 x
V mV V k A mA
VEN
0.12 x -
VEN
- 350 - 3 - 800 10 -
VEN
100 - 1.5
VTxD = 5 V VEN = 0 V; VTxD = 0 V VTxD = 0.9 V
TxD dominant current ITD,L Wake = 0 V; VS = 12 V; standby mode
Preliminary Data Sheet
11
Rev. 1.3, 2004-12-13
TLE 7259 G
Table 4
Electrical Characteristics (cont'd)
7.0 V < VS < 27 V; RL = 500 ; VEN > VEN,ON; -40 C < Tj < 125 C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. Parameter Enable Input EN HIGH level input voltage threshold LOW level input voltage threshold EN input hysteresis EN pull-down resistance Enable inhibit high current Inhibit Output INH Inhibit Ron resistance Maximum INH output current Leakage current Wake Input WK High level input voltage VWK,H Low level input voltage VWK,L Pull-up current High level leakage current Dominant time for wake-up Symbol Limit Values Min. Typ. - - 300 30 - Max. 2 - 450 60 400 V V mV k A normal mode low power mode - - Unit Remarks
VEN,on VEN,off VEN,hys REN IEN, hc
- 0.8 150 15 50
VEN = 5 V, 3 V
RINH,on IINH IINH,lk
- 40 -5.0
36 - -
50 150 5.0
mA A
IINH = -15 mA VINH = 0 V
sleep mode; VINH = 0 V - - -
VS - 1 -
-0.3 -60 -5 30 - -30 - -
VS + 3 V VS V
3.3 V -3 5 150 A A s
IWK,PU IWK,L tWK
VS = 0 V; VWK = 40 V
-
Preliminary Data Sheet
12
Rev. 1.3, 2004-12-13
TLE 7259 G
Table 4
Electrical Characteristics (cont'd)
7.0 V < VS < 27 V; RL = 500 ; VEN > VEN,ON; -40 C < Tj < 125 C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. Parameter Bus Receiver Receiver threshold voltage, recessive to dominant edge Receiver dominant state Receiver threshold voltage, dominant to recessive edge Receiver recessive state Receiver center voltage Receiver hysteresis Symbol Limit Values Min. Typ. Max. V - Unit Remarks
VBUS,rd
0.42 x 0.48 x -
VS VBUS,dom - VBUS,dr
-
VS
- 0.42 x V (LIN Spec 1.3 (2.0); Line 10.1.9 (3.1.9))
VS
0.52 x 0.58 x V
VBUS,rec < VBUS < 27 V
VS VBUS,rec VBUS,c
0.58 x -
VS
- V (LIN Spec 1.3 (2.0); Line 10.1.10 (3.1.10) (LIN Spec 1.3 (2.0); Line 10.1.11 (3.1.11)
VS
0.475 0.5 x x VS VS 0.525 V x VS V
VBUS,hys 0.02 x 0.04 x 0.1 x VS VS VS
0.40 x 0.5 x 0.6 x
VBUS,hys = VBUS,rec - VBUS,dom
(LIN Spec 1.3 (2.0); Line 10.1.12 (3.1.12))
Wake-up threshold voltage Dominant time for bus wake-up
VBUS,wk tWK,bus
V s
- -
VS
30
VS
-
VS
150
Preliminary Data Sheet
13
Rev. 1.3, 2004-12-13
TLE 7259 G
Table 4
Electrical Characteristics (cont'd)
7.0 V < VS < 27 V; RL = 500 ; VEN > VEN,ON; -40 C < Tj < 125 C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. Parameter Bus Transmitter Bus recessive output voltage Bus dominant output voltage Symbol Limit Values Min. Typ. - - Max. Unit Remarks
VBUS,ro VBUS,do
0.8 x
VS
1.2
V V
VTxD = high Level VTxD = 0 V; VS = 5 V; RL = 500 ;
(LIN Spec 1.3; Line 10.1.13)
VS
-
-
-
2.0
V
VS = 18 V; RL = 500 ;
(LIN Spec 1.3; Line 10.1.14)
Bus short circuit current Leakage current
IBUS,sc
40
100
150
mA
VBUS = 13.5 V;
(LIN Spec 1.3 (2.0); Line 10.1.4 (3.1.4))
IBUS,lk
-500
-70
-
A
VS = 0 V; VBUS = -8 V;
(LIN Spec 1.3 (2.0); Line 10.1.7 (3.1.7))
-
10
20
A
VS = 0 V; VBUS = 18 V;
(LIN Spec 1.3 (2.0); Line 10.1.8 (3.1.8))
-1
-
-
mA
VS = 18 V; VBUS = 0 V;
(LIN Spec 1.3 (2.0); Line 10.1.5 (3.1.5))
-
-
20
A
VS = 8 V; VBUS = 18 V;
(LIN Spec 1.3 (2.0); Line 10.1.6 (3.1.6))
Bus pull-up resistance
RBUS
20
30
47
k
Normal mode (LIN Spec 1.3 (2.0); Line 10.2.2 (3.2.2)) Sleep mode
LIN output current
IBUS
5
30
60
A
Preliminary Data Sheet
14
Rev. 1.3, 2004-12-13
TLE 7259 G
Table 4
Electrical Characteristics (cont'd)
7.0 V < VS < 27 V; RL = 500 ; VEN > VEN,ON; -40 C < Tj < 125 C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Min. Dynamic Transceiver Characteristics Slew rate falling edge Typ. - Max. -1 V/s 60% > Vbus > 40%; 1 s < ( = RL x CBUS) < 5 s; VS = 13.5 V; normal mode; (LIN Spec 1.3; Line 10.3.1) 40% < Vbus < 60%; 1 s < ( = RL x CBUS) < 5 s; VS = 13.5 V; normal mode; (LIN Spec 1.3; Line 10.3.1)
1) 1)
Unit Remarks
tfslope
-3
Slew rate rising edge
trslope
1
-
3
V/s
Slope symmetry
tslopesym
-5
-
5
s
tfslope - trslope; VS = 13.5 V;
(LIN Spec 1.3; Line 10.3.2)
Propagation delay TxD LOW to bus Propagation delay TxD HIGH to bus Propagation delay bus dominant to RxD LOW
td(L),T
-
1
4
s
VEN = 5 V;
(LIN Spec 1.3; Line 10.3.6)
td(H),T
-
1
4
s
VEN = 5 V;
(LIN Spec 1.3; Line 10.3.6)
td(L),R
-
1
6
s
VCC = 5 V; CRxD = 20 pF; RRxD = 2.4 k;
(LIN Spec 1.3; Line 10.3.7)
Propagation delay bus recessive to RxD HIGH
td(H),R
-
1
6
s
VCC = 5 V; CRxD = 20 pF; RRxD = 2.4 k;
(LIN Spec 1.3; Line 10.3.7)
Preliminary Data Sheet
15
Rev. 1.3, 2004-12-13
TLE 7259 G
Table 4
Electrical Characteristics (cont'd)
7.0 V < VS < 27 V; RL = 500 ; VEN > VEN,ON; -40 C < Tj < 125 C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. Parameter Receiver delay symmetry Transmitter delay symmetry Wake-up delay time Delay time for change sleep/stand by mode normal mode Delay time for change normal mode - sleep mode Symbol Limit Values Min. Typ. - Max. 2 s -2 Unit Remarks
tsym,R
tsym,R = td(L),R - td(H),R; (LIN Spec 1.3; Line 10.3.7) tsym,T = td(L),T - td(H),T;
(LIN Spec 1.3; Line 10.3.8)
tsym,T
-2
-
2
s
twake
tsnorm
30 -
100 -
150 10
s s
Tj 125 C
-
tnsleep
-
-
10
s
-
TxD dominant time out ttimeout TxD dominant time out ttorec recovery time
6 -
12 10
20 -
ms s
VTxD = 0 V
-
Preliminary Data Sheet
16
Rev. 1.3, 2004-12-13
TLE 7259 G
Table 4
Electrical Characteristics (cont'd)
7.0 V < VS < 27 V; RL = 500 ; VEN > VEN,ON; -40 C < Tj < 125 C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. Parameter Duty cycle D1 (for worst case at 20 kBit/s) Symbol tduty1 Limit Values Min. Typ. Max. - duty cycle 11) THRec(max) = 0.744 x VS; THDom(max) = 0.581 x VS; VS = 7.0 ... 18 V; tbit = 50 s; D1 = tbus_rec(min)/2 tbit; (LIN Spec 2.0; line 3.3.1) duty cycle 21) THRec(max) = 0.422 x VS; THDom(max) = 0.284 x VS VS = 7.6 ... 18 V; tbit = 50 s; D2 = tbus_rec(max)/2 tbit; (LIN Spec 2.0; line 3.3.2) 0.396 - Unit Remarks
Duty cycle D2 (for worst case at 20 kBit/s)
tduty2
-
-
0.581
1) Bus load conditions concerning LIN spec 2.0 Cbus, Rbus = 1 nF, 1 k / 6.8 nF, 660 / 10 nF, 500
Preliminary Data Sheet
17
Rev. 1.3, 2004-12-13
TLE 7259 G
Diagrams
VS 100 nF
EN INH V C TxD RxD 20 pF
1 k
Bus C B us
GND
WK
AEA03611.VSD
Figure 4
VTxD VCC
Test Circuits
GND
VBus VS
td(L),T
td(H),T
t
VBus,rd
GND
VBus,dr
td(L),R
VRxD VCC 0.3 x VCC
td(H),R td(H),TR
0.7 x VCC
t
td(L),TR
GND
t
AET03612.VSD
Figure 5
Timing Diagrams for Dynamic Characteristics
18 Rev. 1.3, 2004-12-13
Preliminary Data Sheet
TLE 7259 G
Application
VB at LIN Bus
Master Node TLE 7259 100 nF 1 k Bus 1 nF INH GND WK VS EN RxD TxD
VC
P
100 nF
GND
INH
5V VQ 22 F GND ECU 1
e. g. TLE 4263 22 F 100 nF VI
Slave Node TLE 7259 100 nF VS EN RxD TxD Bus 220 pF INH GND WK
VC
P
100 nF
GND
INH
VQ
5V
e. g. TLE 4263 22 F 100 nF VI 22 F GND ECU X
AEA03511.VSD
Figure 6
Application Circuit with Bus Short to GND Feature Applied
19 Rev. 1.3, 2004-12-13
Preliminary Data Sheet
TLE 7259 G
VB at LIN Bus
Master Node TLE 7259 100 nF 1 k Bus 1 nF INH GND WK VS EN RxD TxD
VC
P
100 nF
GND
INH
VQ
5V
e. g. TLE 4263 22 F 100 nF VI 22 F GND ECU 1
Slave Node 100 nF VS
VC TLE 7259 EN RxD TxD Bus 220 pF VS INH GND WK 100 nF GND
P
INH
VQ
5V
e. g. TLE 4263 22 F 100 nF VI 22 F GND ECU X
AEA03512.VSD
Figure 7
Application Circuit without Bus Short to GND Feature
Preliminary Data Sheet
20
Rev. 1.3, 2004-12-13
TLE 7259 G
Package Outlines
0.33 0.08 x 45
1.75 MAX. 0.1 MIN. (1.5)
4 -0.21)
1.27 0.41 +0.1 -0.05 8 5
0.1
C
6 0.2
0.64 0.25
0.2 M A C x8
Index Marking 1
4
5 -0.21)
1)
A
Index Marking (Chamfer) Does not include plastic or metal protrusion of 0.15 max. per side
8 MAX.
0.2 +0.05 -0
.01
GPS09032
Figure 8
P-DSO-8-3 (Plastic Dual Small Outline)
You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. SMD = Surface Mounted Device Preliminary Data Sheet 21 Dimensions in mm Rev. 1.3, 2004-12-13
TLE 7259 G
Preliminary Data Sheet
22
Rev. 1.3, 2004-12-13
TLE 7259 G Revision History: Previous Version: Page 3 3 7 9 9 11 11 15 17 17 15 15 15 2004-12-13 Rev.1.2 Rev. 1.3
Subjects (major changes since last revision) List of features change Description changed Description changed for the BUS short to GND Feature Table 2 Output current at INH deleted VINH,G Inhibit Voltage values changed IS Current consumption in stand-by mode added Table 4 voltage range changed to 7.0 V < VS < 27 V tslopesym Slope symmetry updated Duty cycle D3 (for worst case at 10.4 kBit/s) deleted Duty cycle D4 (for worst case at 10.4 kBit/s) deleted tfslope Slew rate falling edge updated according to LIN 1.3 / 2.0 td(L),TPropagation delay TxD LOW to bus (max: 4s) td(H),TPropagation delay TxD HIGH to bus (max: 4s) References to LIN 2.0 added
Template: central_tmplt_a5.fm / 5 / 2003-04-01

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