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HFA1113
Data Sheet July 11, 2005 FN1342.6
850MHz, Low Distortion, Output Limiting, Programmable Gain, Buffer Amplifier
The HFA1113 is a high speed Buffer featuring user programmable gain and output limiting coupled with ultra high speed performance. This buffer is the ideal choice for high frequency applications requiring output limiting, especially those needing ultra fast overload recovery times. The output limiting function allows the designer to set the maximum positive and negative output levels, thereby protecting later stages from damage or input saturation. The sub-nanosecond overdrive recovery time quickly returns the amplifier to linear operation following an overdrive condition. A unique feature of the pinout allows the user to select a voltage gain of +1, -1, or +2, without the use of any external components, as described in the "Application Information" section. Compatibility with existing op amp pinouts provides flexibility to upgrade low gain amplifiers, while decreasing component count. Unlike most buffers, the standard pinout provides an upgrade path should a higher closed loop gain be needed at a future date. Component and composite video systems will also benefit from this buffer's performance, as indicated by the excellent gain flatness, and 0.02%/0.04 Degree Differential Gain/Phase specifications (RL = 150). For Military product, refer to the HFA1113/883 data sheet.
Features
* User Programmable Output Voltage Limiting * User Programmable For Closed-Loop Gains of +1, -1 or +2 Without Use of External Resistors * Wide -3dB Bandwidth. . . . . . . . . . . . . . . . . . . . . . 850MHz * Excellent Gain Flatness (to 100MHz). . . . . . . . . . 0.07dB * Low Differential Gain and Phase . . . 0.02%/0.04 Degrees * Low Distortion (HD3, 30MHz) . . . . . . . . . . . . . . . . -73dBc * Very Fast Slew Rate . . . . . . . . . . . . . . . . . . . . . 2400V/s * Fast Settling Time (0.1%). . . . . . . . . . . . . . . . . . . . . 13ns * High Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 60mA * Excellent Gain Accuracy . . . . . . . . . . . . . . . . . . . 0.99V/V * Overdrive Recovery . . . . . . . . . . . . . . . . . . . . . . . . . <1ns * Standard Operational Amplifier Pinout * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* RF/IF Processors * Driving Flash A/D Converters * High-Speed Communications * Impedance Transformation
Ordering Information
PART NUMBER (BRAND) HFA1113IB (H1113I) HFA1113IBZ (H1113I) (Note) HFA1113IBZ96 (H1113I) (Note) HFA11XXEVAL TEMP. RANGE (oC) PACKAGE -40 to 85 8 Ld SOIC -40 to 85 PKG. DWG. # M8.15
* Line Driving * Video Switching and Routing * Radar Systems
8 Ld SOIC M8.15 (Pb-free) 8 Ld SOIC Tape and Reel M8.15 (Pb-free) DIP Evaluation Board For High Speed Op Amps
* Medical Imaging Systems
Pin Descriptions
NAME NC -IN +IN VPIN NUMBER 1 2 3 4 5 6 7 8 DESCRIPTION No Connection Inverting Input Non-Inverting Input Negative Supply Lower Output Limit Output Positive Supply Upper Output Limit
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout
HFA1113 (SOIC) TOP VIEW
NC -IN +IN V1 300 2 3 4 + 6 5 OUT VL 300 8 7 VH V+
VL OUT V+ VH
-
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1999, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HFA1113
Absolute Maximum Ratings
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Voltage at VH or VL Terminal . . . . . . . . . . . . . . (V+) + 2V to (V-) - 2V Output Current (50% Duty Cycle) . . . . . . . . . . . . . . . . . . . . . . 60mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS Output Offset Voltage
VSUPPLY = 5V, AV = +1, RL = 100, Unless Otherwise Specified TEST CONDITIONS TEMP. (oC) MIN TYP MAX UNITS
25 Full
39 35 25 240 2.5
8 10 45 9 37 25 50 300 2 2.8
25 35 40 65 360 -
mV mV V/oC dB dB nV/Hz pA/Hz A A k pF V
Output Offset Voltage Drift PSRR
Full 25 Full
Input Noise Voltage (Note 3) +Input Noise Current (Note 3) Non-Inverting Input Bias Current
100kHz 100kHz
25 25 25 Full
Non-Inverting Input Resistance Inverting Input Resistance (Note 2) Input Capacitance Input Common Mode Range TRANSFER CHARACTERISTICS Gain AV = +1, VIN = +2V
25 25 25 Full
25 Full
0.980 0.975 1.96 1.95 -
0.990 1.98 0.02
1.020 1.025 2.04 2.05 -
V/V V/V V/V V/V %
AV = +2, VIN = +1V
25 Full
DC Non-Linearity (Note 3) OUTPUT CHARACTERISTICS Output Voltage (Note 3)
AV = +2, 2V Full Scale
25
AV = -1
25 Full
3.0 2.5 50 35 -
3.3 3.0 60 50 0.3
-
V V mA mA
Output Current (Note 3)
RL = 50
25, 85 -40
Closed Loop Output Impedance POWER SUPPLY CHARACTERISTICS Supply Voltage Range Supply Current (Note 3)
DC, AV = +2
25
Full 25 Full
4.5 -
21 -
5.5 26 33
V mA mA
2
FN1342.6 July 11, 2005
HFA1113
Electrical Specifications
PARAMETER AC CHARACTERISTICS -3dB Bandwidth (VOUT = 0.2VP-P, Notes 2, 3) AV = -1 AV = +1 AV = +2 Slew Rate (VOUT = 5VP-P, Note 2) AV = -1 AV = +1 AV = +2 Full Power Bandwidth (VOUT = 5VP-P, Note 3) AV = -1 AV = +1 AV = +2 Gain Flatness (to 30MHz, Notes 2, 3) AV = -1 AV = +1 AV = +2 Gain Flatness (to 50MHz, Notes 2, 3) AV = -1 AV = +1 AV = +2 Gain Flatness (to 100MHz, Notes 2, 3) Linear Phase Deviation (to 100MHz, Note 3) AV = -1 AV = +2 AV = -1 AV = +1 AV = +2 2nd Harmonic Distortion (30MHz, VOUT = 2VP-P, Notes 2, 3) AV = -1 AV = +1 AV = +2 3rd Harmonic Distortion (30MHz, VOUT = 2VP-P, Notes 2, 3) AV = -1 AV = +1 AV = +2 2nd Harmonic Distortion (50MHz, VOUT = 2VP-P, Notes 2, 3) AV = -1 AV = +1 AV = +2 3rd Harmonic Distortion (50MHz, VOUT = 2VP-P, Notes 2, 3) AV = -1 AV = +1 AV = +2 2nd Harmonic Distortion (100MHz, VOUT = 2VP-P, Notes 2, 3) AV = -1 AV = +1 AV = +2 3rd Harmonic Distortion (100MHz, VOUT = 2VP-P , Notes 2, 3) AV = -1 AV = +1 AV = +2 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 450 500 350 1500 800 1100 800 850 550 2400 1500 1900 300 150 220 0.02 0.1 0.015 0.05 0.2 0.036 0.10 0.07 0.13 0.83 0.05 -52 -57 -52 -71 -73 -72 -47 -53 -47 -63 -68 -65 -41 -50 -42 -55 -49 -62 0.04 0.08 0.22 -45 -65 -40 -55 -35 -45 MHz MHz MHz V/s V/s V/s MHz MHz MHz dB dB dB dB dB dB dB dB Degrees Degrees Degrees dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc VSUPPLY = 5V, AV = +1, RL = 100, Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP. (oC) MIN TYP MAX UNITS
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FN1342.6 July 11, 2005
HFA1113
Electrical Specifications
PARAMETER 3rd Order Intercept (AV = +2, Note 3) 1dB Compression (AV = +2, Note 3) Reverse Isolation (S12, Note 3) VSUPPLY = 5V, AV = +1, RL = 100, Unless Otherwise Specified (Continued) TEST CONDITIONS 100MHz 300MHz 100MHz 300MHz 40MHz 100MHz 600MHz TRANSIENT CHARACTERISTICS Rise Time (VOUT = 0.5V Step, Note 2) AV = -1 AV = +1 AV = +2 Rise Time (VOUT = 2V Step) AV = -1 AV = +1 AV = +2 Overshoot (VOUT = 0.5V Step, Input tR/tF = 200ps, Notes 2, 3, 4) 0.1% Settling Time (Note 3) 0.05% Settling Time Differential Gain AV = -1 AV = +1 AV = +2 VOUT = 2V to 0V VOUT = 2V to 0V AV = +1, 3.58MHz, RL = 150 AV = +2, 3.58MHz, RL = 150 Differential Phase AV = +1, 3.58MHz, RL = 150 AV = +2, 3.58MHz, RL = 150 OUTPUT LIMITING CHARACTERISTICS Clamp Accuracy (Note 3) 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 500 480 700 0.82 1.06 1.00 12 45 6 13 20 0.03 0.02 0.05 0.04 800 750 1000 30 65 20 20 33 ps ps ps ns ns ns % % % ns ns % % Degrees Degrees TEMP. (oC) 25 25 25 25 25 25 25 MIN TYP 28 13 19 12 -70 -60 -32 MAX UNITS dBm dBm dBm dBm dB dB dB
AV = +2, VH = +1V, VL = -1V, Unless Otherwise Specified VIN = 1.6V, AV = -1 25 Full 100 7 0.75 -5.0 to +2.0 -2.0 to +5.0 50 500 150 200 1.5 200 300 mV mV % ns V V A A MHz
Clamp Overshoot Overdrive Recovery Time (Note 3) Negative Clamp Range Positive Clamp Range Clamp Input Bias Current (Note 3)
VIN = 1V, Input tR/tF = 500ps VIN = 1V
25 25 25 25 25 Full
Clamp Input Bandwidth (Note 3) NOTES:
VH or VL = 100mVP-P
25
2. This parameter is not tested. The limits are guaranteed based on lab characterization, and reflect lot-to-lot variation. 3. See Typical Performance Curves for more information. 4. Overshoot decreases as input transition times increase, especially for AV = +1. Please refer to Typical Performance Curves.
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FN1342.6 July 11, 2005
HFA1113 Application Information
Closed Loop Gain Selection
The HFA1113 features a novel design which allows the user to select from three closed loop gains, without any external components. The result is a more flexible product, fewer part types in inventory, and more efficient use of board space. This "buffer" operates in closed loop gains of -1, +1, or +2, and gain selection is accomplished via connections to the Inputs. Applying the input signal to +IN and floating -IN selects a gain of +1, while grounding -IN selects a gain of +2. A gain of -1 is obtained by applying the input signal to -IN with +IN grounded. The table below summarizes these connections:
CONNECTIONS GAIN (ACL) -1 +1 +2 +INPUT (PIN 3) GND Input Input -INPUT (PIN 2) Input NC (Floating) GND
50 45 40 AV = +1
avoided by placing a resistor (RS) in series with the output prior to the capacitance. Figure 1 details starting points for the selection of this resistor. The points on the curve indicate the RS and CL combinations for the optimum bandwidth, stability, and settling time, but experimental fine tuning is recommended. Picking a point above or to the right of the curve yields an overdamped response, while points below or left of the curve indicate areas of underdamped performance. RS and CL form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth of 850MHz. By decreasing RS as CLincreases (as illustrated in the curves), the maximum bandwidth is obtained without sacrificing stability. Even so, bandwidth does decrease as you move to the right along the curve. For example, at AV = +1, RS = 50, CL = 30pF, the overall bandwidth is limited to 300MHz, and bandwidth drops to 100MHz at AV = +1, RS = 5, CL = 340pF.
PC Board Layout
The frequency response of this amplifier depends greatly on the amount of care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! Attention should be given to decoupling the power supplies. A large value (10F) tantalum in parallel with a small value chip (0.1F) capacitor works well in most cases. Terminated microstrip signal lines are recommended at the input and output of the device. Capacitance directly on the output must be minimized, or isolated as discussed in the next section. For unity gain applications, care must also be taken to minimize the capacitance to ground seen by the amplifier's inverting input. At higher frequencies this capacitance will tend to short the -INPUT to GND, resulting in a closed loop gain which increases with frequency. This will cause excessive high frequency peaking and potentially other problems as well. An example of a good high frequency layout is the Evaluation Board shown in Figure 3.
RS ()
35 30 25 20 15 10 5 0 0 40 80 120 160 200 240 280 320 360 400 AV = +2
LOAD CAPACITANCE (pF)
FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD CAPACITANCE
Evaluation Board
The performance of the HFA1113 may be evaluated using the HFA11XX Evaluation Board, slightly modified as follows: 1. Remove the 500 feedback resistor (R2), and leave the connection open. 2. a. For AV = +1 evaluation, remove the 500 gain setting resistor (R1), and leave pin 2 floating. b. For AV = +2, replace the 500 gain setting resistor with a 0 resistor to GND. The modified schematic and layout of the board are shown in Figures 2 and 3. To order evaluation boards (part number HFA11XXEVAL), please contact your local sales office.
NOTE: The SOIC version may be evaluated in the DIP board by using a SOIC-to-DIP adapter such as Aries Electronics Part Number 08-350000-10.
FN1342.6 July 11, 2005
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly terminated transmission line will degrade the amplifier's phase margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be
5
HFA1113
.
(AV = +1)
OR 0 (AV = +2) R1 1 50 IN 2 3 4 8 7 50 6 5 GND -5V GND OUT VL VH 0.1F 10F +5V
between the positive and negative inputs. This buffer forces -IN to track +IN, and sets up a slewing current of: (V-IN - VOUT)/RF + V-IN/RG This current is mirrored onto the high impedance node (Z) by QX3-QX4, where it is converted to a voltage and fed to the output via another unity gain buffer. If no clamping is utilized, the high impedance node may swing within the limits defined by QP4 and QN4. Note that when the output reaches its quiescent value, the current flowing through -IN is reduced to only that small current (-IBIAS) required to keep the output at the final voltage. Tracing the path from VH to Z illustrates the effect of the clamp voltage on the high impedance node. VH decreases by 2VBE (QN6 and QP6) to set up the base voltage on QP5.
V+ VH QP3 1 QP4 50K (30K FOR VL ) R1 Z +1 200 QN5 QP2 QP5 QN6 QP6 QN4 V-IN RG (INTERNAL) -IN RF = 300 (INTERNAL) VOUT VH
10F
0.1F
FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC
TOP LAYOUT
+IN OUT V+ VL VGND QP1 +IN VV+ QN1
QN2 ICLAMP
BOTTOM LAYOUT
QN3
V300
FIGURE 4. HFA1113 SIMPLIFIED VH CLAMP CIRCUITRY FIGURE 3. EVALUATION BOARD LAYOUT
Limiting Operation
General
The HFA1113 features user programmable output clamps to limit output voltage excursions. Clamping action is obtained by applying voltages to the VH and VL terminals (pins 8 and 5) of the amplifier. VH sets the upper output limit, while VL sets the lower clamp level. If the amplifier tries to drive the output above VH, or below VL, the clamp circuitry limits the output voltage at VH or VL ( the clamp accuracy), respectively. The low input bias currents of the clamp pins allow them to be driven by simple resistive divider circuits, or active elements such as amplifiers or DACs.
QP5 begins to conduct whenever the high impedance node reaches a voltage equal to QP5's base voltage + 2VBE (QP5 and QN5). Thus, QP5 clamps node Z whenever Z reaches VH. R1 provides a pull-up network to ensure functionality with the clamp inputs floating. A similar description applies to the symmetrical low clamp circuitry controlled by VL. When the output is clamped, the negative input continues to source a slewing current (ICLAMP) in an attempt to force the output to the quiescent voltage defined by the input. QP5 must sink this current while clamping, because the -IN current is always mirrored onto the high impedance node. The clamping current is calculated as: ICLAMP = (V-IN - VOUT CLAMPED)/300 + V-IN/RG. As an example, a unity gain circuit with VIN = 2V, and VH = 1V, would have ICLAMP = (2V - 1V)/300 + 2V/ = 3.33mA (RG = because -IN is floated for unity gain applications). Note that ICC will increase by ICLAMP when the output is clamp limited.
FN1342.6 July 11, 2005
Clamp Circuitry
Figure 4 shows a simplified schematic of the HFA1113 input stage, and the high clamp (VH) circuitry. As with all current feedback amplifiers, there is a unity gain buffer (QX1 - QX2) 6
HFA1113
Clamp Accuracy
The clamped output voltage will not be exactly equal to the voltage applied to VH or VL. Offset errors, mostly due to VBE mismatches, necessitate a clamp accuracy parameter which is found in the device specifications. Clamp accuracy is a function of the clamping conditions. Referring again to Figure 4, it can be seen that one component of clamp accuracy is the VBE mismatch between the QX6 transistors, and the QX5 transistors. If the transistors always ran at the same current level there would be no VBE mismatch, and no contribution to the inaccuracy. The QX6 transistors are biased at a constant current, but as described earlier, the current through QX5 is equivalent to ICLAMP. VBE increases as ICLAMP increases, causing the clamped output voltage to increase as well. ICLAMP is a function of the overdrive level (AVCL x VIN - VOUT CLAMPED), so clamp accuracy degrades as the overdrive increases. As an example, the specified accuracy of 100mV (AV = -1, VH = 1V) for a 1.6X overdrive degrades to 240mV for a 3X (200%) overdrive, as shown in Figure 43. Consideration must also be given to the fact that the clamp voltages have an affect on amplifier linearity. The "Nonlinearity Near Clamp Voltage" curve, Figure 48, illustrates the impact of several clamp levels on linearity. restrictions indicated in the specifications. For example, the HFA1113 could be limited to ECL output levels by setting VH = -0.8V and VL = -1.8V. VH and VL may be connected to the same voltage (GND for instance) but the result won't be in a DC output voltage from an AC input signal. A 150mV - 200mV AC signal will still be present at the output.
Recovery from Overdrive
The output voltage remains at the clamp level as long as the overdrive condition remains. When the input voltage drops below the overdrive level (VCLAMP/AVCL) the amplifier will return to linear operation. A time delay, known as the Overdrive Recovery Time, is required for this resumption of linear operation. The plots of "Unclamped Performance" and "Clamped Performance" (Figures 41 and 42) highlight the HFA1113's subnanosecond recovery time. The difference between the unclamped and clamped propagation delays is the overdrive recovery time. The appropriate propagation delays are 8.0ns for the unclamped pulse, and 8.8ns for the clamped (2X overdrive) pulse yielding an overdrive recovery time of 800ps. The measurement uses the 90% point of the output transition to ensure that linear operation has resumed. Note: The propagation delay illustrated is dominated by the fixturing. The delta shown is accurate, but the true HFA1113 propagation delay is 500ps. Overdrive recovery time is also a function of the overdrive level. Figure 47 details the overdrive recovery time for various clamp and overdrive levels.
Clamp Range
Unlike some competitor devices, both VH and VL have usable ranges that cross 0V. While VH must be more positive than VL , both may be positive or negative, within the range
Typical Performance Curves
200 AV = +2 150 OUTPUT VOLTAGE (mV)
VSUPPLY = 5V, TA = 25oC, RL = 100, Unless Otherwise Specified
2.0 AV = +2 1.5 OUTPUT VOLTAGE (V) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0
100 50 0 -50 -100 -150 -200 TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 5. SMALL SIGNAL PULSE RESPONSE
FIGURE 6. LARGE SIGNAL PULSE RESPONSE
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FN1342.6 July 11, 2005
HFA1113 Typical Performance Curves
200 150 OUTPUT VOLTAGE (mV) 100 50 0 -50 -100 -150 -200 TIME (5ns/DIV.) AV = +1
VSUPPLY = 5V, TA = 25oC, RL = 100, Unless Otherwise Specified (Continued)
2.0 1.5 OUTPUT VOLTAGE (V) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV.) AV = +1
FIGURE 7. SMALL SIGNAL PULSE RESPONSE
FIGURE 8. LARGE SIGNAL PULSE RESPONSE
200 150 OUTPUT VOLTAGE (mV) 100 50 0 -50 -100 -150 -200 TIME (5ns/DIV.) AV = -1
2.0 1.5 OUTPUT VOLTAGE (V) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV.) AV = -1
FIGURE 9. SMALL SIGNAL PULSE RESPONSE
FIGURE 10. LARGE SIGNAL PULSE RESPONSE
NORMALIZED GAIN (dB)
6 3 0 -3 PHASE -6 -9 AV = +2 AV = -1 AV = +1 AV = -1 AV = +2 0 -90 -180 -270 -360 VOUT = 200mVP-P GAIN AV = +1 GAIN (dB) NORMALIZED PHASE (DEGREES) AV = +2, VOUT = 200mVP-P 9 6 3 0 PHASE 0 RL = 100 RL = 50 RL = 1k 0.3 1 10 100 FREQUENCY (MHz) -90 -180 -270 -360 1000 GAIN RL = 50 RL = 100 RL = 1k PHASE (DEGREES)
0.3
1
10 100 FREQUENCY (MHz)
1000
FIGURE 11. FREQUENCY RESPONSE
FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS
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FN1342.6 July 11, 2005
HFA1113 Typical Performance Curves
6 3 GAIN (dB) 0 -3 -6 -9 PHASE (DEGREES) PHASE 0 -90 RL = 100 RL = 50 RL = 1k 0.3 1 10 100 FREQUENCY (MHz) -180 -270 -360 1000 RL = 1k RL = 100 RL = 50 AV = +1, VOUT = 200mVP-P GAIN (dB) GAIN
VSUPPLY = 5V, TA = 25oC, RL = 100, Unless Otherwise Specified (Continued)
6 3 GAIN 0 -3 -6 -9 RL = 100 180 90 RL = 50 RL = 1k 0.3 1 10 100 FREQUENCY (MHz) 0 -90 -180 1000 PHASE (DEGREES) PHASE (DEGREES) PHASE RL = 100 RL = 50 AV = -1, VOUT = 200mVP-P RL = 1k
FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS
FIGURE 14. FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS
12 GAIN (dB) 9 6 3 0
AV = +2 GAIN 4.0VP-P 2.5VP-P PHASE
6 GAIN (dB) 1VP-P 3 0 -3 -6 PHASE (DEGREES) 0 -90 4.0VP-P 2.5VP-P 1VP-P -180 -270 -360
AV = +1 GAIN VOUT = 4VP-P VOUT = 2.5VP-P PHASE VOUT = 1VP-P 0 -90 VOUT = 4VP-P VOUT = 2.5VP-P VOUT = 1VP-P -270 -360 -180
0.3
1
10 100 FREQUENCY (MHz)
1000
0.3
1
10 100 FREQUENCY (MHz)
1000
FIGURE 15. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES
FIGURE 16. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES
6 GAIN (dB) 3 0 -3 -6
15 AV = -1 GAIN VOUT = 2.5VP-P VOUT = 4VP-P VOUT = 1VP-P NORMALIZED GAIN (dB) 12 9 6 3 0 -3 -6 -9 -12
VOUT = 5VP-P
PHASE 180 90 VOUT = 4VP-P VOUT = 2.5VP-P VOUT = 1VP-P 0 -90 -180 0.3 1 10 100 FREQUENCY (MHz) 1000 PHASE (DEGREES)
AV = -1 AV = +2 AV = +1
-15 0.3
1
10 FREQUENCY (MHz)
100
1000
FIGURE 17. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES
FIGURE 18. FULL POWER BANDWIDTH
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FN1342.6 July 11, 2005
HFA1113 Typical Performance Curves
900 850 800 BANDWIDTH (MHz) 750 700 650 600 550 500 -50 -25 0 25 50 75 100 125 TEMPERATURE (oC) AV = +2 AV = +1 NORMALIZED GAIN (dB) AV = -1
VSUPPLY = 5V, TA = 25oC, RL = 100, Unless Otherwise Specified (Continued)
0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 1 10 FREQUENCY (MHz) 100 AV = +2 AV = +1 AV = -1
FIGURE 19. -3dB BANDWIDTH vs TEMPERATURE
FIGURE 20. GAIN FLATNESS
4 3 2 DEVIATION (DEGREES) SETTLING ERROR (%) 1 0 -1 -2 -3 -4 -5 -6 0 15 30 45 60 75 90 105 120 135 150 FREQUENCY (MHz) -2 3 8 13 18 23 28 33 38 43 48 AV = +2 AV = +1 AV = -1 0.6 0.4 0.2 0.1 0 -0.1 -0.2 -0.4 -0.6 AV = +2, VOUT = 2V
TIME (ns)
FIGURE 21. DEVIATION FROM LINEAR PHASE
FIGURE 22. SETTLING RESPONSE
-30 PHASE -36 -42 GAIN (dB) -48 -54 GAIN (dB) -60 -66 -72 -78 -84 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (MHz) AV = +2 AV = -1 AV = +2 AV = -1 AV = +1 AV = -1 -24 -30 -36 -42 -48 -54 -60 100 190 280 370 460 550 640 730 FREQUENCY (MHz) AV = -1 AV = -1 AV = +2 GAIN AV = +2 AV = +1
180 90 45 0
820 910 1000
FIGURE 23. LOW FREQUENCY REVERSE ISOLATION (S12)
FIGURE 24. HIGH FREQUENCY REVERSE ISOLATION (S12)
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FN1342.6 July 11, 2005
PHASE (DEGREES)
-24
235
HFA1113 Typical Performance Curves
OUTPUT POWER AT 1dB COMPRESSION (dBm) 20 18 16 14 12 10 8 6 4 2 0 100 200 300 FREQUENCY (MHz) 400 500 0 100 200 300 FREQUENCY (MHz) 400 AV = +1 AV = +2 INTERCEPT POINT (dBm) AV = -1 AV = -1 20 AV = +2
VSUPPLY = 5V, TA = 25oC, RL = 100, Unless Otherwise Specified (Continued)
30 2 - TONE
AV = +1 10
FIGURE 25. 1dB GAIN COMPRESSION vs FREQUENCY
FIGURE 26. THIRD ORDER INTERMODULATION INTERCEPT vs FREQUENCY
-20 -30
-20 AV = +2 -30 -40 DISTORTION (dBc) -50 -60 -70 -80
AV = +2
DISTORTION (dBc)
-40 -50 -60 100MHz -70 -80 -90 -100 -6 -3 0 3 6 9 12 15 OUTPUT POWER (dBm) 50MHz 30MHz
50MHz -90 -100 -6 -3 0 3 6 9 100MHz
30MHz
12
15
18
OUTPUT POWER (dBm)
FIGURE 27. SECOND HARMONIC DISTORTION vs POUT
FIGURE 28. THIRD HARMONIC DISTORTION vs POUT
-20 -30 -40 DISTORTION (dBc) DISTORTION (dBc) -50 -60 -70 -80 -90 -100 -6 -3 0 3 6 9 OUTPUT POWER (dBm) 12 15 100MHz 50MHz 30MHz AV = +1
-20 AV = +1 -30 -40 -50 -60 -70 100MHz -80 -90 -100 -6 -3 0 3 6 9 OUTPUT POWER (dBm) 12 15 50MHz 30MHz
FIGURE 29. SECOND HARMONIC DISTORTION vs POUT
FIGURE 30. THIRD HARMONIC DISTORTION vs POUT
11
FN1342.6 July 11, 2005
HFA1113 Typical Performance Curves
-20 AV = -1 -30 -40 DISTORTION (dBc) DISTORTION (dBc) -50 -60 -70 100MHz -80 -90 -100 -6 -3 0 3 6 9 OUTPUT POWER (dBm) 12 15 50MHz 30MHz -30 -40 -50 -60 -70 -80 50MHz -90 -100 -6 -3 0 3 6 9 12 15 OUTPUT POWER (dBm) 100MHz 30MHz
VSUPPLY = 5V, TA = 25oC, RL = 100, Unless Otherwise Specified (Continued)
-20 AV = -1
FIGURE 31. SECOND HARMONIC DISTORTION vs POUT
FIGURE 32. THIRD HARMONIC DISTORTION vs POUT
0.04
60 VOUT = 0.5V 50
PERCENT ERROR (%)
0.02 OVERSHOOT (%) 40
AV = +1
0
30
20 AV = -1 10 0 AV = +2 100 300 500 700 900 1100 1300
-0.02
-0.04 -3.0 -2.0 -1.0 0 1.0 INPUT VOLTAGE (V) 2.0 3.0
INPUT RISE TIME (ps)
FIGURE 33. INTEGRAL LINEARITY ERROR
60 VOUT = 1V 50 OVERSHOOT (%) 50 OVERSHOOT (%) 40 30
FIGURE 34. OVERSHOOT vs INPUT RISE TIME
60 VOUT = 2V
40 AV = +1 30
AV = +1 AV = -1
20 AV = -1 10 AV = +2 0 100 300 500 700 900 1100 1300
20
AV = +2
10 0 100
300
INPUT RISE TIME (ps)
500 700 900 INPUT RISE TIME (ps)
1100
1300
FIGURE 35. OVERSHOOT vs INPUT RISE TIME
FIGURE 36. OVERSHOOT vs INPUT RISE TIME
12
FN1342.6 July 11, 2005
HFA1113 Typical Performance Curves
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 5 6 7 8 9 TOTAL SUPPLY VOLTAGE (V+ - V-, V) 10
VSUPPLY = 5V, TA = 25oC, RL = 100, Unless Otherwise Specified (Continued)
25 24 23 SUPPLY CURRENT (mA) 22 21 20 19 18 17 16 15 -50 -25 0 25 50 75 TEMPERATURE (oC) 100 125
SUPPLY CURRENT (mA)
FIGURE 37. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 38. SUPPLY CURRENT vs TEMPERATURE
3.6 3.5 3.4 OUTPUT VOLTAGE (V) 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 -50 -25 0 25 50 TEMPERATURE (oC) 75 100 125 |-VOUT| (RL= 50) |-VOUT| (RL= 100) AV = -1 +VOUT (RL= 50) +VOUT (RL= 100)
50
130
30
90
20 ENI 10 INI 0 0.1 1 10 FREQUENCY (kHz)
70
50
30 100
FIGURE 39. OUTPUT VOLTAGE vs TEMPERATURE
FIGURE 40. INPUT NOISE CHARACTERISTICS
AV = +2 IN 0V TO 0.5V IN 0V TO 1V
AV = +2
OUT 0V TO 1V TIME (20ns/DIV.)
OUT 0V TO 1V TIME (20ns/DIV.)
FIGURE 41. UNCLAMPED PERFORMANCE
FIGURE 42. CLAMPED PERFORMANCE
13
FN1342.6 July 11, 2005
NOISE CURRENT (pA/Hz)
NOISE VOLTAGE (nV/Hz)
40
110
HFA1113 Typical Performance Curves
350 300 CLAMP ACCURACY (mV) 250 VH = 1V 200 150 VH = 2V 100 VH = 100mV 50 0 0 100 200 300 400 500 OVERDRIVE (% OF VH) 0 0 100 200 300 400 500 OVERDRIVE (% OF VL) CLAMP ACCURACY (mV) VH = 500mV 200 VL = -1V 150 AV = 1
VSUPPLY = 5V, TA = 25oC, RL = 100, Unless Otherwise Specified (Continued)
250 AV = 1 VL = -500mV
100 VL = -2V 50 VL = -100mV
FIGURE 43. VH CLAMP ACCURACY vs OVERDRIVE
FIGURE 44. VL CLAMP ACCURACY vs OVERDRIVE
400 AV = 2 CLAMP ACCURACY (mV) 300 VH = 2V 200 VH = 500mV 100 VH = 100mV VH = 1V CLAMP ACCURACY (mV)
250 AV = +2 200 VL = -500mV 150 VL = -2V 100 VL = -1V
50 VL = -100mV
0 0 100 200 300 400 500 OVERDRIVE (% OF VH)
0
0
100
200 300 OVERDRIVE (% OF VL)
400
500
FIGURE 45. VH CLAMP ACCURACY vs OVERDRIVE
FIGURE 46. VL CLAMP ACCURACY vs OVERDRIVE
3500 OVERDRIVE RECOVERY TIME (ps) 3000 2500 2000 1500 VH = 1V 1000 500 0 100 VH = 0.5V VH = 0.1V 200 300 400 OVERDRIVE LEVEL (% OF CLAMP LEVEL) 500 VOUT - (AV x VIN) (mV)
20 15 VL = -3V 10 5 0 -5 -10 -15 -20 -3 -2 -1 0 AV x VIN (V) 1 2 VH = 1V VH = 2V VH = 2V VL = -2V VL = -1V
AV = -1
VH = 3V
3
FIGURE 47. OVERDRIVE RECOVERY vs OVERDRIVE
FIGURE 48. NON-LINEARITY NEAR CLAMP VOLTAGE
14
FN1342.6 July 11, 2005
HFA1113 Typical Performance Curves
140 130 CLAMP ACCURACY (mV) 120 VH 110 100 90 VL 80 70 60 -75 AV = -1, VIN = 1.6V VH = 1V, VL = -1V CLAMP BIAS CURRENT (A)
VSUPPLY = 5V, TA = 25oC, RL = 100, Unless Otherwise Specified (Continued)
130 120 110 100 90 80 70 60 50 40 30 VH VL VH = 1V, VL = -1V
-50
-25
0
25
50
75
100
125
150
20 -75
-50
-25
TEMPERATURE (oC)
75 25 0 50 TEMPERATURE (oC)
100
125
150
FIGURE 49. CLAMP ACCURACY vs TEMPERATURE
FIGURE 50. CLAMP BIAS CURRENT vs TEMPERATURE
6 3 GAIN (dB) 0 -3 -6 -9 -12 VH = 600mVP-P VH = 1.2VP-P VH = 300mVP-P GAIN (dB)
6 3 0 -3 -6 VL = 600mVP-P -9 -12 VL = 1.2VP-P VL = 300mVP-P
1
10
100 FREQUENCY (MHz)
1000
1
10
100 FREQUENCY (MHz)
1000
FIGURE 51. VH CLAMP INPUT BANDWIDTH
FIGURE 52. VL CLAMP INPUT BANDWIDTH
15
FN1342.6 July 11, 2005
HFA1113 Die Characteristics
DIE DIMENSIONS: 63 mils x 44 mils x 19 mils 1600m x 1130m x 483m METALLIZATION: Type: Metal 1: AICu(2%)/TiW Thickness: Metal 1: 8kA 0.4kA Type: Metal 2: AICu(2%) Thickness: Metal 2: 16kA 0.8kA PASSIVATION: Type: Nitride Thickness: 4kA 0.5kA TRANSISTOR COUNT: 52 SUBSTRATE POTENTIAL (POWERED UP): Floating (Recommend Connection to V-)
Metallization Mask Layout
HFA1113
NC
+IN
V-
VL
-IN
NC
VH
V+
OUT
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 16
FN1342.6 July 11, 2005

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