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82077AA CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER
Y
Single-Chip Floppy Disk Solution 100% PC AT Compatible 100% PS 2 Compatible 100% PS 2 Model 30 Compatible Integrated Drive and Data Bus Buffers Integrated Analog Data Separator 250 Kbits sec 300 Kbits sec 500 Kbits sec 1 Mbits sec High Speed Processor Interface Perpendicular Recording Support
Y Y
Integrated Tape Drive Support 12 mA Host Interface Drivers 40 mA Disk Drivers Four Fully Decoded Drive Select and Motor Signals Programmable Write Precompensation Delays Addresses 256 Tracks Directly Supports Unlimited Tracks 16 Byte FIFO 68-Pin PLCC
(See Packaging Spec Order 240800 Package Type N)
Y
Y
Y
Y
Y Y
Y Y
The 82077AA floppy disk controller has completely integrated all of the logic required for floppy disk control The 82077AA a 24 MHz crystal a resistor package and a device chip select implements a PC AT or PS 2 solution All programmable options default to compatible values The dual PLL data separator has better performance than most board level discrete PLL implementations The FIFO allows better system performance in multi-master systems (e g PS 2 EISA) The 82077AA is available in three versions 82077AA-5 82077AA and 82077AA-1 82077AA-1 has all features listed in this data sheet It supports both tape drives and 4 Mb floppy drives The 82077AA supports 4 Mb floppy drives and is capable of operation at all data rates through 1 Mbps The 82077AA-5 supports 500 300 250 Kbps data rates for high and low density floppy drives The 82077AA is fabricated with Intel's CHMOS III technology and is available in a 68-lead PLCC (plastic) package
290166 - 1
Figure 1 82077AA Pinout
PS 2 and PC AT are trademarks of IBM
May 1994
Order Number 290166-007
82077AA CHMOS Single-Chip Floppy Disk Controller
CONTENTS
1 0 INTRODUCTION 1 1 Oscillator 1 2 Perpendicular Recording Mode 2 0 MICROPROCESSOR INTERFACE 2 1 Status Data and Control Registers 2 1 1a Status Register A (SRA PS 2 Mode) 2 1 1b Status Register A (SRA Model 30 Mode) 2 1 2a Status Register B (SRB PS 2 Mode) 2 1 2b Status Register B (SRB Model 30 Mode) 2 1 3 Digital Output Register (DOR) 2 1 4 Tape Drive Register (TDR) 2 1 5 Datarate Select Register (DRS) 2 1 6 Main Status Register (MSR) 2 1 7 FIFO (Data) 2 1 8a Digital Input Register (DIR PC-AT Mode) 2 1 8b Digital Input Register (DIR PS 2 Mode) 2 1 8c Digital Input Register (DIR Model 30 Mode) 2 1 9a Configuration Control Register (CCR PC AT and PS 2 Modes) 2 1 9b Configuration Control Register (CCR Model 30 Mode) 2 2 RESET 2 2 1 Reset Pin (``Hardware'') Reset 2 2 2 DOR Reset vs DSR Reset (``Software'' Reset) PAGE
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CONTENTS
2 3 DMA Transfers 3 0 DRIVE INTERFACE 3 1 Cable Interface 3 2 Data Separator 3 2 1 Jitter Tolerance 3 2 2 Locktime (tLOCK) 3 2 3 Capture Range 3 2 4 Reference Filter 3 3 Write Precompensation 4 0 CONTROLLER PHASES 4 1 Command Phase 4 2 Execution Phase 4 2 1 Non-DMA Mode Transfers from the FIFO to the Host 4 2 2 Non-DMA Mode Transfers from the Host to the FIFO 4 2 3 DMA Mode Transfers from the FIFO to the Host 4 2 4 DMA Mode Transfers from the Host to the FIFO 4 2 5 Data Transfer Termination 4 3 Result Phase 5 0 COMMAND SET DESCRIPTIONS 5 1 Data Transfer Commands 5 1 1 Read Data 5 1 2 Read Deleted Data 5 1 3 Read Track 5 1 4 Write Data 5 1 5 Write Deleted Data 5 1 6 Verify 5 1 7 Format Track 5 1 7 1 Format Fields 5 1 8 Scan Commands
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CONTENTS
5 0 COMMAND SET DESCRIPTIONS (Continued) 5 2 Control Commands 5 2 1 Read ID 5 2 2 Recalibrate 5 2 3 Seek 5 2 4 Sense Interrupt Status 5 2 5 Sense Drive Status 5 2 6 Specify 5 2 7 Configure 5 2 8 Version 5 2 9 Relative Seek 5 2 10 DUMPREG 5 2 11 Perpendicular Mode Command 5 3 Command Set Enhancements 5 3 1 Perpendicular Mode 5 3 2 Lock 5 3 3 Enhanced DUMPREG Command 6 0 STATUS REGISTER ENCODING 6 1 Status Register 0 6 2 Status Register 1 6 3 Status Register 2 6 4 Status Register 3 7 0 COMPATIBILITY 7 1 Register Set Compatibility 7 2 PS 2 vs AT vs Model 30 Mode 7 2 1 PS 2 Mode 7 2 2 PC AT Mode 7 2 3 Model 30 Mode 7 3 Compatibility with the FIFO 7 4 Drive Polling
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CONTENTS
8 0 PROGRAMMING GUIDELINES 8 1 Command and Result Phase Handshaking 8 2 Initialization 8 3 Recalibrates and Seeks 8 4 Read Write Operations 8 5 Formatting 8 6 Verifies
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39 39 40 42 43 43 46 46 46 46 48 50 50 51 51 52 52 52 53
30 30 30 30 31 31 31 32 32 32 33 33 34 34 35 35 36 36 36 37 37 37 37 38 38 38 38 38 39
9 0 DESIGN APPLICATIONS 9 1 PC AT Floppy Disk Controller 9 1 1 PC AT Floppy Disk Controller Architecture 9 1 2 82077AA PC AT Solution 9 2 3 5 Drive Interfacing 9 2 1 3 5 Drives Under the AT Mode 9 2 2 3 5 Drives Under the PS 2 Modes 9 2 3 Combining 5 25 and 3 5 Drives 10 0 D C SPECIFICATIONS 10 1 Absolute Maximum Ratings 10 2 D C Characteristics 11 0 A C SPECIFICATIONS 12 0 DATA SEPARATOR CHARACTERISTICS FOR FLOPPY DISK MODE 13 0 DATA SEPARATOR CHARACTERISTICS FOR TAPE DRIVE MODE 14 0 82077AA 68-LEAD PLCC PACKAGE THERMAL CHARACTERISTICS 15 0 REVISION SUMMARY
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82077AA
Table 1 82077AA Pin Description Symbol Pin IO Description
HOST INTERFACE RESET CS A0 A1 A2 32 6 7 8 10 I I I RESET A high level places the 82077AA in a known idle state All registers are cleared except those set by the Specify command CHIP SELECT Decodes base address range and qualifies RD and WR inputs ADDRESS Selects one of the host interface registers A2 A1 A0 0 0 0 0 1 1 1 1 1 1 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 RD WR DRQ 11 13 14 15 17 19 20 22 4 5 24 0 0 1 1 0 0 0 1 1 1 Register
0 R Status Register A 1 R Status Register B 0 R W Digital Output Register 1 R W Tape Drive Register 0 R Main Status Register 0 W Data Rate Select Register 1 R W Data (FIFO) 0 Reserved 1 R Digital Input Register 1 W Configuration Control Register
I O DATA BUS Data bus with 12 mA drive
I I
READ Control signal WRITE Control signal
O DMA REQUEST Requests service from a DMA controller Normally active high but goes to high impedance in AT and Model 30 modes when the appropriate bit is set in the DOR I DMA ACKNOWLEDGE Control input that qualifies the RD WR inputs in DMA cycles Normally active low but is disabled in AT and Model 30 modes when the appropriate bit is set in the DOR TERMINAL COUNT Control line from a DMA controller that terminates the current disk transfer TC is accepted only while DACK is active This input is active high in the AT and Model 30 modes and active low in the PS 2 mode
DACK
3
TC
25
I
INT
23
O INTERRUPT Signals a data transfer in non-DMA mode and when status is valid Normally active high but goes to high impedance in AT and Model 30 modes when the appropriate bit is set in the DOR CRYSTAL 1 2 Connection for a 24 MHz fundamental mode parallel resonant crystal X1 may be driven with a MOS level clock and X2 would be left unconnected
X1 X2
33 34
4
82077AA
Table 1 82077AA Pin Description (Continued) Symbol Pin IO Description
HOST INTERFACE (Continued) IDENT 27 I IDENTITY Upon Hardware RESET this input (along with MFM pin) selects between the three interface modes After RESET this input selects the type of drive being accessed and alters the level on DENSEL The MFM pin is also sampled at Hardware RESET and then becomes an output again Internal pullups on MFM permit a no connect IDENT 1 1 0 0 MFM 1 or NC 0 1 or NC 0 INTERFACE AT Mode ILLEGAL PS 2 Mode Model 30 Mode
AT MODE Major options are enables DMA Gate logic TC is active high Status Registers A B not available PS 2 MODE Major options are No DMA Gate logic TC is active low Status Registers A B are available MODEL 30 MODE Major options are enable DMA Gate logic TC is active high Status Registers A B available After Hardware reset this pin determines the polarity of the DENSEL pin IDENT at a logic level of ``1'' DENSEL will be active high for high (500 Kbps 1 Mbps) data rates (typically used for 5 25 drives) IDENT at a logic level of ``0'' DENSEL will be active low for high data rates (typically used for 3 5 drives) INVERT is tied to ground DISK CONTROL (All outputs have 40 mA drive capability) INVERT 35 I INVERT Strapping option Determines the polartity of all signals in this section Should be strapped to ground when using the internal buffers and these signals become active LOW When strapped to VCC these signals become active high and external inverting drivers and receivers are required ME0-3 Decoded Motor enables for drives 0 - 3 The motor enable pins are directly controlled via the Digital Output Register
ME0 ME1 ME2 ME3 DS0 DS1 DS2 DS3 HDSEL STEP DIR WRDATA WE
57 61 63 66 58 62 64 67 51 55 56 53 52
O
O
DRIVE SELECT 0 - 3 Decoded drive selects for drives 0 - 3 These outputs are decoded from the select bits in the Digital Output Register and gated by ME0-3 HEAD SELECT Selects which side of a disk is to be used An active level selects side 1 STEP Supplies step pulses to the drive DIRECTION Controls the direction the head moves when a step signal is present The head moves toward the center if active WRITE DATA FM or MFM serial data to the drive Precompensation value is selectable through software WRITE ENABLE Drive control signal that enables the head to write onto the disk
O O O O O
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82077AA
Table 1 82077AA Pin Description (Continued) Symbol Pin IO Description
DISK CONTROL (All outputs have 40 mA drive capability) (Continued) DENSEL DSKCHG DRV2 TRK0 WP INDX 49 31 30 2 1 26 O I I I I I DENSITY SELECT Indicates whether a low (250 300 Kbps) or high (500 Kbps 1 Mbps) data rate has been selected DISK CHANGE This input is reflected in the Digital Input Register DRIVE2 This indicates whether a second drive is installed and is reflected in Status Register A TRACK0 Control line that indicates that the head is on track 0 WRITE PROTECT Indicates whether the disk drive is write protected INDEX Indicates the beginning of the track
PLL SECTION RDDATA HIFIL LOFIL MFM 41 38 37 48 I IO IO IO READ DATA Serial data from the disk INVERT also affects the polarity of this signal HIGH FILTER Analog reference signal for internal data separator compensation This should be filtered by an external capacitor to LOFIL LOW FILTER Low noise ground return for the reference filter capacitor MFM At Hardware RESET aids in configuring the 82077AA Internal pull-up allows a no connect if a ``1'' is required After reset this pin becomes an output and indicates the current data encoding decoding mode (Note If the pin is held at logic level ``0'' during hardware RESET it must be pulled to ``1'' after reset to enable the output The pin can be released on the falling edge of hardware RESET to enable the output) MFM is active high (MFM) DATARATE0-1 Reflects the contents of bits 0 1 of the Data Rate Register (Drive capability of a 6 0 mA 0 4V and b 4 0 mA 2 4V) PLL0 This input optimizes the data separator for either floppy disks or tape drives A ``1'' (or VCC) selects the floppy mode a ``0'' (or GND) selects tape mode Voltage a 5V
DRATE0 DRATE1 PLL0
28 29 39
O I
MISCELLANEOUS VCC 18 40 60 68 9 12 16 21 36 50 54 59 65 46 45 42 43 44 47
GND
Ground
AVCC AVSS NC
Analog Supply Analog Ground No Connection These pins MUST be left unconnected
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82077AA
variation with exceptionally low soft error rates The microprocessor interface has a 12 mA drive buffer on the data bus plus 100% hardware register compatibility for PC-AT's and PS 2's The 16-byte FIFO with programmable thresholds is extremely useful in multi-master systems (PS 2 EISA) or systems with a large amount of bus latency Upon reset (Pin 32) the 82077AA defaults to 8272A functionality New features are either selected via hardware straps or new commands Figure 1-1 is a block diagram of the 82077AA
1 0 INTRODUCTION
The 82077AA is a true single-chip floppy disk and tape drive controller for the PC-AT and PS 2 The 82077AA a 24 MHz crystal a resistor package and a chip select implement a complete design All drive control signals are fully decoded and have 40 mA drive buffers with selectable polarity Signals returned from the drive are sent through on-chip input buffers with hysteresis for noise immunity The integrated analog data separator needs no external compensation yet allows for a wide motor speed
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Figure 1-1 82077AA Block Diagram
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82077AA
ters This interface can be switched between PC AT Model 30 or PS 2 normal modes The PS 2 register sets are a superset of the registers found in a PCAT
1 1 Oscillator
2 1 Status Data and Control Registers
The base address range is supplied via the CS pin For PC-AT or PS 2 designs this would be 3F0 Hex to 3F7 Hex
A2 A1 A0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 0 1 1 1 0 1 0 1 0 0 1 0 1 1 R R RW RW R W RW R W Register Status Register A Status Register B Digital Output Register Tape Drive Register Main Status Register Data Rate Select Register Data (FIFO) Reserved Digital Input Register Configuration Control Register SRA SRB DOR TDR MSR DSR FIFO DIR CCR
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Figure 1-2 Crystal Oscillator Circuit The 24 MHz clock can be supplied either by a crystal or a MOS level square wave All internal timings are referenced to this clock or a scaled count which is data rate dependent The crystal oscillator must be allowed to run for 10 ms after VCC has reached 4 5V or exiting the POWERDOWN mode to guarantee that it is stable Crystal Specifications Frequency Mode 24 MHz g0 1% Parallel Resonant Fundamental Mode
2 1 1a STATUS REGISTER A (SRA PS 2 MODE) This register is read-only and monitors the state of the interrupt pin and several disk interface pins This register is part of the register set and is not accessible in PC-AT mode
7 INT PENDING 6 DRV2 5 STEP 4 TRK0 3 HDSEL 2 INDX 1 WP 0 DIR
Series Resistance Less than 40X Shunt Capacitance Less than 5 pF
1 2 Perpendicular Recording Mode
An added capability of the 82077AA is the ability to interface directly to perpendicular recording floppy drives Perpendicular recording differs from the traditional longitudinal method by orienting the magnetic bits vertically This scheme packs in more data bits for the same area The 82077AA with perpendicular recording drives can read standard 3 5 floppies as well as read and write perpendicular media Some manufacturers offer drives that can read and write standard and perpendicular media in a perpendicular media drive A single command puts the 82077AA into perpendicular mode All other commands operate as they normally do The perpendicular mode requires the 1 Mbps data rate of the 82077AA At this data rate the FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk
The INT PENDING bit is used by software to monitor the state of the 82077AA INTERRUPT pin The bits marked with a `` '' reflect the state of drive signals on the cable and are independent of the state of the INVERT pin As a read-only register there is no default value associated with a reset other than some drive bits will change with a reset The INT PENDING STEP HDSEL and DIR bits will be low after reset 2 1 1b STATUS REGISTER A (SRA MODEL 30 MODE)
7 6 DRQ 5 STEP FF 4 TRKO 3 HDSEL 2 INDEX 1 WP 0 DIR
2 0 MICROPROCESSOR INTERFACE
The interface consists of the standard asynchronous signals RD WR CS A0-A2 INT DMA control and a data bus The address lines select between configuration registers the FIFO and control status regis8
INT PENDING
This register has the following changes in PS 2 Model 30 Mode Disk interface pins (Bits 0 1 2 3 4) are inverted from PS 2 Mode The DRQ bit
82077AA
monitors the status of the DMA Request pin The STEP bit is latched with the Step output going active and is cleared with a read to the DIR register Hardware or Software RESET 2 1 2a STATUS REGISTER B (SRB PS 2 MODE) This register is read-only and monitors the state of several disk interface pins This register is part of the PS 2 register set and is not accessible in PC-AT mode
7 1 6 1 5 DRIVE SEL 0 4 WRDATA TOGGLE 3 RDDATA TOGGLE 2 WE 1 MOT EN1 0 MOT EN0
The MOT ENx bits directly control their respective motor enable pins (ME0 - 3) A one means the pin is active the INVERT pin determines the active level The DRIVE SELx bits are decoded to provide four drive select lines and only one may be active at a time A one is active and the INVERT pin determines the level on the cable Standard programming practice is to set both MOT ENx and DRIVE SELx bits at the same time Table 2-1 lists a set of DOR values to activate the drive select and motor enable for each drive Table 2-1 Drive Activation Values Drive 0 1 2 3 DOR Value 1CH 2DH 4EH 8FH
As the only drive input RDDATA TOGGLE's activity is independent of the INVERT pin level and reflects the level as seen on the cable The two TOGGLE bits do not read back the state of their respective pins directly Instead the pins drive a Flip Flop which produces a wider and more reliably read pulse Bits 6 and 7 are undefined and always return a 1 After any reset the activity on the TOGGLE pins are cleared Drive select and Motor bits cleared by the RESET pin and not software resets 2 1 2b STATUS REGISTER B (SRB MODEL 30 MODE)
7 DRV2 6 DS1 5 DS0 4 WRDATA FF 3 RDDATA FF 2 WE FF 1 DS3 0 DS2
The DMAGATE bit is enabled only in PC-AT and Model 30 Modes If DMAGATE is set low the INT and DRQ outputs are tristated and the DACK and TC inputs are disabled DMAGATE set high will enable INT DRQ TC and DACK to the system In PS 2 Mode DMAGATE has no effect upon INT DRQ TC or DACK pins and they are always active This RESET bit clears the basic core of the 82077AA and the FIFO circuits when the LOCK bit is set to ``0'' (see section 5 3 2 for LOCK bit definition) Once set it remains set until the user clears this bit This bit is set by a chip reset and the 82077AA is held in a reset state until the user clears this bit The RESET bit has no effect upon this register 2 1 4 TAPE DRIVE REGISTER (TDR) This register allows the user to assign tape support to a particular drive during initialization Any future references to that drive number automatically invokes tape support This register is cleared by Hardware reset Software resets have no effect
7 6 5 4 3 2 1 Tape SEL1 0 Tape SEL0
This register has the following changes in Model 30 Mode Bits 0 1 5 and 6 return the decoded value of the Drive Select bits in the DOR register Bits 2 3 and 4 are set by their respective active going edges and are cleared by reading the DIR register The WRDATA bit is triggered by raw WRDATA signals and is not gated by WE Bits 2 3 and 4 are cleared to a low level by either Hardware or Software RESET 2 1 3 DIGITAL OUTPUT REGISTER (DOR) The Digital Output Register contains the drive select and motor enable bits a reset bit and a DMA GATE bit
7 MOT EN3 6 MOT EN2 5 MOT EN1 4 MOT EN0 3 DMA GATE 2 RESET 1 0
Bits 2 thru 7 are not writable and remain tristated if read The Tape Select bits are Hardware RESET to 0's making Drive 0 not available for tape support Drive 0 is ``reserved'' for the floppy boot drive Tape SEL1 0 0 1 1 Tape SEL0 0 1 0 1 DRIVE SELECTED None 1 2 3 9
DRIVE DRIVE SEL 1 SEL 0
82077AA
The tuning of the PLL for tape characteristics can also be done in hardware If a 0 (GND) is applied to pin 39 (PLL0) the PLL is optimized for tape drives a 1 (VCC) optimizes the PLL for floppies This hardware selection mechanism overrides the software selection scheme A typical hardware application would route the Drive Select pin used for tape drive support to pin 39 (PLL0) 2 1 5 DATARATE SELECT REGISTER (DSR) This register is included for compatibility with the 82072 floppy controller and is write-only Changing the data rate changes the timings of the drive control signals To ensure that drive timings are not violated when changing data rates choose a drive timing such that the fastest data rate will not violate the timing
7 SW 6 POWER 5 4 PRE0 2 3 PRE1 2 PRE0 1 0
upon a chip (``Hardware'') reset Other (``Software'') Resets do not affect the DRATE or PRECOMP bits Table 2-2 Precompensation Delays PRECOMP 432 111 001 010 011 100 101 110 000 Precompensation Delay 0 00 ns DISABLED 41 67 ns 83 34 ns 125 00 ns 166 67 ns 208 33 ns 250 00 ns DEFAULT
Table 2-3 Default Precompensation Delays Data Rate 1 Mbps 500 Kbps 300 Kbps 250 Kbps Precompensation Delays 41 67 ns 125 ns 125 ns 125 ns Table 2-4 Data Rates DRATESEL 1 1 0 0 1 0 1 0 1 0 DATA RATE MFM 1 Mbps 500 Kbps 300 Kbps 250 Kbps
RESET DOWN
COMP COMP COMP
DRATE DRATE SEL 1 SEL 0
This register is the same as used in the 82072 except that the internal external PLL select bit is removed It is recommended that bit 5 be written with a 0 for compatibility S W RESET behaves the same as DOR RESET except that this reset is self clearing POWER DOWN deactivates the internal clocks and shuts off the oscillator Disk control pins are put in an inactive state All input signals must be held in a valid state (D C level 1 or 0) POWER DOWN is exited by activating one of the reset functions PRECOMP 0-2 adjusts the WRDATA output to the disk to compensate for magnetic media phenomena known as bit shifting The data patterns that are susceptible to bit shifting are well understood and the 82077AA compensates the data pattern as it is written to the disk The amount of precompensation is dependent upon the drive and media but in most cases the default value is acceptable The 82077AA starts precompensating the data pattern starting on Track 0 The CONFIGURE command can change the track that precompensating starts on Table 2-2 lists the precompensation values that can be selected and Table 2-3 lists the default precompensation values The default value is selected if the three bits are zeros DRATE 0-1 select one of the four data rates as listed in Table 2-4 The default value is 250 Kbps
2 1 6 MAIN STATUS REGISTER (MSR) The Main Status Register is a read-only register and is used for controlling command input and result output for all commands
7 RQM 6 DIO 5 NON DMA 4 CMD BSY 3 DRV 3 BUSY 2 DRV 2 BUSY 1 DRV 1 BUSY 0 DRV 0 BUSY
RQM Indicates that the host can transfer data if set to a 1 No access is permitted if set to a 0 DIO Indicates the direction of a data transfer once RQM is set A 1 indicates a read and a 0 indicates a write is required NON-DMA This mode is selected in the SPECIFY command and will be set to a 1 during the execution phase of a command This is for polled data transfers and helps differentiate between the data transfer phase and the reading of result bytes
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82077AA
COMMAND BUSY This bit is set to a one when a command is in progress This bit will go active after the command byte has been accepted and goes inactive at the end of the results phase If there is no result phase (SEEK RECALIBRATE commands) this bit is returned to a 0 after the last command byte DRV x BUSY These bits are set to ones when a drive is in the seek portion of a command including seeks and recalibrates 2 1 7 FIFO (DATA) All command parameter information and disk data transfers go through the FIFO The FIFO is 16 bytes in size and has programmable threshold values Data transfers are governed by the RQM and DIO bits in the Main Status Register The FIFO defaults to an 8272A compatible mode after a ``Hardware'' reset (Reset via pin 32) ``Software'' Resets (Reset via DOR or DSR register) can also place the 82077AA into 8272A compatible mode if the LOCK bit is set to ``0'' (See section 5 3 2 for the definition of the LOCK bit) This maintains PC-AT hardware compatibility The default values can be changed through the CONFIGURE command (enable full FIFO operation with threshold control) The advantage of the FIFO is that it allows the system a larger DMA latency without causing a disk error Table 2 5 gives several examples of the delays with a FIFO The data is based upon the following formula
Threshold 1 c 8 b 1 5 ms e DELAY c DATA RATE
82077AA enters the command execution phase it clears the FIFO of any data to ensure that invalid data is not transferred An overrun or underrun will terminate the current command and the transfer of data Disk writes will complete the current sector by generating a 00 pattern and valid CRC 2 1 8a DIGITAL INPUT REGISTER (DIR PC-AT MODE) This register is read only in all modes In PC-AT mode only bit 7 is driven all other bits remain tristated
7 DSK CHG 6 5 4 3 2 1 0
DSKCHG monitors the pin of the same name and reflects the opposite value seen on the disk cable regardless of the value of INVERT 2 1 8b DIGITAL INPUT REGISTER (DIR PS 2 MODE)
7 DSK CHG 6 1 5 1 4 1 3 1 2 DRATE SEL1 1 DRATE SEL0 0 HIGH DENS
The following is changed in PS 2 Mode Bits 6 5 4 and 3 return a value of ``1'' and the DRATE SEL1-0 return the value of the current data rate selected (see Table 2-4 for values) HIGH DENS is low whenever the 500 Kbps or 1 Mbps data rates are selected This bit is independent of the effects of the IDENT and INVERT pins Table 2-6 shows the state of the DENSEL pin when INVERT is low Table 2-6 DENSEL Encoding Data Rate 1 Mbps IDENT 0 1 500 Kbps 0 1 300 Kbps 0 1 DENSEL 0 1 0 1 1 0 1 0 11
Table 2-5 FIFO Service Delay FIFO Threshold Examples 1 byte 2 bytes 8 bytes 15 bytes FIFO Threshold Examples 1 byte 2 bytes 8 bytes 15 bytes Maximum Delay to Servicing at 1 Mbps Data Rate 1 c 8 ms b 1 5 ms e 6 5 ms 2 c 8 ms b 1 5 ms e 14 5 ms 8 c 8 ms b 1 5 ms e 62 5 ms 15 c 8 ms b 1 5 ms e 118 5 ms Maximum Delay to Servicing at 500 Kbps Data Rate 1 c 16 ms b 1 5 ms e 14 5 ms 2 c 16 ms b 1 5 ms e 30 5 ms 8 c 16 ms b 1 5 ms e 126 5 ms 15 c 16 ms b 1 5 ms e 238 5 ms
At the start of a command the FIFO action is always disabled and command parameters must be sent based upon the RQM and DIO bit settings As the
250 Kbps
After (``Hardware'') Chip Reset
0 1
82077AA
This pin is set high after a pin RESET and is unaffected by DOR and DSR resets 2 1 8c DIGITAL INPUT REGISTER (DIR MODEL 30 MODE)
7 DSK CHG 6 0 5 0 4 0 3 DMA GATE 2 NOPREC 1 0
On entering the reset state all operations are terminated and the 82077AA enters an idle state Activating reset while a disk write activity is in progress will corrupt the data and CRC On exiting the reset state various internal registers are cleared and the 82077AA waits for a new command Drive polling will start unless disabled by a new CONFIGURE command 2 2 1 RESET PIN (``HARDWARE'') RESET
DRATE DRATE SEL1 SEL0
The following is changed in Model 30 Mode Bits 6 5 and 4 return a value of ``0'' and Bit 7 (DSKCHG) is inverted in Model 30 Mode Bit 3 reflects the value of DMAGATE bit set in the DOR register Bit 2 reflects the value of NOPREC bit set in the CCR register 2 1 9a CONFIGURATION CONTROL REGISTER (CCR PC AT and PS 2 MODES) This register sets the datarate and is write only In the PC-AT it is named the DSR
7 6 5 4 3 2 1 0
The RESET pin is a global reset and clears all registers except those programmed by the SPECIFY command The DOR Reset bit is enabled and must be cleared by the host to exit the reset state 2 2 2 DOR RESET vs DSR RESET (``SOFTWARE'' RESET) These two resets are functionally the same The DSR Reset is included to maintain 82072 compatibility Both will reset the 8272 core which affects drive status information The FIFO circuits will also be reset if the LOCK bit is a ``0'' (See section 5 3 2 for the definition of the LOCK bit) The DSR Reset clears itself automatically while the DOR Reset requires the host to manually clear it DOR Reset has precedence over the DSR Reset The DOR Reset is set automatically upon a pin RESET The user must manually clear this reset bit in the DOR to exit the reset state
DRATE DRATE SEL1 SEL0
Refer to the table in the Data Rate Select Register for values Unused bits should be set to 0 2 1 9b CONFIGURATION CONTROL REGISTER (CCR MODEL 30 MODE)
7 6 5 4 3 2 NOPREC 1 0
2 3 DMA Transfers
DMA transfers are enabled with the SPECIFY command and are initiated by the 82077AA by activating the DRQ pin during a data transfer command The FIFO is enabled directly by asserting DACK and addresses need not be valid CS can be held inactive during DMA transfers
DRATE DRATE SEL1 SEL0
3 0 DRIVE INTERFACE
The 82077AA has integrated all of the logic needed to interface to a floppy disk or tape drives which use floppy interface All drive outputs have 40 mA drive capability and all inputs use a receive buffer with hysteresis The internal analog data separator requires no external components yet allows for an extremely wide capture range with high levels of readdata jitter and ISV The designer needs only to run the 82077AA disk drive signals to the disk or tape drive connector
NOPREC has no function and is reset to ``0'' with a Hardware RESET only
2 2 RESET
There are three sources of reset on the 82077AA the RESET pin a reset generated via a bit in the DOR and a reset generated via a bit in the DSR All resets take the 82077AA out of the power down state
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82077AA
3 1 Cable Interface
The INVERT pin selects between using the internal buffers on the 82077AA or user supplied inverting buffers INVERT pulled to VCC disables the internal buffers pulled to ground will enable them There is no need to use external buffers with the 82077AA in typical PC applications The polarity of the DENSEL pin is controlled through the IDENT pin after hardware reset For 5 25 drives a high on DENSEL tells the drive that either the 500 Kbps or 1 Mbps data rate is selected For some 3 5 drives the polarity of DENSEL changes to a low for high data rates See Table 2-6 DENSEL Encoding for IDENT pin settings Additionally the two types of drives have different electrical interfaces Generally the 5 25 drive uses open collector drivers and the 3 5 drives (as used on PS 2) use totem-pole drivers The output buffers on the 82077AA do not change between open collector or totem-pole they are always totem-pole For design information on interfacing 5 25 and 3 5 drives to a single 82077AA refer to Section 9
3 2 Data Separator
The function of the data separator is to lock onto the incoming serial read data When lock is achieved the serial front end logic of the chip is provided with a clock which is synchronized to the read data The synchronized clock called Data Window is used to internally sample the serial data One state of Data Window is used to sample the data portion of the bit cell and the alternate state samples the clock portion Serial to parallel conversion logic separates the read data into clock and data bytes To support reliable disk tape reads the data separator must track fluctuations in the read data frequency Frequency errors primarily arise from two sources motor rotation speed variation and instantaneous speed variation (ISV) A second condition and one that opposes the ability to track frequency shifts is the response to bit jitter The internal data separator consists of two analog phase lock loops (PLLs) as shown in Figure 3-1 The two PLLs are referred to as the reference PLL and the data PLL The reference PLL (the master PLL) is used to bias the data PLL (the slave PLL) The reference PLL adjusts the data PLL's operating point as a function of process junction temperature and supply voltage Using this architecture it was possible to eliminate the need for external trim components
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Figure 3-1 Data Separator Block Diagram
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82077AA
PHASE LOCK LOOP OVERVIEW
290166 - 5
Figure 3-2 Data PLL Figure 3-2 shows the data PLL The reference PLL has control over the loop gain by its influence on the charge pump and the VCO In addition the reference PLL controls the loop filter time constant As a result the closed loop transfer function of the data PLL is controlled and immune to the first order to environmental factors and process variation Systems with analog PLLs are often very sensitive to noise In the design of this data separator many steps were taken to avoid noise sensitivity problems The analog section of the chip has a separate VSS pin (AVSS) which should be connected externally to a noise free ground This provides a clean basis for VSS referenced signals In addition many analog circuit features were employed to make the overall system as insensitive to noise as possible 3 2 1 JITTER TOLERANCE The jitter immunity of the system is dominated by the data PLL's response to phase impulses This is measured as a percentage of the theoretical data window by dividing the maximum readable bit shift by a bitcell distance For instance if the maximum allowable bit shift is 300 ns for a 500 Kbps data stream the jitter tolerance is 60% The graph in Figures 12-1 thru 12-4 and 13-1 thru 13-4 of the Data Separator Characteristics sections illustrate the jitter tolerance of the 82077AA across each frequency range 3 2 2 LOCKTIME (tLOCK) The lock or settling time of the data PLL is designed to be 64 bit times This corresponds to 8 sync bytes in the MFM mode This value assumes that the sync field jitter is 5% the bit cell or less This level of jitter should be easily achieved for a constant bit pattern since intersymbol interference should be equal thus nearly eliminating random bit shifting 3 2 3 CAPTURE RANGE Capture Range is the maximum frequency range over which the data separator will acquire phase lock with the incoming RDDATA signal In a floppy disk environment this frequency variation is composed of two components drive motor speed error and ISV Frequency is a factor which may determine the maximum level of the ISV (Instantaneous Speed Variation) component In general as frequency increases the allowed magnitude of the ISV component will decrease When determining the capture range requirements the designer should take the maximum amount of frequency error for the disk drive and double it to account for media switching between drives
14
82077AA
290166 - 6
NOTE PS0 1 are 8272A control signals but are not available as outputs on the 82077AA
Figure 3-3 Precompensation Block Diagram 3 2 4 REFERENCE FILTER To provide a clean bias voltage for the internal data separator two pins have been provided to filter this signal It is recommended to place a 0 0047 uF capacitor between HIFIL and LOFIL to filter the reference signal A smaller capacitance will reduce the effectiveness of the filter and could result in a lower jitter tolerance Conversely a larger capacitance has the potential to further improve jitter tolerance but will result in an increased settling time after a change in data rate For instance a filter capacitor of 0 005 uF will yield a settling time of approximately 500 microseconds Since HIFIL generates a relatively low current signal (approximately 10 uA) care also needs to be taken to avoid external leakage on this pin The quality of the capacitor solder flux grease and dirt can all impact the amount of leakage on the board shift register is clocked at the main clock rate (24 MHz) The output is fed into 2 multiplexors one for early and one for late A final stage of multiplexors combines the early late and normal data stream back into one which is the WRDATA output
4 0 CONTROLLER PHASES
For simplicity command handling in the 82077AA can be divided into three phases Command Execution and Result Each phase is described in the following secions
4 1 Command Phase
After a reset the 82077AA enters the command phase and is ready to accept a command from the host For each of the commands a defined set of command code bytes and parameter bytes has to be written to the 82077AA before the command phase is complete (Please refer to Section 5 0 for the command descriptions) These bytes of data must be transferred in the order prescribed Before writing to the 82077AA the host must examine the RQM and DIO bits of the Main Status Register RQM DIO must be equal to ``1'' and ``0'' respectively before command bytes may be written RQM is set false by the 82077AA after each write cycle until the received byte is processed The 82077AA asserts RQM again to request each parameter byte of
3 3 Write Precompensation
The write precompensation logic is used to minimize bit shifts in the RDDATA stream from the disk drive The shifting of bits is a known phenomena of magnetic media and is dependent upon the disk media AND the floppy drive The 82077AA monitors the bit stream that is being sent to the drive The data patterns that require precompensation are well known Depending upon the pattern the bit is shifted either early or late (or not at all) relative to the surrounding bits Figure 3-3 is a block diagram of the internal circuit The top block is a 13-bit shift register with the no delay tap being in the center This allows 6 levels of early and late shifting with respect to nominal The
15
82077AA
the command unless an illegal command condition is detected After the last parameter byte is received RQM remains ``0'' and the 82077AA automatically enters the next phase as defined by the command definition The FIFO is disabled during the command phase to retain compatibility with the 8272A and to provide for the proper handling of the ``Invalid Command'' condition
4 2 1 NON-DMA MODE TRANSFERS FROM THE FIFO TO THE HOST The INT pin and RQM bits in the Main Status Register are activated when the FIFO contains (16 - k threshold l ) bytes or the last bytes of a full sector transfer have been placed in the FIFO The INT pin can be used for interrupt driven systems and RQM can be used for polled sytems The host must respond to the request by reading data from the FIFO This process is repeated until the last byte is transferred out of the FIFO The 82077AA will deactivate the INT pin and RQM bit when the FIFO becomes empty 4 2 2 NON-DMA MODE TRANSFERS FROM THE HOST TO THE FIFO The INT pin and RQM bit in the Main Status Register are activated upon entering the execution phase of data transfer commands The host must respond to the request by writing data into the FIFO The INT pin and RQM bit remain true until the FIFO becomes full They are set true again when the FIFO has k threshold l bytes remaining in the FIFO The INT pin will also be deactivated if TC and DACK both go inactive The 82077AA enters the result phase after the last byte is taken by the 82077AA from the FIFO (i e FIFO empty condition) 4 2 3 DMA MODE TRANSFERS FROM THE FIFO TO THE HOST The 82077AA activates the DRQ pin when the FIFO contains (16 - k threshold l ) bytes or the last byte of a full sector transfer has been placed in the FIFO The DMA controller must respond to the request by reading data from the FIFO The 82077AA will deactivate the DRQ pin when the FIFO becomes empty DRQ goes inactive after DACK goes active for the last byte of a data transfer (or on the active edge of RD on the last byte if no edge is present on DACK ) A data underrun may occur if DRQ is not removed in time to prevent an unwanted cycle
4 2 Execution Phase
All data transfers to or from the 82077AA occur during the execution phase which can proceed in DMA or non-DMA mode as indicated in the SPECIFY command Each data byte is transferred by an INT or DRQ depending on the DMA mode The CONFIGURE command can enable the FIFO and set the FIFO threshold value The following paragraphs detail the operation of the FIFO flow control In these descriptions k threshold l is defined as the number of bytes available to the 82077AA when service is requested from the host and ranges from 1 to 16 The parameter FIFOTHR which the user programs is one less and ranges from 0 to 15 A low threshold value (i e 2) results in longer periods of time between service requests but requires faster servicing of the request for both read and write cases The host reads (writes) from (to) the FIFO until empty (full) then the transfer request goes inactive The host must be very responsive to the service request This is the desired case for use with a ``fast'' system A high value of threshold (i e 12) is used with a ``sluggish'' system by affording a long latency period after a service request but results in more frequent service requests
16
82077AA
side of the FIFO There may be a delay in the removal of the transfer request signal of up to the time taken for the 82077AA to read the last 16 bytes from the FIFO The host must tolerate this delay
4 2 4 DMA MODE TRANSFERS FROM THE HOST TO THE FIFO The 82077AA activates the DRQ pin when entering the execution phase of the data transfer commands The DMA controller must respond by activating the DACK and WR pins and placing data in the FIFO DRQ remains active until the FIFO becomes full DRQ is again set true when the FIFO has k threshold l bytes remaining in the FIFO The 82077AA will also deactivate the DRQ pin when TC becomes true (qualified by DACK ) indicating that no more data is required DRQ goes inactive after DACK goes active for the last byte of a data transfer (or on the active edge of WR of the last byte if no edge is present on DACK ) A data overrun may occur if DRQ is not removed in time to prevent an unwanted cycle 4 2 5 DATA TRANSFER TERMINATION The 82077AA supports terminal count explicitly through the TC pin and implicitly through the underrun overrun and end-of-track (EOT) functions For full sector transfers the EOT parameter can define the last sector to be transferred in a single or multisector transfer If the last sector to be transferred is a partial sector the host can stop transferring the data in mid-sector and the 82077AA will continue to complete the sector as if a hardware TC was received The only difference between these implicit functions and TC is that they return ``abnormal termination'' result status Such status indications can be ignored if they were expected Note that when the host is sending data to the FIFO of the 82077AA the internal sector count will be complete when 82077AA reads the last byte from its
4 3 Result Phase
The generation of INT determines the beginning of the result phase For each of the commands a defined set of result bytes has to be read from the 82077AA before the result phase is complete (Refer to Section 5 0 on command descriptions ) These bytes of data must be read out for another command to start RQM and DIO must both equal ``1'' before the result bytes may be read from the FIFO After all the result bytes have been read the RQM and DIO bits switch to ``1'' and ``0'' respectively and the CB bit is cleared This indicates that the 82077AA is ready to accept the next command
5 0 COMMAND SET DESCRIPTIONS
Commands can be written whenever the 82077AA is in the command phase Each command has a unique set of needed parameters and status results The 82077AA checks to see that the first byte is a valid command and if valid proceeds with the command If it was invalid the next time the RQM bit in the MSR register is a ``1'' the DIO and CB bits will also be ``1'' indicating the FIFO must be read A result byte of 80H will be read out of the FIFO indicating an invalid command was issued After reading the result byte from the FIFO the 82077AA will return to the command phase Table 5-1 is a summary of the Command set
17
82077AA
Table 5-1 82077AA Command Set
Phase RW D7 Command W W W W W W W W W MT 0 D6 MFM 0 D5 SK 0 DATA BUS D4 0 0 C H R N EOT GPL DTL D3 READ DATA 0 0 1 HDS 1 DS1 0 DS0 Command Codes Sector ID information prior to Command execution D2 D1 D0 Remarks
Execution
Data transfer between the FDD and system R R R R R R R ST 0 ST 1 ST 2 C H R N READ DELETED DATA Status information after Command execution
Result
Sector ID information after Command execution
Command
W W W W W W W W W
MT 0
MFM 0
SK 0
0 0 C H R N EOT GPL DTL
1 0
1 HDS
0 DS1
0 DS0
Command Codes Sector ID information prior to Command execution
Execution
Data transfer between the FDD and system R R R R R R R ST 0 ST 1 ST 2 C H R N WRITE DATA Status information after Command execution
Result
Sector ID information after Command execution
Command
W W W W W W W W W
MT 0
MFM 0
0 0
0 0 C H R N EOT GPL DTL
0 0
1 HDS
0 DS1
1 DS0
Command Codes Sector ID information prior to Command execution
Execution
Data transfer between the system and FDD R R R R R R R ST 0 ST 1 ST 2 C H R N Status information after Command execution
Result
Sector ID information after Command execution
18
82077AA
Table 5-1 82077AA Command Set (Continued)
Phase RW D7 Command W W W W W W W W W MT 0 D6 MFM 0 D5 0 0 DATA BUS D4 0 0 C H R N EOT GPL DTL D3 1 0 D2 0 HDS D1 0 DS1 D0 1 DS0 Command Codes Sector ID information prior to Command execution WRITE DELETED DATA Remarks
Execution
Data transfer between the FDD and system R R R R R R R W W W W W W W W W 0 0 MFM 0 0 0 0 0 C H R N EOT GPL DTL ST 0 ST 1 ST 2 C H R N READ TRACK 0 0 0 HDS 1 DS1 0 DS0 Status information after Command execution
Result
Sector ID information after Command execution
Command
Command Codes Sector ID information prior to Command execution
Execution
Data transfer between the FDD and system FDC reads all of cylinders contents from index hole to EOT R R R R R R R W W W W W W W W W MT EC MFM 0 SK 0 1 0 C H R N EOT GPL DTL SC ST 0 ST 1 ST 2 C H R N VERIFY 0 0 1 HDS 1 DS1 0 DS0 Status information after Command execution
Result
Sector ID information after Command execution
Command
Command Codes Sector ID information prior to Command execution
Execution
No data transfer takes place R R R R R R R W R 0 1 0 0 0 0 1 1 ST 0 ST 1 ST 2 C H R N VERSION 0 0 0 0 0 0 0 0 Status information after Command execution
Result
Sector ID information after Command execution
Command Result
Command Code Enhanced Controller
19
82077AA
Table 5-1 82077AA Command Set (Continued)
Phase RW D7 Command W W W W W W 0 0 D6 MFM 0 D5 0 0 DATA BUS D4 0 0 N SC GPL D D3 1 0 D2 1 HDS D1 0 DS1 D0 1 DS0 Command Codes Bytes Sector Sectors Cylinder Gap 3 Filler Byte Remarks
FORMAT TRACK
Execution For Each Sector Repeat
W W W W
C H R N
Input Sector Parameters
82077AA formats an entire cylinder Result R R R R R R R W W W W W W W W W MT 0 MFM 0 SK 0 ST 0 ST 1 ST 2 Undefined Undefined Undefined Undefined SCAN EQUAL Command 1 0 C H R N EOT GPL STP 0 0 0 HDS 0 DS1 1 DS0 Command Codes Sector ID Information Prior to Command Execution Status information after Command execution
Execution
Data Compared Between the FDD and Main-System R R R R R R R W W W W W W W W W MT 0 MFM 0 SK 0 1 0 C H R N EOT GPL STP ST 0 ST 1 ST 2 C H R N SCAN LOW OR EQUAL 1 0 0 HDS 0 DS1 1 DS0 Status Information After Command Execution Sector ID Information After Command Execution Command Codes Sector ID Information Prior to Command Execution
Result
Command
Execution
Data Command Between the FDD and Main-System
20
82077AA
Table 5-1 82077AA Command Set (Continued)
Phase RW D7 Result R R R R R R R W W W W W W W W W MT 0 MFM 0 SK 0 1 0 C H R N EOT GPL STP D6 D5 DATA BUS D4 ST 0 ST 1 ST 2 C H R N SCAN HIGH OR EQUAL Command 1 0 1 HDS 0 DS1 1 DS0 Command Codes Sector ID Information Prior to Command Execution D3 D2 D1 D0 Status Information After Command Execution Sector ID Information After Command Execution Remarks
SCAN LOW OR EQUAL (Continued)
Execution
Data Compared Between the FDD and Main-System R R R R R R R W W 0 0 0 0 0 0 0 0 ST 0 ST 1 ST 2 C H R N RECALIBRATE 0 0 1 0 1 DS1 1 DS0 Status ID Information After Command Execution Sector ID Information After Command Execution Command Codes
Result
Command
Execution SENSE INTERRUPT STATUS Command Result W R R W W W 0 0 SRT HLT SENSE DRIVE STATUS Command Result W W R 0 0 0 0 0 0 0 0 ST 3 SEEK Command W W W 0 0 0 0 0 0 0 0 NCN 1 0 1 HDS 1 DS1 1 DS0 0 0 1 HDS 0 DS1 0 DS0 0 0 0 0 0 0 ST 0 PCN SPECIFY Command 0 0 HUT ND 1 1 1 0 0 0
Head retracted to Track 0 Interrupt Command Codes Status information at the end of each seek operation
Command Codes
Command Codes Status information about FDD Command Codes
Execution CONFIGURE Command W W W W 0 0 0 0 0 EIS 0 0 EFIFO 1 0 0 0 POLL PRETRK 0 0 1 0 FIFOTHR 1 0
Head is positioned over proper Cylinder on Diskette Configure Information
21
82077AA
Table 5-1 82077AA Command Set (Continued)
Phase RW D7 Command W W W 1 0 D6 DIR 0 D5 0 0 DATA BUS D4 0 0 RCN DUMPREG Command Execution Result W R R R R R R R R R R 0 0 0 0 1 1 1 0 Note Registers placed in FIFO D3 1 0 D2 1 HDS D1 1 DS1 D0 1 DS0 Remarks
RELATIVE SEEK
PCN-Drive 0 PCN-Drive 1 PCN-Drive 2 PCN-Drive 3 SRT HLT SC EOT D2 D1 POLL PRETRK READ ID HUT ND D0 GAP FIFOTHR WGATE
LOCK 0
0 EIS
D3 EFIFO
Command Execution
W W
0 0
MFM 0
0 0
0 0
1 0
0 HDS
1 DS1
0 DS0
Commands The first correct ID information on the Cylinder is stored in Data Register
Result
R R R R R R R
ST 0 ST 1 ST 2 C H R N PERPENDICULAR MODE
Status information after Command execution
Disk status after the Command has completed
Command
W W
0 OW
0 0
0 D3 0 0
1 D2 1 LOCK
0 D1 LOCK 0 0 INVALID
0 D0
1 GAP
0 WGATE
Command Codes
Command Result
W R
LOCK 0
0 0
1 0
0 0
0 0
Command Code
Command
W
Invalid Codes
Invalid Command Codes (NoOp 82077AA goes into Standby State) ST 0 e 80H
Result
R
ST 0
SC is returned if the last command that was issued was the FORMAT command EOT is returned if the last command was a READ or WRITE NOTE These bits are used internally only They are not reflected in the Drive Select pins It is the users responsibility to maintain correspondence between these bits and the Drive Select pins (DOR)
PARAMETER ABBREVIATIONS
Symbol C D0 D1 D2 D3 Description Cylinder address The currently selected cylinder address 0 to 255 Drive Select 0-3 Designates which drives are Perpendicular drives a ``1'' indicating Perpendicular drive
Symbol D DIR
Description Data pattern The pattern to be written in each sector data field during formatting Direction control If this bit is 0 then the head will step out from the spindle during a relative seek If set to a 1 the head will step in toward the spindle
22
82077AA
Symbol Description DS1 0 0 1 1 DTL DS0 0 1 0 1 Symbol Lock drive 0 drive 1 drive 2 drive 3 Description Lock defines whether EFIFO FIFOTHR and PRETRK parameters of the CONFIGURE command can be reset to their default values by a ``Software Reset'' (Reset made by setting the proper bit in the DSR or DOR registers) MFM mode selector A one selects the double density (MFM) mode Multi-track selector When set this flag selects the multi-track operating mode In this mode the 82077AA treats a complete cylinder under head 0 and 1 as a single track The 82077AA operates as if this expanded track started at the first sector under head 0 and ended at the last sector under head 1 With this flag set a multitrack read or write operation will automatically continue to the first sector under head 1 when the 82077AA finishes operating on the last sector under head 0 Sector size code This specifies the number of bytes in a sector If this parameter is ``00'' then the sector size is 128 bytes The number of bytes transferred is determined by the DTL parameter Otherwise the sector size is (2 raised to the ``N'th'' power) times 128 All values up to ``07'' hex are allowable ``07''h would equal a sector size of 16k It is the users responsibility to not select combinations that are not possible with the drive N 00 01 02 03 07 NCN ND Sector Size 128 bytes 256 bytes 512 bytes 1024 bytes 16 Kbytes
DS0 DS1 Disk Drive Select
MFM MT
EC
EFIFO
EIS
Special sector size By setting N to zero (00) DTL may be used to control the number of bytes transferred in disk read write commands The sector size (N e 0) is set to 128 If the actual sector (on the diskette) is larger than DTL the remainder of the actual sector is read but is not passed to the host during read commands during write commands the remainder of the actual sector is written with all zero bytes The CRC check code is calculated with the actual sector When N is not zero DTL has no meaning and should be set to FF HEX Enable Count When this bit is ``1'' the ``DTL'' parameter of the Verify Command becomes SC (Number of sectors per track) Enable FIFO When this bit is 0 the FIFO is enabled A ``1'' puts the 82077AA in the 8272A compatible mode where the FIFO is disabled Enable implied seek When set a seek operation will be performed before executing any read or write command that requires the C parameter in the command phase A ``0'' disables the implied seek End of track The final sector number of the current track Alters Gap 2 length when using Perpendicular Mode Gap length The gap 3 size (Gap 3 is the space between sectors excluding the VCO synchronization field) Head address Selected head 0 or 1 (disk side 0 or 1) as encoded in the sector ID field Head load time The time interval that 82077AA waits after loading the head and before initiating a read or write operation Refer to the SPECIFY command for actual delays Head unload time The time interval from the end of the execution phase (of a read or write command) until the head is unloaded Refer to the SPECIFY command for actual delays
N
EOT GAP GPL
H HDS
HLT
HUT
OW
New cylinder number The desired cylinder number Non-DMA mode flag When set to 1 indicates that the 82077AA is to operate in the non-DMA mode In this mode the host is interrupted for each data transfer When set to 0 the 82077AA operates in DMA mode interfacing to a DMA controller by means of the DRQ and DACK signals The bits denoted D0 D1 D2 and D3 of the PERPENDICULAR MODE command can only be overwritten when the OW bit is set to ``1''
23
82077AA
Symbol PCN Description Present cylinder number The current position of the head at the completion of SENSE INTERRUPT STATUS command Polling disable When set the internal polling routine is disabled When clear polling is enabled seek portion fails it will be reflected in the results status normally returned for a READ WRITE DATA command Status Register 0 (ST0) would contain the error code and C would contain the cylinder on which the seek failed 5 1 1 READ DATA A set of nine (9) bytes is required to place the 82077AA into the Read Data Mode After the READ DATA command has been issued the 82077AA loads the head (if it is in the unloaded state) waits the specified head settling time (defined in the SPECIFY command) and begins reading ID Address Marks and ID fields When the sector address read off the diskette matches with the sector address specified in the command the 82077AA reads the sector's data field and transfers the data to the FIFO After completion of the read operation from the current sector the sector address is incremented by one and the data from the next logical sector is read and output via the FIFO This continuous read function is called ``Multi-Sector Read Operation'' Upon receipt of TC or an implied TC (FIFO overrun underrun) the 82077AA stops sending data but will continue to read data from the current sector check the CRC bytes and at the end of the sector terminate the READ DATA Command N determines the number of bytes per sector (see Table 5-2 below) If N is set to zero the sector size is set to 128 The DTL value determines the number of bytes to be transferred If DTL is less than 128 the 82077AA transfers the specified number of bytes to the host For reads it continues to read the entire 128 byte sector and checks for CRC errors For writes it completes the 128 byte sector by filling in zeroes If N is not set to 00 Hex DTL should be set to FF Hex and has no impact on the number of bytes transferred Table 5-2 Sector Sizes N 00 01 02 03 07 Sector Size 128 bytes 256 bytes 512 bytes 1024 bytes 16 Kbytes
POLL
PRETRK Precompensation start track number Programmable from track 00 to FFH R Sector address The sector number to be read or written In multi-sector transfers this parameter specifies the sector number of the first sector to be read or written Relative cylinder number Relative cylinder offset from present cylinder as used by the RELATIVE SEEK command Number of sectors The number of sectors to be initialized by the FORMAT command The number of sectors to be verified during a Verify Command when EC is set Skip flag When set to 1 sectors containing a deleted data address mark will automatically be skipped during the execution of READ DATA If READ DELETED is executed only sectors with a deleted address mark will be accessed When set to ``0'' the sector is read or written the same as the read and write commands Step rate interval The time interval between step pulses issued by the 82077AA Programmable from 0 5 to 8 milliseconds in increments of 0 5 ms at the 1 Mbit data rate Refer to the SPECIFY command for actual delays Status register 0-3 Registers within the 82077AA that store status information after a command has been executed This status information is available to the host during the result phase after command execution Write gate alters timing of WE to allow for pre-erase loads in perpendicular drives
RCN
SC
SK
SRT
ST0 ST1 ST2 ST3
WGATE
5 1 Data Transfer Commands
All of the READ DATA WRITE DATA and VERIFY type commands use the same parameter bytes and return the same results information The only difference being the coding of bits 0-4 in the first byte An implied seek will be executed if the feature was enabled by the CONFIGURE command This seek is completely transparent to the user The Drive Busy bit for the drive will go active in the Main Status Register during the seek portion of the command If the 24
The amount of data which can be handled with a single command to the 82077AA depends upon MT (multi-track) and N (Number of bytes sector)
82077AA
Table 5-3 Effects of MT and N Bits MT 0 1 0 1 0 1 N 1 1 2 2 3 3 Max Transfer Capacity 256 c 26 e 6 656 256 c 52 e 13 312 512 c 15 e 7 680 512 c 30 e 15 360 1024 c 8 e 8 192 1024 c 16 e 16 384 Final Sector Read from Disk 26 at side 0 or 1 26 at side 1 15 at side 0 or 1 15 at side 1 8 at side 0 or 1 16 at side 1
Table 5-4 Skip Bit vs READ DATA Command
SK Bit Value 0 0 Data Address Results Mark Type Sector CM Bit Description of Encountered Read of ST2 Set Results Normal Data Deleted Data Yes Yes No Yes Normal Termination Address Not Incremented Next Sector Not Searched For Normal Termination Normal Termination Sector Not Read (``Skipped'')
The Multi-Track function (MT) allows the 82077AA to read data from both sides of the diskette For a particular cylinder data will be transferred starting at Sector 1 Side 0 and completing at the last sector of the same track at Side 1 If the host terminates a read or write operation in the 82077AA then the ID information in the result phase is dependent upon the state of the MT bit and EOT byte Refer to Table 5-6 At the completion of the READ DATA Command the head is not unloaded until after the Head Unload Time Interval (specified in the SPECIFY command) has elapsed If the host issues another command before the head unloads then the head settling time may be saved between subsequent reads If the 82077AA detects a pulse on the IDX pin twice without finding the specified sector (meaning that the diskette's index hole passes through index detect logic in the drive twice) the 82077AA sets the IC code in Status Register 0 to ``01'' (Abnormal termination) and sets the ND bit in Status Register 1 to ``1'' indicating a sector not found and terminates the READ DATA Command After reading the ID and Data Fields in each sector the 82077AA checks the CRC bytes If a CRC error occurs in the ID or data field the 82077AA sets the IC code in Status Register 0 to ``01'' (Abnormal termination) sets the DE bit flag in Status Register 1 to `'1'' sets the DD bit in Status Register 2 to ``1'' if CRC is incorrect in the ID field and terminates the READ DATA Command Table 5-4 describes the affect of the SK bit on the READ DATA command execution and results
1 1
Normal Data Deleted Data
Yes No
No Yes
Except where noted in Table 5-4 the C or R value of the sector address is automatically incremented (see Table 5-6) 5 1 2 READ DELETED DATA This command is the same as the READ DATA command only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field Table 5-5 describes the affect of the SK bit on the READ DELETED DATA command execution and results Table 5-5 Skip Bit vs READ DELETED DATA Command
SK Bit Value 0 Data Address Mark Type Encountered Normal Data Results Sector Read Yes CM Bit of ST2 Set Yes Description of Results Address Not Incremented Next Sector Not Searched For Normal Termination Normal Termination Sector Not Read (``Skipped'') Normal Termination
0 1
Deleted Data Normal Data
Yes No
No Yes
1
Deleted Data
Yes
No
Except where noted in Table 5-5 above the C or R value of the sector address is automatically incremented (See Table 5-6) 25
82077AA
Table 5-6 Result Phase Table MT Head 0 0 1 0 1 1 Final Sector Transferred to Host Less than EOT Equal to EOT Less than EOT Equal to EOT Less than EOT Equal to EOT Less than EOT Equal to EOT ID Information at Result Phase C NC Ca1 NC Ca1 NC NC NC Ca1 H NC NC NC NC NC LSB NC LSB R Ra1 01 Ra1 01 Ra1 01 Ra1 01 N NC NC NC NC NC NC NC NC
NC no change the same value as the one at the beginning of command execution LSB least significant bit the LSB of H is complemented
5 1 3 READ TRACK This command is similar to the READ DATA command except that the entire data field is read continuously from each of the sectors of a track Immediately after encountering a pulse on the IDX pin the 82077AA starts to read all data fields on the track as continuous blocks of data without regard to logical sector numbers If the 82077AA finds an error in the ID or DATA CRC check bytes it continues to read data from the track and sets the appropriate error bits at the end of the command The 82077AA compares the ID information read from each sector with the specified value in the command and sets the ND flag of Status Register 1 to a ``1'' if there is no comparison Multi-track or skip operations are not allowed with this command The MT and SK bits (Bits D7 and D5 of the first command byte respectively) should always be set to ``0'' This command terminates when the EOT specified number of sectors have been read If the 82077AA does not find an ID Address Mark on the diskette after the second occurrence of a pulse on the IDX pin then it sets the IC code in Status Register 0 to ``01'' (Abnormal termination) sets the MA bit in Status Register 1 to ``1'' and terminates the command 5 1 4 WRITE DATA After the WRITE DATA command has been issued the 82077AA loads the head (if it is in the unloaded state) waits the specified head load time if unloaded (defined in the SPECIFY command) and begins reading ID Fields When the sector address read from the diskette matches the sector address specified in the command the 82077AA reads the data from the host via the FIFO and writes it to the sector's data field After writing data into the current sector the 82077AA computes the CRC value and writes it into the CRC field at the end of the sector transfer The 26
Sector Number stored in ``R'' is incremented by one and the 82077AA continues writing to the next data field The 82077AA continues this ``Multi-Sector Write Operation'' Upon receipt of a terminal count signal or if a FIFO over under run occurs while a data field is being written then the remainder of the data field is filled with zeros The 82077AA reads the ID field of each sector and checks the CRC bytes If it detects a CRC error in one of the ID Fields it sets the IC code in Status Register 0 to ``01'' (Abnormal termination) sets the DE bit of Status Register 1 to ``1'' and terminates the WRITE DATA command The WRITE DATA command operates in much the same manner as the READ DATA command The following items are the same Please refer to the READ DATA Command for details

Transfer Capacity EN (End of Cylinder) bit ND (No Data) bit Head Load Unload Time Interval ID information when the host terminates the command not e 0
Definition of DTL when N e 0 and when N does
5 1 5 WRITE DELETED DATA This command is almost the same as the WRITE DATA command except that a Deleted Data Address Mark is written at the beginning of the Data Field instead of the normal Data Address Mark This command is typically used to mark a bad sector containing an error on the floppy disk 5 1 6 VERIFY The VERIFY command is used to verify the data stored on a disk This command acts exactly like a READ DATA command except that no data is transferred to the host Data is read from the disk CRC
82077AA
computed and checked against the previously stored value Because no data is transferred to the host TC (pin 25) cannot be used to terminate this command By setting the EC bit to ``1'' an implicit TC will be issued to the 82077AA This implicit TC will occur when the SC value has decrement to 0 (an SC value of 0 will verify 256 sectors) This command can also be terminated by setting the EC bit to ``0'' and the EOT value equal to the final sector to be checked If EC is set to ``0'' DTL SC should be programmed to 0FFH Refer to Table 5-6 and Table 5-7 for information concerning the values of MT and EC versus SC and EOT value Definitions Sectors Per Side e Number of formatted sectors per each side of the disk Sectors Remaining e Number of formatted sectors left which can be read including side 1 of the disk if MT is set to ``1'' 5 1 7 FORMAT TRACK The FORMAT command allows an entire track to be formatted After a pulse from the IDX pin is detected the 82077AA starts writing data on the disk including Gaps Address Marks ID Fields and Data Fields per the IBM System 34 (MFM) The particular values that will be written to the gap and data field are controlled by the values programmed into N SC GPL and D which are specified by the host during the command phase The data field of the sector is filled with the data byte specified by D The ID Field for each sector is supplied by the host that is four data bytes per sector are needed by the 82077AA for C H R and N (cylinder head sector number and sector size respectively) After formatting each sector the host must send new values for C H R and N to the 82077AA for the next sector on the track The R value (sector number) is the only value that must be changed by the host after each sector is formatted This allows the disk to be formatted with nonsequential sector addresses (interleaving) This incrementing and formatting continues for the whole track until the 82077AA encounters a pulse on the IDX pin again and it terminates the command Table 5-8 contains typical values for gap fields which are dependent upon the size of the sector and the number of sectors on each track Actual values can vary due to drive electronics
Table 5-7 Verify Command Result Phase Table MT 0 0 0 EC 0 0 1 SC EOT Value SC e DTL EOT s Sectors Per Side SC e DTL EOT l Sectors Per Side SC s Sectors Remaining AND EOT s Sectors Per Side Termination Result Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid Unsuccessful Termination Result Phase Invalid
0
1
SC l
Sectors Remaining OR EOT l Sectors Per Side
1 1 1
0 0 1
SC e DTL EOT s Sectors Per Side SC e DTL EOT l Sectors Per Side SC s Sectors Remaining AND EOT s Sectors Per Side
1
1
SC l
Sectors Remaining OR EOT l Sectors Per Side
NOTE If MT is set to ``1'' and the SC value is greater than the number of remaining formatted sectors on Side 0 verifying will continue on Side 1 of the disk
27
82077AA
Table 5-8 Typical Values for Formatting Sector Size 256 256 512 1024 2048 4096 256 512 1024 N 01 01 02 03 04 05 1 2 3 SC 12 10 09 04 02 01 0F 09 05 GPL1 0A 20 2A 80 C8 C8 0E 1B 35 GPL2 0C 32 50 F0 FF FF 36 54 74
5 25 Drive
MFM
3 5 Drive
MFM
GPL1 e suggested GPL values in read and write commands to avoid splice point between data field and ID field of contiguous sections GPL2 e suggested GPL value in FORMAT TRACK command PC-AT values (typical) PS 2 values (typical) Applies with 1 0 MB and 2 0 MB drives NOTE All values except Sector Size are in Hex
5 1 7 1 Format Fields
GAP 4a 80x 4E SYNC 12x 00 IAM 3x C2 FC GAP 1 50x 4E SYNC 12x 00 IDAM 3x A1 FE C Y L H D S E C N O C R C GAP 2 22x 4E SYNC 12x 00 DATA AM 3x A1 FB F8 DATA C R C
GAP 3
GAP 4b
Figure 5-1 System 34 Format Double Density
IAM 3x C2 FC IDAM 3x A1 FE DATA AM 3x A1 FB F8 DATA
GAP 4a 80x 4E
SYNC 12x 00
GAP 1 50x 4E
SYNC 12x 00
C Y L
H D
S E C
N O
C R C
GAP 2 41x 4E
SYNC 12x 00
C R C
GAP 3
GAP 4b
Figure 5-2 Perpendicular Format
28
82077AA
sector of data is compared if the conditions are not met the sector number is incremented (R a STP R) and the scan operation is continued The scan operation continues until one of the following conditions occur the conditions for scan are met (equal low or high) the last sector on the track is reached (EOT) or the terminal count signal is received
5 1 8 SCAN COMMANDS The SCAN Commands allow data which is being read from the diskette to be compared against data which is being supplied from the main system (Processor in NON-DMA mode and DMA Controller in DMA mode) The FDC compares the data on a byteby-byte basis and looks for a sector on data which meets the conditions of DFDD e DProcessor DFDD s DProcessor or DFDD t DProcessor Ones complement arithmetic is used for comparison (FF e largest number 00 e smallest number) After a whole
x
If the conditions for scan are met then the FDC sets the SH (Scan Hit) flag of Status Register 2 to a 1 (high) and terminates the Scan Command If the
Table 5-9 Scan Status Codes Command Scan Equal Scan Low or Equal 0 1 0 0 1 0 0 1 Status Register 2 Bit 2 e SN Bit 3 e SH 1 0 1 0 0 1 0 0 DFDD e DProcessor DFDD i DProcessor DFDD e DProcessor DFDD k DProcessor DFDD p DProcessor DFDD e DProcessor DFDD l DProcessor DFDD o DProcessor Comments
Scan High or Equal
conditions for scan are not met between the starting sector (as specified by R) and the last sector on the cylinder (EOT) then the FDC sets the SN (Scan Not Satisfied) flag of Status Register 2 to a 1 (high) and terminates the Scan Command The receipt of a TERMINAL COUNT signal from the Processor or DMA Controller during the scan operation will cause the FDC to complete the comparison of the particular byte which is in process and then to terminate the command Table 10 shows the status of bits SH and SN under various conditions of SCAN If the FDC encounters a Deleted Data Address Mark on one of the sectors (and SK e 0) then it regards the sector as the last sector on the cylinder sets CM (Control Mark) flag of Status Register 2 to a 1 (high) and terminates the command If SK e 1 the FDC skips the sector with the Deleted Address Mark and reads the next sector In the second case (SK e 1) the FDC sets the CM (Control Mark) flag on Status Register 2 to a 1 (high) in order to show that a Deleted Sector had been encountered
When either the STP (contiguous sectors STP e 01 or alternate sectors STP e 02 sectors are read) or the MT (Multi-Track) are programmed it is necessary to remember that the last sector on the track must be read For example if STP e 02 MT e 0 the sectors are numbered sequentially 1 through 26 and we start the Scan Command at sector 21 the following will happen Sectors 21 23 and 25 will be read then the next sector (26) will be skipped and the Index Hole will be encountered before the EOT value of 26 can be read This will result in an abnormal termination of the command If the EOT had been set at 25 or the scanning started at sector 20 then the Scan Command would be completed in a normal manner During the Scan Command data is supplied by either the processor or DMA Controller for comparison against the data read from the diskette In order to avoid having the OR (Over Run) flag set in Status Register 1 it is necessary to have the data available in less than 13 ms (MFM Mode) If an Overrun occurs the FDC terminates the command
29
82077AA
The RECALIBRATE command does not have a result phase SENSE INTERRUPT STATUS command must be issued after the RECALIBRATE command to effectively terminate it and to provide verification of the head position (PCN) During the command phase of the recalibrate operation the 82077AA is in the BUSY state but during the execution phase it is in a NON BUSY state At this time another RECALIBRATE command may be issued and in this manner parallel RECALIBRATE operations may be done on up to 4 drives at once Upon power up the software must issue a RECALIBRATE command to properly initialize all drives and the controller 5 2 3 SEEK The read write head within the drive is moved from track to track under the control of the SEEK Command The 82077AA compares the PCN which is the current head position with the NCN and performs the following operation if there is a difference PCN k NCN Direction signal to drive set to ``1'' (step in) and issues step pulses PCN l NCN Direction signal to drive set to ``0'' (step out) and issues step pulses The rate at which step pulses are issued is controlled by SRT (Stepping Rate Time) in the SPECIFY command After each step pulse is issued NCN is compared against PCN and when NCN e PCN then the SE bit in Status Register 0 is set to ``1'' and the command is terminated During the command phase of the seek or recalibrate operation the 82077AA is in the BUSY state but during the execution phase it is in the NON BUSY state
5 2 Control Commands
Control commands differ from the other commands in that no data transfer takes place Three commands generate an interrupt when complete READ ID RECALIBRATE and SEEK The other control commands do not generate an interrupt 5 2 1 READ ID The READ ID command is used to find the present position of the recording heads The 82077AA stores the values from the first ID Field it is able to read into its registers If the 82077AA does not find an ID Address Mark on the diskette after the second occurrence of a pulse on the IDX pin it then sets the IC code in Status Register 0 to ``01'' (Abnormal termination) sets the MA bit in Status Register 1 to `'1'' and terminates the command The following commands will generate an interrupt upon completion They do not return any result bytes It is highly recommended that control commands be followed by the SENSE INTERRUPT STATUS command Otherwise valuable interrupt status information will be lost 5 2 2 RECALIBRATE This command causes the read write head within the 82077AA to retract to the track 0 position The 82077AA clears the contents of the PCN counter and checks the status of the TRK0 pin from the FDD As long as the TRK0 pin is low the DIR pin remains 0 and step pulses are issued When the TRK0 pin goes high the SE bit in Status Register 0 is set to ``1'' and the command is terminated If the TRK0 pin is still low after 79 step pulses have been issued the 82077AA sets the SE and the EC bits of Status Register 0 to ``1'' and terminates the command Disks capable of handling more than 80 tracks per side may require more than one RECALIBRATE command to return the head back to physical Track 0
30
82077AA
Note that if implied seek is not enabled the read and write commands should be preceded by 1) SEEK command Step to the proper track 2) SENSE INTERRUPT Terminate the Seek STATUS command command 3) READ ID 4) Issue READ WRITE command The SEEK command does not have a result phase Therefore it is highly recommended that the SENSE INTERRUPT STATUS Command be issued after the SEEK command to terminate it and to provide verification of the head position (PCN) The H bit (Head Address) in ST0 will always return a ``0'' When exiting POWERDOWN mode the 82077AA clears the PCN value and the status information to zero Prior to issuing the POWERDOWN command it is highly recommended that the user service all pending interrupts through the SENSE INTERRUPT STATUS command 5 2 4 SENSE INTERRUPT STATUS An interrupt signal on INT pin is generated by the 82077AA for one of the following reasons 1 Upon entering the Result Phase of a READ DATA Command b READ TRACK Command c d e f READ ID Command READ DELETED DATA Command WRITE DATA Command FORMAT TRACK Command Verify head is on proper track
Table 5-9 Interrupt Identification SE 0 1 1 IC 11 00 01 Interrupt Due To Polling Normal Termination of SEEK or RECALIBRATE command Abnormal Termination of SEEK or RECALIBRATE command
The SEEK RELATIVE SEEK and the RECALIBRATE commands have no result phase SENSE INTERRUPT STATUS command must be issued immediately after these commands to terminate them and to provide verification of the head position (PCN) The H (Head Address) bit in ST0 will always return a ``0'' If a SENSE INTERRUPT STATUS is not issued the drive will continue to be BUSY and may effect the operation of the next command 5 2 5 SENSE DRIVE STATUS SENSE DRIVE STATUS obtains drive status information It has no execution phase and goes directly to the result phase from the command phase STATUS REGISTER 3 contains the drive status information 5 2 6 SPECIFY The SPECIFY command sets the initial values for each of the three internal timers The HUT (Head Unload Time) defines the time from the end of the execution phase of one of the read write commands to the head unload state The SRT (Step Rate Time) defines the time interval between adjacent step pulses Note that the spacing between the first and second step pulses may be shorter than the remaining step pulses The HLT (Head Load Time) defines the time between the Head Load signal goes high and the read write operation starts The values change with the data rate speed selection and are documented in Table 5-10
g WRITE DELETED DATA Command h VERIFY Command 2 End of SEEK RELATIVE SEEK or RECALIBRATE Command 3 82077AA requires a data transfer during the execution phase in the non-DMA Mode The SENSE INTERRUPT STATUS command resets the interrupt signal and via the IC code and SE bit of Status Register 0 identifies the cause of the interrupt If a SENSE INTERRUPT STATUS command is issued when no active interrupt condition is present the status register ST0 will return a value of 80H (invalid command)
31
82077AA
EFIFO A ``1'' puts the FIFO into the 8272A compatible mode where the FIFO is disabled This means data transfers are asked for on a byte by byte basis Defaults to ``1'' FIFO disabled The threshold defaults to one POLL Disable polling of the drives Defaults to ``0'' polling enabled When enabled a single interrupt is generated after a RESET No polling is performed while the drive head is loaded and the head unload delay has not expired FIFOTHR The FIFO threshold in the execution phase of read or write commands This is programmable from 1 to 16 bytes Defaults to one byte A ``00'' selects one byte ``0F'' selects 16 bytes PRETRK Pre-compensation start track number Programmable from track 0 to 255 Defaults to track 0 A ``00'' selects track 0 ``FF'' selects 255 5 2 8 VERSION The choice of DMA or NON-DMA operations is made by the ND bit When this bit is ``1'' the NONDMA mode is selected and when ND is ``0'' the DMA mode is selected In DMA mode data transfers are signalled by the DRQ pin Non-DMA mode uses the RQM bit and the INT pin to signal data transfers 5 2 7 CONFIGURE Issued to select the special features of the 82077AA A CONFIGURE command need not be issued if the default values of the 82077AA meet the system requirements CONFIGURE DEFAULT VALUES EIS EFIFO POLL FIFOTHR PRETRK No Implied Seeks FIFO Disabled Polling Enabled FIFO Threshold Set to 1 Byte Pre-Compensation Set to Track 0 RCN The VERSION command checks to see if the controller is an enhanced type or the older type (8272A 765A) A value of 90 H is returned as the result byte defining an enhanced FDD controller is in use No interrupts are generated 5 2 9 RELATIVE SEEK The command is coded the same as for SEEK except for the MSB of the first byte and the DIR bit DIR Head Step Direction Control DIR 0 1 Action Step Head Out Step Head In
Table 5-10 Drive Control Delays (ms)
HUT SRT
1M 500K 300K 250K 1M 500K 300K 250K 0 128 1 8 E 112 F 120 256 16 224 240 426 26 7 373 400 512 8 0 32 7 5 448 480 10 05 16 15 2 1 26 7 25 3 33 1 67 32 30 4 2
HLT 1M 00 01 02 7F 7F 128 1 2 126 127 500K 256 2 4 252 254 300K 426 33 67 420 423 250K 512 4 8 504 508
Relative Cylinder Number that determines how many tracks to step the head in or out from the current track number
EIS Enable implied seek When set to ``1'' the 82077AA will perform a SEEK operation before executing a read or write command Defaults to no implied seek
The RELATIVE SEEK command differs from the SEEK command in that it steps the head the absolute number of tracks specified in the command instead of making a comparison against an internal register The SEEK command is good for drives that support a maximum of 256 tracks RELATIVE SEEKs cannot be overlapped with other RELATIVE SEEKs Only one RELATIVE SEEK can be active at a time Bit 4 of Status Register 0 (EC) will be set if RELATIVE SEEK attempts to step outward beyond Track 0
32
82077AA
As an example assume that a floppy drive has 300 useable tracks and that the host needs to read track 300 and the head is on any track (0-255) If a SEEK command was issued the head would stop at track 255 If a RELATIVE SEEK command was issued the 82077AA would move the head the specified number of tracks regardless of the internal cylinder position register (but would increment the register) If the head had been on track 40 (D) the maximum track that the 82077AA could position the head on using RELATIVE SEEK would be 296 (D) the initial track a 256 (D) The maximum count that the head can be moved with a single RELATIVE SEEK command is 256 (D) The internal register PCN would overflow as the cylinder number crossed track 255 and would contain 40 (D) The resulting PCN value is thus (NCN a PCN) mod 256 Functionally the 82077AA starts counting from 0 again as the track number goes above 255(D) It is the users responsibility to compensate 82077AA functions (precompensation track number) when accessing tracks greater than 255 The 82077AA does not keep track that it is working in an ``extended track area'' (greater than 255) Any command issued would use the current PCN value except for the RECALIBRATE command which only looks for the TRACK0 signal RECALIBRATE would return an error if the head was farther than 79 due to its limitation of issuing a maximum 80 step pulses The user simply needs to issue a second RECALIBRATE command The SEEK command and implied seeks will function correctly within the 44 (D) track (299-255) area of the ``extended track area'' It is the users responsibility not to issue a new track position that would exceed the maximum track that is present in the extended area To return to the standard floppy range (0 - 255) of tracks a RELATIVE SEEK would be issued to cross the track 255 boundary A RELATIVE SEEK can be used instead of the normal SEEK but the host is required to calculate the difference between the current head location and the new (target) head location This may require the host to issue a READ ID command to ensure that the head is physically on the track that software assumes it to be Different 82077AA commands will return different cylinder results which may be difficult to keep track of with software without the READ ID command 5 2 10 DUMPREG The DUMPREG command is designed to support system run-time diagnostics and application software development and debug 5 2 11 PERPENDICULAR MODE COMMAND The PERPENDICULAR MODE command should be issued prior to executing READ WRITE FORMAT commands that access a disk drive with perpendicular recording capability With this command the length of the Gap2 field and VCO enable timing can be altered to accommodate the unique requirements of these drives Table 5-11 describes the effects of the WGATE and GAP bits for the PERPENDICULAR MODE command Upon a reset the 82077AA will default to the conventional mode (WGATE e 0 GAP e 0)
Table 5-11 Effects of WGATE and GAP Bits GAP WGATE 0 0 1 1 0 1 0 1 MODE Conventional Mode Perpendicular Mode (500 Kbps Data Rate) Reserved (Conventional) Perpendicular Mode (1 Mbps Data Rate) VCO Low Length of Portion of Gap2 Gap2 VCO Time after Gap2 Format Written by Write Low Time for Index Pulse Field Data Operation Read Operations 33 Bytes 33 Bytes 33 Bytes 18 Bytes 22 Bytes 22 Bytes 22 Bytes 41 Bytes 0 Bytes 19 Bytes 0 Bytes 38 Bytes 24 Bytes 24 Bytes 24 Bytes 43 Bytes
33
82077AA
Selection of the 500 Kbps and 1 Mbps perpendicular modes is independent of the actual data rate selected in the Data rate Select Register The user must ensure that the two data rates remain consistent The Gap2 and VCO timing requirements for perpendicular recording type drives are dictated by the design of the read write head In the design of this head a pre-erase head precedes the normal read write head by a distance of 200 micrometers This works out to about 38 bytes at a 1 Mbps recording density Whenever the write head is enabled by the Write Gate signal the pre-erase head is also activated at the same time Thus when the write head is initially turned on flux transitions recorded on the media for the first 38 bytes will not be preconditioned with the pre-erase head since it has not yet been activated To accommodate this head activation and deactivation time the Gap2 field is expanded to a length of 41 bytes The format field shown in Figure 5-2 illustrates the change in the Gap2 field size for the perpendicular format On the read back by the 82077AA the controller must begin synchronization at the beginning of the Sync field For the conventional mode the internal PLL VCO is enabled (VCOEN) approximately 24 bytes from the start of the Gap2 field But when the controller operates in the 1 Mbps perpendicular mode (WGATE e 1 GAP e 1) VCOEN goes active after 43 bytes to accommodate the increased Gap2 field size For both cases an approximate 2 byte cushion is maintained from the beginning of the sync field for the purposes of avoiding write splices in the presence of motor speed variation For the WRITE DATA case the 82077AA activates Write Gate at the beginning of the sync field under the conventional mode The controller then writes a new sync field data address mark data field and CRC as shown in Figure 5-1 With the pre-erase head of the perpendicular drive the write head must be activated in the Gap2 field to insure a proper write of the new sync field For the 1 Mbps perpendicular mode (WGATE e 1 GAP e 1) 38 bytes will be written in the Gap2 space Since the bit density is Old PERPENDICULAR MODE command Phase RW D7 D6 D5 D4 proportional to the data rate 19 bytes will be written in the Gap2 field for the 500 Kbps perpendicular mode (WGATE e 1 GAP e 0) It should be noted that none of the alterations in Gap2 size VCO timing or Write Gate timing affect normal program flow The information provided here is just for background purposes and is not needed for normal operation Once the PERPENDICULAR MODE command is invoked 82077AA software behavior from the user standpoint is unchanged
5 3 Command Set Enhancements
The PERPENDICULAR MODE and DUMPREG commands were enhanced along with the addition of a new LOCK command These enhancements are explained in this section of the data sheet The commands were enhanced added in order to provide protection against older software application package which could inadvertently cause system compatibility problems The modifications addition are fully backward compatible with the older 82077AAs which do not support the enhancements All 82077AAs will support these enhancements as of Q1 1991 For more information regarding which 82077AA do or do not support the enhancements please contact your local Intel Sales office 5 3 1 PERPENDICULAR MODE The PERPENDICULAR MODE Command is enhanced to allow the system designers to designate specific drives as Perpendicular recording drives This enhancement is made so that the system designer does not have to worry about older application software packages which bypass their system's FDC (Floppy Disk Controller) routines The enhancement will also allow data transfers between Conventional and Perpendicular drives without having to issue PERPENDICULAR MODE commands between the accesses of the two different drives nor having to change write pre-compensation values The following is an explanation of how this enhancement is implemented Data Bus D3 D2 D1 D0
Remarks
PERPENDICULAR MODE Command W W 0 0 0 0 0 0 1 0 0 0 0 0 1 GAP 0 WGATE Command Code
NOTE For the definition of GAP and WGATE bits see Table 5-11 and Section 5 2 11 of the data sheet For the Enhanced PERPENDICULAR MODE command definition see Table 5-1
34
82077AA
With the old implementation the user must properly program both the PERPENDICULAR MODE command and write pre-compensation value before accessing either a Conventional or Perpendicular drive These programmed values apply to all drives (D0-D3) which the 82077AA may access It should also be noted that any form of RESET ``Hardware'' or ``Software'' will configure the PERPENDICULAR MODE command for Conventional mode (GAP and WGATE e ``0'') With the enhanced implementation both the GAP and WGATE bits have the same affects as the old implementation except for when they are both programmed for value of ``0'' (Conventional mode) For the case when both GAP and WGATE equal ``0'' the PERPENDICULAR MODE command will have the following effect on the 82077AA 1) If any of the new bits D0 D1 D2 and D3 are programmed to ``1'' the corresponding drive will automatically be programmed for Perpendicular mode (ie GAP2 being written during a write operation the programmed Data Rate will determine the length of GAP2 ) and data will be written with 0 ns write pre-compensation 2) any of the new bits (D0-D3) that are programmed for ``0'' the designated drive will be programmed for Conventional Mode and data will be written with the currently programmed write precompensation value 3) Bits D0 D1 D2 and D3 can only be over written when the OW bit is written as a ``1'' The status of these bits can be determined by interpreting the eighth result byte of the enhanced DUMPREG Command (See Section 5 3 3) (Note if either the GAP or WGATE bit is a ``1'' then bits D0 - D3 are ignored ) ``Software'' and ``Hardware'' RESET will have the following effects on the enhanced PERPENDICULAR MODE command 1) ``Software'' RESETs (Reset via DOR or DSR registers) will only clear GAP and WGATE bits to ``0'' D3 D2 D1 and D0 will retain their previously programmed values 2) ``Hardware'' RESETs (Reset via pin 32) will clear all bits (GAP Wgate D0 D1 D2 and D3) to ``0'' (All Drives Conventional Mode) 5 3 2 LOCK In order to protect a system with long DMA latencies against older application software packages that can disable the 82077AA's FIFO the following LOCK Command has been added to the 82077AA's command set Note This command should only be used by the system's FDC routines and ISVs (Independent Software Vendors) should refrain from using it If an ISV's application calls for having the 82077AA FIFO disabled a CONFIGURE Command should be used to toggle the EFIFO (Enable FIFO) bit ISV can determine the value of the LOCK bit by interpreting the eighth result byte of an DUMPREG Command (See Section 5 3 3) The LOCK command defines whether EFIFO FIFOTHR and PRETRK parameters of the CONFIGURE command can be RESET by the DOR and DSR registers When the LOCK bit is set to a ``1'' all subsequent ``software'' RESETs by the DOR and DSR registers will not change the previously set parameter values in the CONFIGURE command When the LOCK bit is set to a ``0'' ``software'' RESETs by the DOR or DSR registers will return these parameters to their default values (See Section 5 2 7) All ``hardware'' Resets by pin 32 will set the LOCK bit to a ``0'' value and will return EFIFO FIFOTHR and PRETRK to their default values A Status byte is returned immediately after issuing the command byte This Status byte reflects the value of the Lock bit set by the command byte (Note No interrupts are generated at the end of this command ) 5 3 3 ENHANCED DUMPREG COMMAND To accommodate the new LOCK command and enhanced PERPENDICULAR MODE command the eighth result byte of DUMPREG command has been modified in the following manner Remarks
Phase R W
Data Bus D7 D6 D5 D4 D3 D2 D1 D0
DUMPREG Result R R Eighth Result Byte Undefined D3 D2 D1 Old Enhanced
LOCK
0
D0
GAP
WGATE
NOTES 1 Data bit 7 reflects the status of the new LOCK bit set by the LOCK Command 2 Data Bits D0-D5 reflect the status for bits D3 D2 D1 D0 GAP and WGATE set by the PERPENDICULAR MODE Command
35
82077AA
6 0 STATUS REGISTER ENCODING
The contents of these registers are available only through a command sequence
6 1 Status Register 0
Bit No 76 Symbol IC Name Interrupt Code Description 00-Normal termination of command The specified command was properly executed and completed without error 01-Abnormal termination of command Command execution was started but was not successfully completed 10-Invalid command The requested command could not be executed 11-Abnormal termination caused by Polling The 82077AA completed a SEEK or RECALIBRATE command or a READ or WRITE with implied seek command The TRK0 pin failed to become a ``1'' after 1 80 step pulses in the RECALIBRATE command 2 The RELATIVE SEEK command causes the 82077AA to step outward beyond Track 0 Unused This bit is always ``0'' H DS1 0 Head Address Drive Select The current head address The current selected drive
5 4
SE EC
Seek End Equipment Check
3 2 10
6 2 Status Register 1
Bit No 7 Symbol EN Name End of Cylinder Description The 82077AA tried to access a sector beyond the final sector of the track (255D) Will be set if TC is not issued after Read or Write Data Command Unused This bit is always ``0'' DE OR Data Error Overrun Underrun The 82077AA detected a CRC error in either the ID field or the data field of a sector Becomes set if the 82077AA does not receive CPU or DMA service within the required time interval resulting in data overrun or underrun Unused This bit is always ``0'' ND No Data Any one of the following 1 READ DATA READ DELETED DATA command the 82077AA did not find the specified sector 2 READ ID command the 82077AA cannot read the ID field without an error 3 READ TRACK command the 82077AA cannot find the proper sector sequence WP pin became a ``1'' while the 82077AA is executing a WRITE DATA WRITE DELETED DATA or FORMAT TRACK command Any one of the following 1 The 82077AA did not detect an ID address mark at the specified track after encountering the index pulse from the IDX pin twice 2 The 82077AA cannot detect a data address mark or a deleted data address mark on the specified track
6 5 4
3 2
1
NW
Not Writable
0
MA
Missing Address Mark
36
82077AA
6 3 Status Register 2
Bit No 7 6 CM Control Mark Symbol Name Description Unused This bit is always ``0'' Any one of the following 1 READ DATA command the 82077AA encounters a deleted data address mark 2 READ DELETED DATA command the 82077AA encounters a data address mark The 82077AA detected a CRC error in the data field
5
DD
Data Error in Data Field Wrong Cylinder
4 3 2 1
WC
The track address from the sector ID field is different from the track address maintained inside the 82077AA Unused This bit is always ``0'' Unused This bit is always ``0''
BC
Bad Cylinder
The track address from the sector ID field is different from the track address maintained inside the 82077AA and is equal to FF hex which indicates a bad track with a hard error according to the IBM soft-sectored format The 82077AA cannot detect a data address mark or a deleted data address mark
0
MD
Missing Data Address Mark
6 4 Status Register 3
Bit No 7 6 5 4 3 2 10 HD DS1 0 Head Address Drive Select T0 TRACK 0 WP Write Protected Symbol Name Description Unused This bit is always ``0'' Indicates the status of the WP pin Unused This bit is always ``1'' Indicates the status of the TRK0 pin Unused This bit is always ``1'' Indicates the status of the HDSEL pin Indicates the status of the DS1 DS0 pins IDENT and MFM pins are sampled during Hardware Reset
7 0 COMPATIBILITY
The 82077AA was designed with software compatibility in mind It is a fully backwards compatible solution with the older generation 8272A and NEC765A B disk controllers The 82077AA also implements on-board registers for compatibility with the Personal System 2s as well as PC AT and PC XT floppy disk controller subsystems Upon a hardware reset of the 82077AA all registers functions and enhancements default to a PS 2 PC AT or PS 2 Model 30 compatible operating mode depending on how the
7 1 Register Set Compatibility
The register set contained within the 82077AA is a culmination of hardware registers based on the architectural growth of the IBM personal computer line Table 7-1 indicates the registers required for compatibility based on the type of computer
37
82077AA
If the DMAGATE bit is written to a ``0'' in the Digital Output Register (DOR) DRQ and INT will tristate If DMAGATE is written to a ``1'' then DRQ and INT will be driven appropriately by the 82077AA TC is an active high input signal that is internally qualified by DACK being active low 7 2 3 MODEL 30 MODE IDENT strapped low causes the polarity of DENSEL to be active low for high (500 Kbps 1 Mbps) data rates (typically used for 3 5 drives) This polarity of DENSEL assumes INVERT to be low A comprehensive description of DENSEL behavior is given in Table 2-6 DMAGATE and TC function the same as in PC AT Mode
Table 7-1 82077AA Register Support 82077AA Mod 8272A 82072 PC XT PC AT PS 2 Register 30 SRA SRB DOR MSR DSR Data (FIFO) DIR CCR X X X X X X X X X X X X X X X X X X X X X X X X X X X X
CCR is emulated by DSR in an 82072 PC AT design
7 2 PS 2 vs AT vs Model 30 Mode
To maintain compatibility between PS 2 PC AT and Model 30 environments the IDENT and MFM pins are provided The 82077AA is placed into the proper mode of operations upon Hardware RESET with the appropriate settings of the IDENT and MFM pins The proper settings of the IDENT and MFM pins are described in IDENT's pin description Differences between the three modes are described in the following sections 7 2 1 PS 2 MODE IDENT strapped low causes the polarity of DENSEL to be active low for high (500 Kbps 1 Mbps) data rates (typically used for 3 5 drives) This polalrity of DENSEL assumes INVERT to be low A comprehensive description of DENSEL behavior is given in Table 2-6 The DMAGATE bit in the Digital Output Register (DOR) will not cause the DRQ or INT output signals to tristate This maintains consistency with the operation of the floppy disk controller subsystem in the PS 2 architecture TC is an active low input signal that is internally qualified by DACK being active low 7 2 2 PC AT MODE IDENT strapped high causes the polarity of DENSEL to be active high for high (500 Kbps 1 Mbps) data rates (typically used for 5 25 drives) This polarity of DENSEL assumes INVERT to be low A comprehensive description of DENSEL behavior is given in Table 2-6
7 3 Compatibility with the FIFO
The FIFO of the 82077AA is designed to be transparent to non-FIFO disk controller software developed on the older generation 8272A standard Operation of the 82077AA FIFO can be broken down into two tiers of compatibility For first tier compatibility the FIFO is left in the default disabled condition upon a ``Hardware'' reset (via pin 32) In this mode the FIFO operates in a byte mode and provides complete compability with non-FIFO based software For second tier compatibility the FIFO is enabled via the CONFIGURE command When the FIFO is enabled it will temporarily enter a byte mode during the command and result phase of disk controller operation This allows for compatible operation when interrogating the Main Status Register (MSR) for the purpose of transferring a byte at a time to or from the disk controller For normal disk controller applications the system designer can still take advantage of the FIFO for time critical data transfers during the execution phase and not create any conflicts with non-FIFO software during the command or result phase In some instances use of the FIFO in any form has conflicted with certain specialized software An example of a compatibility conflict using the FIFO is with software that monitors the progress of a data transfer during the execution phase If the software assumed the disk controller was operating in a single byte mode and counted the number of bytes transferred to or from the disk controller to trigger some time dependent event on the disk media (i e head position over a specific data field) the same software will not have an identical time relationship if the FIFO is enabled This is because the FIFO allows data to be queued up and then burst trans-
38
82077AA
ferred across the host bus To accommodate software of this type it is recommended that the FIFO be disabled followed with a SENSE INTERRUPT STATUS command from the host to clear the interrupt condition for each of the four logical drives
7 4 Drive Polling
The 82077AA supports the polling mode of the older generation 8272A This mode is enabled upon a reset and can be disabled via the CONFIGURE command This mode is supported for the sole purpose of providing backwards compatibility with software that expects it's presence The intended purpose of drive polling dates back to 8 drives as a means to monitor any change in status for each disk drive present in the system Each of the drives is selected for a period of time and its READY signal sampled After a delay the next drive is selected Since the 82077AA does not support READY in this capacity (internally tied true) the polling sequence is only simulated and does not affect the drive select lines (DS0-DS3) when it is active If enabled it occurs whenever the 82077AA is waiting for a command or during SEEKs and RECALIBRATEs (but not IMPLIED SEEKs) Each drive is assumed to be not ready after a reset and a ``ready'' value for each drive is saved in an internal register as the simulated drive is polled An interrupt will be generated on the first polling loop because of the initial ``not ready'' status This interrupt must be
8 0 PROGRAMMING GUIDELINES
Programming the 82077AA is identical to any other 8272A compatible disk controller with the exception of some additional commands For the new designer it is useful to provide some guidelines on how to program the 82077AA A typical disk operation involves more than issuing a command and waiting for the results The control of the floppy disk drive is a low level operation that requires software intervention at different stages New commands and features have been added to the 82077AA to reduce the complexity of this software interface
8 1 Command and Result Phase Handshaking
Before a command or parameter byte can be issued to the 82077AA the Main Status Register (MSR) must be interrogated for a ready status and proper FIFO direction A typical floppy controller device driver should contain a subroutine for sending command or parameter bytes For this discussion the routine will be called ``Send byte'' with the flowchart shown in Figure 8-1
290166 - 22
Figure 8-1 Send Byte Routine
39
82077AA
The routine loops until RQM is 1 and DIO is 0 indicating a ready status and FIFO direction is inward If this condition is true the 82077AA is ready to accept a command or parameter byte A timeout counter is used to insure software response within a reasonable amount of time in case of no response by the 82077AA As a note the programmer must be careful how the maximum delay is chosen to avoid unnecessary timeouts For example if a new command is issued when the 82077AA is in the middle of a polling routine the MSR will not indicate a ready status for the next parameter byte until the polling sequence completes the loop This could cause a delay between the first and second bytes of up to 250 ms ( 250 Kbps) If polling is disabled this maximum delay is 175 ms There should also be enough timeout margin to accommodate a shift of the software to a higher speed system A timeout value that results in satisfactory operation on a 16 MHz CPU might fail when the software is moved to a system with a 25 MHz CPU A recommended solution is to derive the timeout counter from a system hardware counter that is fixed in frequency from CPU clock to CPU clock For reading result bytes from the 82077AA a similar routine is used Figure 8-2 illustrates the flowchart for the routine ``Get byte'' The MSR is polled until RQM is 1 and DIO is 1 which indicates a ready status and outward FIFO direction At this point the host can read a byte from the FIFO As in the Send byte routine a timout counter should be incorporated in case of a disk controller lock-up condition For example if a disk was not inserted into the disk drive at the time of a read operation the controller would fail to receive the index pulse and lockup since the index pulses are required for termination of the execution phase
8 2 Initialization
Initializing the 82077AA involves setting up the appropriate configuration after a reset Parameters set by the SPECIFY command are undefined after a system reset and will need to be reinitialized CONFIGURE command parameters default to a known state after a system reset but will need to be reinitialized if the system requirements are different from the default settings The flowchart for the recommended initialization sequence of the 82077AA is shown in Figure 8-3
290166 - 23
Figure 8-2 Get Byte Routine
40
82077AA
Following a reset of the 82077AA the Configuration Control Register (CCR) should be reinitialized for the appropriate data rate An external reset via the RESET pin will cause the data rate and write precompensation values to default to 250 Kbps (10b) and 125 ns (000b) respectively Since the 125 ns write precompensation value is optimal for the 5 and disk drive environment most applications will 3 not require the value to be changed in the initialization sequence As a note a software reset issued via the DOR or DSR will not affect the data rate or write precompensation values But it is recommended as a safe programming practice to always program the data rate after a reset regardless of the type Since polling is enabled after a reset of the 82077AA four SENSE INTERRUPT STATUS commands need to be issued afterwards to clear the status flags for each drive The flowchart in Figure 83 illustrates how the software clears each of the four interrupt status flags internally queued by the 82077AA It should be noted that although four SENSE INTERRUPT STATUS commands are issued the INT pin is only active until the first SENSE INTERRUPT STATUS command is executed
290166 - 24
Figure 8-3 Initialization Flowchart
41
82077AA
As a note if the CONFIGURE command is issued within 250 ms of the trailing edge of reset ( 1 Mbps) the polling mode of the 82077AA can be disabled before the polling initiated interrupt occurs Since polling stops when the 82077AA enters the command phase it is only time critical up to the first byte of the CONFIGURE command If disabled in time the system software no longer needs to issue the four SENSE INTERRUPT STATUS commands to clear the internal interrupt flags normally caused by polling The CONFIGURE command should also be issued if the system requirements are different from the default settings (as described in Section 5 2 7) For example the CONFIGURE command can be used to enable the FIFO set the threshold and enable Implied Seeks The non-DMA mode flag step rate (SRT) head load (HLT) and head unload times (HUT) programmed by the SPECIFY command do not default to a known state after a reset This behavior is consistent with the 8272A and has been preserved here for compatibility Thus it is necessary to always issue a SPECIFY command in the initialization routine
8 3 Recalibrates and Seeks
Commands that position the disk head are different from the typical READ WRITE FORMAT command in the sense that there is no result phase Once a RECALIBRATE SEEK or RELATIVE SEEK command has been issued the 82077AA will return a ready status in the Main Status Register (MSR) and perform the head positioning operation as a background task When the seek is complete the 82077AA will assert the INT signal to request service A SENSE INTERRUPT STATUS command should then be asserted to clear the interrupt and read the status of the operation Since the drive and motor enable signals are directly controlled through the Digital Output Register (DOR) on the 82077AA a write to the DOR will need to precede the RECALIBRATE or SEEK command if the drive and motor is not already enabled Figure 8-4 shows the flow chart for this operation
290166 - 25
Figure 8-4 Recalibrate and Seek Operations
42
82077AA
If implied seeks are not enabled the disk drive head must be positioned over the correct cylinder by executing a SEEK command After the seek is complete a head settling time needs to be asserted before the read or write operation begins For most drives this delay should be a minimum of 15 ms When using implied seeks the minimum head settling time can be enforced by the head load time (HLT) parameter designated in the SPECIFY command For example a HLT value of 8 will yield an effective head settling time of 16 ms for a programmed data rate of 500 Kbps Of course if the head is already positioned over the correct cylinder the head settling time does not need to be enforced The DMA controller is then initialized for the data transfer and the read or write command is executed Typically the DMA controller will assert Terminal Count (TC) when the data transfer is complete The 82077AA will then complete the current data transfer and assert the INT signal signifying it has entered the result phase The result phase can also be entered by the 82077AA if an error is encountered or the last sector number equals the End of Track (EOT) parameter Based on the algorithm in Figure 8-5 if an error is encountered after reading the result bytes two more retries are performed by reinitializing the DMA controller and re-issuing the read or write data command A persisting failure could indicate the seek operation did not achieve proper alignment between the head and the track The disk head should then be recalibrated and the seek repeated for a maximum of two more tries Unsuccessful operation after this point should be reported as a disk failure to the operating system
8 4 Read Write Data Operations
A read or write data operation requires several steps to complete successfully The motor needs to be turned on the head positioned to the correct cylinder the DMA controller initialized the read or write command initiated and an error recovery scheme implemented The flowchart in Figure 8-5 highlights a recommended algorithm for performing a read or write data operation Before data can be transferred to or from the diskette the disk drive motor must be brought up to speed For most 3 disk drives the spin-up time is 300 ms while the 5 drive usually requires about 500 ms due to the increased moment of inertia associated with the larger diameter diskette One technique for minimizing the motor spin-up delay in the read data case is to begin the read operation immediately after the motor is turned on When the motor is not initially up to speed the internal data separator will fail to lock onto the incoming data stream and report a failure in the status registers The read operation is then repeated until successful status is obtained There is no risk of a data integrity problem since the data field is CRC validated But it is not recommended to use this technique for the write data operation even though it requires successful reading of the ID field before the write takes place The data separator performance of the 82077AA is such that locking to the data stream could take place while the motor speed variation is still significant This could result in errors when an attempt is made to read the disk media by other disk controllers that have a narrower incoming data stream frequency bandwidth After the motor has been turned on the matching data rate for the media inserted into the disk drive should then be programmed to the 82077AA via the Configuration Control Register (CCR) The 82077AA is designed to allow a different data rate to be programmed arbitrarily without disrupting the integrity of the device In some applications it is required to automatically determine the recorded data rate of the inserted media One technique for doing this is to perform a READ ID operation at each available data rate until a successful status is returned in the result phase
8 5 Formatting
The disk formatting procedure involves positioning the head on each track and creating a fixed format field used for organizing the data fields The flowchart in Figure 8-6 highlights the typical format procedure
43
82077AA
290166 - 26
Figure 8-5 Read Write Operation
44
82077AA
290166 - 27
Figure 8-6 Formatting
45
82077AA
After the motor has been turned on and the correct data rate programmed the disk head is recalibrated to track 0 The disk is then allowed to come up to speed via a 500 ms delay It is important the disk speed has stabilized before the actual formatting to avoid any data rate frequency variations Since the format fields contain critical information used by the data separator of the disk controller for synchronization purposes frequency stability of the data stream is imperative for media interchangeability among different systems The ID field data created on the disk during the format process is provided by the DMA controller during the execution phase The DMA controller is initialized to send the C H R and N values for each sector ID field For example to format cylinder 7 on head 1 with 9 sectors and a sector size of 2 (512 bytes) the DMA controller should be programmed to transfer 36 bytes (9 sectors x 4 bytes per sector) with the following data field 7 1 1 2 7 1 2 2 7 1 3 2 7 1 9 2 Since the values provided to the 82077AA during the execution phase of the format command are directly recorded as the ID fields on the disk the data contents can be arbitrary Some forms of copy protection have been implemented by taking advantage of this capability After each head for a cylinder has been formatted a seek operation to the next cylinder is performed and the format process is repeated Since the FORMAT TRACK command does not have implied seek capability the SEEK command must be used Also as discussed in Section 8-2 the head settling time needs to be adhered to after each seek operation operation The 82077AA supports this older verify technique but also provides a new VERIFY command that does not require the use of the DMA controller To verify a write data transfer or format track operation using the VERIFY command the software simply issues the command with the same format as a READ DATA command but without the support of the DMA controller The 82077AA will then perform a disk read operation without a host data transfer The CRC will be calculated for each sector read and compared against the value stored on the disk When the VERIFY command is complete the status register will report any detected CRC errors
9 0 DESIGN APPLICATIONS 9 1 PC AT Floppy Disk Controller
This section presents a design application of a PC AT compatible floppy disk controller With an 82077AA a 24 MHz crystal a resistor package and a device chip select a complete floppy disk controller can be built The 82077AA integrates all the necessary building blocks for a reliable and low cost solution But before we discuss the design application using the 82077AA it is helpful to describe the architecture of the original IBM PC AT floppy disk controller design that uses the 8272A 9 1 1 PC AT FLOPPY DISK CONTROLLER ARCHITECTURE The standard IBM PC AT floppy disk controller using the 8272A requires 34 devices for a complete solution The block diagram in Figure 9-1 illustrates the complexity of the disk controller A major portion of this logic involves the design of the data separator The reliability of the disk controller is primarily dictated by the performance and stability of the data separator Discrete board level analog phase lock loops generally offer good bit jitter margins but suffer from instability and tuning problems in the manufacturing stage if not carefully designed While digital data separator designs offer stability and generally a lower chip count they suffer from poor performance in the recovery of data
8 6 Verifies
In some applications the sector data needs to be verified immediately after each write operation The verify technique historically used with the 8272A or 82072 disk controller involved reinitializing the DMA controller to perform a read transfer or verify transfer (DACK is asserted but not RD ) immediately after each write operation A read command is then to be issued to the disk controller and the resulting status indicates if the CRC validated the previously written data This technique has the drawback of requiring additional software intervention by having to reprogram the DMA controller between each sector write
46
82077AA
290166 - 28
Figure 9-1 Standard IBM PC AT Floppy Disk Controller Table 9-1 indicates the drive and media types the IBM PC AT disk controller can support This requires the data separator to operate at three different data rates 250 Kbps 300 Kbps and 500 Kbps Clocks to the data separator and disk controller need to be prescaled correspondingly to accommodate each of these data rates The clock prescaling is controlled by the Data rate Select Register (DSR) Supporting all three data rates can compromise the performance of the phase lock loop (PLL) if steps are not taken in the design to adjust the performance parameters of the PLL with the data rate Table 9-1 Standard PC AT Drives and Media Formats Capacity Drive Speed Data Rate Sectors Cylinders 9 9 15 40 40 80
360 Kbyte 300 RPM 250 Kbps 360 Kbyte 360 RPM 300 Kbps 1 2 Mbyte 360 RPM 500 Kbps
360 Kbyte diskette in a 1 2 Mbyte drive
47
82077AA
The PC AT disk controller provides direct control of the drive selects and motors via the Digital Output Register (DOR) As a result drive selects on the 8272A are not utilized This places drive selection and motor speed-up control responsibility with the software The DOR is also used to perform a software reset of the disk controller and tristate the DRQ2 and IRQ6 output signals on the PC bus The design of the disk controller also requires address decode logic for the disk controller and register set buffering for both the disk interface and PC bus support for write precompensation and monitoring of the disk change signal via a separate read only register (DIR) An I O address map of the complete register set for the PC AT floppy disk controller is shown in Table 9-2 Table 9-2 I O Address Map for the PC AT
IO Address 3F0H 3F1H 3F2H 3F3H 3F4H 3F5H 3F6H 3F7H 3F7H Access Type Description Unused Unused Digital Output Register Unused Main Status Register Data Register Unused Data Rate Select Register Digital Input Register
9 1 2 82077AA PC AT SOLUTION The 82077AA integrates the entire PC AT controller design with the exception of the address decode on a single chip The schematic for this solution is shown in Figure 9-2 The chip select for the 82077AA is generated by a 16L8 PAL that is programmed to decode addresses 03F0H thru 03F7H when AEN (Address Enable) is low The programming equation for the PAL is shown in a ABEL file format in Figure 9-3 An alternative address decode solution could be provided by using a 74LS133 13 input NAND gate and 74LS04 inverter to decode A3 - A14 and AEN Although the PC AT allows for a 64K I O address space decoding down to a 32K I O address space is sufficient with the existing base of add-in cards A direct connection between the disk interface and the 82077AA is provided by on-chip output buffers with a 40 mA sink capability Open collector outputs from the disk drive are terminated at the disk controller with a 150X resistor pack The 82077AA disk interface inputs contain a schmitt trigger input structure for higher noise immunity The host interface is a similar direct connection with 12 mA sink capabilities on DB0 - DB7 INT and DRQ
Write Read Read Write Write Read
48
Typical values for 5 25 inch disk drives For 3 5 inch disk drives use 1 KX resistors
Figure 9-2 82077AA PC AT Floppy Disk Controller
82077AA
290166- 29
49
82077AA
MODULE PCAT077 LOGIC TITLE `82077AA PC AT FLOPPY DISK CONTROLLER' PCAT077 DEVICE `P16L8' GND VCC SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 AEN CS077 EQUATIONS `` CHIP SELECT FOR THE 82077AA (3F0H CS077 4 ( SA15 SA14 SA9 SA8 SA7 SA13 SA6 3F7H) SA10 AEN) PIN PIN PIN PIN 10 20 12345678 9 11 13 14 15 16 12
SA12 SA11 SA5 SA4 SA3
END PCAT077 LOGIC Figure 9-3 PAL Equation File for a PC AT Compatible FDC Board
9 2 3 5 Drive Interfacing
The 82077AA is designed to interface to both 3 5 and 5 25 disk drives This is facilitated by the 82077AA by orienting IDENT to get the proper polarity of DENSEL for the disk drive being used Typically DENSEL is active high for high (500 Kbps 1 Mbps) data rates on 5 25 drives And DENSEL is typically active low for high data rates on 3 5 drives A complete description of how to orient IDENT to get the proper polarity for DENSEL is given in Table 2-6 921 35 DRIVES UNDER THE AT MODE
Outputs of the disk drive will drive both high or low voltage levels when the drive is selected and float only when the drive has been deselected These totem pole outputs generally can only sink or source 4 mA of current As a result it is recommended to replace the 150X termination resistor pack with a 4 7 KX package to pull floating signals inactive Some other 3 5 drives do have an open collector interface but have limited sink capability In these cases the drive manufacturer manuals usually suggest a 1 KX termination A second possible change required under ``AT mode'' operation involves high capacity 3 5 disk drives that utilize a density select signal to switch between media recorded at a 250 Kbps and 500 Kbps data rate The polarity of this signal is typically inverted for 3 5 drives versus 5 25 drives Thus an inverter can be added between the DENSEL output of the 82077AA and the disk drive interface connector when using 3 5 drives
When interfacing the 82077AA floppy disk controller with a 3 5 disk drive in a PC AT application it is possible that two design changes will need to be implemented for the design discussed in Section 9 1 Most 3 5 disk drives incorporate a totem pole interface structure as opposed to open collector
50
82077AA
But drives that do not support both data rates or drives with an automatic density detection feature via an optical sensor do not require the use of the DENSEL signal Another method is to change the polarity of IDENT with a drive select signal ORing RESET with the drive select signal (DS0-3) used for the 3 5 disk drive will produce the proper polarity for DENSEL (assuming INVERT is low) 922 35 DRIVES UNDER THE PS 2 MODES tion problems on the disk interface Since 3 5 drives do not have a large sink capability the 150X termination resistor pack required by 5 25 drives cannot be used with the 3 5 drive To accommodate both drives with the same disk controller the outputs of the 3 5 drive should be buffered before connecting to the 82077AA disk interface inputs The 82077AA inputs are then connected to the necessary resistive termination load for the 5 25 interface The block diagram in Figure 9-4 highlights how a combined interface could be designed In this example the 5 25 drive is connected to drive select 0 (DS0) and the 3 5 drive is connected to drive select 1 (DS1) DS1 is also used to enable a 74LS244 buffer on the output signals of the 3 5 drive The drive select logic of the 82077AA is mutually exclusive and prevents the activation of the buffer and 5 25 drive at the same time Since the 74LS244 has an IOL of 24 mA the termination resistor should be increased to 220X This could impact the reliability of the 5 25 drive interface if the cable lengths are greater than 5 feet To accommodate the polarity reversal of the DENSEL signal for 3 5 drives it is routed through an inverter for the 3 5 drive interface A 1 KX pull-up should be placed on the output of the inverter to satisfy the IOH requirements for the 3 5 drive when using a 74LS04
If IDENT is strapped to ground the DENSEL output signal polarity will reflect a typical 3 5 drive mode of operation That is DENSEL will be high for 250 Kbps or 300 Kbps and low for 500 Kbps or 1 Mbps (assuming INVERT is low) Thus the only change from the disk interface shown in Figure 9-2 is to replace the 150X termination resistor pack with a value of about 10 KX This will prevent excessive current consumption on the CMOS inputs of the 82077AA by pulling them inactive when the drive(s) are deselected 9 2 3 COMBINING 5 25 AND 3 5 DRIVES
If 5 25 and 3 5 drives are to be combined in a design then steps need to be taken to avoid conten-
290166 - 30
Figure 9-4 Combined 3 5 and 5 25 Drive Interface
51
82077AA
10 0 D C SPECIFICATIONS 10 1 Absolute Maximum Ratings
Storage Temperature Supply Voltage Voltage on Any Input Voltage on Any Output Power Dissipation
b 65 C to a 150 C b 0 5 to a 8 0V
NOTICE This is a production data sheet The specifications are subject to change without notice
GND b 2V to 6 5V GND b 0 5V to VCC a 0 5V 1 Watt
WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability
10 2 D C Characteristics
TA e 0 C to e 70 C VCC e a 5V g10% VSS e AVSS e 0V Symbol VILC VIHC VIL VIH VOL Parameter Input Low Voltage X1 Input High Voltage X1 Input Low Voltage (all pins except X1) Input High Voltage (all pins except X1) Output Low Voltage MFM DRATE0-1 DB0-7 INT and DRQ ME0-3 DS0-3 DIR STP WRDATA WE HDSEL and DENSEL VOH Output High Voltage MFM All Other Outputs All Outputs ICC1 ICC2 ICC3 ICC4 ICCSB IIL IOFL VCC Supply Current (Total) 1 Mbps Data Rate VIL e VSS VIH e VCC 1 Mbps Data Rate VIL e 0 45 VIH e 2 4 500 Kbps Data Rate VIL e VSS VIH e VCC 500 Kbps Data Rate VIL e 0 45 VIH e 2 4 ICC in Powerdown Input Load Current (all input pins) Data Bus Output Float Leakage 30 30 VCC b 0 4 45 50 35 40 15 10
b 10
g10
Min
b0 5
Max 08 VCC a 0 5 08 VCC a 0 5 04 04 04 04
Unit V V V V V V V V
Test Conditions
39
b0 5
20
IOL e 2 5 mA IOL e 6 0 mA IOL e 12 mA IOL e 40 mA
V V V mA mA mA mA mA mA mA mA
IOH e b 2 5 mA IOH e b 4 0 mA IOH e b 100 mA (Notes 1 (Notes 1 (Notes 1 (Notes 1 (Note 3) VIN e VCC VIN e 0V 0 45 k VOUT k VCC 2) 2) 2) 2)
NOTES 1 The data bus are the only inputs that may be floated 2 Tested while reading a sync field of ``00'' Outputs not connected to D C loads 3 VIL e VSS VIH e VCC Outputs not connected to D C loads
52
82077AA
Capacitance
CIN CIN1 CI O Input Capacitance Clock Input Capacitance Input Output Capacitance 10 20 20 pF pF pF F e 1 MHz TA e 25 C Sampled not 100% Tested
NOTE All pins except pins under test are tied to AC ground
LOAD CIRCUIT
A C TESTING INPUT OUTPUT WAVEFORM
82077AA
290166 - 7 Cload e 50 pF for all logic outputs 100 pF for the data bus
290166 - 8
11 0 A C SPECIFICATIONS
TA e 0 C to 70 C VCC e a 5V g10% VSS e AVSS e 0V Symbol CLOCK TIMINGS t1 Clock Rise Time Clock Fall Time t2 t3 t4 t5 Clock High Time(7) Clock Low Time(7) Clock Period Internal Clock Period(3) 16 16 41 66 10 10 26 26 41 66 ns ns ns ns ns Parameter Min Max Unit
HOST READ CYCLES t7 t8 t9 t10 t11 t12 t13 t14 Address Setup to RD RD Pulse Width Address Hold from RD Data Valid from RD(12) Command Inactive Output Float Delay INT Delay from RD Data Hold from RD 5 60 35 t5 a 125 5 90 0 80 ns ns ns ns ns ns ns ns
53
82077AA
A C SPECIFICATIONS (Continued)
TA e 0 C to 70 C VCC e a 5V g10% VSS e AVSS e 0V Symbol HOST WRITE CYCLES t15 t16 t17 t18 t19 t20 t21 DMA CYCLES t22 t23 t24 t25 t26 t27 t28 t29 RESET t30 t30a t31 ``Hardware'' Reset Width(5) ``Software'' Reset Width(5) Reset to Control Inactive Write Data Width(6) DIR Setup to STEP(14) DIR Hold from STEP STEP Active Time (High) STEP Cycle Time(2) INDEX Pulse Width WE to HDSEL Change 5 (Note 13) 170 (Note 11) 2 t4 ms ms DRQ Cycle Period(1) DACK to DRQ Inactive RD to DRQ Inactive(4) DACK Setup to RD WR DACK Hold from RD WR DRQ to RD WR Active(1) Terminal Count Width(10) TC to DRQ Inactive 5 0 0 50 150 6 65 75 100 ms ns ns ns ns ms ns ns Address Setup to WR WR Pulse Width Address Hold from WR Command Inactive Data Setup to WR Data Hold from WR INT Delay from WR 5 90 0 60 70 0 t5 a 125 ns ns ns ns ns ns ns Parameter Min Max Unit
WRITE DATA TIMING t32 ns
DRIVE CONTROL t35 t36 t37 t38 t39 t41 10 10 25 ms ms ms ms t5 ms
54
82077AA
A C SPECIFICATIONS (Continued)
TA e 0 C to 70 C VCC e a 5V g10% VSS e AVSS e 0V Symbol READ DATA TIMING t40 f44 Read Data Pulse Width PLL Data Rate 82077AA-1 82077AA(15) 82077AA-5(15) t44 tLOCK Data Rate Period 1 f44 Lockup Time 64 t44 50 1M 500K ns bit s bit s Parameter Min Max Unit
NOTES 1 This timing is for FIFO threshold e 1 When FIFO threshold is N bytes the value should be multiplied by N and subtract 1 5 ms The value shown is for 1 Mbps scales linearly with data rate 2 This value can range from 0 5 ms to 8 0 ms and is dependent upon data rate and the Specify command value 3 Many timings are a function of the selected data rate The nominal values for the internal clock period (t5) for the various data rates are 1 Mbps 500 Kbps 300 Kbps 250 Kbps 3 6 10 12 x x x x oscillator oscillator oscillator oscillator period period period period
e e e e
125 250 420 500
ns ns ns ns
4 If DACK transitions before RD then this specification is ignored If there is no transition on DACK then this becomes the DRQ inactive delay 5 Reset requires a stable oscillator to meet the minimum active period 6 Based on the internal clock period (t5) For various data rates the Write Data Width minimum values are 1 Mbps 500 Kbps 300 Kbps 250 Kbps 5 10 16 19 x x x x oscillator oscillator oscillator oscillator period period period period
b 50 b 50 b 50 b 50
ns ns ns ns
e e e e
150 360 615 740
ns ns ns ns
7 Test points for clock high time are 3 5V Due to transitional times clock high time max and clock low time max cannot be met simultaneously Clock high time min and clock low time max cannot be met simultaneously 8 Based on internal clock period (t5) Maximum bit shift from nominal position c 100% 9 Jitter tolerance is defined as 1 4 period of nominal data rate It is a measure of the allowable bit jitter that may be present and still be correctly detected The data separator jitter tolerance is measured under dynamic conditions that jitters the bit stream according to a reverse precompensation algorithm 10 TC width is defined as the time that both TC and DACK are active 11 The minimum Reset active period for a Software Reset is dependent on the Data Rate after the 82077AA has been properly reset using the t30 spec The minimum Software Reset period then becomes 1 Mbps 21 x t4 e 0 875 ms 500 Kbps 42 x t4 e 1 75 ms 300 Kbps 70 x t4 e 2 9 ms 250 Kbps 84 x t4 e 3 5 ms 12 Status Register's status bits which are not latched may be updated during a Host read operation 13 The minimum MFM values for WE to HDSEL change (t41) for the various data rates are 1 Mbps 0 5 ms a 8 x GPL 500 Kbps 1 0 ms a 16 x GPL 300 Kbps 1 6 ms a 26 66 x GPL 250 Kbps 2 0 ms a 32 x GPL
GPL is the size of gap 3 defined in the sixth byte of a Write Command
55
82077AA
14 This timing is a function of the selected data rate as follows 1 Mbps 1 0 ms Min 500 Kbps 2 0 ms Min 300 Kbps 3 3 ms Min 250 Kbps 4 0 ms Min 15
Part Specification Tape Drive Mode 82077AA-1 82077AA 82077AA-5 X
Supported Feature Perpendicular Drive Support X X
CLOCK TIMINGS
290166 - 9
HOST READ CYCLES
290166 - 10
56
82077AA
HOST WRITE CYCLES
290166 - 11
DMA CYCLES
290166 - 12
TERMINAL COUNT
290166 - 13
57
82077AA
RESET
290166 - 14
NOTE MFM(0) refers to the MFM pin left open during hardware reset
WRITE DATA TIMING
290166 - 15
NOTE Invert high
58
82077AA
DRIVE CONTROL
290166 - 16
NOTE For overlapped seeks only one step pulse per drive selection is issued Non-overlapped seeks will issue all programmed step pulses Invert high
INTERNAL PLL
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NOTE Invert high
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82077AA
12 0 DATA SEPARATOR CHARACTERISTICS FOR FLOPPY DISK MODE
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Figure 12-1 Typical Jitter Tolerance vs Data Rate (Capture Range) (250 Kbps)
Figure 12-2 Typical Jitter Tolerance vs Data Rate (Capture Range) (300 Kbps)
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Figure 12-3 Typical Jitter Tolerance vs Data Rate (Capture Range) (500 Kbps)
Figure 12-4 Typical Jitter Tolerance vs Data Rate (Capture Range) (1 Mbps) 82077AA-1
Jitter Tolerance measured in percent See datasheet Section 3 2 1 capture range expressed as a percent of data rate i e g3% e Test Points 250 300 500 Kbps 1 Mbps are center g3% 68% jitter g5% 65% jitter Test points are tested at temperature and VCC limits Refer to the datasheet Typical conditions are room temperature nominal VCC
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82077AA
13 0 DATA SEPARATOR CHARACTERISTICS FOR TAPE DRIVE MODE
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Figure 13-1 Typical Jitter Tolerance vs Data Rate (Capture Range) (g0% ISV 500 Kbps)
Figure 13-2 Typical Jitter Tolerance vs Data Rate (Capture Range) (g0% ISV 1 Mbps)
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Figure 13-3 Typical Jitter Tolerance vs Data Rate (Capture Range) (g3% ISV 500 Kbps)
Figure 13-4 Typical Jitter Tolerance vs Data Rate (Capture Range) (g3% ISV 1 Mbps)
NOTES 1 Jitter Tolerance measured in percent See datasheet Section 3 2 1 capture range expressed as a percent of data rate i e g5% 2 Typical conditions are room temperature nominal VCC
14 0 82077AA 68-Lead PLCC Package Thermal Characteristics
TA Ambient Temp ( C) 70 Typical Values Tc ( C) 75 Tj ( C) 75 Icc (mA) 30 Vcc (V) 50 ija ( C W) 36 ijc ( C W) 5
NOTES Case Temperature Formula Tc e Ta a P ija b ijc Junction Temperature Formula Tj e Tc a p ijc P e Power dissipated ijc e thermal resistance from the junction to the case ija e thermal resistance from the junction to the ambient ICC Outputs not connected to D C loads
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82077AA
15 0
REVISION SUMMARY
82077AA Revision Summary
The following changes have been made since revision 007 All references to the FM Mode have been removed The 82077AA does not support the FM Mode The following change has been made since revision 006 1 The 82077AA does not support the FM mode The following changes have been made since revision 005 Title Page First paragraph last sentence deleted and replaced with The 82077AA is available in three versions 82077AA-5 82077AA and 82077AA-1 82077AA-1 has all features listed in the data sheet It supports both tapes drives and 4 MB floppy drives The 82077AA supports 4 MB floppy drives and is capable of operation at all dates rates through 1 Mbps The 82077AA-5 supports 500 300 250 Kbps data rates for high and low density floppy drives New sentence added to end of paragraph This sentence reads ``CS can be held inactive during DMA transfers '' Addition of Scan Equal Scan Low or Equal and Scan High or Equal to Table 5-1 New section added titled ``Scan Commands''
Section 2 3 Section 5 0 Section 5 1 8
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