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HI1166
September 1998 File Number 3579.4
8-Bit, 250 MSPS, Flash A/D Converter
The HI1166 is an 8-bit, ultra high speed, flash Analog-toDigital converter IC capable of digitizing analog signals at a maximum rate of 250 MSPS. The digital I/O levels of the converter are compatible with ECL 100K/10KH/10K.
Features
* Differential Linearity Error . . . . . . . . . . 0.5 LSB or Less * Integral Linearity Error . . . . . . . . . . . . . 0.5 LSB or Less * Built-In Integral Linearity Compensation Circuit * Ultra High Speed Operation with Maximum Conversion Rate (Min) . . . . . . . . . . . . . . . . . . . 250 MSPS
Applications
* Spectrum Analyzers * Radar Systems * Direct RF Down-Conversion * Video Digitizing * Communication Systems * Digital Oscilloscopes
* Low Input Capacitance 18pF (Typ) * Wide Analog Input Bandwidth (Min for Full Scale Input) . . . . . . . . . . . . . . . . . . . 250MHz * Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . . -5.2V * Low Power Consumption . . . . . . . . . . . . . . . . . 1.4W (Typ)
Ordering Information
PART NUMBER HI1166AIL HI1166-EV TEMP. RANGE (oC) -20 to 100 25 PACKAGE 68 Ld CLCC PKG. NO. J68.A
* Low Error Rate * Capable of Driving 50 Loads * Evaluation Board Available * Direct Replacement for Sony CXA1166K
Evaluation Board
Pinout
HI1166 (CLCC) TOP VIEW
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61 60 NC 59 NC 58 AVEE 57 NC 56 AGND 55 VIN1 54 VIN1 53 AGND 52 VRM 51 AGND 50 VIN2 49 VIN2 48 AGND 47 NC 46 NC 45 NC 44 NC
NC 10 NC D2 D2 D3 D3 DGND2 DGND2 DGND1 D4 D4 D5 D5 NC NC NC NC
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
NC DVEE
NC AVEE
AVEE VRBS VRB
NC AVEE
D7 D7 MINV CLK
D6 D6
CLK
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
AGND
AGND
NC DVEE
D1 D1 D0 D0 OR OR LINV NC AVEE
AVEE VRTS VRT NC AVEE
HI1166 Functional Block Diagram
MINV R1 VRT 64 VRTS 65 R2 R 1 R 31 D7 (MSB) 2 R 32 D7 29 D6 30 D6 63 VIN1 54 55 R 64 R 65 OUTPUT 21 D5 22 D5 19 D4 20 D4 14 D3 R 15 D3 126 R R3 VRM 52 R 128 R 4 D0 (LSB) 129 5 D0 127 ENCODE LOGIC 12 D2 13 D2 6 D1 7 D1 R/2 0 2 OR 3 OR 33 COMPARATOR
R 191 R VIN2 49 50 192 R 193
R 254 R R4 VRBS 39 VRB 40 R5 CLK 35 CLK 34 CLOCK DRIVER 1 LINV R/2 255
2
HI1166
Absolute Maximum Ratings TA = 25oC
Supply Voltage (AVEE, DVEE) . . . . . . . . . . . . . . . . . . . . -7V to +0.5V Analog Input Voltage (VIN). . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V Reference Input Voltage VRT, VRB, VRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V |VRT -VRB | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V Digital Input Voltage MINV, LINV, CLK, CLK . . . . . . . . . . . . . . . . . . . . . . . . -4V to +0.5V |CLK-CLK| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V VRM Pin Input Current (IVRM) . . . . . . . . . . . . . . . . . . -3mA to +3mA Digital Output Current (ID0 to ID7, IOR, ID0 to ID7, IOR) . . . . . . . . . . . . . -30mA to 0mA Temperature Range, TA (Note 5) . . . . . . . . . . . . . . . -20oC to 100oC TC . . . . . . . . . . . . . . . . . . . . . -20oC to 125oC
Thermal Information
Thermal Resistance (Typical, Note 2) JAoC/W JCoC/W CLCC Package. . . . . . . . . . . . . . . . . . . 38 10 Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .2.1W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .175oC Maximum Storage Temperature Range (TSTG). . . . -65oC to 150oC Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . .300oC
Operating Conditions
(Note 1) TYP -5.2 0 0 MAX -4.95V 0.05V 0.05V Reference Input Voltage MIN TYP MAX VRT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.1V -2 0.1V VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.2V -2 -1.8V Analog Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . .VRB to VRT
Supply Voltage MIN AVEE, DVEE . . . . . . . . . . . . . . . . . . . . . . . -5.5V AVEE - DVEE . . . . . . . . . . . . . . . . . . . . . . -0.05V AGND - DGND . . . . . . . . . . . . . . . . . . . . . -0.05V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Electrical Specifications guaranteed within stated operating conditions. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL Differential Linearity Error, DNL DYNAMIC CHARACTERISTICS Signal to Noise Ratio, SINAD RMS Signal = ----------------------------------------------------------------RMS Noise + Distortion Error Rate
TA = 25oC, AVEE = DVEE = -5.2V, VRT, VRTS = 0V, VRB , VRBS = -2V (Note 1) TEST CONDITIONS MIN TYP MAX UNIT
fC = 250 MSPS fC = 250 MSPS Input = 1kHz, Full Scale fC = 250MHz Input = 60kHz, Full Scale fC = 250MHz Input = 50MHz, Full Scale Error > 16 LSB, fC = 250MHz Input = 62.499MHz, Full Scale Error > 16 LSB, fC = 250MHz -
8 0.3 0.3
0.5 0.5
Bits LSB LSB
44 250 0.4
46 37 10-8 1.0 0.5 1.0 9 1.4
10-9 10-6 2.4
dB dB TPS (Note 3) TPS (Note 3) % Degree ns MSPS ps ns
Differential Gain Error, DG Differential Phase Error, DP Overrange Recovery Time Maximum Conversion Rate, fC Aperture Jitter, tAJ Sampling Delay, tDS ANALOG INPUT Analog Input Capacitance, CIN Analog Input Resistance, RIN Input Bias Current, IIN Full Scale Input Bandwidth REFERENCE INPUTS Reference Resistance, RREF
NTSC 40 IRE Mod. Ramp, fC = 250 MSPS
VIN - 1V + 0.07VRMS VIN = -1V VIN = 2VP-P
50 20 200
18 120 250
450 -
pF k A MHz
83
125
182
3
HI1166
Electrical Specifications
PARAMETER Residual Resistance R1 R2 R3 R4 R5 DIGITAL INPUTS Logic H Level, VIH Logic L Level, VIL Logic H Current, IIH Logic L Current, IIL Input Capacitance DIGITAL OUTPUTS Logic H Level, VOH Logic L Level, VOL TIMING CHARACTERISTICS H Pulse Width of Clock, tPW1 L Pulse Width of Clock, tPW0 Output Rise Time, tr Output Fall Time, tf Output Delay, tOD POWER SUPPLY CHARACTERISTICS Supply Current, IEE Power Consumption, PD NOTES: 1. Electrical Specifications guaranteed within stated operating conditions. 2. See Functional Block Diagram. 3. TPS: Times Per Sample. ( V RT - V RB ) 4. PD = I EEA * AV EE + I EED * DV EE + -----------------------------------R
REF 2
TA = 25oC, AVEE = DVEE = -5.2V, VRT, VRTS = 0V, VRB , VRBS = -2V (Note 1) (Continued) TEST CONDITIONS Note 2 MIN 0.1 300 0.5 300 0.1 TYP 0.6 500 2.0 500 0.6 MAX 2.0 700 5.0 700 2.0 UNIT
-1.13 Input Connected to GND Input Connected to -2V 0 -50 -
4
-1.5 70 50 -
V V A A pF
RL = 50 RL = 50
-1.0 -
-
-1.6
V V
1.8 1.8 RL = 50 RL = 50 RL = 50 1.8
0.6 0.6 2.5
1.5 1.5 3.2
ns ns ns ns ns
-360 Note 4 -
-270 1.4
1.9
mA W
5. TA is specified in still air and without heat sink. To extend temperature range, appropriate heat management techniques must be employed (See Figure 2).
Timing Diagram
tSD ANALOG IN N N+1 N+2 tPW1 CLK CLK DIGITAL OUT tOD N-1 20% 80% tr N 80% N+1 20% tf tPW0
FIGURE 1.
4
HI1166 Typical Performance Curves
50 THERMAL RESISTANCE JA (oC/W) 25
SOCKET AMP: 173061-5 (WITHOUT HEAT SINK) 40 SOCKET AMP: 173257-3 (WITH HEAT SINK) 30
INPUT CAPACITANCE (pF)
20
15
SOCKET: YAMAICHI ELECTRONICS CO., LTD IC61-0684-048 0 1.0 2.0 AIR FLOW (m/s) 3.0 10 -2.0 -1.5 -1.0 INPUT VOLTAGE (V) -0.5 0
FIGURE 2. THERMAL RESISTANCE OF THE CONVERTER MOUNTED ON A BOARD
FIGURE 3. VIN PIN CAPACITANCE vs VOLTAGE CHARACTERISTICS
150 ANALOG INPUT RESISTANCE (k)
200
125 IIN (A) 100 10 -2.0
100
-1.5
-1.0 INPUT VOLTAGE (V)
-0.5
0
0 -2.0
-1.5
-1.0 INPUT VOLTAGE (V)
-0.5
0
FIGURE 4. VIN PIN INPUT RESISTANCE vs VOLTAGE CHARACTERISTICS
FIGURE 5. VIN PIN INPUT CURRENT vs VOLTAGE CHARACTERISTICS
200 RESISTOR STRING CURRENT (mA) 0 50 100 CASE TEMPERATURE (oC) 150
-12 -14
150 INPUT CURRENT (A)
-16
100
-18
-20
50
-22 -24 -50 0 50 100 CASE TEMPERATURE (oC) 150
0 -50
FIGURE 6. VIN PIN INPUT CURRENT vs TEMPERATURE CHARACTERISTICS
FIGURE 7. RESISTOR STRING CURRENT vs TEMPERATURE CHARACTERISTICS
5
HI1166 Typical Performance Curves
-1.25
(Continued)
-0.7
CLK OPEN VOLTAGE (V)
-1.30
-0.8
-1.35
VOH (V) -50 0 50 100 CASE TEMPERATURE (oC) 150
-0.9
-1.40
-1.0
-1.45
-1.1 -50 0 50 100 CASE TEMPERATURE (oC) 150
FIGURE 8. CLK OPEN VOLTAGE vs TEMPERATURE CHARACTERISTICS
FIGURE 9. VOH vs TEMPERATURE CHARACTERISTICS
-1.7
50
45 -1.8 SINAD (dB) 0 50 100 CASE TEMPERATURE (oC) 150 40
VOL (V)
-1.9
35
-2.0 30
-2.1 -50
25 1 10 100 INPUT FREQUENCY (MHz)
FIGURE 10. VOL vs TEMPERATURE CHARACTERISTICS
FIGURE 11. SINAD vs INPUT FREQUENCY RESPONSE CHARACTERISTICS
CLOCK FREQUENCY = 250MHz HIGH FREQUENCY DISTORTION (dB) -30 -40 THIRD HARMONIC CLK (MHz) SECOND HARMONIC
300
250
-50
200
-60
-70 -80 0.1
150
ERROR RATE = 10-8 TPS INPUT FREQUENCY = CLOCK FREQUENCY/4 - 1kHz ERROR RATE > 16 LSB
1
10 100 INPUT FREQUENCY (MHz)
1000
-25
25 75 125 AMBIENT TEMPERATURE (oC)
FIGURE 12. HARMONIC DISTORTION vs INPUT FREQUENCY RESPONSE CHARACTERISTICS
FIGURE 13. MAXIMUM CONVERSION RATE vs TEMPERATURE CHARACTERISTICS
6
HI1166 Typical Performance Curves
(Continued)
INPUT FREQUENCY = CLOCK FREQUENCY/4 - 1kHz ERROR RATE > 16 LSB 10-7 ERROR RATE (TPS) ERROR RATE (TPS) 10-7
INPUT = 125MHz, FULL SCALE CLK = 250MHz, ERROR RATE > 16 LSB
10-8
10-9
10-8
10-10 200 250 300 CLOCK FREQUENCY (MHz)
10-9 25
30
35
50 40 45 55 CLK DUTY CYCLE (%)
60
65
70
FIGURE 14. ERROR RATE vs CONVERSION RATE
-200
FIGURE 15. ERROR RATE vs CLOCK DUTY CYCLE
SUPPLY CURRENT (mA)
-250
-300
-350 -50
0
50
100
150
CASE TEMPERATURE (oC)
FIGURE 16. SUPPLY CURRENT vs TEMPERATURE CHARACTERISTICS
Pin Descriptions
PIN NUMBER 4, 5 6, 7 12, 13 14, 15 19, 20 21, 22 29, 30 31, 32 2, 3 SYMBOL D0, D0 D1, D1 D2, D2 D3, D3 D4, D4 D5, D5 D6, D6 D7, D7 OR, OR
DVEE 8 28 Di Di
I/O O
STANDARD VOLTAGE LEVEL ECL
EQUIVALENT CIRCUIT
DGND2 16
DESCRIPTION LSB and complementary LSB output. D1 to D6: Data Output. D1 to D6: Complementary Data Output.
MSB Complementary MSB Data Output. Overrange and Complementary Overrange Output.
7
HI1166 Pin Descriptions
PIN NUMBER 1 SYMBOL LINV (Continued) I/O I STANDARD VOLTAGE LEVEL ECL EQUIVALENT CIRCUIT
DGND1 18
DESCRIPTION Polarity selection for LSBs (refer to the A/D Output Code Table.) Pulled low when left open.
33
MINV
I
ECL
R R R LINV 1 OR MINV 33 R 8 DVEE 28 -1.3V
Polarity selection for MSB (refer to the A/D Output Code Table). Pulled low when left open.
35 34
CLK CLK
I I
ECL ECL
DGND1 18
CLK Input. Complementary CLK Input. Pulled down to -1.3V when left open.
R R R
CLK 35 34 CLK DVEE 8 28
R
R
R
64 65 52 39 40
VRT VRTS VRM VRBS VRB
I O I O I
0V 0V VRB/2 -2V
VRT 64 VRTS 65 R/2 R2 R1
Analog Reference Voltage (Top) (0V Typ). Reference Voltage Sense (Top). Reference Voltage Mid Point. Can be used for linearity compensation. Reference Voltage Sense (Bottom). Analog Reference Voltage (Bottom).
R
-2V
VRM 52 R3 R TO COMPARATORS
R VRBS 39 VRB 40 R5 R/2
R4
8
HI1166 Pin Descriptions
PIN NUMBER 49, 50 54, 55 SYMBOL VIN2 VIN1 (Continued) I/O I STANDARD VOLTAGE LEVEL VRTS to VRBS
VIN2 49 50 54 55 VIN1 0 TO 127 TO COMP. 128 TO 255
EQUIVALENT CIRCUIT
43, 48, 51, 53, 56, 61
DESCRIPTION Analog Input. All of the pins must be wired externally.
AGND
43, 48, 51, 53, 56, 61 37, 38, 42, 58, 62, 66, 67 18 16, 17 8, 28
AGND AVEE
0V
61
AGND 48 51 53 56
DGND1 18
DGND2 16 17
Analog ground. Analog supply. Internally connected to DVEE (resistance: 4 to 6).
-5.2V
43
DGND1 DGND2 DVEE
0V 0V -5.2V
INTERNAL ANALOG CIRCUIT
INTERNAL DIGITAL CIRCUIT 4 TO 6
Digital ground. Digital ground for output drive.
D1 D1
42 62
37 38 AVEE
58 66 67
Digital supply. Internally connected to AVEE (resistance: 4 to 6).
8
28
DVEE
TABLE 1. A/D OUTPUT CODE VIN (NOTE 6) 0V 0 1 STEP OR 0 1 1 MINV 1, LINV 1 D7 D0 000 * * * * * 00 000 * * * * * 00 000 * * * * * 01 * * * 011 * * * * * 11 100 * * * * * 00 * * * 111 * * * * * 10 111 * * * * * 11 111 * * * * * 11 OR 0 1 1 0, 1 D7 D0 OR 0 1 1 1, 0 D7 D0 OR 0 1 1 0, 0 D0 D7
-1V
127 128
1 1
1 1
254 255 -2V NOTE:
1 1 1
1 1 1
100 * * * * * 00 100 * * * * * 00 100 * * * * * 01 * * * 111 * * * * * 11 000 * * * * * 00 * * * 011 * * * * * 10 011 * * * * * 11 011 * * * * * 11
1 1
1 1 1
011 * * * * * 11 011 * * * * * 11 011 * * * * * 10 * * * 000 * * * * * 00 111 * * * * * 11 * * * 100 * * * * * 01 100 * * * * * 00 100 * * * * * 00
1 1
1 1 1
111 * * * * * 11 111 * * * * * 11 111 * * * * * 10 * * * 100 * * * * * 00 011 * * * * * 11 * * * 000 * * * * * 01 000 * * * * * 00 000 * * * * * 00
6. VRT = VRTS = 0V, VRM = -1V or open, VRB = VRBS = -2V.
9
HI1166 Test Circuits and Waveforms
FUNC. GENERATOR 100 1 2 NTSC SIGNAL SOURCE AMP 2 VIN DUT HI1166 CLK CLK 21 -4.5V SG (CW) 50 DUTY DIVIDER SWITCH POSITION 1. MAXIMUM CONVERSION RATE 2. DG/DP VECTOR SCOPE DG/DP OSCILLOSCOPE MAXIMUM CONVERSION RATE 8 110 ECL LATCH 100 8 110 HI20201 10-BIT D/A AMP fms 0V -2V
FIGURE 17. MAXIMUM CONVERSION RATE TEST CIRCUIT
+V
S2
+ S1
S1 : A < B : ON S2 : A > B : ON
-V AB 8
COMPARATOR A8 TO A1 A0 B8 TO B1 B0 BUFFER
DVM "0" CLK (250MHz)
"1" 8 000 * * * 00 TO 111 * * * 10
CONTROLLER
FIGURE 18. INTEGRAL AND DIFFERENTIAL LINEARITY ERROR TEST CIRCUIT
10
HI1166 Test Circuits and Waveforms
(Continued)
IIN A -1V
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
-2V
HI1166
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A IEEA -5.2V
A IEED -5.2V
FIGURE 19. POWER SUPPLY AND ANALOG INPUT BIAS CURRENT TEST CIRCUIT
VIN 0V -1V -2V
CLK
t VIN 60MHz AMP
t
129 128 127 126 125
(LSB)
: VARIABLE
VIN fR CLK OSC2 60MHz ECL BUFFER HI1166 8 LOGIC ANALYZER 1024 SAMPLES
OSC1
CLK
APERTURE JITTER APERTURE JITTER IS DEFINED AS FOLLOWS: 256 t AJ = ------ = --------- x 2f 2 t
Where (unit: LSB) is the deviation of the output codes when the input frequency is exactly the same as the clock and is sampled at the largest slew rate point.
FIGURE 20A.
FIGURE 20B. APERTURE JITTER TEST METHOD
FIGURE 20. SAMPLING DELAY AND APERTURE JITTER TEST CIRCUIT
11
HI1166 Ceramic Leadless Chip Carrier Packages (CLCC)
0.010 S E H S D D3
J68.A
68 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE INCHES SYMBOL A A1 B B1 B3 D D1 D2 D3 MIN 0.067 0.058 0.033 0.006 0.940 MAX 0.087 0.072 0.039 0.022 0.965 MILLIMETERS MIN 1.70 1.47 0.85 0.15 23.88 MAX 2.20 1.83 0.99 0.56 24.51 NOTES 6, 7 2, 4 2 2 1.40 1.40 2.41 0.38 17 17 68 2 5 3 3 3 Rev. 0 5/18/94 NOTES: 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol "N" is the maximum number of terminals. Symbols "ND" and "NE" are the number of terminals along the sides of length "D" and "E", respectively. 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension "A" controls the overall package thickness. The maximum "A" dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Controlling dimension: INCH.
j x 45o
B
E3
E
0.800 BSC 0.400 BSC 0.616 0.940 0.632 0.965
20.32 BSC 10.16 BSC 15.65 23.88 16.05 24.51
h x 45o 0.010 S E F S A A1 PLANE 2 PLANE 1
E E1 E2 E3 e e1 j L L1
0.007 M E F S H S B1
0.800 BSC 0.400 BSC 0.616 0.015 0.040 Ref 0.045 0.045 0.075 0.003 17 17 68 0.055 0.055 0.095 0.015 0.632 0.050 BSC
20.32 BSC 10.16 BSC 15.65 0.38 1.00 Ref 1.14 1.14 1.91 0.08 16.05 1.27 BSC
-E-
L2 L3 ND
L3
e
L -H-
NE N
-FE1 B3
E2
L2 B2
L1
e1
D1
D2
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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